risc-v/esp32c6: Add ESP32-C6 basic support

1. Bring up OS kernel.
  2. Add interrupt support.
  3. Add system timer support.
  4. Add the ESP32-C6 devkit board.
  5. Add basic UART support for console.
  6. Add clock configuration.
  7. Add board reset support.

Documentation/platforms/risc-v/esp32c6/index.rst

@@ -0,0 +1,68 @@
+==================
+Espressif ESP32-C6
+==================
+
+The ESP32-C6 is an ultra-low-power and highly integrated SoC with a RISC-V
+core and supports 2.4 GHz Wi-Fi 6, Bluetooth 5 (LE) and the 802.15.4 protocol.
+
+* Address Space
+  - 800 KB of internal memory address space accessed from the instruction bus
+  - 560 KB of internal memory address space accessed from the data bus
+  - 1016 KB of peripheral address space
+  - 8 MB of external memory virtual address space accessed from the instruction bus
+  - 8 MB of external memory virtual address space accessed from the data bus
+  - 480 KB of internal DMA address space
+* Internal Memory
+  - 320 KB ROM
+  - 512 KB SRAM (16 KB can be configured as Cache)
+  - 16 KB of SRAM in RTC
+* External Memory
+  - Up to 16 MB of external flash
+* Peripherals
+  - 35 peripherals
+* GDMA
+  - 7 modules are capable of DMA operations.
+
+ESP32-C6 Toolchain
+==================
+
+A generic RISC-V toolchain can be used to build ESP32-C6 projects.
+SiFive's toolchain can be downloaded from: https://github.com/sifive/freedom-tools/releases
+
+Second stage bootloader and partition table
+===========================================
+
+The NuttX port for now relies on IDF's second stage bootloader to carry on some hardware
+initializations.  The binaries for the bootloader and the partition table can be found in
+this repository: https://github.com/espressif/esp-nuttx-bootloader
+That repository contains a dummy IDF project that's used to build the bootloader and
+partition table, these are then presented as Github assets and can be downloaded
+from: https://github.com/espressif/esp-nuttx-bootloader/releases
+Download ``bootloader-esp32c6.bin`` and ``partition-table-esp32c6.bin`` and place them
+in a folder, the path to this folder will be used later to program them. This
+can be: ``../esp-bins``
+
+Building and flashing
+=====================
+
+First make sure that ``esptool.py`` is installed.  This tool is used to convert
+the ELF to a compatible ESP32-C6 image and to flash the image into the board.
+It can be installed with: ``pip install esptool``.
+
+Configure the NUttX project: ``./tools/configure.sh esp32c6-devkit:nsh``
+Run ``make`` to build the project.  Note that the conversion mentioned above is
+included in the build process.  
+The `esptool.py` command to flash all the binaries is::
+
+     esptool.py --chip esp32c6 --port /dev/ttyUSBXX --baud 921600 write_flash 0x0 bootloader.bin 0x8000 partition-table.bin 0x10000 nuttx.bin
+
+However, this is also included in the build process and we can build and flash with::
+
+   make flash ESPTOOL_PORT=<port> ESPTOOL_BINDIR=../esp-bins
+
+Where ``<port>`` is typically ``/dev/ttyUSB0`` or similar and ``../esp-bins`` is 
+the path to the folder containing the bootloader and the partition table
+for the ESP32-C6 as explained above.
+Note that this step is required only one time.  Once the bootloader and partition
+table are flashed, we don't need to flash them again.  So subsequent builds
+would just require: ``make flash ESPTOOL_PORT=/dev/ttyUSBXX``

arch/risc-v/Kconfig

@@ -87,6 +87,29 @@ config ARCH_CHIP_ESP32C3
 	---help---
 		Espressif ESP32-C3 (RV32IMC).
 
+config ARCH_CHIP_ESP32C6
+	bool "Espressif ESP32-C6"
+	select ARCH_RV32
+	select ARCH_RV_ISA_M
+	select ARCH_RV_ISA_A
+	select ARCH_RV_ISA_C
+	select ARCH_VECNOTIRQ
+	select ARCH_HAVE_RESET
+	select LIBC_ARCH_MEMCPY
+	select LIBC_ARCH_MEMCHR
+	select LIBC_ARCH_MEMCMP
+	select LIBC_ARCH_MEMMOVE
+	select LIBC_ARCH_MEMSET
+	select LIBC_ARCH_STRCHR
+	select LIBC_ARCH_STRCMP
+	select LIBC_ARCH_STRCPY
+	select LIBC_ARCH_STRLCPY
+	select LIBC_ARCH_STRNCPY
+	select LIBC_ARCH_STRLEN
+	select LIBC_ARCH_STRNLEN
+	---help---
+		Espressif ESP32-C6 (RV32IMAC).
+
 config ARCH_CHIP_C906
 	bool "THEAD C906"
 	select ARCH_RV64
@@ -199,6 +222,7 @@ config ARCH_CHIP
 	default "litex"		if ARCH_CHIP_LITEX
 	default "bl602"		if ARCH_CHIP_BL602
 	default "esp32c3"	if ARCH_CHIP_ESP32C3
+	default "esp32c6"	if ARCH_CHIP_ESP32C6
 	default "c906"		if ARCH_CHIP_C906
 	default "mpfs"		if ARCH_CHIP_MPFS
 	default "rv32m1"	if ARCH_CHIP_RV32M1
@@ -329,6 +353,9 @@ endif
 if ARCH_CHIP_ESP32C3
 source "arch/risc-v/src/esp32c3/Kconfig"
 endif
+if ARCH_CHIP_ESP32C6
+source "arch/risc-v/src/esp32c6/Kconfig"
+endif
 if ARCH_CHIP_C906
 source "arch/risc-v/src/c906/Kconfig"
 endif

arch/risc-v/include/esp32c6/chip.h

@@ -0,0 +1,24 @@
+/****************************************************************************
+ * arch/risc-v/include/esp32c6/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_ESP32C6_CHIP_H
+#define __ARCH_RISCV_INCLUDE_ESP32C6_CHIP_H
+
+#endif /* __ARCH_RISCV_INCLUDE_ESP32C6_CHIP_H */

arch/risc-v/include/esp32c6/irq.h

@@ -0,0 +1,260 @@
+/****************************************************************************
+ * arch/risc-v/include/esp32c6/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_ESP32C6_IRQ_H
+#define __ARCH_RISCV_INCLUDE_ESP32C6_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#  include <arch/csr.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Interrupt Matrix
+ * The Interrupt Matrix embedded in the ESP32-C6 independently allocates
+ * peripheral interrupt sources to the CPUs’ peripheral interrupts.
+ * This configuration is highly flexible in order to meet many different
+ * needs.
+ *
+ * Features
+ * - Accepts 77 peripheral interrupt sources as input.
+ * - Generate 31 peripheral interrupts to CPU as output.
+ * - Queries current interrupt status of peripheral interrupt sources.
+ */
+
+#define ESP32C6_WIFI_MAC_PERIPH             0      /* interrupt of WiFi MAC, level */
+#define ESP32C6_WIFI_MAC_NMI_PERIPH         1      /* interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI */
+#define ESP32C6_WIFI_PWR_PERIPH             2
+#define ESP32C6_WIFI_BB_PERIPH              3      /* interrupt of WiFi BB, level, we can do some calibartion */
+#define ESP32C6_BT_MAC_PERIPH               4
+#define ESP32C6_BT_BB_PERIPH                5      /* interrupt of BT BB, level */
+#define ESP32C6_BT_BB_NMI_PERIPH            6      /* interrupt of BT BB, NMI, use if BB have bug to fix in NMI */
+#define ESP32C6_LP_TIMER_PERIPH             7
+#define ESP32C6_COEX_PERIPH                 8
+#define ESP32C6_BLE_TIMER_PERIPH            9
+#define ESP32C6_BLE_SEC_PERIPH              10
+#define ESP32C6_I2C_MASTER_PERIPH           11      /* interrupt of I2C Master, level */
+#define ESP32C6_ZB_MAC_PERIPH               12
+#define ESP32C6_PMU_PERIPH                  13
+#define ESP32C6_EFUSE_PERIPH                14      /* interrupt of efuse, level, not likely to use */
+#define ESP32C6_LP_RTC_TIMER_PERIPH         15
+#define ESP32C6_LP_UART_PERIPH              16
+#define ESP32C6_LP_I2C_PERIPH               17
+#define ESP32C6_LP_WDT_PERIPH               18
+#define ESP32C6_LP_PERI_TIMEOUT_PERIPH      19
+#define ESP32C6_LP_APM_M0_PERIPH            20
+#define ESP32C6_LP_APM_M1_PERIPH            21
+#define ESP32C6_FROM_CPU_PERIPH0            22      /* interrupt0 generated from a CPU, level */
+#define ESP32C6_FROM_CPU_PERIPH1            23      /* interrupt1 generated from a CPU, level */
+#define ESP32C6_FROM_CPU_PERIPH2            24      /* interrupt2 generated from a CPU, level */
+#define ESP32C6_FROM_CPU_PERIPH3            25      /* interrupt3 generated from a CPU, level */
+#define ESP32C6_ASSIST_DEBUG_PERIPH         26      /* interrupt of Assist debug module, level */
+#define ESP32C6_TRACE_PERIPH                27
+#define ESP32C6_CACHE_PERIPH                28
+#define ESP32C6_CPU_PERI_TIMEOUT_PERIPH     29
+#define ESP32C6_GPIO_PERIPH                 30      /* interrupt of GPIO, level */
+#define ESP32C6_GPIO_NMI_PERIPH             31      /* interrupt of GPIO, NMI */
+#define ESP32C6_PAU_PERIPH                  32
+#define ESP32C6_HP_PERI_TIMEOUT_PERIPH      33
+#define ESP32C6_MODEM_PERI_TIMEOUT_PERIPH   34
+#define ESP32C6_HP_APM_M0_PERIPH            35
+#define ESP32C6_HP_APM_M1_PERIPH            36
+#define ESP32C6_HP_APM_M2_PERIPH            37
+#define ESP32C6_HP_APM_M3_PERIPH            38
+#define ESP32C6_LP_APM0_PERIPH              39
+#define ESP32C6_MSPI_PERIPH                 40
+#define ESP32C6_I2S1_PERIPH                 41      /* interrupt of I2S1, level */
+#define ESP32C6_UHCI0_PERIPH                42      /* interrupt of UHCI0, level */
+#define ESP32C6_UART0_PERIPH                43      /* interrupt of UART0, level */
+#define ESP32C6_UART1_PERIPH                44      /* interrupt of UART1, level */
+#define ESP32C6_LEDC_PERIPH                 45      /* interrupt of LED PWM, level */
+#define ESP32C6_TWAI0_PERIPH                46      /* interrupt of can0, level */
+#define ESP32C6_TWAI1_PERIPH                47      /* interrupt of can1, level */
+#define ESP32C6_USB_SERIAL_JTAG_PERIPH      48      /* interrupt of USB, level */
+#define ESP32C6_RMT_PERIPH                  49      /* interrupt of remote controller, level */
+#define ESP32C6_I2C_EXT0_PERIPH             50      /* interrupt of I2C controller1, level */
+#define ESP32C6_TG0_T0_LEVEL_PERIPH         51      /* interrupt of TIMER_GROUP0, TIMER0, level */
+#define ESP32C6_TG0_T1_LEVEL_PERIPH         52      /* interrupt of TIMER_GROUP0, TIMER1, level */
+#define ESP32C6_TG0_WDT_LEVEL_PERIPH        53      /* interrupt of TIMER_GROUP0, WATCH DOG, level */
+#define ESP32C6_TG1_T0_LEVEL_PERIPH         54      /* interrupt of TIMER_GROUP1, TIMER0, level */
+#define ESP32C6_TG1_T1_LEVEL_PERIPH         55      /* interrupt of TIMER_GROUP1, TIMER1, level */
+#define ESP32C6_TG1_WDT_LEVEL_PERIPH        56      /* interrupt of TIMER_GROUP1, WATCHDOG, level */
+#define ESP32C6_SYSTIMER_TARGET0_EDGE_PERIPH 57     /* interrupt of system timer 0, EDGE */
+#define ESP32C6_SYSTIMER_TARGET1_EDGE_PERIPH 58     /* interrupt of system timer 1, EDGE */
+#define ESP32C6_SYSTIMER_TARGET2_EDGE_PERIPH 59     /* interrupt of system timer 2, EDGE */
+#define ESP32C6_APB_ADC_PERIPH               60     /* interrupt of APB ADC, level */
+#define ESP32C6_MCPWM0_PERIPH                61     /* interrupt of MCPWM0, level */
+#define ESP32C6_PCNT_PERIPH                  62 
+#define ESP32C6_PARL_IO_PERIPH               63
+#define ESP32C6_SLC0_PERIPH                  64 
+#define ESP32C6_SLC_PERIPH                   65
+#define ESP32C6_DMA_IN_CH0_PERIPH            66     /* interrupt of general DMA IN channel 0, level */
+#define ESP32C6_DMA_IN_CH1_PERIPH            67     /* interrupt of general DMA IN channel 1, level */
+#define ESP32C6_DMA_IN_CH2_PERIPH            68     /* interrupt of general DMA IN channel 2, level */
+#define ESP32C6_DMA_OUT_CH0_PERIPH           69     /* interrupt of general DMA OUT channel 0, level */
+#define ESP32C6_DMA_OUT_CH1_PERIPH           70     /* interrupt of general DMA OUT channel 1, level */
+#define ESP32C6_DMA_OUT_CH2_PERIPH           71     /* interrupt of general DMA OUT channel 2, level */
+#define ESP32C6_GSPI2_PERIPH                 72 
+#define ESP32C6_AES_PERIPH                   73     /* interrupt of AES accelerator, level */
+#define ESP32C6_SHA_PERIPH                   74     /* interrupt of SHA accelerator, level */
+#define ESP32C6_RSA_PERIPH                   75     /* interrupt of RSA accelerator, level */
+#define ESP32C6_ECC_PERIPH                   76     /* interrupt of ECC accelerator, level */
+
+/* Total number of peripherals */
+
+#define ESP32C6_NPERIPHERALS            77
+
+/* CPU Interrupts.
+ * The ESP32-C6 CPU interrupt controller accepts 31 asynchronous interrupts.
+ */
+
+#define ESP32C6_CPUINT_MIN             1
+#define ESP32C6_CPUINT_MAX             31
+
+#define ESP32C6_NCPUINTS               32
+
+#define ESP32C6_CPUINT_PERIPHSET       0xffffffff
+
+/* IRQ numbers. */
+
+/* ecall is dispatched like normal interrupts.  It occupies an IRQ number. */
+
+#define RISCV_NIRQ_INTERRUPTS       16  /* Number of RISC-V dispatched interrupts. */
+#define ESP32C6_IRQ_FIRSTPERIPH     16  /* First peripheral IRQ number */
+
+/* IRQ numbers for peripheral interrupts coming through the Interrupt
+ * Matrix.
+ */
+
+#define ESP32C6_IRQ2PERIPH(irq)       ((irq) - ESP32C6_IRQ_FIRSTPERIPH)
+#define ESP32C6_PERIPH2IRQ(id)        ((id) + ESP32C6_IRQ_FIRSTPERIPH)
+
+/* Peripheral IRQs */
+
+#define ESP32C6_IRQ_WIFI_MAC            (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_WIFI_MAC_PERIPH)
+#define ESP32C6_IRQ_WIFI_MAC_NMI        (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_WIFI_MAC_NMI_PERIPH)
+#define ESP32C6_IRQ_WIFI_PWR            (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_WIFI_PWR_PERIPH)
+#define ESP32C6_IRQ_WIFI_BB             (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_WIFI_BB_PERIPH)
+
+#define ESP32C6_IRQ_BT_MAC              (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_BT_MAC_PERIPH)
+#define ESP32C6_IRQ_BT_BB               (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_BT_BB_PERIPH)
+#define ESP32C6_IRQ_BT_BB_NMI           (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_BT_BB_NMI_PERIPH)
+#define ESP32C6_IRQ_LP_TIMER            (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_TIMER_PERIPH)
+
+#define ESP32C6_IRQ_COEX                (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_COEX_PERIPH)
+#define ESP32C6_IRQ_BLE_TIMER           (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_BLE_TIMER_PERIPH)
+#define ESP32C6_IRQ_BLE_SEC             (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_BLE_SEC_PERIPH)
+#define ESP32C6_IRQ_I2C_MASTER          (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_I2C_MASTER_PERIPH)
+
+#define ESP32C6_IRQ_ZB_MAC              (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_ZB_MAC_PERIPH)
+#define ESP32C6_IRQ_PMU                 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_PMU_PERIPH)
+#define ESP32C6_IRQ_EFUSE               (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_EFUSE_PERIPH)
+#define ESP32C6_IRQ_LP_RTC_TIMER        (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_RTC_TIMER_PERIPH)
+
+#define ESP32C6_IRQ_LP_UART             (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_UART_PERIPH)
+#define ESP32C6_IRQ_LP_I2C              (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_I2C_PERIPH)
+#define ESP32C6_IRQ_LP_WDT              (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_WDT_PERIPH)
+#define ESP32C6_IRQ_LP_PERI_TIMEOUT     (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_PERI_TIMEOUT_PERIPH)
+
+#define ESP32C6_IRQ_LP_APM_M0           (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_APM_M0_PERIPH)
+#define ESP32C6_IRQ_LP_APM_M1           (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_APM_M1_PERIPH)
+#define ESP32C6_IRQ_FROM_CPU_PERIPH0    (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_FROM_CPU_PERIPH0)
+#define ESP32C6_IRQ_FROM_CPU_PERIPH1    (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_FROM_CPU_PERIPH1)
+
+#define ESP32C6_IRQ_FROM_CPU_PERIPH2    (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_FROM_CPU_PERIPH2)
+#define ESP32C6_IRQ_FROM_CPU_PERIPH3    (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_FROM_CPU_PERIPH3)
+#define ESP32C6_IRQ_ASSIST_DEBUG        (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_ASSIST_DEBUG_PERIPH)
+#define ESP32C6_IRQ_TRACE               (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TRACE_PERIPH)
+
+#define ESP32C6_IRQ_CACHE               (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_CACHE_PERIPH)
+#define ESP32C6_IRQ_CPU_PERI_TIMEOUT    (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_CPU_PERI_TIMEOUT_PERIPH)
+#define ESP32C6_IRQ_GPIO                (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_GPIO_PERIPH)
+#define ESP32C6_IRQ_GPIO_NMI            (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_GPIO_NMI_PERIPH)
+
+#define ESP32C6_IRQ_PAU                 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_PAU_PERIPH)
+#define ESP32C6_IRQ_HP_PERI_TIMEOUT     (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_HP_PERI_TIMEOUT_PERIPH)
+#define ESP32C6_IRQ_MODEM_PERI_TIMEOUT  (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_MODEM_PERI_TIMEOUT_PERIPH)
+#define ESP32C6_IRQ_HP_APM_M0           (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_HP_APM_M0_PERIPH)
+
+#define ESP32C6_IRQ_HP_APM_M1           (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_HP_APM_M1_PERIPH)
+#define ESP32C6_IRQ_HP_APM_M2           (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_HP_APM_M2_PERIPH)
+#define ESP32C6_IRQ_HP_APM_M3           (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_HP_APM_M3_PERIPH)
+#define ESP32C6_IRQ_LP_APM0             (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_APM0_PERIPH)
+
+#define ESP32C6_IRQ_MSPI                (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_MSPI_PERIPH)
+#define ESP32C6_IRQ_I2S1                (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_I2S1_PERIPH)
+#define ESP32C6_IRQ_UHCI0               (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_UHCI0_PERIPH)
+#define ESP32C6_IRQ_UART0               (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_UART0_PERIPH)
+
+#define ESP32C6_IRQ_UART1               (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_UART1_PERIPH)
+#define ESP32C6_IRQ_LEDC                (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LEDC_PERIPH)
+#define ESP32C6_IRQ_TWAI0               (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TWAI0_PERIPH)
+#define ESP32C6_IRQ_TWAI1               (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TWAI1_PERIPH)
+
+#define ESP32C6_IRQ_USB_SERIAL_JTAG     (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_USB_SERIAL_JTAG_PERIPH)
+#define ESP32C6_IRQ_RMT                 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_RMT_PERIPH)
+#define ESP32C6_IRQ_I2C_EXT0            (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_I2C_EXT0_PERIPH)
+#define ESP32C6_IRQ_TG0_T0_LEVEL        (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TG0_T0_LEVEL_PERIPH)
+
+#define ESP32C6_IRQ_TG0_T1_LEVEL        (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TG0_T1_LEVEL_PERIPH)
+#define ESP32C6_IRQ_TG0_WDT_LEVEL       (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TG0_WDT_LEVEL_PERIPH)
+#define ESP32C6_IRQ_TG1_T0_LEVEL        (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TG1_T0_LEVEL_PERIPH)
+#define ESP32C6_IRQ_TG1_T1_LEVEL        (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TG1_T1_LEVEL_PERIPH)
+
+#define ESP32C6_IRQ_TG1_WDT_LEVEL             (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TG1_WDT_LEVEL_PERIPH)
+#define ESP32C6_IRQ_SYSTIMER_TARGET0_EDGE     (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_SYSTIMER_TARGET0_EDGE_PERIPH)
+#define ESP32C6_IRQ_SYSTIMER_TARGET1_EDGE     (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_SYSTIMER_TARGET1_EDGE_PERIPH)
+#define ESP32C6_IRQ_SYSTIMER_TARGET2_EDGE     (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_SYSTIMER_TARGET2_EDGE_PERIPH)
+
+#define ESP32C6_IRQ_APB_ADC             (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_APB_ADC_PERIPH)
+#define ESP32C6_IRQ_MCPWM0              (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_MCPWM0_PERIPH)
+#define ESP32C6_IRQ_PCNT                (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_PCNT_PERIPH)
+#define ESP32C6_IRQ_PARL_IO             (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_PARL_IO_PERIPH)
+
+#define ESP32C6_IRQ_SLC0                (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_SLC0_PERIPH)
+#define ESP32C6_IRQ_SLC                 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_SLC_PERIPH)
+#define ESP32C6_IRQ_DMA_IN_CH0          (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_DMA_IN_CH0_PERIPH)
+#define ESP32C6_IRQ_DMA_IN_CH1          (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_DMA_IN_CH1_PERIPH)
+
+#define ESP32C6_IRQ_DMA_IN_CH2          (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_DMA_IN_CH2_PERIPH)
+#define ESP32C6_IRQ_DMA_OUT_CH0         (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_DMA_OUT_CH0_PERIPH)
+#define ESP32C6_IRQ_DMA_OUT_CH1         (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_DMA_OUT_CH1_PERIPH)
+#define ESP32C6_IRQ_DMA_OUT_CH2         (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_DMA_OUT_CH2_PERIPH)
+
+#define ESP32C6_IRQ_GSPI2               (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_GSPI2_PERIPH)
+#define ESP32C6_IRQ_AES                 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_AES_PERIPH)
+#define ESP32C6_IRQ_SHA                 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_SHA_PERIPH)
+#define ESP32C6_IRQ_RSA                 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_RSA_PERIPH)
+
+#define ESP32C6_IRQ_CACHE_CORE0_ACS     (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_ECC_PERIPH)
+
+#define ESP32C6_NIRQ_PERIPH             ESP32C6_NPERIPHERALS
+
+/* Total number of IRQs: ecall + Number of peripheral IRQs + GPIOs IRQs. */
+
+#define NR_IRQS  (RISCV_NIRQ_INTERRUPTS + ESP32C6_NIRQ_PERIPH)
+
+#endif /* __ARCH_RISCV_INCLUDE_ESP32C6_IRQ_H */

arch/risc-v/src/esp32c6/Kconfig

@@ -0,0 +1,119 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_CHIP_ESP32C6
+
+comment "ESP32-C6 Configuration Options"
+
+choice
+	prompt "ESP32-C6 Chip Selection"
+	default ARCH_CHIP_ESP32C6WROOM1
+	depends on ARCH_CHIP_ESP32C6
+
+config ARCH_CHIP_ESP32C6X
+	bool "ESP32-C6"
+	select ESP32C6_ESP32C6XXX
+	---help---
+		ESP32 chip with a single RISC-V IMC core, no embedded Flash memory
+
+config ARCH_CHIP_ESP32C6FX4
+	bool "ESP32-C6Fx4"
+	select ESP32C6_ESP32C6XXX
+	select ESP32C6_FLASH_4M
+	---help---
+		ESP32 chip with a single RISC-V IMC core, 4 MB of in-package Flash memory
+
+config ARCH_CHIP_ESP32C6MINI1
+	bool "ESP32-C6-MINI-1"
+	select ESP32C6_ESP32C6XXX
+	select ESP32C6_FLASH_4M
+	---help---
+		Generic module with an embedded ESP32-C6Fx4 chip
+
+config ARCH_CHIP_ESP32C6WROOM1
+	bool "ESP32-C6-WROOM-1"
+	select ESP32C6_ESP32C6XXX
+	select ESP32C6_FLASH_4M
+	---help---
+		Generic module with an embedded ESP32-C6 chip, 4 MB of Flash memory
+
+endchoice # ESP32-C6 Chip Selection
+
+comment "Selected ESP32-C6 chip without embedded Flash, an external Flash memory is required."
+	depends on ARCH_CHIP_ESP32C6X
+
+config ESP32C6_SINGLE_CPU
+	bool
+	default n
+
+config ESP32C6_DUAL_CPU
+	bool
+	default n
+
+config ESP32C6_FLASH_2M
+	bool
+	default n
+
+config ESP32C6_FLASH_4M
+	bool
+	default n
+
+config ESP32C6_FLASH_8M
+	bool
+	default n
+
+config ESP32C6_FLASH_16M
+	bool
+	default n
+
+config ESP32C6_ESP32C6XXX
+	bool
+	default n
+	select ESP32C6_SINGLE_CPU
+
+choice ESP32C6_CPU_FREQ
+	prompt "CPU frequency"
+	default ESP32C6_CPU_FREQ_160
+	help
+		CPU frequency to be set on application startup.
+
+config ESP32C6_CPU_FREQ_80
+	bool "80 MHz"
+
+config ESP32C6_CPU_FREQ_120
+	bool "120 MHz"
+
+config ESP32C6_CPU_FREQ_160
+	bool "160 MHz"
+
+endchoice # CPU frequency
+
+config ESP32C6_CPU_FREQ_MHZ
+	int
+	default 80 if ESP32C6_CPU_FREQ_80
+	default 120 if ESP32C6_CPU_FREQ_120
+	default 160 if ESP32C6_CPU_FREQ_160
+
+menu "ESP32-C6 Peripheral Support"
+
+config ESP32C6_UART
+	bool
+	default n
+
+config ESP32C6_UART0
+	bool "UART0"
+	default y
+	select ESP32C6_UART
+	select UART0_SERIALDRIVER
+
+config ESP32C6_UART1
+	bool "UART1"
+	default n
+	select ESP32C6_UART
+	select UART1_SERIALDRIVER
+
+endmenu
+
+endif # ARCH_CHIP_ESP32C6

arch/risc-v/src/esp32c6/Make.defs

@@ -0,0 +1,38 @@
+############################################################################
+# arch/risc-v/src/esp32c6/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include common/Make.defs
+
+# Specify our HEAD assembly file.  This will be linked as
+# the first object file, so it will appear at address 0
+
+HEAD_ASRC = esp32c6_head.S
+
+CHIP_ASRCS = esp32c6_vectors.S
+
+# Specify our general Assembly files
+
+CMN_ASRCS := $(filter-out riscv_vectors.S,$(CMN_ASRCS))
+
+# Specify our C code within this directory to be included
+
+CHIP_CSRCS  = esp32c6_allocateheap.c esp32c6_start.c esp32c6_idle.c
+CHIP_CSRCS += esp32c6_irq.c esp32c6_timerisr.c esp32c6_systemreset.c
+CHIP_CSRCS += esp32c6_serial.c esp32c6_lowputc.c esp32c6_clockconfig.c

arch/risc-v/src/esp32c6/chip.h

@@ -0,0 +1,39 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C6_CHIP_H
+#define __ARCH_RISCV_SRC_ESP32C6_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "esp32c6_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Section for exception handler. */
+
+#define EXCEPTION_SECTION .iram1
+
+#endif /* __ARCH_RISCV_SRC_ESP32C6_CHIP_H */

arch/risc-v/src/esp32c6/esp32c6.h

@@ -0,0 +1,49 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C6_ESP32C6_H
+#define __ARCH_RISCV_SRC_ESP32C6_ESP32C6_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <arch/irq.h>
+
+#include "riscv_internal.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#define setbits(bs, a)     modifyreg32(a, 0, bs)
+#define resetbits(bs, a)   modifyreg32(a, bs, 0)
+
+#endif
+
+#endif /* __ARCH_RISCV_SRC_ESP32C6_ESP32C6_H */

arch/risc-v/src/esp32c6/esp32c6_allocateheap.c

@@ -0,0 +1,92 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_allocateheap.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+#include <sys/types.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/mm/mm.h>
+#include <arch/board/board.h>
+
+#include "esp32c6.h"
+#include "hardware/esp32c6_rom_layout.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ *   This function will be called to dynamically set aside the heap region.
+ *
+ *   For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and
+ *   user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
+ *   size of the unprotected, user-space heap.
+ *
+ *   If a protected kernel-space heap is provided, the kernel heap must be
+ *   allocated (and protected) by an analogous up_allocate_kheap().
+ *
+ ****************************************************************************/
+
+void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
+{
+  /* These values come from the linker scripts (legacy_sections.ld and
+   * flat_memory.ld).
+   * Check boards/risc-v/esp32c6.
+   */
+
+  extern uint8_t _sheap[];
+  extern const struct esp32c6_rom_layout_s *ets_rom_layout_p;
+
+  board_autoled_on(LED_HEAPALLOCATE);
+
+  *heap_start = _sheap;
+  *heap_size  = ets_rom_layout_p->dram0_rtos_reserved_start -
+                (uintptr_t)_sheap;
+}
+
+/****************************************************************************
+ * Name: riscv_addregion
+ *
+ * Description:
+ *   RAM may be added in non-contiguous chunks.  This routine adds all chunks
+ *   that may be used for heap.
+ *
+ ****************************************************************************/
+
+#if CONFIG_MM_REGIONS > 1
+void riscv_addregion(void)
+{
+}
+#endif
+

arch/risc-v/src/esp32c6/esp32c6_attr.h

@@ -0,0 +1,53 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_attr.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C6_ESP32C6_ATTR_H
+#define __ARCH_RISCV_SRC_ESP32C6_ESP32C6_ATTR_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Forces code into IRAM instead of flash */
+
+#define IRAM_ATTR __attribute__((section(".iram1")))
+
+/* Forces data into DRAM instead of flash */
+
+#define DRAM_ATTR __attribute__((section(".dram1")))
+
+/* Forces code into RTC fast memory */
+
+#define RTC_IRAM_ATTR __attribute__((section(".rtc.text")))
+
+/* Forces data into RTC slow memory
+ * Any variable marked with this attribute will keep its value
+ * during a deep sleep / wake cycle.
+ */
+
+#define RTC_DATA_ATTR __attribute__((section(".rtc.data")))
+
+/* Forces read-only data into RTC slow memory
+ * Makes constant data available to RTC wake stubs.
+ */
+
+#define RTC_RODATA_ATTR __attribute__((section(".rtc.rodata")))
+
+#endif /* __ARCH_RISCV_SRC_ESP32C6_ESP32C6_ATTR_H */

arch/risc-v/src/esp32c6/esp32c6_clockconfig.c

@@ -0,0 +1,288 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#include "riscv_internal.h"
+#include "hardware/esp32c6_soc.h"
+#include "hardware/esp32c6_pcr.h"
+
+#include "esp32c6_attr.h"
+#include "esp32c6_clockconfig.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef MIN
+  #define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+enum cpu_clksrc_e
+{
+  XTAL_CLK,
+  PLL_CLK,
+  FOSC_CLK
+};
+
+/****************************************************************************
+ * ROM Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ets_update_cpu_frequency
+ *
+ * Description:
+ *   Set the real CPU ticks per us to the ets, so that ets_delay_us will be
+ *   accurate. Call this function when CPU frequency is changed.
+ *
+ * Input Parameters:
+ *   ticks_per_us - CPU ticks per us.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
+
+/****************************************************************************
+ * Name: ets_get_cpu_frequency
+ *
+ * Description:
+ *   Get the real CPU ticks per us to the ets.
+ *   This function do not return real CPU ticks per us, just the record in
+ *   ets. It can be used to check with the real CPU frequency.
+ *
+ * Input Parameters:
+ *   None.
+ *
+ * Returned Value:
+ *   CPU ticks per us record in ets.
+ *
+ ****************************************************************************/
+
+extern uint32_t ets_get_cpu_frequency(void);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c6_cpuclksrc
+ *
+ * Description:
+ *   Select a clock source for CPU clock.
+ *
+ * Input Parameters:
+ *   src - Any source from cpu_clksrc_e.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void esp32c6_cpuclksrc(enum cpu_clksrc_e src)
+{
+  uint32_t value;
+  value = VALUE_TO_FIELD(src, PCR_SOC_CLK_SEL);
+  modifyreg32(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL_M, value);
+}
+
+/****************************************************************************
+ * Name: esp32c6_cpudiv
+ *
+ * Description:
+ *   Select a divider for the CPU clk.
+ *   NOTE: The divider is not necessarily the real divisor. See TRM for the
+ *   equivalences.
+ *
+ * Input Parameters:
+ *   divider - A value between 3 to 6.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void esp32c6_cpudiv(uint8_t divider)
+{
+  uint32_t value = (divider / 3) - 1;
+  bool force_120m = (divider == 4) ? 1 : 0;
+  value = VALUE_TO_FIELD(value, PCR_CPU_HS_DIV_NUM);
+  modifyreg32(PCR_CPU_FREQ_CONF_REG, PCR_CPU_HS_DIV_NUM_M, value);
+  value = VALUE_TO_FIELD(force_120m, PCR_CPU_HS_120M_FORCE);
+  modifyreg32(PCR_CPU_FREQ_CONF_REG, PCR_CPU_HS_120M_FORCE_M, value);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name:  esp32c6_update_cpu_freq
+ *
+ * Description:
+ *   Set the real CPU ticks per us to the ets, so that ets_delay_us
+ *   will be accurate. Call this function when CPU frequency is changed.
+ *
+ * Input Parameters:
+ *   ticks_per_us - CPU ticks per us
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR esp32c6_update_cpu_freq(uint32_t ticks_per_us)
+{
+  /* Update scale factors used by esp_rom_delay_us */
+
+  ets_update_cpu_frequency(ticks_per_us);
+}
+
+/****************************************************************************
+ * Name: esp32c6_set_cpu_freq
+ *
+ * Description:
+ *   Switch to one of PLL-based frequencies.
+ *
+ * Input Parameters:
+ *   cpu_freq_mhz - Target CPU frequency
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR esp32c6_set_cpu_freq(int cpu_freq_mhz)
+{
+  switch (cpu_freq_mhz)
+    {
+      case 80:
+        /* 80 MHz is obtained from the 480 MHz PLL.
+         * In this case CPU_CLK = PLL_CLK / 6.  Config the PLL as 480 MHz
+         * with a 6 divider and set the source clock as PLL_CLK.
+         */
+
+        esp32c6_cpudiv(6);
+        break;
+
+      case 120:
+        /* 120 MHz is obtained from the 480 MHz PLL.
+         * In this case CPU_CLK = PLL_CLK / 4.  Config the PLL as 480 MHz
+         * with a 4 divider and set the source clock as PLL_CLK.
+         */
+
+        esp32c6_cpudiv(4);
+        break;
+
+      case 160:
+        /* 160 MHz is obtained from the 480 MHz PLL.
+         * In this case CPU_CLK = PLL_CLK / 3.  Config the PLL as 480 MHz
+         * with a 3 divider and set the source clock as PLL_CLK.
+         */
+
+        esp32c6_cpudiv(3);
+        break;
+
+      default:
+
+        /* Unsupported clock config. */
+
+        return;
+    }
+
+  esp32c6_cpuclksrc(PLL_CLK);
+  esp32c6_update_cpu_freq(cpu_freq_mhz);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c6_clockconfig
+ *
+ * Description:
+ *   Called to initialize the ESP32-C6. This does whatever setup is needed to
+ *   put the SoC in a usable state.
+ *
+ * Input Parameters:
+ *   None.
+ *
+ * Returned Value:
+ *   None.
+ *
+ ****************************************************************************/
+
+void esp32c6_clockconfig(void)
+{
+  /* Configure the CPU frequency */
+
+  esp32c6_set_cpu_freq(CONFIG_ESP32C6_CPU_FREQ_MHZ);
+}
+
+/****************************************************************************
+ * Name:  esp_clk_cpu_freq
+ *
+ * Description:
+ *   Get CPU frequency
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   CPU frequency
+ *
+ ****************************************************************************/
+
+int IRAM_ATTR esp_clk_cpu_freq(void)
+{
+  return (int)ets_get_cpu_frequency() * MHZ;
+}
+
+/****************************************************************************
+ * Name:  esp_clk_apb_freq
+ *
+ * Description:
+ *   Return current APB clock frequency.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   APB clock frequency, in Hz
+ *
+ ****************************************************************************/
+
+int IRAM_ATTR esp_clk_apb_freq(void)
+{
+  return MIN(ets_get_cpu_frequency(), 80) * MHZ;
+}

arch/risc-v/src/esp32c6/esp32c6_clockconfig.h

@@ -0,0 +1,119 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_clockconfig.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C6_ESP32C6_CLOCKCONFIG_H
+#define __ARCH_RISCV_SRC_ESP32C6_ESP32C6_CLOCKCONFIG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name:  esp32c6_update_cpu_freq
+ *
+ * Description:
+ *   Set the real CPU ticks per us to the ets, so that ets_delay_us
+ *   will be accurate. Call this function when CPU frequency is changed.
+ *
+ * Input Parameters:
+ *   ticks_per_us - CPU ticks per us
+ *
+ * Returned Value:
+ *   None.
+ *
+ ****************************************************************************/
+
+void esp32c6_update_cpu_freq(uint32_t ticks_per_us);
+
+/****************************************************************************
+ * Name: esp32c6_set_cpu_freq
+ *
+ * Description:
+ *   Switch to one of PLL-based frequencies.
+ *   Current frequency can be XTAL or PLL.
+ *
+ * Input Parameters:
+ *   cpu_freq_mhz - new CPU frequency
+ *
+ * Returned Value:
+ *   None.
+ *
+ ****************************************************************************/
+
+void esp32c6_set_cpu_freq(int cpu_freq_mhz);
+
+/****************************************************************************
+ * Name: esp32c6_clockconfig
+ *
+ * Description:
+ *   Called to initialize the ESP32-C6. This does whatever setup is needed to
+ *   put the SoC in a usable state.
+ *
+ * Input Parameters:
+ *   None.
+ *
+ * Returned Value:
+ *   None.
+ *
+ ****************************************************************************/
+
+void esp32c6_clockconfig(void);
+
+/****************************************************************************
+ * Name:  esp_clk_cpu_freq
+ *
+ * Description:
+ *   Get the current CPU frequency.
+ *
+ * Input Parameters:
+ *   None.
+ *
+ * Returned Value:
+ *   CPU frequency in Hz.
+ *
+ ****************************************************************************/
+
+int esp_clk_cpu_freq(void);
+
+/****************************************************************************
+ * Name:  esp_clk_apb_freq
+ *
+ * Description:
+ *   Return current APB clock frequency.
+ *
+ * Input Parameters:
+ *   None.
+ *
+ * Returned Value:
+ *   APB clock frequency in Hz.
+ *
+ ****************************************************************************/
+
+int esp_clk_apb_freq(void);
+
+#endif /* __ARCH_RISCV_SRC_ESP32C6_ESP32C6_CLOCKCONFIG_H */

arch/risc-v/src/esp32c6/esp32c6_config.h

@@ -0,0 +1,65 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_config.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C6_ESP32C6_CONFIG_H
+#define __ARCH_RISCV_SRC_ESP32C6_ESP32C6_CONFIG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/chip/chip.h>
+#include <arch/board/board.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* UARTs ********************************************************************/
+
+/* Are any UARTs enabled? */
+
+#undef HAVE_UART_DEVICE
+#if defined(CONFIG_ESP32C6_UART0) || defined(CONFIG_ESP32C6_UART1)
+#  define HAVE_UART_DEVICE 1 /* Flag to indicate a UART has been selected */
+#endif
+
+/* Serial Console ***********************************************************/
+
+/* Is there a serial console?  There should be no more than one defined.  It
+ * could be on any UARTn. n E {0,1}
+ */
+
+#undef HAVE_SERIAL_CONSOLE
+#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESP32C6_UART0)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  define HAVE_SERIAL_CONSOLE 1
+#  define CONSOLE_UART 1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESP32C6_UART1)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  define HAVE_SERIAL_CONSOLE 1
+#  define CONSOLE_UART 1
+#else
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#endif
+
+#endif /* __ARCH_XTENSA_SRC_ESP32C6_ESP32C6_CONFIG_H */

arch/risc-v/src/esp32c6/esp32c6_head.S

@@ -0,0 +1,77 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_head.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/irq.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Public Symbols
+ ****************************************************************************/
+
+  .global  __start
+
+/****************************************************************************
+ * Section: .text
+ ****************************************************************************/
+
+  .section .text
+
+/****************************************************************************
+ * Name: __start
+ ****************************************************************************/
+
+__start:
+  .option push
+  .option norelax
+
+  /* Set stack pointer to the idle thread stack */
+
+  lui  sp, %hi(ESP32C6_IDLESTACK_TOP)
+  addi sp, sp, %lo(ESP32C6_IDLESTACK_TOP)
+
+  /* Set gp pointer */
+
+  la   gp, __global_pointer$
+
+  /* Disable all interrupts (i.e. timer, external) in mstatus */
+
+  csrw mstatus, zero
+
+  .option pop
+
+  /* Initialize the Machine Trap-Vector */
+
+  lui  t0, %hi(_vector_table)
+  addi t0, t0, %lo(_vector_table)
+  csrw  mtvec, t0
+
+  /* Jump to __esp32c6_start */
+
+  jal  x1, __esp32c6_start
+
+  /* We shouldn't return from __esp32c6_start */
+
+  ret

arch/risc-v/src/esp32c6/esp32c6_idle.c

@@ -0,0 +1,73 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_idle.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/power/pm.h>
+
+#include "esp32c6.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idle
+ *
+ * Description:
+ *   up_idle() is the logic that will be executed when their is no other
+ *   ready-to-run task.  This is processor idle time and will continue until
+ *   some interrupt occurs to cause a context switch from the idle task.
+ *
+ *   Processing in this state may be processor-specific. e.g., this is where
+ *   power management operations might be performed.
+ *
+ ****************************************************************************/
+
+void up_idle(void)
+{
+#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
+  /* If the system is idle and there are no timer interrupts, then process
+   * "fake" timer interrupts. Hopefully, something will wake up.
+   */
+
+  nxsched_process_timer();
+#else
+  /* This would be an appropriate place to put some MCU-specific logic to
+   * sleep in a reduced power mode until an interrupt occurs to save power
+   */
+
+  asm("WFI");
+
+#endif
+}

arch/risc-v/src/esp32c6/esp32c6_irq.c

@@ -0,0 +1,592 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_irq.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "riscv_internal.h"
+
+#include "esp32c6.h"
+#include "esp32c6_attr.h"
+
+#include "esp32c6_irq.h"
+#include "hardware/esp32c6_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define ESP32C6_DEFAULT_INT_THRESHOLD   1
+
+#define IRQ_UNMAPPED            0xff
+
+/* CPU interrupts to peripheral mapping:
+ *
+ * Encoding: EPPPPPP
+ *  E: CPU interrupt status (0 = Disabled, 1 = Enabled).
+ *  P: Attached peripheral.
+ */
+
+#define CPUINT_UNASSIGNED       0x7f
+#define CPUINT_GETEN(m)         (((m) & 0x80) >> 0x07)
+#define CPUINT_GETIRQ(m)        ((m) & 0x7f)
+#define CPUINT_ASSIGN(c)        (((c) & 0x7f) | 0x80)
+#define CPUINT_DISABLE(m)       ((m) & 0x7f)
+#define CPUINT_ENABLE(m)        ((m) | 0x80)
+
+/* CPU interrupts can be detached from any peripheral source by setting the
+ * map register to an internal CPU interrupt (1~31).
+ */
+
+#define NO_CPUINT               0
+
+/* Priority range is 1-15 */
+
+#define ESP32C6_MIN_PRIORITY    1
+#define ESP32C6_MAX_PRIORITY    15
+#define ESP32C6_PRIO_INDEX(p)   ((p) - ESP32C6_MIN_PRIORITY)
+
+#define ESP32C6_WIFI_RESERVE_INT  (BIT(1))
+#define ESP32C6_BLE_RESERVE_INT   (BIT(5) | BIT(8))
+#define ESP32C6_DISABLED_INT      (BIT(6))
+#define ESP32C6_INVALID_INT       (BIT(0) | BIT(3) | BIT(4) | BIT(7))
+
+#define ESP32C6_RESERVE_INT       (ESP32C6_WIFI_RESERVE_INT | \
+                                   ESP32C6_BLE_RESERVE_INT | \
+                                   ESP32C6_DISABLED_INT | \
+                                   ESP32C6_INVALID_INT)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
+
+static uint8_t g_cpu_intmap[ESP32C6_NCPUINTS];
+
+static volatile uint8_t g_irqmap[NR_IRQS];
+
+/* Bitsets for free, unallocated CPU interrupts available to peripheral
+ * devices.
+ */
+
+static uint32_t g_cpu_freeints = ESP32C6_CPUINT_PERIPHSET &
+                                 (~ESP32C6_RESERVE_INT);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name:  esp32c6_getcpuint
+ *
+ * Description:
+ *   Get a free CPU interrupt for a peripheral device.  This function will
+ *   not ignore all of the pre-allocated CPU interrupts for internal
+ *   devices.
+ *
+ * Returned Value:
+ *   On success, a CPU interrupt number is returned.
+ *   A negated errno is returned on failure.
+ *
+ ****************************************************************************/
+
+static int esp32c6_getcpuint(void)
+{
+  uint32_t bitmask;
+  uint32_t intset;
+  int cpuint = 0;
+  int ret = -ENOMEM;
+
+  /* Check if there are CPU interrupts with the requested properties
+   * available.
+   */
+
+  intset = g_cpu_freeints;
+  if (intset != 0)
+    {
+      /* Skip over initial unavailable CPU interrupts quickly in groups
+       * of 8 interrupt.
+       */
+
+      for (cpuint = 0, bitmask = 0xff;
+           cpuint <= ESP32C6_CPUINT_MAX && (intset & bitmask) == 0;
+           cpuint += 8, bitmask <<= 8);
+
+      /* Search for an unallocated CPU interrupt number in the remaining
+       * intset.
+       */
+
+      for (; cpuint <= ESP32C6_CPUINT_MAX; cpuint++)
+        {
+          /* If the bit corresponding to the CPU interrupt is '1', then
+           * that CPU interrupt is available.
+           */
+
+          bitmask = 1ul << cpuint;
+          if ((intset & bitmask) != 0)
+            {
+              /* Got it! */
+
+              g_cpu_freeints &= ~bitmask;
+              ret = cpuint;
+              break;
+            }
+        }
+    }
+
+  /* Enable the CPU interrupt now.  The interrupt is still not attached
+   * to any peripheral and thus has no effect.
+   */
+
+  if (ret >= 0)
+    {
+      setbits(1 << cpuint, PLIC_MXINT_ENABLE_REG);
+    }
+
+  return cpuint;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+  int periphid;
+
+  /* Indicate that no peripheral interrupts are assigned to CPU interrupts */
+
+  for (int i = 0; i < NR_IRQS; i++)
+    {
+      g_irqmap[i] = IRQ_UNMAPPED;
+    }
+
+  /* Clear all peripheral interrupts from "bootloader" */
+
+  for (periphid = 0; periphid < ESP32C6_NPERIPHERALS; periphid++)
+    {
+      putreg32(0, DR_REG_INTERRUPT_MATRIX_BASE + periphid * 4);
+    }
+
+  /* Set CPU interrupt threshold level */
+
+  putreg32(ESP32C6_DEFAULT_INT_THRESHOLD, PLIC_MXINT_THRESH_REG);
+
+  /* Attach the common interrupt handler */
+
+  riscv_exception_attach();
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+
+  /* And finally, enable interrupts */
+
+  up_irq_enable();
+#endif
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ *   Enable the interrupt specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+  int cpuint = g_irqmap[irq];
+  irqstate_t irqstate;
+
+  irqinfo("irq=%d | cpuint=%d\n", irq, cpuint);
+
+  DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32C6_CPUINT_MAX);
+
+  irqstate = enter_critical_section();
+  setbits(1 << cpuint, PLIC_MXINT_ENABLE_REG);
+  SET_CSR(mie, 1 << cpuint);
+  leave_critical_section(irqstate);
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ *   Disable the interrupt specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+  int cpuint = g_irqmap[irq];
+
+  irqinfo("irq=%d | cpuint=%d \n", irq, cpuint);
+
+  DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32C6_CPUINT_MAX);
+
+  if (cpuint == IRQ_UNMAPPED)
+    {
+      /* This interrupt is already disabled. */
+
+      return;
+    }
+  else
+    {
+      irqstate_t irqstate;
+
+      g_cpu_intmap[cpuint] = CPUINT_DISABLE(g_cpu_intmap[cpuint]);
+
+      irqstate = enter_critical_section();
+      CLEAR_CSR(mie, 1 << cpuint);
+      resetbits(1 << cpuint, PLIC_MXINT_ENABLE_REG);
+      leave_critical_section(irqstate);
+    }
+}
+
+/****************************************************************************
+ * Name: esp32c6_free_cpuint
+ *
+ * Description:
+ *   Free CPU interrupt.
+ *
+ * Input Parameters:
+ *   periphid - Peripheral ID.
+ *
+ * Returned Value:
+ *   None.
+ *
+ ****************************************************************************/
+
+void esp32c6_free_cpuint(uint8_t periphid)
+{
+  irqstate_t irqstate;
+  uint8_t cpuint;
+
+  DEBUGASSERT(periphid < ESP32C6_NPERIPHERALS);
+
+  irqstate = enter_critical_section();
+
+  /* Get the CPU interrupt ID mapped to this peripheral. */
+
+  cpuint = getreg32(DR_REG_INTERRUPT_MATRIX_BASE + periphid * 4) & 0x1f;
+
+  irqinfo("INFO: irq[%" PRIu8 "]=%" PRIu8 "\n", periphid, cpuint);
+
+  if (cpuint != 0)
+    {
+      /* Undo the allocation process:
+       *   1.  Unmap the peripheral from the CPU interrupt ID.
+       *   2.  Reset the interrupt type.
+       *   3.  Reset the interrupt priority.
+       *   4.  Clear the CPU interrupt.
+       */
+
+      DEBUGASSERT(g_cpu_intmap[cpuint] != CPUINT_UNASSIGNED);
+
+      g_cpu_intmap[cpuint] = CPUINT_UNASSIGNED;
+      putreg32(0, DR_REG_INTERRUPT_MATRIX_BASE + periphid * 4);
+      resetbits(1 << cpuint, PLIC_MXINT_TYPE_REG);
+      putreg32(0, PLIC_MXINT0_PRI_REG + cpuint * 4);
+      resetbits(1 << cpuint, PLIC_MXINT_ENABLE_REG);
+    }
+
+  leave_critical_section(irqstate);
+}
+
+/****************************************************************************
+ * Name:  esp32c6_cpuint_initialize
+ *
+ * Description:
+ *   Initialize CPU interrupts
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; A negated errno value is returned on
+ *   any failure.
+ *
+ ****************************************************************************/
+
+int esp32c6_cpuint_initialize(void)
+{
+  /* Disable all CPU interrupts on this CPU */
+
+  for (int i = 0; i < ESP32C6_NCPUINTS; i++)
+    {
+      putreg32(0, PLIC_MXINT0_PRI_REG + i * 4);
+    }
+
+  /* Detach all interrupts from peripheral sources */
+
+  for (int i = 0; i < ESP32C6_NPERIPHERALS; i++)
+    {
+      putreg32(0, DR_REG_INTERRUPT_MATRIX_BASE + i * 4);
+    }
+
+  /* Indicate that no peripheral interrupts are assigned to CPU interrupts */
+
+  memset(g_cpu_intmap, CPUINT_UNASSIGNED, ESP32C6_NCPUINTS);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: esp32c6_bind_irq
+ *
+ * Description:
+ *   Bind IRQ and resource with given parameters.
+ *
+ * Input Parameters:
+ *   cpuint    - CPU interrupt ID
+ *   periphid  - Peripheral ID
+ *   prio      - Interrupt priority
+ *   flags     - Interrupt flags
+ *
+ * Returned Value:
+ *   None.
+ *
+ ****************************************************************************/
+
+void esp32c6_bind_irq(uint8_t cpuint, uint8_t periphid, uint8_t prio,
+                      uint32_t flags)
+{
+  /* Disable the CPU interrupt. */
+
+  resetbits(1 << cpuint, PLIC_MXINT_ENABLE_REG);
+
+  /* Set the interrupt priority. */
+
+  putreg32(prio, PLIC_MXINT0_PRI_REG + cpuint * 4);
+
+  /* Set the interrupt type (Edge or Level). */
+
+  if (flags & ESP32C6_INT_EDGE)
+    {
+      setbits(1 << cpuint, PLIC_MXINT_TYPE_REG);
+    }
+  else
+    {
+      resetbits(1 << cpuint, PLIC_MXINT_TYPE_REG);
+    }
+
+  /* Map the CPU interrupt ID to the peripheral. */
+
+  putreg32(cpuint, DR_REG_INTERRUPT_MATRIX_BASE + periphid * 4);
+}
+
+/****************************************************************************
+ * Name:  esp32c6_setup_irq
+ *
+ * Description:
+ *   This function sets up the IRQ. It allocates a CPU interrupt of the given
+ *   priority and type and attaches it to the given peripheral.
+ *
+ * Input Parameters:
+ *   periphid - The peripheral number from irq.h to be assigned to
+ *              a CPU interrupt.
+ *   priority - Interrupt's priority (1 - 15).
+ *   type     - Interrupt's type (level or edge).
+ *
+ * Returned Value:
+ *   The allocated CPU interrupt on success, a negated errno value on
+ *   failure.
+ *
+ ****************************************************************************/
+
+int esp32c6_setup_irq(int periphid, int priority, int type)
+{
+  irqstate_t irqstate;
+  int irq;
+  int cpuint;
+
+  irqinfo("periphid = %d\n", periphid);
+
+  irqstate = enter_critical_section();
+
+  /* Setting up an IRQ includes the following steps:
+   *    1. Allocate a CPU interrupt.
+   *    2. Attach that CPU interrupt to the peripheral.
+   *    3. Map the CPU interrupt to the IRQ to ease searching later.
+   */
+
+  cpuint = esp32c6_getcpuint();
+  if (cpuint < 0)
+    {
+      irqerr("Unable to allocate CPU interrupt for priority=%d and type=%d",
+             priority, type);
+      leave_critical_section(irqstate);
+
+      return cpuint;
+    }
+
+  irq = ESP32C6_PERIPH2IRQ(periphid);
+
+  DEBUGASSERT(periphid >= 0 && periphid < ESP32C6_NPERIPHERALS);
+  DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32C6_CPUINT_MAX);
+  DEBUGASSERT(g_cpu_intmap[cpuint] == CPUINT_UNASSIGNED);
+
+  g_cpu_intmap[cpuint] = CPUINT_ASSIGN(periphid + ESP32C6_IRQ_FIRSTPERIPH);
+  g_irqmap[irq] = cpuint;
+
+  esp32c6_bind_irq(cpuint, periphid, priority, type);
+
+  leave_critical_section(irqstate);
+
+  return cpuint;
+}
+
+/****************************************************************************
+ * Name:  esp32c6_teardown_irq
+ *
+ * Description:
+ *   This function undoes the operations done by esp32c6_setup_irq.
+ *   It detaches a peripheral interrupt from a CPU interrupt and frees the
+ *   CPU interrupt.
+ *
+ * Input Parameters:
+ *   periphid - The peripheral number from irq.h to be detached from the
+ *              CPU interrupt.
+ *   cpuint   - The CPU interrupt from which the peripheral interrupt will
+ *              be detached.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void esp32c6_teardown_irq(int periphid, int cpuint)
+{
+  irqstate_t irqstate;
+  uintptr_t regaddr;
+  int irq;
+
+  irqstate = enter_critical_section();
+
+  /* Tearing down an IRQ includes the following steps:
+   *   1. Free the previously allocated CPU interrupt.
+   *   2. Detach the interrupt from the peripheral.
+   *   3. Unmap the IRQ from the IRQ-to-cpuint map.
+   */
+
+  esp32c6_free_cpuint(cpuint);
+
+  irq = ESP32C6_PERIPH2IRQ(periphid);
+
+  DEBUGASSERT(periphid >= 0 && periphid < ESP32C6_NPERIPHERALS);
+
+  DEBUGASSERT(g_cpu_intmap[cpuint] != CPUINT_UNASSIGNED);
+  g_cpu_intmap[cpuint] = CPUINT_UNASSIGNED;
+  g_irqmap[irq] = IRQ_UNMAPPED;
+  regaddr = CORE_MAP_REGADDR(periphid);
+
+  putreg32(NO_CPUINT, regaddr);
+
+  leave_critical_section(irqstate);
+}
+
+/****************************************************************************
+ * Name: riscv_dispatch_irq
+ *
+ * Description:
+ *   Process interrupt and its callback function.
+ *
+ * Input Parameters:
+ *   mcause - RISC-V "mcause" register.
+ *   regs   - Saved registers reference.
+ *
+ * Returned Value:
+ *   None.
+ *
+ ****************************************************************************/
+
+IRAM_ATTR uintptr_t *riscv_dispatch_irq(uintptr_t mcause, uintptr_t *regs)
+{
+  int irq;
+  uint8_t cpuint = mcause & RISCV_IRQ_MASK;
+  bool is_irq = (RISCV_IRQ_BIT & mcause) != 0;
+
+  irqinfo("INFO: mcause=%08" PRIXPTR "\n", mcause);
+
+  DEBUGASSERT(cpuint <= ESP32C6_CPUINT_MAX);
+
+  irqinfo("INFO: cpuint=%" PRIu8 "\n", cpuint);
+
+  if (is_irq)
+    {
+      /* Clear edge interrupts. */
+
+      putreg32(1 << cpuint, PLIC_MXINT_CLEAR_REG);
+      irq = CPUINT_GETIRQ(g_cpu_intmap[cpuint]);
+    }
+  else
+    {
+      /* It's exception */
+
+      irq = mcause;
+    }
+
+  irqinfo("INFO: IRQ=%d\n", irq);
+
+  regs = riscv_doirq(irq, regs);
+
+  /* Toggle the bit back to zero. */
+
+  if (is_irq)
+    {
+      putreg32(0, PLIC_MXINT_CLEAR_REG);
+    }
+
+  return regs;
+}
+
+/****************************************************************************
+ * Name: up_irq_enable
+ *
+ * Description:
+ *   Return the current interrupt state and enable interrupts
+ *
+ ****************************************************************************/
+
+irqstate_t up_irq_enable(void)
+{
+  irqstate_t flags;
+
+  /* Read mstatus & set machine interrupt enable (MIE) in mstatus */
+
+  flags = READ_AND_SET_CSR(mstatus, MSTATUS_MIE);
+  return flags;
+}

arch/risc-v/src/esp32c6/esp32c6_irq.h

@@ -0,0 +1,146 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C6_ESP32C6_IRQ_H
+#define __ARCH_RISCV_SRC_ESP32C6_ESP32C6_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* CPU interrupt types. */
+
+#define ESP32C6_INT_LEVEL           (0 << 0)
+#define ESP32C6_INT_EDGE            (1 << 0)
+
+#define ESP32C6_INT_PRIO_MIN        1
+#define ESP32C6_INT_PRIO_MAX        7
+
+#define ESP32C6_INT_PRIO_DEF        1
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c6_bind_irq
+ *
+ * Description:
+ *   Bind IRQ and resource with given parameters.
+ *
+ * Input Parameters:
+ *   cpuint    - CPU interrupt ID
+ *   periphid  - Peripheral ID
+ *   prio      - Interrupt priority
+ *   flags     - Interrupt flags
+ *
+ * Returned Value:
+ *   None.
+ *
+ ****************************************************************************/
+
+void esp32c6_bind_irq(uint8_t cpuint, uint8_t periphid, uint8_t prio,
+                      uint32_t flags);
+
+/****************************************************************************
+ * Name:  esp32c6_cpuint_initialize
+ *
+ * Description:
+ *   Initialize CPU interrupts
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; A negated errno value is returned on
+ *   any failure.
+ *
+ ****************************************************************************/
+
+int esp32c6_cpuint_initialize(void);
+
+/****************************************************************************
+ * Name:  esp32c6_setup_irq
+ *
+ * Description:
+ *   This function sets up the IRQ. It allocates a CPU interrupt of the given
+ *   priority and type and attaches it to the given peripheral.
+ *
+ * Input Parameters:
+ *   periphid - The peripheral number from irq.h to be assigned to
+ *              a CPU interrupt.
+ *   priority - Interrupt's priority (1 - 5).
+ *   type     - Interrupt's type (level or edge).
+ *
+ * Returned Value:
+ *   The allocated CPU interrupt on success, a negated errno value on
+ *   failure.
+ *
+ ****************************************************************************/
+
+int esp32c6_setup_irq(int periphid, int priority, int type);
+
+/****************************************************************************
+ * Name:  esp32c6_teardown_irq
+ *
+ * Description:
+ *   This function undoes the operations done by esp32c6_setup_irq.
+ *   It detaches a peripheral interrupt from a CPU interrupt and frees the
+ *   CPU interrupt.
+ *
+ * Input Parameters:
+ *   periphid - The peripheral number from irq.h to be detached from the
+ *              CPU interrupt.
+ *   cpuint   - The CPU interrupt from which the peripheral interrupt will
+ *              be detached.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void esp32c6_teardown_irq(int periphid, int cpuint);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_ESP32C6_ESP32C6_IRQ_H */

arch/risc-v/src/esp32c6/esp32c6_lowputc.c

@@ -0,0 +1,510 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#include "riscv_internal.h"
+#include "chip.h"
+
+#include "hardware/esp32c6_uart.h"
+#include "esp32c6_lowputc.h"
+#include "esp32c6_config.h"
+#include "hardware/esp32c6_soc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32C6_UART0
+
+struct esp32c6_uart_s g_uart0_config =
+{
+  .base = REG_UART_BASE(0),
+  .periph = ESP32C6_UART0_PERIPH,
+  .id = 0,
+  .irq = ESP32C6_IRQ_UART0,
+  .baud = CONFIG_UART0_BAUD,
+  .bits = CONFIG_UART0_BITS,
+  .parity = CONFIG_UART0_PARITY,
+  .stop_b2 =  CONFIG_UART0_2STOP,
+  .int_pri = 1
+};
+
+#endif /* CONFIG_ESP32C6_UART0 */
+
+#ifdef CONFIG_ESP32C6_UART1
+
+struct esp32c6_uart_s g_uart1_config =
+{
+  .base = REG_UART_BASE(1),
+  .periph = ESP32C6_UART1_PERIPH,
+  .id = 1,
+  .irq = ESP32C6_IRQ_UART1,
+  .baud = CONFIG_UART1_BAUD,
+  .bits = CONFIG_UART1_BITS,
+  .parity = CONFIG_UART1_PARITY,
+  .stop_b2 =  CONFIG_UART1_2STOP,
+  .int_pri = 1
+};
+
+#endif /* CONFIG_ESP32C6_UART1 */
+
+#endif /* HAVE_UART_DEVICE */
+
+#if 0
+#ifdef HAVE_SERIAL_CONSOLE
+#  if defined(CONFIG_UART0_SERIAL_CONSOLE)
+
+static struct esp32c6_uart_s g_console_config =
+{
+  .base = REG_UART_BASE(0),
+  .id = 0,
+  .irq = -1, /* TODO */
+  .baud = CONFIG_UART0_BAUD,
+  .bits = CONFIG_UART0_BITS,
+  .parity = CONFIG_UART0_PARITY,
+  .stop_b2 =  CONFIG_UART0_2STOP,
+  .int_pri = 1
+};
+
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+
+static struct esp32c6_uart_s g_uart1_config =
+{
+  .base = REG_UART_BASE(1),
+  .id = 1,
+  .irq = -1, /* TODO */
+  .baud = CONFIG_UART1_BAUD,
+  .bits = CONFIG_UART1_BITS,
+  .parity = CONFIG_UART1_PARITY,
+  .stop_b2 =  CONFIG_UART1_2STOP,
+  .int_pri = 1
+};
+#endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#endif /* HAVE_SERIAL_CONSOLE */
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_reset_core
+ *   Reset both TX and RX core
+ ****************************************************************************/
+
+void esp32c6_lowputc_reset_core(const struct esp32c6_uart_s *conf)
+{
+  uint32_t set_bit = 1 << UART_RST_CORE_S;
+  modifyreg32(UART_CLK_CONF_REG(conf->id), UART_RST_CORE_M, set_bit);
+  modifyreg32(UART_CLK_CONF_REG(conf->id), UART_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_enable_sclk
+ *    Enable clock for whole core
+ ****************************************************************************/
+
+void esp32c6_lowputc_enable_sclk(const struct esp32c6_uart_s *conf)
+{
+  modifyreg32(UART_CLK_CONF_REG(conf->id), UART_SCLK_EN_M,
+              1 << UART_SCLK_EN_S);
+  modifyreg32(UART_CLK_CONF_REG(conf->id), UART_RX_SCLK_EN_M,
+              1 << UART_RX_SCLK_EN_S);
+  modifyreg32(UART_CLK_CONF_REG(conf->id), UART_TX_SCLK_EN_M,
+              1 << UART_TX_SCLK_EN_S);
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_disable_sclk
+ *    Disable clock for whole core
+ ****************************************************************************/
+
+void esp32c6_lowputc_disable_sclk(const struct esp32c6_uart_s *conf)
+{
+  modifyreg32(UART_CLK_CONF_REG(conf->id), UART_SCLK_EN_M, 0);
+  modifyreg32(UART_CLK_CONF_REG(conf->id), UART_RX_SCLK_EN_M, 0);
+  modifyreg32(UART_CLK_CONF_REG(conf->id), UART_TX_SCLK_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_set_sclk
+ *    Set a source clock for UART
+ *    APB_CLK  = 1  80 MHz
+ *    CLK_8    = 2  8 MHz
+ *    XTAL_CLK = 3
+ ****************************************************************************/
+
+void esp32c6_lowputc_set_sclk(const struct esp32c6_uart_s *conf, enum
+                              uart_sclk source)
+{
+  uint32_t clk = (uint32_t)source << UART_SCLK_SEL_S;
+  modifyreg32(UART_CLK_CONF_REG(conf->id), UART_SCLK_SEL_M, clk);
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_get_sclk
+ *    Get the source clock for UART
+ ****************************************************************************/
+
+uint32_t esp32c6_lowputc_get_sclk(const struct esp32c6_uart_s * conf)
+{
+  uint32_t clk_conf_reg;
+  uint32_t ret = -ENODATA;
+  clk_conf_reg   = getreg32(UART_CLK_CONF_REG(conf->id));
+  clk_conf_reg  &= UART_SCLK_SEL_M;
+  clk_conf_reg >>= UART_SCLK_SEL_S;
+  switch (clk_conf_reg)
+    {
+      case 1:
+        ret = APB_CLK_FREQ;
+        break;
+      case 2:
+        ret = RTC_CLK_FREQ;
+        break;
+      case 3:
+        ret = XTAL_CLK_FREQ;
+        break;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_baud
+ *    Set the baud rate
+ ****************************************************************************/
+
+void esp32c6_lowputc_baud(const struct esp32c6_uart_s * conf)
+{
+  const int sclk_div = 1;
+  uint32_t sclk_freq = esp32c6_lowputc_get_sclk(conf);
+  uint32_t clk_div = ((sclk_freq) << 4) / conf->baud;
+  uint32_t int_part = clk_div >> 4;
+  uint32_t frag_part = clk_div &  0xf;
+
+  /* The baud rate configuration register is divided into
+   * an integer part and a fractional part.
+   */
+
+  modifyreg32(UART_CLKDIV_SYNC_REG(conf->id), UART_CLKDIV_M, int_part);
+  modifyreg32(UART_CLKDIV_SYNC_REG(conf->id), UART_CLKDIV_FRAG_M,
+                              frag_part << UART_CLKDIV_FRAG_S);
+  modifyreg32(UART_CLK_CONF_REG(conf->id), UART_SCLK_DIV_NUM_M,
+                                (sclk_div - 1) << UART_SCLK_DIV_NUM_S);
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_normal_mode
+ *    Set the UART to operate in normal mode
+ ****************************************************************************/
+
+void esp32c6_lowputc_normal_mode(const struct esp32c6_uart_s * conf)
+{
+  /* Disable RS485 mode */
+
+  modifyreg32(UART_RS485_CONF_SYNC_REG(conf->id), UART_RS485_EN_M, 0);
+  modifyreg32(UART_RS485_CONF_SYNC_REG(conf->id), UART_RS485TX_RX_EN_M, 0);
+  modifyreg32(UART_RS485_CONF_SYNC_REG(conf->id), UART_RS485RXBY_TX_EN_M, 0);
+
+  /* Disable IRDA mode */
+
+  modifyreg32(UART_CONF0_SYNC_REG(conf->id), UART_IRDA_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_parity
+ *    Set the parity
+ ****************************************************************************/
+
+void esp32c6_lowputc_parity(const struct esp32c6_uart_s * conf)
+{
+  if (conf->parity == UART_PARITY_DISABLE)
+    {
+      modifyreg32(UART_CONF0_SYNC_REG(conf->id), UART_PARITY_EN_M, 0);
+    }
+  else
+    {
+      modifyreg32(UART_CONF0_SYNC_REG(conf->id), UART_PARITY_M,
+                  ((conf->parity & 0x1) << UART_PARITY_S));
+      modifyreg32(UART_CONF0_SYNC_REG(conf->id), UART_PARITY_EN_M,
+                                 1 << UART_PARITY_EN_S);
+    }
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_data_length
+ *    Set the data length
+ ****************************************************************************/
+
+int esp32c6_lowputc_data_length(const struct esp32c6_uart_s * conf)
+{
+  int ret = OK;
+  uint32_t length = (conf->bits - 5);
+
+  /* If it is the allowed range */
+
+  if (length >= UART_DATA_5_BITS && length <= UART_DATA_8_BITS)
+    {
+      modifyreg32(UART_CONF0_SYNC_REG(conf->id), UART_BIT_NUM_M,
+                    length << UART_BIT_NUM_S);
+    }
+  else
+    {
+      ret = -EINVAL;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_stop_length
+ *    Set the stop length
+ ****************************************************************************/
+
+void esp32c6_lowputc_stop_length(const struct esp32c6_uart_s * conf)
+{
+  if (conf->stop_b2 == 0)
+    {
+      modifyreg32(UART_CONF0_SYNC_REG(conf->id), UART_STOP_BIT_NUM_M,
+                    UART_STOP_BITS_1 << UART_STOP_BIT_NUM_S);
+    }
+  else
+    {
+      modifyreg32(UART_CONF0_SYNC_REG(conf->id), UART_STOP_BIT_NUM_M,
+                    UART_STOP_BITS_2 << UART_STOP_BIT_NUM_S);
+    }
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_set_tx_idle_time
+ *    Set the idle time between transfers
+ ****************************************************************************/
+
+void esp32c6_lowputc_set_tx_idle_time(const struct esp32c6_uart_s *
+                                      conf, uint32_t time)
+{
+  time = time << UART_TX_IDLE_NUM_S;
+  time = time & UART_TX_IDLE_NUM_M; /* Just in case value overloads */
+  modifyreg32(UART_IDLE_CONF_SYNC_REG(conf->id), UART_TX_IDLE_NUM_M,
+              time);
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_send_byte
+ *    Send one byte
+ ****************************************************************************/
+
+void esp32c6_lowputc_send_byte(const struct esp32c6_uart_s * conf,
+                               char byte)
+{
+  putreg32((uint32_t) byte, UART_FIFO_REG(conf->id));
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_is_tx_fifo_full
+ *    Verifies if TX FIFO is full
+ ****************************************************************************/
+
+bool esp32c6_lowputc_is_tx_fifo_full(const struct esp32c6_uart_s *
+                                     conf)
+{
+  uint32_t reg;
+  reg = getreg32(UART_STATUS_REG(conf->id));
+  reg = reg >> UART_TXFIFO_CNT_S;
+  reg = reg & UART_TXFIFO_CNT_V;
+  if (reg < (UART_TX_FIFO_SIZE -1))
+    {
+      return false;
+    }
+  else
+    {
+      return true;
+    }
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_disable_all_uart_int
+ *
+ * Description:
+ *   Disable all UART interrupts.
+ *
+ * Parameters:
+ *   priv           - Pointer to the private driver struct.
+ *   current_status - Pointer to a variable to store the current status of
+ *                    the interrupt enable register before disabling
+ *                    UART interrupts.
+ *
+ ****************************************************************************/
+
+void esp32c6_lowputc_disable_all_uart_int(const struct esp32c6_uart_s *priv,
+                                          uint32_t *current_status)
+{
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+
+  if (current_status != NULL)
+    {
+      /* Save current status */
+
+      *current_status = getreg32(UART_INT_ENA_REG(priv->id));
+    }
+
+  /* Disable all UART int */
+
+  putreg32(0, UART_INT_ENA_REG(priv->id));
+
+  /* Clear all ints */
+
+  putreg32(0xffffffff, UART_INT_CLR_REG(priv->id));
+
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_restore_all_uart_int
+ *
+ * Description:
+ *   Restore all UART interrupts.
+ *
+ * Parameters:
+ *   priv        - Pointer to the private driver struct.
+ *   last_status - Pointer to a variable that stored the last state of the
+ *                 interrupt enable register.
+ *
+ ****************************************************************************/
+
+void esp32c6_lowputc_restore_all_uart_int(const struct esp32c6_uart_s *priv,
+                                          uint32_t *last_status)
+{
+  /* Restore the previous behaviour */
+
+  putreg32(*last_status, UART_INT_ENA_REG(priv->id));
+}
+
+/****************************************************************************
+ * Name: riscv_lowputc
+ *
+ * Description:
+ *   Output one byte on the serial console.
+ *
+ * Parameters:
+ *   ch        - Byte to be sent.
+ *
+ ****************************************************************************/
+
+void riscv_lowputc(char ch)
+{
+#ifdef CONSOLE_UART
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+  struct esp32c6_uart_s *priv = &g_uart0_config;
+#elif defined (CONFIG_UART1_SERIAL_CONSOLE)
+  struct esp32c6_uart_s *priv = &g_uart1_config;
+#endif
+
+  /* Wait until the TX FIFO has space to insert new char */
+
+  while (esp32c6_lowputc_is_tx_fifo_full(priv));
+
+  /* Then send the character */
+
+  esp32c6_lowputc_send_byte(priv, ch);
+
+#endif /* CONSOLE_UART */
+}
+
+/****************************************************************************
+ * Name: esp32c6_lowsetup
+ *
+ * Description:
+ *   This performs basic initialization of the UART used for the serial
+ *   console.  Its purpose is to get the console output available as soon
+ *   as possible.
+ *
+ ****************************************************************************/
+
+void esp32c6_lowsetup(void)
+{
+  /* Enable and configure the selected console device */
+
+#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+  struct esp32c6_uart_s *priv = &g_uart0_config;
+#elif defined (CONFIG_UART1_SERIAL_CONSOLE)
+  struct esp32c6_uart_s *priv = &g_uart1_config;
+#endif
+
+  /* Configure Clock */
+
+  /* esp32c6_lowputc_set_sclk(&g_console_config, APB_CLK); */
+
+  /* Configure the UART Baud Rate */
+
+  /* esp32c6_lowputc_baud(&g_console_config); */
+
+  /* Set a mode */
+
+  esp32c6_lowputc_normal_mode(priv);
+
+  /* Parity */
+
+  esp32c6_lowputc_parity(priv);
+
+  /* Data Frame size */
+
+  esp32c6_lowputc_data_length(priv);
+
+  /* Stop bit */
+
+  esp32c6_lowputc_stop_length(priv);
+
+  /* No Tx idle interval */
+
+  esp32c6_lowputc_set_tx_idle_time(priv, 0);
+
+  /* Enable cores */
+
+  esp32c6_lowputc_enable_sclk(priv);
+
+#endif /* HAVE_SERIAL_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
+}

arch/risc-v/src/esp32c6/esp32c6_lowputc.h

@@ -0,0 +1,252 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_lowputc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C6_ESP32C6_LOWPUTC_H
+#define __ARCH_RISCV_SRC_ESP32C6_ESP32C6_LOWPUTC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#include "hardware/esp32c6_uart.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+enum uart_sclk
+{
+  APB_CLK = 1, /* 80 MHz */
+  CLK_8,       /* 8 MHz */
+  XTAL_CLK
+};
+
+enum uart_parity
+{
+  UART_PARITY_DISABLE,
+  UART_PARITY_ODD,
+  UART_PARITY_EVEN
+};
+
+enum uart_data_length
+{
+  UART_DATA_5_BITS,
+  UART_DATA_6_BITS,
+  UART_DATA_7_BITS,
+  UART_DATA_8_BITS
+};
+
+enum uart_stop_length
+{
+    UART_STOP_BITS_1   = 0x1,  /* stop bit: 1 bit */
+    UART_STOP_BITS_2   = 0x3,  /* stop bit: 2bits */
+};
+
+/* Default FIFOs size */
+
+#define UART_TX_FIFO_SIZE 128
+#define UART_RX_FIFO_SIZE 128
+
+/* Struct used to store uart driver information and to
+ * manipulate uart driver
+ */
+
+struct esp32c6_uart_s
+{
+  uint32_t  base;           /* Base address of UART registers */
+  uint8_t   periph;         /* UART peripheral ID */
+  int       cpuint;         /* CPU interrupt assigned to this UART */
+  uint8_t   id;             /* UART ID */
+  uint8_t   irq;            /* IRQ associated with this UART */
+  uint32_t  baud;           /* Configured baud rate */
+  uint8_t   bits;
+  uint8_t   parity;         /* 0=no parity, 1=odd parity, 2=even parity */
+  uint8_t   stop_b2;        /* Use 2 stop bits? 0 no, others yes */
+  uint8_t   int_pri;        /* UART Interrupt Priority */
+};
+
+#ifdef CONFIG_ESP32C6_UART0
+extern struct esp32c6_uart_s g_uart0_config;
+#endif
+
+#ifdef CONFIG_ESP32C6_UART1
+extern struct esp32c6_uart_s g_uart1_config;
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_reset_core
+ *  Reset both TX and RX core
+ ****************************************************************************/
+
+void esp32c6_lowputc_reset_core(const struct esp32c6_uart_s *conf);
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_enable_sclk
+ *    Enable clock for whole core
+ ****************************************************************************/
+
+void esp32c6_lowputc_enable_sclk(const struct esp32c6_uart_s *conf);
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_disable_sclk
+ *    Disable clock for whole core
+ ****************************************************************************/
+
+void esp32c6_lowputc_disable_sclk(const struct esp32c6_uart_s *conf);
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_set_sclk
+ *    Set a source clock for UART
+ *    APB_CLK  = 1  80 MHz
+ *    CLK_8    = 2        8 MHz
+ *    XTAL_CLK = 3
+ ****************************************************************************/
+
+void esp32c6_lowputc_set_sclk(const struct esp32c6_uart_s *conf, enum
+                              uart_sclk source);
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_get_sclk
+ *    Get the source clock for UART
+ ****************************************************************************/
+
+uint32_t esp32c6_lowputc_get_sclk(const struct esp32c6_uart_s *conf);
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_baud
+ *    Set the baud rate
+ ****************************************************************************/
+
+void esp32c6_lowputc_baud(const struct esp32c6_uart_s * conf);
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_normal_mode
+ *    Set the UART to operate in normal mode
+ ****************************************************************************/
+
+void esp32c6_lowputc_normal_mode(const struct esp32c6_uart_s * conf);
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_parity
+ *    Set the parity
+ ****************************************************************************/
+
+void esp32c6_lowputc_parity(const struct esp32c6_uart_s * conf);
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_data_length
+ *    Set the data length
+ ****************************************************************************/
+
+int esp32c6_lowputc_data_length(const struct esp32c6_uart_s * conf);
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_stop_length
+ *    Set the stop length
+ ****************************************************************************/
+
+void esp32c6_lowputc_stop_length(const struct esp32c6_uart_s * conf);
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_set_tx_idle_time
+ *    Set the idle time between transfers
+ ****************************************************************************/
+
+void esp32c6_lowputc_set_tx_idle_time(const struct esp32c6_uart_s *
+                                      conf, uint32_t time);
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_send_byte
+ *    Send one byte
+ ****************************************************************************/
+
+void esp32c6_lowputc_send_byte(const struct esp32c6_uart_s * conf,
+                               char byte);
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_is_tx_fifo_full
+ *    Send one byte
+ ****************************************************************************/
+
+bool esp32c6_lowputc_is_tx_fifo_full(const struct esp32c6_uart_s *conf);
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_disable_all_uart_int
+ *
+ * Description:
+ *   Disable all UART interrupts.
+ *
+ * Parameters:
+ *   priv           - Pointer to the private driver struct.
+ *   current_status - Pointer to a variable to store the current status of
+ *                    the interrupt enable register before disabling
+ *                    UART interrupts.
+ *
+ ****************************************************************************/
+
+void esp32c6_lowputc_disable_all_uart_int(const struct esp32c6_uart_s *priv,
+                                          uint32_t *current_status);
+
+/****************************************************************************
+ * Name: esp32c6_lowputc_restore_all_uart_int
+ *
+ * Description:
+ *   Restore all UART interrupts.
+ *
+ * Parameters:
+ *   priv        - Pointer to the private driver struct.
+ *   last_status - Pointer to a variable that stored the last state of the
+ *                 interrupt enable register.
+ *
+ ****************************************************************************/
+
+void esp32c6_lowputc_restore_all_uart_int(const struct esp32c6_uart_s *priv,
+                                          uint32_t *last_status);
+
+/****************************************************************************
+ * Name: esp32c6_lowsetup
+ *
+ * Description:
+ *   This performs basic initialization of the UART used for the serial
+ *   console.  Its purpose is to get the console output available as soon
+ *   as possible.
+ *
+ ****************************************************************************/
+
+void esp32c6_lowsetup(void);
+
+#endif /* __ARCH_RISCV_SRC_ESP32C6_ESP32C6_LOWPUTC_H */

arch/risc-v/src/esp32c6/esp32c6_memorymap.h

@@ -0,0 +1,43 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef _ARCH_RISCV_SRC_ESP32C6_ESP32C6_MEMORYMAP_H
+#define _ARCH_RISCV_SRC_ESP32C6_ESP32C6_MEMORYMAP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Idle thread stack starts from _ebss */
+
+#ifndef __ASSEMBLY__
+#define ESP32C6_IDLESTACK_BASE  (uint32_t)&g_idlestack
+#else
+#define ESP32C6_IDLESTACK_BASE  g_idlestack
+#endif
+
+#define ESP32C6_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3)
+#define ESP32C6_IDLESTACK_TOP  (ESP32C6_IDLESTACK_BASE + ESP32C6_IDLESTACK_SIZE)
+
+#endif /* _ARCH_RISCV_SRC_ESP32C6_ESP32C6_MEMORYMAP_H */

arch/risc-v/src/esp32c6/esp32c6_serial.c

@@ -0,0 +1,714 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include "riscv_internal.h"
+#include "chip.h"
+#include "hardware/esp32c6_uart.h"
+
+#include "esp32c6_lowputc.h"
+#include "esp32c6_config.h"
+#include "esp32c6_irq.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+#  if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#    define CONSOLE_DEV     g_uart0_dev     /* UART0 is console */
+#    define TTYS0_DEV       g_uart0_dev     /* UART0 is ttyS0 */
+#    define UART0_ASSIGNED      1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_uart1_dev  /* UART1 is console */
+#    define TTYS0_DEV           g_uart1_dev  /* UART1 is ttyS0 */
+#    define UART1_ASSIGNED      1
+#  endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+#  undef  CONSOLE_DEV
+#  if defined(CONFIG_ESP32C6_UART0)
+#    define TTYS0_DEV           g_uart0_dev  /* UART0 is ttyS0 */
+#    define UART0_ASSIGNED      1
+#  elif defined(CONFIG_ESP32C6_UART1)
+#    define TTYS0_DEV           g_uart1_dev  /* UART1 is ttyS0 */
+#    define UART1_ASSIGNED      1
+#  endif
+#endif /* CONSOLE_UART */
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32C6_UART0) && !defined(UART0_ASSIGNED)
+#  define TTYS1_DEV           g_uart0_dev  /* UART0 is ttyS1 */
+#  define UART0_ASSIGNED      1
+#elif defined(CONFIG_ESP32C5_UART1) && !defined(UART1_ASSIGNED)
+#  define TTYS1_DEV           g_uart1_dev  /* UART1 is ttyS1 */
+#  define UART1_ASSIGNED      1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C6_UART
+
+/* Serial driver methods */
+
+static int  esp32c6_setup(struct uart_dev_s *dev);
+static void esp32c6_shutdown(struct uart_dev_s *dev);
+static int  esp32c6_attach(struct uart_dev_s *dev);
+static void esp32c6_detach(struct uart_dev_s *dev);
+static void esp32c6_txint(struct uart_dev_s *dev, bool enable);
+static void esp32c6_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32c6_rxavailable(struct uart_dev_s *dev);
+static bool esp32c6_txready(struct uart_dev_s *dev);
+static bool esp32c6_txempty(struct uart_dev_s *dev);
+static void esp32c6_send(struct uart_dev_s *dev, int ch);
+static int  esp32c6_receive(struct uart_dev_s *dev, unsigned int *status);
+static int  esp32c6_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32c6_rxflowcontrol(struct uart_dev_s *dev,
+                                  unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C6_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+    .setup       = esp32c6_setup,
+    .shutdown    = esp32c6_shutdown,
+    .attach      = esp32c6_attach,
+    .detach      = esp32c6_detach,
+    .txint       = esp32c6_txint,
+    .rxint       = esp32c6_rxint,
+    .rxavailable = esp32c6_rxavailable,
+    .txready     = esp32c6_txready,
+    .txempty     = esp32c6_txempty,
+    .send        = esp32c6_send,
+    .receive     = esp32c6_receive,
+    .ioctl       = esp32c6_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+    .rxflowcontrol  = esp32c6_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32C6_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+    .isconsole = true,
+#else
+    .isconsole = false,
+#endif
+    .xmit =
+    {
+        .size   = CONFIG_UART0_TXBUFSIZE,
+        .buffer = g_uart0_txbuffer,
+    },
+    .recv =
+    {
+        .size   = CONFIG_UART0_RXBUFSIZE,
+        .buffer = g_uart0_rxbuffer,
+    },
+
+    .ops = &g_uart_ops,
+    .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32C6_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+    .isconsole = true,
+#else
+    .isconsole = false,
+#endif
+    .xmit =
+    {
+        .size   = CONFIG_UART1_TXBUFSIZE,
+        .buffer = g_uart1_txbuffer,
+    },
+    .recv =
+    {
+        .size   = CONFIG_UART1_RXBUFSIZE,
+        .buffer = g_uart1_rxbuffer,
+    },
+
+    .ops = &g_uart_ops,
+    .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32C6_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C6_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ *   This is the UART interrupt handler.  It will be invoked when an
+ *   interrupt is received on the 'irq'  It should call uart_xmitchars or
+ *   uart_recvchars to perform the appropriate data transfers.  The
+ *   interrupt handling logic must be able to map the 'irq' number into the
+ *   appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, FAR void *context, FAR void *arg)
+{
+  struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+  struct esp32c6_uart_s *priv = dev->priv;
+  uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+  uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+  uint32_t int_status;
+
+  int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+  /* Tx fifo empty interrupt or UART tx done int */
+
+  if (int_status & tx_mask)
+    {
+      uart_xmitchars(dev);
+      modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+    }
+
+  /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+  if (int_status & rx_mask)
+    {
+      uart_recvchars(dev);
+      modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: esp32c6_setup
+ *
+ * Description:
+ *      Configure the UART baud, bits, parity, fifos, etc. This method is
+ *      called the first time that the serial port is opened.
+ *      For the serial console, this will occur very early in initialization,
+ *      for other serial ports this will occur when the port is first opened.
+ *      This setup does not include attaching or enabling interrupts.
+ *      That portion of the UART setup is performed when the attach() method
+ *      is called.
+ *
+ ****************************************************************************/
+
+static int esp32c6_setup(struct uart_dev_s *dev)
+{
+  return OK;
+}
+
+/****************************************************************************
+ * Name: esp32c6_shutdown
+ *
+ * Description:
+ * Disable the UART.  This method is called when the serial port is closed.
+ * This method reverses the operation the setup method.  NOTE that the serial
+ * console is never shutdown.
+ *
+ ****************************************************************************/
+
+static void esp32c6_shutdown(struct uart_dev_s *dev)
+{
+  struct esp32c6_uart_s *priv = dev->priv;
+
+  /* Disable ints */
+
+  esp32c6_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32c6_attach
+ *
+ * Description:
+ *   Configure the UART to operation in interrupt driven mode.  This method
+ *   is called when the serial port is opened.  Normally, this is just after
+ *   the the setup() method is called, however, the serial console may
+ *   operate in a non-interrupt driven mode during the boot phase.
+ *
+ *   RX and TX interrupts are not enabled when by the attach method (unless
+ *   the hardware supports multiple levels of interrupt enabling).  The RX
+ *   and TX interrupts are not enabled until the txint() and rxint() methods
+ *   are called.
+ *
+ ****************************************************************************/
+
+static int esp32c6_attach(struct uart_dev_s *dev)
+{
+  struct esp32c6_uart_s *priv = dev->priv;
+  int ret;
+
+  DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+  /* Set up to receive peripheral interrupts */
+
+  priv->cpuint = esp32c6_setup_irq(priv->periph, priv->int_pri,
+                                   ESP32C6_INT_LEVEL);
+  if (priv->cpuint < 0)
+    {
+      return priv->cpuint;
+    }
+
+  /* Attach and enable the IRQ */
+
+  ret = irq_attach(priv->irq, uart_handler, dev);
+  if (ret == OK)
+    {
+      up_enable_irq(priv->irq);
+    }
+  else
+    {
+      up_disable_irq(priv->irq);
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: esp32_detach
+ *
+ * Description:
+ *   Detach UART interrupts.  This method is called when the serial port is
+ *   closed normally just before the shutdown method is called.  The
+ *   exception is the serial console which is never shutdown.
+ *
+ ****************************************************************************/
+
+static void esp32c6_detach(struct uart_dev_s *dev)
+{
+  struct esp32c6_uart_s *priv = dev->priv;
+
+  DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+  /* Disable and detach the CPU interrupt */
+
+  up_disable_irq(priv->irq);
+  irq_detach(priv->irq);
+
+  /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+  esp32c6_teardown_irq(priv->periph, priv->cpuint);
+  priv->cpuint = -ENOMEM;
+}
+
+/****************************************************************************
+ * Name: esp32c6_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void esp32c6_txint(struct uart_dev_s *dev, bool enable)
+{
+  struct esp32c6_uart_s *priv = dev->priv;
+  uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M;
+
+  if (enable)
+    {
+      /* Set to receive an interrupt when the TX holding register register
+       * is empty
+       */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+    }
+  else
+    {
+      /* Disable the TX interrupt */
+
+      modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+    }
+}
+
+/****************************************************************************
+ * Name: esp32c6_rxint
+ *
+ * Description:
+ *   Call to enable or disable RXRDY interrupts
+ *
+ ****************************************************************************/
+
+static void esp32c6_rxint(struct uart_dev_s *dev, bool enable)
+{
+  struct esp32c6_uart_s *priv = dev->priv;
+  uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M |
+                       UART_RXFIFO_FULL_INT_ENA_M;
+
+  if (enable)
+    {
+      /* Receive an interrupt when their is anything in the Rx data register
+       * (or an Rx timeout occurs).
+       */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M,
+                  UART_RX_TOUT_EN_M);
+      modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+    }
+  else
+    {
+      modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0);
+
+      /* Disable the RX interrupts */
+
+      modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+    }
+}
+
+/****************************************************************************
+ * Name: esp32c6_rxavailable
+ *
+ * Description:
+ *   Return true if the receive holding register is not empty
+ *
+ ****************************************************************************/
+
+static bool esp32c6_rxavailable(struct uart_dev_s *dev)
+{
+  struct esp32c6_uart_s *priv = dev->priv;
+  uint32_t status_reg;
+  uint32_t bytes;
+
+  status_reg = getreg32(UART_STATUS_REG(priv->id));
+  bytes = status_reg & UART_RXFIFO_CNT_M;
+
+  return (bytes > 0) ? true : false;
+}
+
+/****************************************************************************
+ * Name: esp32c6_txready
+ *
+ * Description:
+ * Return true if the tranmsit hardware is ready to send another byte.  This
+ * is used to determine if send() method can be called.
+ *
+ ****************************************************************************/
+
+static bool esp32c6_txready(struct uart_dev_s *dev)
+{
+  return (esp32c6_lowputc_is_tx_fifo_full(dev->priv)) ? false : true;
+}
+
+/****************************************************************************
+ * Name: esp32c6_txempty
+ *
+ * Description:
+ * Return true if all characters have been sent.  If for example, the UART
+ * hardware implements FIFOs, then this would mean the transmit FIFO is
+ * empty.  This method is called when the driver needs to make sure that
+ * all characters are "drained" from the TX hardware.
+ *
+ ****************************************************************************/
+
+static bool esp32c6_txempty(struct uart_dev_s *dev)
+{
+  uint32_t reg;
+  struct esp32c6_uart_s *priv = dev->priv;
+
+  reg = getreg32(UART_INT_RAW_REG(priv->id));
+  reg = reg & UART_TXFIFO_EMPTY_INT_RAW_M;
+
+  return (reg > 0) ? true : false;
+}
+
+/****************************************************************************
+ * Name: esp32c6_send
+ *
+ * Description:
+ *    Send a unique character
+ *
+ * Parameters:
+ *   dev        -  Pointer to the serial driver struct.
+ *   ch         -  Byte to be sent.
+ *
+ ****************************************************************************/
+
+static void esp32c6_send(struct uart_dev_s *dev, int ch)
+{
+  /* Then send the character */
+
+  esp32c6_lowputc_send_byte(dev->priv, ch);
+}
+
+/****************************************************************************
+ * Name: esp32c6_receive
+ *
+ * Description:
+ *   Called (usually) from the interrupt level to receive one
+ *   character from the UART.  Error bits associated with the
+ *   receipt are provided in the return 'status'.
+ *
+ ****************************************************************************/
+
+static int esp32c6_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+  uint32_t rx_fifo;
+  struct esp32c6_uart_s *priv = dev->priv;
+
+  rx_fifo = getreg32(UART_FIFO_REG(priv->id));
+  rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M;
+
+  /* Since we don't have error bits associated with receipt, we set zero */
+
+  *status = 0;
+
+  return (int)rx_fifo;
+}
+
+/****************************************************************************
+ * Name: esp32c6_ioctl
+ *
+ * Description:
+ *   All ioctl calls will be routed through this method.
+ *   Here it's employed to implement the TERMIOS ioctls and TIOCSERGSTRUCT.
+ *
+ * Parameters:
+ *   filep    Pointer to a file structure instance.
+ *   cmd      The ioctl command.
+ *   arg      The argument of the ioctl cmd.
+ *
+ * Returned Value:
+ *   Returns a non-negative number on success;  A negated errno value is
+ *   returned on any failure (see comments ioctl() for a list of appropriate
+ *   errno values).
+ *
+ ****************************************************************************/
+
+static int esp32c6_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+  return OK;
+}
+
+#endif /* CONFIG_ESP32C6_UART */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef USE_EARLYSERIALINIT
+
+/****************************************************************************
+ * Name: riscv_earlyserialinit
+ *
+ * Description:
+ *   Performs the low level UART initialization early in debug so that the
+ *   serial console will be available during bootup.  This must be called
+ *   before riscv_serialinit.  NOTE:  This function depends on GPIO pin
+ *   configuration performed in up_consoleinit() and main clock
+ *   initialization performed in up_clkinitialize().
+ *
+ ****************************************************************************/
+
+void riscv_earlyserialinit(void)
+{
+  /* NOTE:  All GPIO configuration for the UARTs was performed in
+   * esp32c6_lowsetup
+   */
+
+  /* Disable all UARTS interrupts */
+
+#ifdef TTYS0_DEV
+  esp32c6_lowputc_disable_all_uart_int(TTYS0_DEV.priv, NULL);
+#endif
+
+#ifdef TTYS1_DEV
+  esp32c6_lowputc_disable_all_uart_int(TTYS1_DEV.priv, NULL);
+#endif
+
+  /* Configure console in early step.
+   * Setup for other serials will be perfomed when the serial driver is
+   * open.
+   */
+
+#ifdef CONSOLE_UART
+  esp32c6_setup(&CONSOLE_DEV);
+#endif
+}
+
+#endif /* USE_EARLYSERIALINIT */
+
+/****************************************************************************
+ * Name: riscv_serialinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes
+ *   that riscv_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void riscv_serialinit(void)
+{
+#ifdef HAVE_SERIAL_CONSOLE
+  uart_register("/dev/console", &CONSOLE_DEV);
+#endif
+
+#ifdef TTYS0_DEV
+  uart_register("/dev/ttyS0", &TTYS0_DEV);
+#endif
+
+#ifdef TTYS1_DEV
+  uart_register("/dev/ttyS1", &TTYS1_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug  writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef CONSOLE_UART
+  uint32_t int_status;
+
+  esp32c6_lowputc_disable_all_uart_int(CONSOLE_DEV.priv, &int_status);
+#endif
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      riscv_lowputc('\r');
+    }
+
+  riscv_lowputc(ch);
+
+#ifdef CONSOLE_UART
+  esp32c6_lowputc_restore_all_uart_int(CONSOLE_DEV.priv, &int_status);
+#endif
+  return ch;
+}
+
+#endif /* HAVE_UART_DEVICE */
+
+#else /* USE_SERIALDRIVER */
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef CONSOLE_UART
+  uint32_t int_status;
+
+  esp32c6_lowputc_disable_all_uart_int(CONSOLE_DEV.priv, &int_status);
+#endif
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      riscv_lowputc('\r');
+    }
+
+  riscv_lowputc(ch);
+
+#ifdef CONSOLE_UART
+  esp32c6_lowputc_restore_all_uart_int(CONSOLE_DEV.priv, &int_status);
+#endif
+  return ch;
+}
+
+#endif /* USE_SERIALDRIVER */

arch/risc-v/src/esp32c6/esp32c6_start.c

@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_start.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/init.h>
+
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "esp32c6.h"
+#include "esp32c6_irq.h"
+#include "esp32c6_lowputc.h"
+#include "esp32c6_clockconfig.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_FEATURES
+#  define showprogress(c) riscv_lowputc(c)
+#else
+#  define showprogress(c)
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Address of the IDLE thread */
+
+uint8_t g_idlestack[CONFIG_IDLETHREAD_STACKSIZE]
+  aligned_data(16) locate_data(".noinit");
+uintptr_t g_idle_topstack = ESP32C6_IDLESTACK_TOP;
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: __esp32c6_start
+ ****************************************************************************/
+
+void __esp32c6_start(void)
+{
+  /* Set CPU frequency */
+
+  esp32c6_clockconfig();
+
+  /* Configure the UART so we can get debug output */
+
+  esp32c6_lowsetup();
+
+  showprogress('A');
+
+  /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
+   * certain that there are no issues with the state of global variables.
+   */
+
+  for (uint32_t *dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; )
+    {
+      *dest++ = 0;
+    }
+
+  showprogress('B');
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+
+  /* Put the CPU Interrupts in initial state */
+
+  esp32c6_cpuint_initialize();
+#endif
+
+  /* Call nx_start() */
+
+  nx_start();
+
+  for (; ; );
+}

arch/risc-v/src/esp32c6/esp32c6_systemreset.c

@@ -0,0 +1,53 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_systemreset.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <nuttx/arch.h>
+
+#include "esp32c6.h"
+#include "hardware/esp32c6_lp_aon.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_systemreset
+ *
+ * Description:
+ *   Internal reset logic.
+ *
+ ****************************************************************************/
+
+void up_systemreset(void)
+{
+  putreg32(LP_AON_HPSYS_SW_RESET, LP_AON_SYS_CFG_REG);
+
+  /* Wait for the reset */
+
+  for (; ; );
+}

arch/risc-v/src/esp32c6/esp32c6_timerisr.c

@@ -0,0 +1,127 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_timerisr.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <time.h>
+
+#include <arch/board/board.h>
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "esp32c6.h"
+#include "esp32c6_irq.h"
+#include "hardware/esp32c6_systimer.h"
+#include "hardware/esp32c6_pcr.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define ESP32C6_SYSTIMER_TICKS_PER_SEC  (16 * 1000 * 1000)
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: systimer_isr
+ ****************************************************************************/
+
+static int systimer_isr(int irq, FAR void *context, FAR void *arg)
+{
+  setbits(SYSTIMER_TARGET0_INT_CLR, SYSTIMER_INT_CLR_REG);
+
+  /* Process timer interrupt */
+
+  nxsched_process_timer();
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_timer_initialize
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ****************************************************************************/
+
+void up_timer_initialize(void)
+{
+  uint32_t regval;
+
+  /* Enable timer clock */
+
+  setbits(PCR_SYSTIMER_CLK_EN, PCR_SYSTIMER_CONF_REG);
+  resetbits(PCR_SYSTIMER_RST_EN, PCR_SYSTIMER_CONF_REG);
+
+  setbits(SYSTIMER_CLK_EN, SYSTIMER_CONF_REG);
+  setbits(SYSTIMER_ETM_EN, SYSTIMER_CONF_REG);
+
+  /* Configure alarm0 counter1 */
+
+  regval = SYSTIMER_TARGET0_PERIOD_MODE |
+           (1 << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) |
+           ((ESP32C6_SYSTIMER_TICKS_PER_SEC / CLOCKS_PER_SEC) <<
+            SYSTIMER_TARGET0_PERIOD_S);
+  putreg32(regval, SYSTIMER_TARGET0_CONF_REG);
+
+  putreg32(SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_COMP0_LOAD_REG);
+
+  /* Stall timer when stall CPU, specially when using JTAG to debug */
+
+  setbits(SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN, SYSTIMER_CONF_REG);
+
+  /* Enable interrupt */
+
+  setbits(SYSTIMER_TARGET0_INT_CLR, SYSTIMER_INT_CLR_REG);
+  setbits(SYSTIMER_TARGET0_INT_ENA, SYSTIMER_INT_ENA_REG);
+
+  regval = SYSTIMER_TARGET0_WORK_EN;
+  setbits(regval, SYSTIMER_CONF_REG);
+
+  /* Start alarm0 counter1 */
+
+  regval = SYSTIMER_TIMER_UNIT1_WORK_EN;
+  setbits(regval, SYSTIMER_CONF_REG);
+  esp32c6_setup_irq(ESP32C6_SYSTIMER_TARGET0_EDGE_PERIPH,
+                    ESP32C6_INT_PRIO_DEF,
+                    ESP32C6_INT_LEVEL);
+
+  /* Attach the timer interrupt. */
+
+  irq_attach(ESP32C6_IRQ_SYSTIMER_TARGET0_EDGE, (xcpt_t)systimer_isr, NULL);
+
+  /* Enable the allocated CPU interrupt. */
+
+  up_enable_irq(ESP32C6_IRQ_SYSTIMER_TARGET0_EDGE);
+}

arch/risc-v/src/esp32c6/esp32c6_vectors.S

@@ -0,0 +1,56 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/esp32c6_vectors.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/esp32c6/irq.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Public Symbols
+ ****************************************************************************/
+
+  .global  _vector_table
+
+/****************************************************************************
+ * Section: .exception_vectors.text
+ ****************************************************************************/
+
+  .section .exception_vectors.text
+
+/****************************************************************************
+ * Name: _vector_table
+ ****************************************************************************/
+
+  .balign   0x100
+  .type     _vector_table, @function
+
+_vector_table:
+  .option push
+  .option norvc
+
+  .rept (32)
+  j    exception_common
+  .endr

arch/risc-v/src/esp32c6/hardware/esp32c6_lp_aon.h

@@ -0,0 +1,541 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/hardware/esp32c6_lp_aon.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_LP_AON_H
+#define __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_LP_AON_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32c6_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* LP_AON_STORE0_REG register
+ * need_des
+ */
+
+#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0)
+
+/* LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_LP_AON_STORE0    0xffffffff
+#define LP_AON_LP_AON_STORE0_M  (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S)
+#define LP_AON_LP_AON_STORE0_V  0xffffffff
+#define LP_AON_LP_AON_STORE0_S  0
+
+/* LP_AON_STORE1_REG register
+ * need_des
+ */
+
+#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4)
+
+/* LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_LP_AON_STORE1    0xffffffff
+#define LP_AON_LP_AON_STORE1_M  (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S)
+#define LP_AON_LP_AON_STORE1_V  0xffffffff
+#define LP_AON_LP_AON_STORE1_S  0
+
+/* LP_AON_STORE2_REG register
+ * need_des
+ */
+
+#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8)
+
+/* LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_LP_AON_STORE2    0xffffffff
+#define LP_AON_LP_AON_STORE2_M  (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S)
+#define LP_AON_LP_AON_STORE2_V  0xffffffff
+#define LP_AON_LP_AON_STORE2_S  0
+
+/* LP_AON_STORE3_REG register
+ * need_des
+ */
+
+#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc)
+
+/* LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_LP_AON_STORE3    0xffffffff
+#define LP_AON_LP_AON_STORE3_M  (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S)
+#define LP_AON_LP_AON_STORE3_V  0xffffffff
+#define LP_AON_LP_AON_STORE3_S  0
+
+/* LP_AON_STORE4_REG register
+ * need_des
+ */
+
+#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10)
+
+/* LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_LP_AON_STORE4    0xffffffff
+#define LP_AON_LP_AON_STORE4_M  (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S)
+#define LP_AON_LP_AON_STORE4_V  0xffffffff
+#define LP_AON_LP_AON_STORE4_S  0
+
+/* LP_AON_STORE5_REG register
+ * need_des
+ */
+
+#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14)
+
+/* LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_LP_AON_STORE5    0xffffffff
+#define LP_AON_LP_AON_STORE5_M  (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S)
+#define LP_AON_LP_AON_STORE5_V  0xffffffff
+#define LP_AON_LP_AON_STORE5_S  0
+
+/* LP_AON_STORE6_REG register
+ * need_des
+ */
+
+#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18)
+
+/* LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_LP_AON_STORE6    0xffffffff
+#define LP_AON_LP_AON_STORE6_M  (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S)
+#define LP_AON_LP_AON_STORE6_V  0xffffffff
+#define LP_AON_LP_AON_STORE6_S  0
+
+/* LP_AON_STORE7_REG register
+ * need_des
+ */
+
+#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c)
+
+/* LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_LP_AON_STORE7    0xffffffff
+#define LP_AON_LP_AON_STORE7_M  (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S)
+#define LP_AON_LP_AON_STORE7_V  0xffffffff
+#define LP_AON_LP_AON_STORE7_S  0
+
+/* LP_AON_STORE8_REG register
+ * need_des
+ */
+
+#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20)
+
+/* LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_LP_AON_STORE8    0xffffffff
+#define LP_AON_LP_AON_STORE8_M  (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S)
+#define LP_AON_LP_AON_STORE8_V  0xffffffff
+#define LP_AON_LP_AON_STORE8_S  0
+
+/* LP_AON_STORE9_REG register
+ * need_des
+ */
+
+#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24)
+
+/* LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_LP_AON_STORE9    0xffffffff
+#define LP_AON_LP_AON_STORE9_M  (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S)
+#define LP_AON_LP_AON_STORE9_V  0xffffffff
+#define LP_AON_LP_AON_STORE9_S  0
+
+/* LP_AON_GPIO_MUX_REG register
+ * need_des
+ */
+
+#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28)
+
+/* LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_GPIO_MUX_SEL    0x000000ff
+#define LP_AON_GPIO_MUX_SEL_M  (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S)
+#define LP_AON_GPIO_MUX_SEL_V  0x000000ff
+#define LP_AON_GPIO_MUX_SEL_S  0
+
+/* LP_AON_GPIO_HOLD0_REG register
+ * need_des
+ */
+
+#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c)
+
+/* LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_GPIO_HOLD0    0xffffffff
+#define LP_AON_GPIO_HOLD0_M  (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S)
+#define LP_AON_GPIO_HOLD0_V  0xffffffff
+#define LP_AON_GPIO_HOLD0_S  0
+
+/* LP_AON_GPIO_HOLD1_REG register
+ * need_des
+ */
+
+#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30)
+
+/* LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_GPIO_HOLD1    0xffffffff
+#define LP_AON_GPIO_HOLD1_M  (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S)
+#define LP_AON_GPIO_HOLD1_V  0xffffffff
+#define LP_AON_GPIO_HOLD1_S  0
+
+/* LP_AON_SYS_CFG_REG register
+ * need_des
+ */
+
+#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34)
+
+/* LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_HPSYS_SW_RESET    (BIT(31))
+#define LP_AON_HPSYS_SW_RESET_M  (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S)
+#define LP_AON_HPSYS_SW_RESET_V  0x00000001
+#define LP_AON_HPSYS_SW_RESET_S  31
+
+/* LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_FORCE_DOWNLOAD_BOOT    (BIT(30))
+#define LP_AON_FORCE_DOWNLOAD_BOOT_M  (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S)
+#define LP_AON_FORCE_DOWNLOAD_BOOT_V  0x00000001
+#define LP_AON_FORCE_DOWNLOAD_BOOT_S  30
+
+/* LP_AON_CPUCORE0_CFG_REG register
+ * need_des
+ */
+
+#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38)
+
+/* LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_CPU_CORE0_DRESET_MASK    (BIT(31))
+#define LP_AON_CPU_CORE0_DRESET_MASK_M  (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S)
+#define LP_AON_CPU_CORE0_DRESET_MASK_V  0x00000001
+#define LP_AON_CPU_CORE0_DRESET_MASK_S  31
+
+/* LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1;
+ * need_des
+ */
+
+#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL    (BIT(30))
+#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M  (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S)
+#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V  0x00000001
+#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S  30
+
+/* LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET    (BIT(29))
+#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M  (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S)
+#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V  0x00000001
+#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S  29
+
+/* LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_CPU_CORE0_SW_RESET    (BIT(28))
+#define LP_AON_CPU_CORE0_SW_RESET_M  (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S)
+#define LP_AON_CPU_CORE0_SW_RESET_V  0x00000001
+#define LP_AON_CPU_CORE0_SW_RESET_S  28
+
+/* LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_CPU_CORE0_SW_STALL    0x000000ff
+#define LP_AON_CPU_CORE0_SW_STALL_M  (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S)
+#define LP_AON_CPU_CORE0_SW_STALL_V  0x000000ff
+#define LP_AON_CPU_CORE0_SW_STALL_S  0
+
+/* LP_AON_IO_MUX_REG register
+ * need_des
+ */
+
+#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c)
+
+/* LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_IO_MUX_RESET_DISABLE    (BIT(31))
+#define LP_AON_IO_MUX_RESET_DISABLE_M  (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S)
+#define LP_AON_IO_MUX_RESET_DISABLE_V  0x00000001
+#define LP_AON_IO_MUX_RESET_DISABLE_S  31
+
+/* LP_AON_EXT_WAKEUP_CNTL_REG register
+ * need_des
+ */
+
+#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40)
+
+/* LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_EXT_WAKEUP_FILTER    (BIT(31))
+#define LP_AON_EXT_WAKEUP_FILTER_M  (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S)
+#define LP_AON_EXT_WAKEUP_FILTER_V  0x00000001
+#define LP_AON_EXT_WAKEUP_FILTER_S  31
+
+/* LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_EXT_WAKEUP_LV    0x000000ff
+#define LP_AON_EXT_WAKEUP_LV_M  (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S)
+#define LP_AON_EXT_WAKEUP_LV_V  0x000000ff
+#define LP_AON_EXT_WAKEUP_LV_S  23
+
+/* LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_EXT_WAKEUP_SEL    0x000000ff
+#define LP_AON_EXT_WAKEUP_SEL_M  (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S)
+#define LP_AON_EXT_WAKEUP_SEL_V  0x000000ff
+#define LP_AON_EXT_WAKEUP_SEL_S  15
+
+/* LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_EXT_WAKEUP_STATUS_CLR    (BIT(14))
+#define LP_AON_EXT_WAKEUP_STATUS_CLR_M  (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S)
+#define LP_AON_EXT_WAKEUP_STATUS_CLR_V  0x00000001
+#define LP_AON_EXT_WAKEUP_STATUS_CLR_S  14
+
+/* LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_EXT_WAKEUP_STATUS    0x000000ff
+#define LP_AON_EXT_WAKEUP_STATUS_M  (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S)
+#define LP_AON_EXT_WAKEUP_STATUS_V  0x000000ff
+#define LP_AON_EXT_WAKEUP_STATUS_S  0
+
+/* LP_AON_USB_REG register
+ * need_des
+ */
+
+#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44)
+
+/* LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_USB_RESET_DISABLE    (BIT(31))
+#define LP_AON_USB_RESET_DISABLE_M  (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S)
+#define LP_AON_USB_RESET_DISABLE_V  0x00000001
+#define LP_AON_USB_RESET_DISABLE_S  31
+
+/* LP_AON_LPBUS_REG register
+ * need_des
+ */
+
+#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48)
+
+/* LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1;
+ * need_des
+ */
+
+#define LP_AON_FAST_MEM_MUX_SEL    (BIT(31))
+#define LP_AON_FAST_MEM_MUX_SEL_M  (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S)
+#define LP_AON_FAST_MEM_MUX_SEL_V  0x00000001
+#define LP_AON_FAST_MEM_MUX_SEL_S  31
+
+/* LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_FAST_MEM_MUX_SEL_UPDATE    (BIT(30))
+#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M  (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S)
+#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V  0x00000001
+#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S  30
+
+/* LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1;
+ * need_des
+ */
+
+#define LP_AON_FAST_MEM_MUX_SEL_STATUS    (BIT(29))
+#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M  (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S)
+#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V  0x00000001
+#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S  29
+
+/* LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1;
+ * need_des
+ */
+
+#define LP_AON_FAST_MEM_MUX_FSM_IDLE    (BIT(28))
+#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M  (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S)
+#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V  0x00000001
+#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S  28
+
+/* LP_AON_FAST_MEM_RA : R/W; bitpos: [23:22]; default: 0;
+ * This field controls fast memory RA parameter.
+ */
+
+#define LP_AON_FAST_MEM_RA    0x00000003
+#define LP_AON_FAST_MEM_RA_M  (LP_AON_FAST_MEM_RA_V << LP_AON_FAST_MEM_RA_S)
+#define LP_AON_FAST_MEM_RA_V  0x00000003
+#define LP_AON_FAST_MEM_RA_S  22
+
+/* LP_AON_FAST_MEM_WA : R/W; bitpos: [21:19]; default: 4;
+ * This field controls fast memory WA parameter.
+ */
+
+#define LP_AON_FAST_MEM_WA    0x00000007
+#define LP_AON_FAST_MEM_WA_M  (LP_AON_FAST_MEM_WA_V << LP_AON_FAST_MEM_WA_S)
+#define LP_AON_FAST_MEM_WA_V  0x00000007
+#define LP_AON_FAST_MEM_WA_S  19
+
+/* LP_AON_FAST_MEM_WPULSE : R/W; bitpos: [18:16]; default: 0;
+ * This field controls fast memory WPULSE parameter.
+ */
+
+#define LP_AON_FAST_MEM_WPULSE    0x00000007
+#define LP_AON_FAST_MEM_WPULSE_M  (LP_AON_FAST_MEM_WPULSE_V << LP_AON_FAST_MEM_WPULSE_S)
+#define LP_AON_FAST_MEM_WPULSE_V  0x00000007
+#define LP_AON_FAST_MEM_WPULSE_S  16
+
+/* LP_AON_SDIO_ACTIVE_REG register
+ * need_des
+ */
+
+#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c)
+
+/* LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10;
+ * need_des
+ */
+
+#define LP_AON_SDIO_ACT_DNUM    0x000003ff
+#define LP_AON_SDIO_ACT_DNUM_M  (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S)
+#define LP_AON_SDIO_ACT_DNUM_V  0x000003ff
+#define LP_AON_SDIO_ACT_DNUM_S  22
+
+/* LP_AON_LPCORE_REG register
+ * need_des
+ */
+
+#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50)
+
+/* LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_LPCORE_DISABLE    (BIT(31))
+#define LP_AON_LPCORE_DISABLE_M  (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S)
+#define LP_AON_LPCORE_DISABLE_V  0x00000001
+#define LP_AON_LPCORE_DISABLE_S  31
+
+/* LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG    (BIT(1))
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M  (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S)
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V  0x00000001
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S  1
+
+/* LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR    (BIT(0))
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M  (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S)
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V  0x00000001
+#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S  0
+
+/* LP_AON_SAR_CCT_REG register
+ * need_des
+ */
+
+#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54)
+
+/* LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_SAR2_PWDET_CCT    0x00000007
+#define LP_AON_SAR2_PWDET_CCT_M  (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S)
+#define LP_AON_SAR2_PWDET_CCT_V  0x00000007
+#define LP_AON_SAR2_PWDET_CCT_S  29
+
+/* LP_AON_DATE_REG register
+ * need_des
+ */
+
+#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
+
+/* LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0;
+ * need_des
+ */
+
+#define LP_AON_CLK_EN    (BIT(31))
+#define LP_AON_CLK_EN_M  (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S)
+#define LP_AON_CLK_EN_V  0x00000001
+#define LP_AON_CLK_EN_S  31
+
+/* LP_AON_DATE : R/W; bitpos: [30:0]; default: 35672704;
+ * need_des
+ */
+
+#define LP_AON_DATE    0x7fffffff
+#define LP_AON_DATE_M  (LP_AON_DATE_V << LP_AON_DATE_S)
+#define LP_AON_DATE_V  0x7fffffff
+#define LP_AON_DATE_S  0
+
+#endif /* __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_LP_AON_H */

arch/risc-v/src/esp32c6/hardware/esp32c6_rom_layout.h

@@ -0,0 +1,102 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/hardware/esp32c6_rom_layout.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_ROM_LAYOUT_H
+#define __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_ROM_LAYOUT_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Structure and functions for returning ROM global layout
+ *
+ * This is for address symbols defined in the linker script,
+ * which may change during ECOs.
+ */
+
+struct esp32c6_rom_layout_s
+{
+  uintptr_t dram0_stack_shared_mem_start;
+  uintptr_t dram0_rtos_reserved_start;
+  uintptr_t stack_sentry;
+  uintptr_t stack;
+
+  /* BTDM data */
+
+  uintptr_t data_start_btdm;
+  uintptr_t data_end_btdm;
+  uintptr_t bss_start_btdm;
+  uintptr_t bss_end_btdm;
+  uintptr_t data_start_btdm_rom;
+  uintptr_t data_start_interface_btdm;
+  uintptr_t data_end_interface_btdm;
+  uintptr_t bss_start_interface_btdm;
+  uintptr_t bss_end_interface_btdm;
+
+  /* BTBB data */
+
+  uintptr_t dram_start_btbbrom;
+  uintptr_t dram_end_btbbrom;
+
+  /* PHY data */
+
+  uintptr_t dram_start_phyrom;
+  uintptr_t dram_end_phyrom;
+
+  /* Wi-Fi data */
+
+  uintptr_t dram_start_net80211;
+  uintptr_t dram_end_net80211;
+  uintptr_t data_start_interface_net80211;
+  uintptr_t data_end_interface_net80211;
+  uintptr_t bss_start_interface_net80211;
+  uintptr_t bss_end_interface_net80211;
+  uintptr_t dram_start_pp;
+  uintptr_t dram_end_pp;
+  uintptr_t data_start_interface_pp;
+  uintptr_t data_end_interface_pp;
+  uintptr_t bss_start_interface_pp;
+  uintptr_t bss_end_interface_pp;
+
+  /* Coexist data */
+
+  uintptr_t dram_start_coexist;
+  uintptr_t dram_end_coexist;
+  uintptr_t data_start_interface_coexist;
+  uintptr_t data_end_interface_coexist;
+  uintptr_t bss_start_interface_coexist;
+  uintptr_t bss_end_interface_coexist;
+
+  /* USB device data */
+
+  uintptr_t dram_start_usbdev_rom;
+  uintptr_t dram_end_usbdev_rom;
+  uintptr_t dram_start_uart_rom;
+  uintptr_t dram_end_uart_rom;
+};
+
+#endif /* __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_ROM_LAYOUT_H */
+

arch/risc-v/src/esp32c6/hardware/esp32c6_soc.h

@@ -0,0 +1,157 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/hardware/esp32c6_soc.h
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_SOC_H
+#define __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_SOC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define DR_REG_PLIC_MX_BASE                     0x20001000
+#define DR_REG_PLIC_UX_BASE                     0x20001400
+#define DR_REG_CLINT_M_BASE                     0x20001800
+#define DR_REG_CLINT_U_BASE                     0x20001C00
+
+#define DR_REG_UART_BASE                        0x60000000
+#define DR_REG_UART1_BASE                       0x60001000
+#define DR_REG_SPI0_BASE                        0x60002000
+#define DR_REG_SPI1_BASE                        0x60003000
+#define DR_REG_I2C_EXT_BASE                     0x60004000
+#define DR_REG_UHCI0_BASE                       0x60005000
+#define DR_REG_RMT_BASE                         0x60006000
+#define DR_REG_LEDC_BASE                        0x60007000
+#define DR_REG_TIMERGROUP0_BASE                 0x60008000
+#define DR_REG_TIMERGROUP1_BASE                 0x60009000
+#define DR_REG_SYSTIMER_BASE                    0x6000A000
+#define DR_REG_TWAI0_BASE                       0x6000B000
+#define DR_REG_I2S_BASE                         0x6000C000
+#define DR_REG_TWAI1_BASE                       0x6000D000
+#define DR_REG_APB_SARADC_BASE                  0x6000E000
+#define DR_REG_USB_SERIAL_JTAG_BASE             0x6000F000
+#define DR_REG_INTERRUPT_MATRIX_BASE            0x60010000
+#define DR_REG_ATOMIC_BASE                      0x60011000
+#define DR_REG_PCNT_BASE                        0x60012000
+#define DR_REG_SOC_ETM_BASE                     0x60013000
+#define DR_REG_MCPWM_BASE                       0x60014000
+#define DR_REG_PARL_IO_BASE                     0x60015000
+#define DR_REG_HINF_BASE                        0x60016000
+#define DR_REG_SLC_BASE                         0x60017000
+#define DR_REG_SLCHOST_BASE                     0x60018000
+#define DR_REG_PVT_MONITOR_BASE                 0x60019000
+#define DR_REG_GDMA_BASE                        0x60080000
+#define DR_REG_SPI2_BASE                        0x60081000
+#define DR_REG_AES_BASE                         0x60088000
+#define DR_REG_SHA_BASE                         0x60089000
+#define DR_REG_RSA_BASE                         0x6008A000
+#define DR_REG_ECC_MULT_BASE                    0x6008B000
+#define DR_REG_DS_BASE                          0x6008C000
+#define DR_REG_HMAC_BASE                        0x6008D000
+#define DR_REG_IO_MUX_BASE                      0x60090000
+#define DR_REG_GPIO_BASE                        0x60091000
+#define DR_REG_GPIO_EXT_BASE                    0x60091f00 //ESP32C6-TODO
+#define DR_REG_MEM_MONITOR_BASE                 0x60092000
+#define DR_REG_PAU_BASE                         0x60093000
+#define DR_REG_HP_SYSTEM_BASE                   0x60095000
+#define DR_REG_PCR_BASE                         0x60096000
+#define DR_REG_TEE_BASE                         0x60098000
+#define DR_REG_HP_APM_BASE                      0x60099000
+#define DR_REG_LP_APM0_BASE                     0x60099800
+#define DR_REG_MISC_BASE                        0x6009F000
+
+#define DR_REG_PMU_BASE                         0x600B0000
+#define DR_REG_LP_CLKRST_BASE                   0x600B0400
+#define DR_REG_EFUSE_BASE                       0x600B0800
+#define DR_REG_LP_TIMER_BASE                    0x600B0C00
+#define DR_REG_LP_AON_BASE                      0x600B1000
+#define DR_REG_LP_UART_BASE                     0x600B1400
+#define DR_REG_LP_I2C_BASE                      0x600B1800
+#define DR_REG_LP_WDT_BASE                      0x600B1C00
+#define DR_REG_LP_IO_BASE                       0x600B2000
+#define DR_REG_LP_I2C_ANA_MST_BASE              0x600B2400
+#define DR_REG_LPPERI_BASE                      0x600B2800
+#define DR_REG_LP_ANALOG_PERI_BASE              0x600B2C00
+#define DR_REG_LP_TEE_BASE                      0x600B3400
+#define DR_REG_LP_APM_BASE                      0x600B3800
+#define DR_REG_OPT_DEBUG_BASE                   0x600B3C00
+
+#define DR_REG_TRACE_BASE                       0x600C0000
+#define DR_REG_ASSIST_DEBUG_BASE                0x600C2000
+#define DR_REG_CPU_BUS_MONITOR_BASE             0x600C2000
+#define DR_REG_INTPRI_BASE                      0x600C5000
+#define DR_REG_EXTMEM_BASE                      0x600C8000
+
+/* Registers Operation */
+
+#define REG_UHCI_BASE(i)      (DR_REG_UHCI0_BASE - (i) * 0x8000)
+#define REG_UART_BASE(i)      (DR_REG_UART_BASE + (i) * 0x1000)
+#define REG_UART_AHB_BASE(i)  (DR_REG_UART_BASE + (i) * 0x10000)
+#define UART_FIFO_AHB_REG(i)  (REG_UART_AHB_BASE(i) + 0x0)
+#define REG_I2S_BASE(i)       (DR_REG_I2S_BASE)
+#define REG_TIMG_BASE(i)      (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000)
+#define REG_SPI_MEM_BASE(i)   (DR_REG_SPI0_BASE + (i) * 0x1000)
+#define REG_SPI_BASE(i)       (DR_REG_SPI2_BASE)
+#define REG_I2C_BASE(i)       (DR_REG_I2C_EXT_BASE)
+#define REG_MCPWM_BASE(i)     (DR_REG_MCPWM_BASE)
+#define REG_TWAI_BASE(i)      (DR_REG_TWAI_BASE + (i) * 0x2000)
+
+/* Peripheral Clock */
+
+#define APB_CLK_FREQ_ROM        (40 * 1000000)
+#define CPU_CLK_FREQ_ROM        APB_CLK_FREQ_ROM
+#define UART_CLK_FREQ_ROM       (40 * 1000000)
+#define EFUSE_CLK_FREQ_ROM      (20 * 1000000)
+#define CPU_CLK_FREQ            APB_CLK_FREQ
+#define APB_CLK_FREQ            (80 * 1000000)
+#define REF_CLK_FREQ            (1000000)
+#define RTC_CLK_FREQ            (20 * 1000000)
+#define XTAL_CLK_FREQ           (40 * 1000000)
+#define UART_CLK_FREQ           APB_CLK_FREQ
+#define WDT_CLK_FREQ            APB_CLK_FREQ
+#define TIMER_CLK_FREQ          (80000000 >> 4) /* 80MHz divided by 16 */
+#define SPI_CLK_DIV             4
+#define TICKS_PER_US_ROM        40    /* CPU is 80MHz */
+#define GPIO_MATRIX_DELAY_NS    0
+
+#define PLIC_MXINT_ENABLE_REG          (DR_REG_PLIC_MX_BASE + 0x0)
+#define PLIC_MXINT_TYPE_REG            (DR_REG_PLIC_MX_BASE + 0x4)
+#define PLIC_MXINT_CLEAR_REG           (DR_REG_PLIC_MX_BASE + 0x8)
+#define PLIC_MXINT_THRESH_REG          (DR_REG_PLIC_MX_BASE + 0x90)
+#define PLIC_MXINT0_PRI_REG            (DR_REG_PLIC_MX_BASE + 0x10)
+
+#define INTC_INT_PRIO_REG(n)           (PLIC_MXINT0_PRI_REG + (n)*4)
+
+/* Mapping Peripheral IDs to map register addresses. */
+
+#define CORE_MAP_REGADDR(n)            (DR_REG_INTERRUPT_MATRIX_BASE + ((n) << 2))
+
+#define BIT(nr)                     (1UL << (nr))
+
+/* Helper to place a value in a field */
+
+#define VALUE_TO_FIELD(_value, _field) (((_value) << (_field##_S)) & (_field##_M))
+
+#define MHZ (1000000)
+
+#endif /* __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_SOC_H */

arch/risc-v/src/esp32c6/hardware/esp32c6_systimer.h

@@ -0,0 +1,817 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c6/hardware/esp32c6_systimer.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_SYSTIMER_H
+#define __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_SYSTIMER_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32c6_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* SYSTIMER_CONF_REG register
+ * Configure system timer clock
+ */
+
+#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
+
+/* SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
+ * register file clk gating
+ */
+
+#define SYSTIMER_CLK_EN    (BIT(31))
+#define SYSTIMER_CLK_EN_M  (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
+#define SYSTIMER_CLK_EN_V  0x00000001
+#define SYSTIMER_CLK_EN_S  31
+
+/* SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
+ * timer unit0 work enable
+ */
+
+#define SYSTIMER_TIMER_UNIT0_WORK_EN    (BIT(30))
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_M  (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_S  30
+
+/* SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
+ * timer unit1 work enable
+ */
+
+#define SYSTIMER_TIMER_UNIT1_WORK_EN    (BIT(29))
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_M  (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_S  29
+
+/* SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
+ * If timer unit0 is stalled when core0 stalled
+ */
+
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN    (BIT(28))
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S  28
+
+/* SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
+ * If timer unit0 is stalled when core1 stalled
+ */
+
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN    (BIT(27))
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S  27
+
+/* SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
+ * If timer unit1 is stalled when core0 stalled
+ */
+
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN    (BIT(26))
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S  26
+
+/* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
+ * If timer unit1 is stalled when core1 stalled
+ */
+
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN    (BIT(25))
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S  25
+
+/* SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
+ * target0 work enable
+ */
+
+#define SYSTIMER_TARGET0_WORK_EN    (BIT(24))
+#define SYSTIMER_TARGET0_WORK_EN_M  (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
+#define SYSTIMER_TARGET0_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET0_WORK_EN_S  24
+
+/* SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
+ * target1 work enable
+ */
+
+#define SYSTIMER_TARGET1_WORK_EN    (BIT(23))
+#define SYSTIMER_TARGET1_WORK_EN_M  (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
+#define SYSTIMER_TARGET1_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET1_WORK_EN_S  23
+
+/* SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
+ * target2 work enable
+ */
+
+#define SYSTIMER_TARGET2_WORK_EN    (BIT(22))
+#define SYSTIMER_TARGET2_WORK_EN_M  (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
+#define SYSTIMER_TARGET2_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET2_WORK_EN_S  22
+
+/* SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0;
+ * enable systimer's etm task and event
+ */
+
+#define SYSTIMER_ETM_EN    (BIT(1))
+#define SYSTIMER_ETM_EN_M  (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S)
+#define SYSTIMER_ETM_EN_V  0x00000001
+#define SYSTIMER_ETM_EN_S  1
+
+/* SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
+ * systimer clock force on
+ */
+
+#define SYSTIMER_SYSTIMER_CLK_FO    (BIT(0))
+#define SYSTIMER_SYSTIMER_CLK_FO_M  (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
+#define SYSTIMER_SYSTIMER_CLK_FO_V  0x00000001
+#define SYSTIMER_SYSTIMER_CLK_FO_S  0
+
+/* SYSTIMER_UNIT0_OP_REG register
+ * system timer unit0 value update register
+ */
+
+#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
+
+/* SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
+ * update timer_unit0
+ */
+
+#define SYSTIMER_TIMER_UNIT0_UPDATE    (BIT(30))
+#define SYSTIMER_TIMER_UNIT0_UPDATE_M  (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
+#define SYSTIMER_TIMER_UNIT0_UPDATE_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_UPDATE_S  30
+
+/* SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
+ * timer value is sync and valid
+ */
+
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID    (BIT(29))
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S  29
+
+/* SYSTIMER_UNIT1_OP_REG register
+ * system timer unit1 value update register
+ */
+
+#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
+
+/* SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
+ * update timer unit1
+ */
+
+#define SYSTIMER_TIMER_UNIT1_UPDATE    (BIT(30))
+#define SYSTIMER_TIMER_UNIT1_UPDATE_M  (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
+#define SYSTIMER_TIMER_UNIT1_UPDATE_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_UPDATE_S  30
+
+/* SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
+ * timer value is sync and valid
+ */
+
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID    (BIT(29))
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S  29
+
+/* SYSTIMER_UNIT0_LOAD_HI_REG register
+ * system timer unit0 value high load register
+ */
+
+#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
+
+/* SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
+ * timer unit0 load high 20 bits
+ */
+
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI    0x000fffff
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M  (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V  0x000fffff
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S  0
+
+/* SYSTIMER_UNIT0_LOAD_LO_REG register
+ * system timer unit0 value low load register
+ */
+
+#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
+
+/* SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ * timer unit0 load low 32 bits
+ */
+
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO    0xffffffff
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M  (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V  0xffffffff
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S  0
+
+/* SYSTIMER_UNIT1_LOAD_HI_REG register
+ * system timer unit1 value high load register
+ */
+
+#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
+
+/* SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
+ * timer unit1 load high 20 bits
+ */
+
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI    0x000fffff
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M  (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V  0x000fffff
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S  0
+
+/* SYSTIMER_UNIT1_LOAD_LO_REG register
+ * system timer unit1 value low load register
+ */
+
+#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
+
+/* SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ * timer unit1 load low 32 bits
+ */
+
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO    0xffffffff
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M  (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V  0xffffffff
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S  0
+
+/* SYSTIMER_TARGET0_HI_REG register
+ * system timer comp0 value high register
+ */
+
+#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
+
+/* SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
+ * timer taget0 high 20 bits
+ */
+
+#define SYSTIMER_TIMER_TARGET0_HI    0x000fffff
+#define SYSTIMER_TIMER_TARGET0_HI_M  (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
+#define SYSTIMER_TIMER_TARGET0_HI_V  0x000fffff
+#define SYSTIMER_TIMER_TARGET0_HI_S  0
+
+/* SYSTIMER_TARGET0_LO_REG register
+ * system timer comp0 value low register
+ */
+
+#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
+
+/* SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
+ * timer taget0 low 32 bits
+ */
+
+#define SYSTIMER_TIMER_TARGET0_LO    0xffffffff
+#define SYSTIMER_TIMER_TARGET0_LO_M  (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
+#define SYSTIMER_TIMER_TARGET0_LO_V  0xffffffff
+#define SYSTIMER_TIMER_TARGET0_LO_S  0
+
+/* SYSTIMER_TARGET1_HI_REG register
+ * system timer comp1 value high register
+ */
+
+#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
+
+/* SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
+ * timer taget1 high 20 bits
+ */
+
+#define SYSTIMER_TIMER_TARGET1_HI    0x000fffff
+#define SYSTIMER_TIMER_TARGET1_HI_M  (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
+#define SYSTIMER_TIMER_TARGET1_HI_V  0x000fffff
+#define SYSTIMER_TIMER_TARGET1_HI_S  0
+
+/* SYSTIMER_TARGET1_LO_REG register
+ * system timer comp1 value low register
+ */
+
+#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
+
+/* SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
+ * timer taget1 low 32 bits
+ */
+
+#define SYSTIMER_TIMER_TARGET1_LO    0xffffffff
+#define SYSTIMER_TIMER_TARGET1_LO_M  (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
+#define SYSTIMER_TIMER_TARGET1_LO_V  0xffffffff
+#define SYSTIMER_TIMER_TARGET1_LO_S  0
+
+/* SYSTIMER_TARGET2_HI_REG register
+ * system timer comp2 value high register
+ */
+
+#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
+
+/* SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
+ * timer taget2 high 20 bits
+ */
+
+#define SYSTIMER_TIMER_TARGET2_HI    0x000fffff
+#define SYSTIMER_TIMER_TARGET2_HI_M  (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
+#define SYSTIMER_TIMER_TARGET2_HI_V  0x000fffff
+#define SYSTIMER_TIMER_TARGET2_HI_S  0
+
+/* SYSTIMER_TARGET2_LO_REG register
+ * system timer comp2 value low register
+ */
+
+#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
+
+/* SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
+ * timer taget2 low 32 bits
+ */
+
+#define SYSTIMER_TIMER_TARGET2_LO    0xffffffff
+#define SYSTIMER_TIMER_TARGET2_LO_M  (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
+#define SYSTIMER_TIMER_TARGET2_LO_V  0xffffffff
+#define SYSTIMER_TIMER_TARGET2_LO_S  0
+
+/* SYSTIMER_TARGET0_CONF_REG register
+ * system timer comp0 target mode register
+ */
+
+#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
+
+/* SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ * select which unit to compare
+ */
+
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S  31
+
+/* SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ * Set target0 to period mode
+ */
+
+#define SYSTIMER_TARGET0_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET0_PERIOD_MODE_M  (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
+#define SYSTIMER_TARGET0_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET0_PERIOD_MODE_S  30
+
+/* SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ * target0 period
+ */
+
+#define SYSTIMER_TARGET0_PERIOD    0x03ffffff
+#define SYSTIMER_TARGET0_PERIOD_M  (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
+#define SYSTIMER_TARGET0_PERIOD_V  0x03ffffff
+#define SYSTIMER_TARGET0_PERIOD_S  0
+
+/* SYSTIMER_TARGET1_CONF_REG register
+ * system timer comp1 target mode register
+ */
+
+#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
+
+/* SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ * select which unit to compare
+ */
+
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S  31
+
+/* SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ * Set target1 to period mode
+ */
+
+#define SYSTIMER_TARGET1_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET1_PERIOD_MODE_M  (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
+#define SYSTIMER_TARGET1_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET1_PERIOD_MODE_S  30
+
+/* SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ * target1 period
+ */
+
+#define SYSTIMER_TARGET1_PERIOD    0x03ffffff
+#define SYSTIMER_TARGET1_PERIOD_M  (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
+#define SYSTIMER_TARGET1_PERIOD_V  0x03ffffff
+#define SYSTIMER_TARGET1_PERIOD_S  0
+
+/* SYSTIMER_TARGET2_CONF_REG register
+ * system timer comp2 target mode register
+ */
+
+#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
+
+/* SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ * select which unit to compare
+ */
+
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S  31
+
+/* SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ * Set target2 to period mode
+ */
+
+#define SYSTIMER_TARGET2_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET2_PERIOD_MODE_M  (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
+#define SYSTIMER_TARGET2_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET2_PERIOD_MODE_S  30
+
+/* SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ * target2 period
+ */
+
+#define SYSTIMER_TARGET2_PERIOD    0x03ffffff
+#define SYSTIMER_TARGET2_PERIOD_M  (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
+#define SYSTIMER_TARGET2_PERIOD_V  0x03ffffff
+#define SYSTIMER_TARGET2_PERIOD_S  0
+
+/* SYSTIMER_UNIT0_VALUE_HI_REG register
+ * system timer unit0 value high register
+ */
+
+#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
+
+/* SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
+ * timer read value high 20bits
+ */
+
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI    0x000fffff
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M  (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V  0x000fffff
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S  0
+
+/* SYSTIMER_UNIT0_VALUE_LO_REG register
+ * system timer unit0 value low register
+ */
+
+#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
+
+/* SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
+ * timer read value low 32bits
+ */
+
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO    0xffffffff
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M  (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V  0xffffffff
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S  0
+
+/* SYSTIMER_UNIT1_VALUE_HI_REG register
+ * system timer unit1 value high register
+ */
+
+#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
+
+/* SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
+ * timer read value high 20bits
+ */
+
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI    0x000fffff
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M  (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V  0x000fffff
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S  0
+
+/* SYSTIMER_UNIT1_VALUE_LO_REG register
+ * system timer unit1 value low register
+ */
+
+#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
+
+/* SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
+ * timer read value low 32bits
+ */
+
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO    0xffffffff
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M  (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V  0xffffffff
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S  0
+
+/* SYSTIMER_COMP0_LOAD_REG register
+ * system timer comp0 conf sync register
+ */
+
+#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
+
+/* SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
+ * timer comp0 sync enable signal
+ */
+
+#define SYSTIMER_TIMER_COMP0_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP0_LOAD_M  (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
+#define SYSTIMER_TIMER_COMP0_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP0_LOAD_S  0
+
+/* SYSTIMER_COMP1_LOAD_REG register
+ * system timer comp1 conf sync register
+ */
+
+#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
+
+/* SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
+ * timer comp1 sync enable signal
+ */
+
+#define SYSTIMER_TIMER_COMP1_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP1_LOAD_M  (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
+#define SYSTIMER_TIMER_COMP1_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP1_LOAD_S  0
+
+/* SYSTIMER_COMP2_LOAD_REG register
+ * system timer comp2 conf sync register
+ */
+
+#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
+
+/* SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
+ * timer comp2 sync enable signal
+ */
+
+#define SYSTIMER_TIMER_COMP2_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP2_LOAD_M  (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
+#define SYSTIMER_TIMER_COMP2_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP2_LOAD_S  0
+
+/* SYSTIMER_UNIT0_LOAD_REG register
+ * system timer unit0 conf sync register
+ */
+
+#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
+
+/* SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
+ * timer unit0 sync enable signal
+ */
+
+#define SYSTIMER_TIMER_UNIT0_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_UNIT0_LOAD_M  (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_LOAD_S  0
+
+/* SYSTIMER_UNIT1_LOAD_REG register
+ * system timer unit1 conf sync register
+ */
+
+#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
+
+/* SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
+ * timer unit1 sync enable signal
+ */
+
+#define SYSTIMER_TIMER_UNIT1_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_UNIT1_LOAD_M  (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_LOAD_S  0
+
+/* SYSTIMER_INT_ENA_REG register
+ * systimer interrupt enable register
+ */
+
+#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
+
+/* SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ * interupt2 enable
+ */
+
+#define SYSTIMER_TARGET2_INT_ENA    (BIT(2))
+#define SYSTIMER_TARGET2_INT_ENA_M  (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
+#define SYSTIMER_TARGET2_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET2_INT_ENA_S  2
+
+/* SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ * interupt1 enable
+ */
+
+#define SYSTIMER_TARGET1_INT_ENA    (BIT(1))
+#define SYSTIMER_TARGET1_INT_ENA_M  (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
+#define SYSTIMER_TARGET1_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET1_INT_ENA_S  1
+
+/* SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ * interupt0 enable
+ */
+
+#define SYSTIMER_TARGET0_INT_ENA    (BIT(0))
+#define SYSTIMER_TARGET0_INT_ENA_M  (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
+#define SYSTIMER_TARGET0_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET0_INT_ENA_S  0
+
+/* SYSTIMER_INT_RAW_REG register
+ * systimer interrupt raw register
+ */
+
+#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
+
+/* SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ * interupt2 raw
+ */
+
+#define SYSTIMER_TARGET2_INT_RAW    (BIT(2))
+#define SYSTIMER_TARGET2_INT_RAW_M  (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
+#define SYSTIMER_TARGET2_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET2_INT_RAW_S  2
+
+/* SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ * interupt1 raw
+ */
+
+#define SYSTIMER_TARGET1_INT_RAW    (BIT(1))
+#define SYSTIMER_TARGET1_INT_RAW_M  (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
+#define SYSTIMER_TARGET1_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET1_INT_RAW_S  1
+
+/* SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ * interupt0 raw
+ */
+
+#define SYSTIMER_TARGET0_INT_RAW    (BIT(0))
+#define SYSTIMER_TARGET0_INT_RAW_M  (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
+#define SYSTIMER_TARGET0_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET0_INT_RAW_S  0
+
+/* SYSTIMER_INT_CLR_REG register
+ * systimer interrupt clear register
+ */
+
+#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
+
+/* SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
+ * interupt2 clear
+ */
+
+#define SYSTIMER_TARGET2_INT_CLR    (BIT(2))
+#define SYSTIMER_TARGET2_INT_CLR_M  (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
+#define SYSTIMER_TARGET2_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET2_INT_CLR_S  2
+
+/* SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
+ * interupt1 clear
+ */
+
+#define SYSTIMER_TARGET1_INT_CLR    (BIT(1))
+#define SYSTIMER_TARGET1_INT_CLR_M  (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
+#define SYSTIMER_TARGET1_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET1_INT_CLR_S  1
+
+/* SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
+ * interupt0 clear
+ */
+
+#define SYSTIMER_TARGET0_INT_CLR    (BIT(0))
+#define SYSTIMER_TARGET0_INT_CLR_M  (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
+#define SYSTIMER_TARGET0_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET0_INT_CLR_S  0
+
+/* SYSTIMER_INT_ST_REG register
+ * systimer interrupt status register
+ */
+
+#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
+
+/* SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
+ * interupt2 status
+ */
+
+#define SYSTIMER_TARGET2_INT_ST    (BIT(2))
+#define SYSTIMER_TARGET2_INT_ST_M  (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
+#define SYSTIMER_TARGET2_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET2_INT_ST_S  2
+
+/* SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
+ * interupt1 status
+ */
+
+#define SYSTIMER_TARGET1_INT_ST    (BIT(1))
+#define SYSTIMER_TARGET1_INT_ST_M  (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
+#define SYSTIMER_TARGET1_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET1_INT_ST_S  1
+
+/* SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
+ * interupt0 status
+ */
+
+#define SYSTIMER_TARGET0_INT_ST    (BIT(0))
+#define SYSTIMER_TARGET0_INT_ST_M  (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
+#define SYSTIMER_TARGET0_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET0_INT_ST_S  0
+
+/* SYSTIMER_REAL_TARGET0_LO_REG register
+ * system timer comp0 actual target value low register
+ */
+
+#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
+
+/* SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
+ * actual target value value low 32bits
+ */
+
+#define SYSTIMER_TARGET0_LO_RO    0xffffffff
+#define SYSTIMER_TARGET0_LO_RO_M  (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
+#define SYSTIMER_TARGET0_LO_RO_V  0xffffffff
+#define SYSTIMER_TARGET0_LO_RO_S  0
+
+/* SYSTIMER_REAL_TARGET0_HI_REG register
+ * system timer comp0 actual target value high register
+ */
+
+#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
+
+/* SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
+ * actual target value value high 20bits
+ */
+
+#define SYSTIMER_TARGET0_HI_RO    0x000fffff
+#define SYSTIMER_TARGET0_HI_RO_M  (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
+#define SYSTIMER_TARGET0_HI_RO_V  0x000fffff
+#define SYSTIMER_TARGET0_HI_RO_S  0
+
+/* SYSTIMER_REAL_TARGET1_LO_REG register
+ * system timer comp1 actual target value low register
+ */
+
+#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
+
+/* SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
+ * actual target value value low 32bits
+ */
+
+#define SYSTIMER_TARGET1_LO_RO    0xffffffff
+#define SYSTIMER_TARGET1_LO_RO_M  (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
+#define SYSTIMER_TARGET1_LO_RO_V  0xffffffff
+#define SYSTIMER_TARGET1_LO_RO_S  0
+
+/* SYSTIMER_REAL_TARGET1_HI_REG register
+ * system timer comp1 actual target value high register
+ */
+
+#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
+
+/* SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
+ * actual target value value high 20bits
+ */
+
+#define SYSTIMER_TARGET1_HI_RO    0x000fffff
+#define SYSTIMER_TARGET1_HI_RO_M  (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
+#define SYSTIMER_TARGET1_HI_RO_V  0x000fffff
+#define SYSTIMER_TARGET1_HI_RO_S  0
+
+/* SYSTIMER_REAL_TARGET2_LO_REG register
+ * system timer comp2 actual target value low register
+ */
+
+#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
+
+/* SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
+ * actual target value value low 32bits
+ */
+
+#define SYSTIMER_TARGET2_LO_RO    0xffffffff
+#define SYSTIMER_TARGET2_LO_RO_M  (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
+#define SYSTIMER_TARGET2_LO_RO_V  0xffffffff
+#define SYSTIMER_TARGET2_LO_RO_S  0
+
+/* SYSTIMER_REAL_TARGET2_HI_REG register
+ * system timer comp2 actual target value high register
+ */
+
+#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
+
+/* SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
+ * actual target value value high 20bits
+ */
+
+#define SYSTIMER_TARGET2_HI_RO    0x000fffff
+#define SYSTIMER_TARGET2_HI_RO_M  (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
+#define SYSTIMER_TARGET2_HI_RO_V  0x000fffff
+#define SYSTIMER_TARGET2_HI_RO_S  0
+
+/* SYSTIMER_DATE_REG register
+ * system timer version control register
+ */
+
+#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
+
+/* SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795;
+ * systimer register version
+ */
+
+#define SYSTIMER_DATE    0xffffffff
+#define SYSTIMER_DATE_M  (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
+#define SYSTIMER_DATE_V  0xffffffff
+#define SYSTIMER_DATE_S  0
+
+#endif /* __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_SYSTIMER_H */

boards/Kconfig

@@ -409,6 +409,15 @@ config ARCH_BOARD_ET_STM32_STAMP
 		The ET-STM32 Stamp features the STM32F103RET6 (Cortex M3) microcontroller.
 		For board details, see: https://www.futurlec.com/ET-STM32_Stamp.shtml
 
+config ARCH_BOARD_ESP32C6_DEVKIT
+	bool "Espressif ESP32-C6 DevKit"
+	depends on ARCH_CHIP_ESP32C6MINI1 || ARCH_CHIP_ESP32C6WROOM1
+	---help---
+		The ESP32-C6 DevKit features the ESP32-C6 CPU with a RISC-V core.
+		It comes in two flavors, the ESP32-C6-DevKitM-1 and the ESP32-C6-DevKitC-02.
+		The ESP32-C6-DevKitM-1 version contains the ESP32-C6-MINI-1 module and the
+		ESP32-C6-DevKitC-02 version the ESP32-C6-WROOM-1.
+
 config ARCH_BOARD_EZ80F910200KITG
 	bool "ZiLOG ez80f910200kitg development kit"
 	depends on ARCH_CHIP_EZ80F91
@@ -2749,6 +2758,7 @@ config ARCH_BOARD
 	default "franzininho-wifi"          if ARCH_BOARD_FRANZININHO_WIFI
 	default "esp32s3-devkit"            if ARCH_BOARD_ESP32S3_DEVKIT
 	default "esp32s3-eye"               if ARCH_BOARD_ESP32S3_EYE
+	default "esp32c6-devkit"            if ARCH_BOARD_ESP32C6_DEVKIT
 	default "et-stm32-stamp"            if ARCH_BOARD_ET_STM32_STAMP
 	default "tlsr8278adk80d"            if ARCH_BOARD_TLSR8278ADK80D
 	default "ez80f910200kitg"           if ARCH_BOARD_EZ80F910200KITG
@@ -3730,6 +3740,9 @@ endif
 if ARCH_BOARD_ESP32S3_EYE
 source "boards/xtensa/esp32s3/esp32s3-eye/Kconfig"
 endif
+if ARCH_BOARD_ESP32C6_DEVKIT
+source "boards/risc-v/esp32c6/esp32c6-devkit/Kconfig"
+endif
 if ARCH_BOARD_SIM
 source "boards/sim/sim/sim/Kconfig"
 endif

boards/risc-v/esp32c6/common/Makefile

@@ -0,0 +1,29 @@
+#############################################################################
+# boards/risc-v/esp32c6/common/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+#############################################################################
+
+include $(TOPDIR)/Make.defs
+
+include board/Make.defs
+
+DEPPATH += --dep-path board
+
+include $(TOPDIR)/boards/Board.mk
+
+BOARDDIR = $(ARCHSRCDIR)$(DELIM)board

boards/risc-v/esp32c6/common/scripts/.gitignore

@@ -0,0 +1,2 @@
+/*.ld.tmp
+

boards/risc-v/esp32c6/common/scripts/esp32c6_rom.ld

@@ -0,0 +1,517 @@
+/****************************************************************************
+ * boards/risc-v/esp32c6/common/scripts/esp32c6_rom.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* ROM function interface esp32c6_rom.ld for esp32c6
+ *
+ *
+ * Generated from ./interface-esp32c6.yml md5sum 93b28a9e1fe42d212018eb4336849208
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group common
+ ***************************************/
+
+/* Functions */
+rtc_get_reset_reason = 0x40000018;
+analog_super_wdt_reset_happened = 0x4000001c;
+rtc_get_wakeup_cause = 0x40000020;
+rtc_unhold_all_pads = 0x40000024;
+ets_printf = 0x40000028;
+ets_install_putc1 = 0x4000002c;
+ets_install_putc2 = 0x40000030;
+ets_install_uart_printf = 0x40000034;
+ets_install_usb_printf = 0x40000038;
+ets_get_printf_channel = 0x4000003c;
+ets_delay_us = 0x40000040;
+ets_get_cpu_frequency = 0x40000044;
+ets_update_cpu_frequency = 0x40000048;
+ets_install_lock = 0x4000004c;
+UartRxString = 0x40000050;
+UartGetCmdLn = 0x40000054;
+uart_tx_one_char = 0x40000058;
+uart_tx_one_char2 = 0x4000005c;
+uart_rx_one_char = 0x40000060;
+uart_rx_one_char_block = 0x40000064;
+uart_rx_intr_handler = 0x40000068;
+uart_rx_readbuff = 0x4000006c;
+uartAttach = 0x40000070;
+uart_tx_flush = 0x40000074;
+uart_tx_wait_idle = 0x40000078;
+uart_div_modify = 0x4000007c;
+ets_write_char_uart = 0x40000080;
+uart_tx_switch = 0x40000084;
+roundup2 = 0x40000088;
+multofup = 0x4000008c;
+software_reset = 0x40000090;
+software_reset_cpu = 0x40000094;
+ets_clk_assist_debug_clock_enable = 0x40000098;
+clear_super_wdt_reset_flag = 0x4000009c;
+disable_default_watchdog = 0x400000a0;
+esp_rom_set_rtc_wake_addr = 0x400000a4;
+esp_rom_get_rtc_wake_addr = 0x400000a8;
+send_packet = 0x400000ac;
+recv_packet = 0x400000b0;
+GetUartDevice = 0x400000b4;
+UartDwnLdProc = 0x400000b8;
+GetSecurityInfoProc = 0x400000bc;
+Uart_Init = 0x400000c0;
+ets_set_user_start = 0x400000c4;
+/* Data (.data, .bss, .rodata) */
+ets_rom_layout_p = 0x4004fffc;
+ets_ops_table_ptr = 0x4087fff8;
+g_saved_pc = 0x4087fffc;
+
+
+/***************************************
+ Group miniz
+ ***************************************/
+
+/* Functions */
+mz_adler32 = 0x400000c8;
+mz_free = 0x400000cc;
+tdefl_compress = 0x400000d0;
+tdefl_compress_buffer = 0x400000d4;
+tdefl_compress_mem_to_heap = 0x400000d8;
+tdefl_compress_mem_to_mem = 0x400000dc;
+tdefl_compress_mem_to_output = 0x400000e0;
+tdefl_get_adler32 = 0x400000e4;
+tdefl_get_prev_return_status = 0x400000e8;
+tdefl_init = 0x400000ec;
+tdefl_write_image_to_png_file_in_memory = 0x400000f0;
+tdefl_write_image_to_png_file_in_memory_ex = 0x400000f4;
+tinfl_decompress = 0x400000f8;
+tinfl_decompress_mem_to_callback = 0x400000fc;
+tinfl_decompress_mem_to_heap = 0x40000100;
+tinfl_decompress_mem_to_mem = 0x40000104;
+
+
+/***************************************
+ Group tjpgd
+ ***************************************/
+
+/* Functions */
+jd_prepare = 0x40000108;
+jd_decomp = 0x4000010c;
+
+
+/***************************************
+ Group spiflash_legacy
+ ***************************************/
+
+/* Functions */
+esp_rom_spiflash_wait_idle = 0x40000110;
+esp_rom_spiflash_write_encrypted = 0x40000114;
+esp_rom_spiflash_write_encrypted_dest = 0x40000118;
+esp_rom_spiflash_write_encrypted_enable = 0x4000011c;
+esp_rom_spiflash_write_encrypted_disable = 0x40000120;
+esp_rom_spiflash_erase_chip = 0x40000124;
+_esp_rom_spiflash_erase_sector = 0x40000128;
+_esp_rom_spiflash_erase_block = 0x4000012c;
+_esp_rom_spiflash_write = 0x40000130;
+_esp_rom_spiflash_read = 0x40000134;
+_esp_rom_spiflash_unlock = 0x40000138;
+_SPIEraseArea = 0x4000013c;
+_SPI_write_enable = 0x40000140;
+esp_rom_spiflash_erase_sector = 0x40000144;
+esp_rom_spiflash_erase_block = 0x40000148;
+esp_rom_spiflash_write = 0x4000014c;
+esp_rom_spiflash_read = 0x40000150;
+esp_rom_spiflash_unlock = 0x40000154;
+SPIEraseArea = 0x40000158;
+SPI_write_enable = 0x4000015c;
+esp_rom_spiflash_config_param = 0x40000160;
+esp_rom_spiflash_read_user_cmd = 0x40000164;
+esp_rom_spiflash_select_qio_pins = 0x40000168;
+esp_rom_spi_flash_auto_sus_res = 0x4000016c;
+esp_rom_spi_flash_send_resume = 0x40000170;
+esp_rom_spi_flash_update_id = 0x40000174;
+esp_rom_spiflash_config_clk = 0x40000178;
+esp_rom_spiflash_config_readmode = 0x4000017c;
+esp_rom_spiflash_read_status = 0x40000180;
+esp_rom_spiflash_read_statushigh = 0x40000184;
+esp_rom_spiflash_write_status = 0x40000188;
+spi_cache_mode_switch = 0x4000018c;
+spi_common_set_dummy_output = 0x40000190;
+spi_common_set_flash_cs_timing = 0x40000194;
+esp_rom_spi_set_address_bit_len = 0x40000198;
+SPILock = 0x4000019c;
+SPIMasterReadModeCnfig = 0x400001a0;
+SPI_Common_Command = 0x400001a4;
+SPI_WakeUp = 0x400001a8;
+SPI_block_erase = 0x400001ac;
+SPI_chip_erase = 0x400001b0;
+SPI_init = 0x400001b4;
+SPI_page_program = 0x400001b8;
+SPI_read_data = 0x400001bc;
+SPI_sector_erase = 0x400001c0;
+SelectSpiFunction = 0x400001c4;
+SetSpiDrvs = 0x400001c8;
+Wait_SPI_Idle = 0x400001cc;
+spi_dummy_len_fix = 0x400001d0;
+Disable_QMode = 0x400001d4;
+Enable_QMode = 0x400001d8;
+spi_flash_attach = 0x400001dc;
+spi_flash_get_chip_size = 0x400001e0;
+spi_flash_guard_set = 0x400001e4;
+spi_flash_guard_get = 0x400001e8;
+spi_flash_read_encrypted = 0x400001ec;
+/* Data (.data, .bss, .rodata) */
+rom_spiflash_legacy_funcs = 0x4087fff0;
+rom_spiflash_legacy_data = 0x4087ffec;
+g_flash_guard_ops = 0x4087fff4;
+
+/* Note: esp_rom_spiflash_write_disable was moved from esp32c6.rom.spiflash.ld */
+esp_rom_spiflash_write_disable = 0x40000278;
+
+/***************************************
+ Group hal_wdt
+ ***************************************/
+
+/* Functions */
+wdt_hal_init = 0x40000394;
+wdt_hal_deinit = 0x40000398;
+wdt_hal_config_stage = 0x4000039c;
+wdt_hal_write_protect_disable = 0x400003a0;
+wdt_hal_write_protect_enable = 0x400003a4;
+wdt_hal_enable = 0x400003a8;
+wdt_hal_disable = 0x400003ac;
+wdt_hal_handle_intr = 0x400003b0;
+wdt_hal_feed = 0x400003b4;
+wdt_hal_set_flashboot_en = 0x400003b8;
+wdt_hal_is_enabled = 0x400003bc;
+
+
+/***************************************
+ Group hal_systimer
+ ***************************************/
+
+/* Functions */
+/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
+/* systimer_hal_init = 0x400003c0; */
+/* systimer_hal_deinit = 0x400003c4; */
+
+systimer_hal_set_tick_rate_ops = 0x400003c8;
+systimer_hal_get_counter_value = 0x400003cc;
+systimer_hal_get_time = 0x400003d0;
+systimer_hal_set_alarm_target = 0x400003d4;
+systimer_hal_set_alarm_period = 0x400003d8;
+systimer_hal_get_alarm_value = 0x400003dc;
+systimer_hal_enable_alarm_int = 0x400003e0;
+systimer_hal_on_apb_freq_update = 0x400003e4;
+systimer_hal_counter_value_advance = 0x400003e8;
+systimer_hal_enable_counter = 0x400003ec;
+systimer_hal_select_alarm_mode = 0x400003f0;
+systimer_hal_connect_alarm_counter = 0x400003f4;
+systimer_hal_counter_can_stall_by_cpu = 0x400003f8;
+
+
+/***************************************
+ Group cache
+ ***************************************/
+
+/* Functions */
+Cache_Get_ICache_Line_Size = 0x40000628;
+Cache_Get_Mode = 0x4000062c;
+Cache_Address_Through_Cache = 0x40000630;
+ROM_Boot_Cache_Init = 0x40000634;
+MMU_Set_Page_Mode = 0x40000638;
+MMU_Get_Page_Mode = 0x4000063c;
+Cache_Invalidate_ICache_Items = 0x40000640;
+Cache_Op_Addr = 0x40000644;
+Cache_Invalidate_Addr = 0x40000648;
+Cache_Invalidate_ICache_All = 0x4000064c;
+Cache_Mask_All = 0x40000650;
+Cache_UnMask_Dram0 = 0x40000654;
+Cache_Suspend_ICache_Autoload = 0x40000658;
+Cache_Resume_ICache_Autoload = 0x4000065c;
+Cache_Start_ICache_Preload = 0x40000660;
+Cache_ICache_Preload_Done = 0x40000664;
+Cache_End_ICache_Preload = 0x40000668;
+Cache_Config_ICache_Autoload = 0x4000066c;
+Cache_Enable_ICache_Autoload = 0x40000670;
+Cache_Disable_ICache_Autoload = 0x40000674;
+Cache_Enable_ICache_PreLock = 0x40000678;
+Cache_Disable_ICache_PreLock = 0x4000067c;
+Cache_Lock_ICache_Items = 0x40000680;
+Cache_Unlock_ICache_Items = 0x40000684;
+Cache_Lock_Addr = 0x40000688;
+Cache_Unlock_Addr = 0x4000068c;
+Cache_Disable_ICache = 0x40000690;
+Cache_Enable_ICache = 0x40000694;
+Cache_Suspend_ICache = 0x40000698;
+Cache_Resume_ICache = 0x4000069c;
+Cache_Freeze_ICache_Enable = 0x400006a0;
+Cache_Freeze_ICache_Disable = 0x400006a4;
+Cache_Set_IDROM_MMU_Size = 0x400006a8;
+Cache_Get_IROM_MMU_End = 0x400006ac;
+Cache_Get_DROM_MMU_End = 0x400006b0;
+Cache_MMU_Init = 0x400006b4;
+Cache_MSPI_MMU_Set = 0x400006b8;
+Cache_Travel_Tag_Memory = 0x400006bc;
+Cache_Get_Virtual_Addr = 0x400006c0;
+/* Data (.data, .bss, .rodata) */
+rom_cache_op_cb = 0x4087ffcc;
+rom_cache_internal_table_ptr = 0x4087ffc8;
+
+
+/***************************************
+ Group clock
+ ***************************************/
+
+/* Functions */
+ets_clk_get_xtal_freq = 0x400006c4;
+ets_clk_get_cpu_freq = 0x400006c8;
+ets_clk_apb_wait_ready = 0x400006cc;
+ets_clk_mspi_apb_wait_ready = 0x400006d0;
+
+
+/***************************************
+ Group gpio
+ ***************************************/
+
+/* Functions */
+gpio_input_get = 0x400006d4;
+gpio_matrix_in = 0x400006d8;
+gpio_matrix_out = 0x400006dc;
+gpio_output_disable = 0x400006e0;
+gpio_output_enable = 0x400006e4;
+gpio_output_set = 0x400006e8;
+gpio_pad_hold = 0x400006ec;
+gpio_pad_input_disable = 0x400006f0;
+gpio_pad_input_enable = 0x400006f4;
+gpio_pad_pulldown = 0x400006f8;
+gpio_pad_pullup = 0x400006fc;
+gpio_pad_select_gpio = 0x40000700;
+gpio_pad_set_drv = 0x40000704;
+gpio_pad_unhold = 0x40000708;
+gpio_pin_wakeup_disable = 0x4000070c;
+gpio_pin_wakeup_enable = 0x40000710;
+gpio_bypass_matrix_in = 0x40000714;
+
+
+/***************************************
+ Group interrupts
+ ***************************************/
+
+/* Functions */
+esprv_intc_int_set_priority = 0x40000718;
+esprv_intc_int_set_threshold = 0x4000071c;
+esprv_intc_int_enable = 0x40000720;
+esprv_intc_int_disable = 0x40000724;
+esprv_intc_int_set_type = 0x40000728;
+PROVIDE( intr_handler_set = 0x4000072c );
+intr_matrix_set = 0x40000730;
+ets_intr_lock = 0x40000734;
+ets_intr_unlock = 0x40000738;
+ets_isr_attach = 0x4000073c;
+ets_isr_mask = 0x40000740;
+ets_isr_unmask = 0x40000744;
+
+
+/***************************************
+ Group crypto
+ ***************************************/
+
+/* Functions */
+md5_vector = 0x40000748;
+MD5Init = 0x4000074c;
+MD5Update = 0x40000750;
+MD5Final = 0x40000754;
+crc32_le = 0x40000758;
+crc16_le = 0x4000075c;
+crc8_le = 0x40000760;
+crc32_be = 0x40000764;
+crc16_be = 0x40000768;
+crc8_be = 0x4000076c;
+esp_crc8 = 0x40000770;
+ets_sha_enable = 0x40000774;
+ets_sha_disable = 0x40000778;
+ets_sha_get_state = 0x4000077c;
+ets_sha_init = 0x40000780;
+ets_sha_process = 0x40000784;
+ets_sha_starts = 0x40000788;
+ets_sha_update = 0x4000078c;
+ets_sha_finish = 0x40000790;
+ets_sha_clone = 0x40000794;
+ets_hmac_enable = 0x40000798;
+ets_hmac_disable = 0x4000079c;
+ets_hmac_calculate_message = 0x400007a0;
+ets_hmac_calculate_downstream = 0x400007a4;
+ets_hmac_invalidate_downstream = 0x400007a8;
+ets_jtag_enable_temporarily = 0x400007ac;
+ets_aes_enable = 0x400007b0;
+ets_aes_disable = 0x400007b4;
+ets_aes_setkey = 0x400007b8;
+ets_aes_block = 0x400007bc;
+ets_aes_setkey_dec = 0x400007c0;
+ets_aes_setkey_enc = 0x400007c4;
+ets_bigint_enable = 0x400007c8;
+ets_bigint_disable = 0x400007cc;
+ets_bigint_multiply = 0x400007d0;
+ets_bigint_modmult = 0x400007d4;
+ets_bigint_modexp = 0x400007d8;
+ets_bigint_wait_finish = 0x400007dc;
+ets_bigint_getz = 0x400007e0;
+ets_ds_enable = 0x400007e4;
+ets_ds_disable = 0x400007e8;
+ets_ds_start_sign = 0x400007ec;
+ets_ds_is_busy = 0x400007f0;
+ets_ds_finish_sign = 0x400007f4;
+ets_ds_encrypt_params = 0x400007f8;
+ets_mgf1_sha256 = 0x400007fc;
+/* Data (.data, .bss, .rodata) */
+crc32_le_table_ptr = 0x4004fff8;
+crc16_le_table_ptr = 0x4004fff4;
+crc8_le_table_ptr = 0x4004fff0;
+crc32_be_table_ptr = 0x4004ffec;
+crc16_be_table_ptr = 0x4004ffe8;
+crc8_be_table_ptr = 0x4004ffe4;
+
+
+/***************************************
+ Group efuse
+ ***************************************/
+
+/* Functions */
+ets_efuse_read = 0x40000800;
+ets_efuse_program = 0x40000804;
+ets_efuse_clear_program_registers = 0x40000808;
+ets_efuse_write_key = 0x4000080c;
+ets_efuse_get_read_register_address = 0x40000810;
+ets_efuse_get_key_purpose = 0x40000814;
+ets_efuse_key_block_unused = 0x40000818;
+ets_efuse_find_unused_key_block = 0x4000081c;
+ets_efuse_rs_calculate = 0x40000820;
+ets_efuse_count_unused_key_blocks = 0x40000824;
+ets_efuse_secure_boot_enabled = 0x40000828;
+ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4000082c;
+ets_efuse_cache_encryption_enabled = 0x40000830;
+ets_efuse_download_modes_disabled = 0x40000834;
+ets_efuse_find_purpose = 0x40000838;
+ets_efuse_force_send_resume = 0x4000083c;
+ets_efuse_get_flash_delay_us = 0x40000840;
+ets_efuse_get_mac = 0x40000844;
+ets_efuse_get_uart_print_control = 0x40000848;
+ets_efuse_direct_boot_mode_disabled = 0x4000084c;
+ets_efuse_security_download_modes_enabled = 0x40000850;
+ets_efuse_set_timing = 0x40000854;
+ets_efuse_jtag_disabled = 0x40000858;
+ets_efuse_usb_print_is_disabled = 0x4000085c;
+ets_efuse_usb_download_mode_disabled = 0x40000860;
+ets_efuse_usb_device_disabled = 0x40000864;
+ets_efuse_secure_boot_fast_wake_enabled = 0x40000868;
+
+
+/***************************************
+ Group secureboot
+ ***************************************/
+
+/* Functions */
+ets_emsa_pss_verify = 0x4000086c;
+ets_rsa_pss_verify = 0x40000870;
+ets_secure_boot_verify_bootloader_with_keys = 0x40000874;
+ets_secure_boot_verify_signature = 0x40000878;
+ets_secure_boot_read_key_digests = 0x4000087c;
+ets_secure_boot_revoke_public_key_digest = 0x40000880;
+
+
+/***************************************
+ Group usb_device_uart
+ ***************************************/
+
+/* Functions */
+usb_serial_device_rx_one_char = 0x40000a80;
+usb_serial_device_rx_one_char_block = 0x40000a84;
+usb_serial_device_tx_flush = 0x40000a88;
+usb_serial_device_tx_one_char = 0x40000a8c;
+
+
+/***************************************
+ Group lldesc
+ ***************************************/
+
+/* Functions */
+lldesc_build_chain = 0x40000a90;
+
+
+/***************************************
+ Group sip
+ ***************************************/
+
+/* Functions */
+sip_after_tx_complete = 0x40000a94;
+sip_alloc_to_host_evt = 0x40000a98;
+sip_download_begin = 0x40000a9c;
+sip_get_ptr = 0x40000aa0;
+sip_get_state = 0x40000aa4;
+sip_init_attach = 0x40000aa8;
+sip_install_rx_ctrl_cb = 0x40000aac;
+sip_install_rx_data_cb = 0x40000ab0;
+sip_is_active = 0x40000ab4;
+sip_post_init = 0x40000ab8;
+sip_reclaim_from_host_cmd = 0x40000abc;
+sip_reclaim_tx_data_pkt = 0x40000ac0;
+sip_send = 0x40000ac4;
+sip_to_host_chain_append = 0x40000ac8;
+sip_to_host_evt_send_done = 0x40000acc;
+
+
+/***************************************
+ Group slc
+ ***************************************/
+
+/* Functions */
+slc_add_credits = 0x40000ad0;
+slc_enable = 0x40000ad4;
+slc_from_host_chain_fetch = 0x40000ad8;
+slc_from_host_chain_recycle = 0x40000adc;
+slc_has_pkt_to_host = 0x40000ae0;
+slc_init_attach = 0x40000ae4;
+slc_init_credit = 0x40000ae8;
+slc_reattach = 0x40000aec;
+slc_send_to_host_chain = 0x40000af0;
+slc_set_host_io_max_window = 0x40000af4;
+slc_to_host_chain_recycle = 0x40000af8;
+
+/***************************************
+ Group memory and string
+ ***************************************/
+
+memset = 0x400004a8;
+memcpy = 0x400004ac;
+memmove = 0x400004b0;
+memcmp = 0x400004b4;
+memccpy = 0x40000518;
+memchr = 0x4000051c;
+memrchr = 0x40000520;
+strcpy = 0x400004b8;
+strncpy = 0x400004bc;
+strcmp = 0x400004c0;
+strncmp = 0x400004c4;
+strlen = 0x400004c8;
+strstr = 0x400004cc;
+strchr = 0x40000534;
+strlcpy = 0x40000544;
+strnlen = 0x40000558;
+bzero = 0x400004d0;

boards/risc-v/esp32c6/common/scripts/flat_memory.ld

@@ -0,0 +1,104 @@
+/****************************************************************************
+ * boards/risc-v/esp32c6/common/scripts/flat_memory.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * This file describes the memory layout (memory blocks) as virtual
+ * memory addresses.
+ *
+ * legacy_sections.ld contains output sections to link compiler
+ * output into these memory blocks.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#define SRAM_IRAM_START     0x40800000
+#define SRAM_DRAM_START     0x40800000
+
+#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)
+
+/* 2nd stage bootloader iram_loader_seg start address */
+
+#define SRAM_DRAM_END       0x40880000 - I_D_SRAM_OFFSET
+
+#define SRAM_IRAM_ORG       (SRAM_IRAM_START)
+#define SRAM_DRAM_ORG       (SRAM_DRAM_START)
+
+#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG
+
+/* IDRAM0_2_SEG_SIZE_DEFAULT is used when page size is 64KB */
+
+#define CONFIG_MMU_PAGE_SIZE 0x10000
+#define IDRAM0_2_SEG_SIZE   (CONFIG_MMU_PAGE_SIZE << 8)
+
+#define DRAM0_0_SEG_LEN     I_D_SRAM_SIZE
+
+MEMORY
+{
+  /* All these values assume the flash cache is on, and have the blocks it
+   * uses subtracted from the length of the various regions. The 'data access
+   * port' dram/drom regions map to the same iram/irom regions but are 
+   * connected to the data port of the CPU and eg allow byte-wise access.
+   */
+
+  iram0_0_seg (RX) :      org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
+
+  /* Flash mapped instruction data.
+   *
+   * The 0x20 offset is a convenience for the app binary image generation.
+   * Flash cache has 64KB pages. The .bin file which is flashed to the chip
+   * has a 0x18 byte file header, and each segment has a 0x08 byte segment
+   * header. Setting this offset makes it simple to meet the flash cache MMU's
+   * constraint that (paddr % 64KB == vaddr % 64KB).
+   */
+
+  irom0_0_seg (RX) :      org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
+
+  /* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
+   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease
+   * the amount of RAM available.
+   */
+
+  dram0_0_seg (RW) :      org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
+
+  /* Flash mapped constant data */
+
+  drom0_0_seg (R) :       org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
+
+  /* RTC fast memory (executable). Persists over deep sleep. */
+
+  rtc_iram_seg(RWX) :     org = 0x50000000, len = 0x4000
+
+}
+
+/* Heap ends at the start of the static data of the ROM bootloader */
+
+_eheap = 0x4086ad08;
+
+#if CONFIG_ESP32C6_DEVKIT_RUN_IRAM
+  REGION_ALIAS("default_rodata_seg", dram0_0_seg);
+  REGION_ALIAS("default_code_seg", iram0_0_seg);
+#else
+  REGION_ALIAS("default_rodata_seg", drom0_0_seg);
+  REGION_ALIAS("default_code_seg", irom0_0_seg);
+#endif /* CONFIG_ESP32C6_DEVKIT_RUN_IRAM */
+  REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
+  REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
+  REGION_ALIAS("rtc_data_location", rtc_iram_seg );

boards/risc-v/esp32c6/common/scripts/legacy_sections.ld

@@ -0,0 +1,232 @@
+/****************************************************************************
+ * boards/risc-v/esp32c6/common/scripts/legacy_sections.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Default entry point: */
+
+ENTRY(__start);
+
+SECTIONS
+{
+  .iram0.text :
+  {
+    _iram_start = ABSOLUTE(.);
+
+    /* Vectors go to start of IRAM */
+
+    KEEP(*(.exception_vectors.text));
+    . = ALIGN(4);
+
+    *(.iram1)
+    *(.iram1.*)
+
+  } >iram0_0_seg
+
+  /* Marks the end of IRAM code segment */
+
+  .iram0.text_end (NOLOAD) :
+  {
+    . = ALIGN (16);
+  } >iram0_0_seg
+
+  .iram0.data :
+  {
+    . = ALIGN(16);
+    *(.iram.data)
+    *(.iram.data*)
+  } >iram0_0_seg
+
+  .iram0.bss (NOLOAD) :
+  {
+    . = ALIGN(16);
+    *(.iram.bss)
+    *(.iram.bss*)
+
+    . = ALIGN(16);
+    _iram_end = ABSOLUTE(.);
+  } >iram0_0_seg
+
+  /* This section is required to skip .iram0.text area because iram0_0_seg
+   * and dram0_0_seg reflect the same address space on different buses.
+   */
+
+  .dram0.dummy (NOLOAD):
+  {
+    . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
+  } >dram0_0_seg
+
+  /* Shared RAM */
+
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _sbss = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(.bss.*)
+    *(.share.mem)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+
+    . = ALIGN (8);
+    _ebss = ABSOLUTE(.);
+
+   /* Uninitialized .bss */
+
+    *(.noinit)
+    *(.noinit.*)
+
+  } >dram0_0_seg
+
+  .dram0.data :
+  {
+    _sdata = ABSOLUTE(.);
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    *(.data1)
+    __global_pointer$ = . + 0x800;
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    *(.jcr)
+    *(.dram1)
+    *(.dram1.*)
+    . = ALIGN(4);
+    _edata = ABSOLUTE(.);
+
+    /* Heap starts at the end of .data */
+
+    _sheap = ABSOLUTE(.);
+  } >dram0_0_seg
+
+  .flash.text :
+  {
+    _stext = .;
+
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _etext = .;
+
+    /* Similar to _iram_start, this symbol goes here so it is
+     * resolved by addr2line in preference to the first symbol in
+     * the flash.text segment.
+     */
+
+    _flash_cache_start = ABSOLUTE(0);
+  } >default_code_seg
+
+  .flash_rodata_dummy (NOLOAD):
+  {
+    . = SIZEOF(.flash.text);
+    . = ALIGN(0x10000) + 0x20;
+  } >drom0_0_seg
+
+  .flash.rodata : ALIGN(0x10)
+  {
+    _srodata = ABSOLUTE(.);
+
+    *(.rodata)
+    *(.rodata.*)
+    *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table .gcc_except_table.*)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    . = (. + 3) & ~ 3;
+    __eh_frame = ABSOLUTE(.);
+    KEEP(*(.eh_frame))
+    . = (. + 7) & ~ 3;
+
+    /* C++ constructor and destructor tables: */
+
+    _sinit = ABSOLUTE(.);
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    _einit = ABSOLUTE(.);
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+
+    /* C++ exception handlers table: */
+
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    _erodata = ABSOLUTE(.);
+
+    /* Literals are also RO data. */
+
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+  } >default_rodata_seg
+
+  /* RTC fast memory holds RTC wake stub code !*/
+
+  .rtc.text :
+  {
+    . = ALIGN(4);
+    *(.rtc.literal .rtc.text)
+  } >rtc_iram_seg
+
+  /* This section is required to skip rtc.text area because the text and
+   * data segements reflect the same address space on different buses.
+   */
+
+  .rtc.dummy :
+  {
+    . = SIZEOF(.rtc.text);
+  } >rtc_iram_seg
+
+  /* RTC data section holds RTC wake stub data/rodata. */
+
+  .rtc.data :
+  {
+    *(.rtc.data)
+    *(.rtc.rodata)
+  } >rtc_iram_seg
+}

boards/risc-v/esp32c6/esp32c6-devkit/Kconfig

@@ -0,0 +1,13 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_ESP32C6_DEVKIT
+
+config ESP32C6_DEVKIT_RUN_IRAM
+	bool "Run from IRAM"
+	default n
+	---help---
+
+endif # ARCH_BOARD_ESP32C6_DEVKIT

boards/risc-v/esp32c6/esp32c6-devkit/configs/nsh/defconfig

@@ -0,0 +1,48 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="esp32c6-devkit"
+CONFIG_ARCH_BOARD_COMMON=y
+CONFIG_ARCH_BOARD_ESP32C6_DEVKIT=y
+CONFIG_ARCH_CHIP="esp32c6"
+CONFIG_ARCH_CHIP_ESP32C6=y
+CONFIG_ARCH_CHIP_ESP32C6WROOM1=y
+CONFIG_ARCH_INTERRUPTSTACK=1536
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=15000
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEV_ZERO=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FS_PROCFS=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_NSH_STRERROR=y
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_BACKTRACE=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_START_DAY=29
+CONFIG_START_MONTH=11
+CONFIG_START_YEAR=2019
+CONFIG_SYSTEM_DUMPSTACK=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_UART0_SERIAL_CONSOLE=y

boards/risc-v/esp32c6/esp32c6-devkit/include/board.h

@@ -0,0 +1,33 @@
+/****************************************************************************
+ * boards/risc-v/esp32c6/esp32c6-devkit/include/board.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKIT_INCLUDE_BOARD_H
+#define __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKIT_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking *****************************************************************/
+
+#define BOARD_XTAL_FREQUENCY  40000000
+
+#endif /* __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKIT_INCLUDE_BOARD_H */
+

boards/risc-v/esp32c6/esp32c6-devkit/scripts/Make.defs

@@ -0,0 +1,56 @@
+############################################################################
+# boards/risc-v/esp32c6/esp32c6-devkit/scripts/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+###########################################################################
+
+include $(TOPDIR)/.config
+include $(TOPDIR)/tools/Config.mk
+include $(TOPDIR)/tools/esp32c6/Config.mk
+include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
+
+ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32c6_rom.ld
+
+# Pick the linker scripts from the board level if they exist, if not
+# pick the common linker scripts.
+
+ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
+ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
+
+ARCHPICFLAGS = -fpic
+
+CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -Werror=return-type -Werror
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
+AFLAGS := $(CFLAGS) -D__ASSEMBLY__
+
+# Loadable module definitions
+
+CMODULEFLAGS = $(CFLAGS)
+
+LDMODULEFLAGS = -melf32lriscv -r -e module_initialize
+LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld)
+
+# ELF module definitions
+
+CELFFLAGS = $(CFLAGS)
+CXXELFFLAGS = $(CXXFLAGS)
+
+LDELFFLAGS = -melf32lriscv -r -e main
+LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)$(DELIM)binfmt$(DELIM)libelf$(DELIM)gnu-elf.ld)

boards/risc-v/esp32c6/esp32c6-devkit/src/Make.defs

@@ -0,0 +1,34 @@
+#############################################################################
+# boards/risc-v/esp32c6/esp32c6-devkit/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+#############################################################################
+
+include $(TOPDIR)/Make.defs
+
+CSRCS  = esp32c6_boot.c esp32c6_bringup.c
+
+ifeq ($(CONFIG_BOARDCTL),y)
+CSRCS += esp32c6_appinit.c
+ifeq ($(CONFIG_BOARDCTL_RESET),y)
+CSRCS += esp32c6_reset.c
+endif
+endif
+
+DEPPATH += --dep-path board
+VPATH += :board
+CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board)

boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6-devkit.h

@@ -0,0 +1,67 @@
+/****************************************************************************
+ * boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6-devkit.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKIT_SRC_ESP32C6_DEVKIT_H
+#define __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKIT_SRC_ESP32C6_DEVKIT_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+#include <stdint.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c6_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y :
+ *     Called from board_late_initialize().
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
+ *     Called from the NSH library via board_app_initialize()
+ *
+ ****************************************************************************/
+
+int esp32c6_bringup(void);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKIT_SRC_ESP32C6_DEVKIT_H */

boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_appinit.c

@@ -0,0 +1,80 @@
+/****************************************************************************
+ * boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_appinit.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <nuttx/board.h>
+
+#include "esp32c6-devkit.h"
+
+#ifdef CONFIG_BOARDCTL
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ *   Perform application specific initialization.  This function is never
+ *   called directly from application code, but only indirectly via the
+ *   (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ *   arg - The boardctl() argument is passed to the board_app_initialize()
+ *         implementation without modification.  The argument has no
+ *         meaning to NuttX; the meaning of the argument is a contract
+ *         between the board-specific initialization logic and the
+ *         matching application logic.  The value could be such things as a
+ *         mode enumeration value, a set of DIP switch settings, a
+ *         pointer to configuration data read from a file or serial FLASH,
+ *         or whatever you would like to do with it.  Every implementation
+ *         should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(uintptr_t arg)
+{
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+  /* Board initialization already performed by board_late_initialize() */
+
+  return OK;
+#else
+  /* Perform board-specific initialization */
+
+  return esp32c6_bringup();
+#endif
+}
+
+#endif /* CONFIG_BOARDCTL */

boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_boot.c

@@ -0,0 +1,87 @@
+/****************************************************************************
+ * boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "esp32c6-devkit.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c6_board_initialize
+ *
+ * Description:
+ *   All ESP32C6 architectures must provide the following entry point.
+ *   This entry point is called early in the initialization -- after all
+ *   memory has been configured and mapped but before any devices have been
+ *   initialized.
+ *
+ ****************************************************************************/
+
+void esp32c6_board_initialize(void)
+{
+  /* Configure on-board LEDs if LED support has been selected. */
+
+#ifdef CONFIG_ARCH_LEDS
+  board_autoled_initialize();
+#endif
+}
+
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ *   If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ *   initialization call will be performed in the boot-up sequence to a
+ *   function called board_late_initialize().  board_late_initialize() will
+ *   be called immediately after up_initialize() is called and just before
+ *   the initial application is started.  This additional initialization
+ *   phase may be used, for example, to initialize board-specific device
+ *   drivers.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+  /* Perform board-specific initialization */
+
+  esp32c6_bringup();
+}
+#endif

boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_bringup.c

@@ -0,0 +1,86 @@
+/****************************************************************************
+ * boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_bringup.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <syslog.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include <sys/types.h>
+#include <sys/mount.h>
+#include <syslog.h>
+#include <debug.h>
+#include <stdio.h>
+
+#include <syslog.h>
+
+#include "esp32c6-devkit.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c6_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y :
+ *     Called from board_late_initialize().
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
+ *     Called from the NSH library
+ *
+ ****************************************************************************/
+
+int esp32c6_bringup(void)
+{
+  int ret;
+
+#ifdef CONFIG_FS_PROCFS
+  /* Mount the procfs file system */
+
+  ret = mount(NULL, "/proc", "procfs", 0, NULL);
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret);
+    }
+#endif
+
+  /* If we got here then perhaps not all initialization was successful, but
+   * at least enough succeeded to bring-up NSH with perhaps reduced
+   * capabilities.
+   */
+
+  UNUSED(ret);
+  return OK;
+}

boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_reset.c

@@ -0,0 +1,63 @@
+/****************************************************************************
+ * boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_reset.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+
+#ifdef CONFIG_BOARDCTL_RESET
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_reset
+ *
+ * Description:
+ *   Reset board.  Support for this function is required by board-level
+ *   logic if CONFIG_BOARDCTL_RESET is selected.
+ *
+ * Input Parameters:
+ *   status - Status information provided with the reset event.  This
+ *            meaning of this status information is board-specific.  If not
+ *            used by a board, the value zero may be provided in calls to
+ *            board_reset().
+ *
+ * Returned Value:
+ *   If this function returns, then it was not possible to power-off the
+ *   board due to some constraints.  The return value in this case is a
+ *   board-specific reason for the failure to shutdown.
+ *
+ ****************************************************************************/
+
+int board_reset(int status)
+{
+  up_systemreset();
+
+  return 0;
+}
+
+#endif /* CONFIG_BOARDCTL_RESET */

tools/esp32c6/Config.mk

@@ -0,0 +1,77 @@
+############################################################################
+# tools/esp32c6/Config.mk
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# These are the macros that will be used in the NuttX make system to compile
+# and assemble source files and to insert the resulting object files into an
+# archive.  These replace the default definitions at tools/Config.mk
+
+ifdef ESPTOOL_BINDIR
+	BL_OFFSET=0x0
+	PT_OFFSET=0x8000
+	BOOTLOADER=$(ESPTOOL_BINDIR)/bootloader.bin
+	PARTITION_TABLE=$(ESPTOOL_BINDIR)/partition-table.bin
+	FLASH_BL=$(BL_OFFSET) $(BOOTLOADER)
+	FLASH_PT=$(PT_OFFSET) $(PARTITION_TABLE)
+endif
+
+ifeq ($(CONFIG_ESP32C6_FLASH_2M),y)
+	FLASH_SIZE="2MB"
+else ifeq ($(CONFIG_ESP32C6_FLASH_4M),y)
+	FLASH_SIZE="4MB"
+else ifeq ($(CONFIG_ESP32C6_FLASH_8M),y)
+	FLASH_SIZE="8MB"
+else ifeq ($(CONFIG_ESP32C6_FLASH_16M),y)
+	FLASH_SIZE="16MB"
+endif
+
+# POSTBUILD -- Perform post build operations
+
+define POSTBUILD
+	$(Q) echo "MKIMAGE: ESP32-C6 binary"
+	$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
+		echo ""; \
+		echo "esptool.py not found.  Please run: \"pip install esptool\""; \
+		echo "Or run: \"make -C $(TOPDIR)/tools/esp32c6\" to install all IDF tools."; \
+		echo ""; \
+		echo "Run make again to create the nuttx.bin image."; \
+		exit 1; \
+	fi
+	$(Q) if [ -z $(FLASH_SIZE) ]; then \
+		echo "Missing Flash memory size configuration for the ESP32-C6 chip."; \
+		exit 1; \
+	fi
+	esptool.py --chip esp32c6 elf2image --flash_mode dio --flash_size $(FLASH_SIZE) -o nuttx.bin nuttx
+	$(Q) echo "Generated: nuttx.bin (ESP32-C6 compatible)"
+endef
+
+# ESPTOOL_BAUD -- Serial port baud rate used when flashing/reading via esptool.py
+
+ESPTOOL_BAUD ?= 921600
+
+# DOWNLOAD -- Download binary image via esptool.py
+
+define DOWNLOAD
+	$(Q) if [ -z $(ESPTOOL_PORT) ]; then \
+		echo "DOWNLOAD error: Missing serial port device argument."; \
+		echo "USAGE: make download ESPTOOL_PORT=<port> [ ESPTOOL_BAUD=<baud> ]"; \
+		exit 1; \
+	fi
+	esptool.py --chip esp32c6 --port $(ESPTOOL_PORT) --baud $(ESPTOOL_BAUD) write_flash $(FLASH_BL) $(FLASH_PT) 0x10000 $(1).bin
+endef