arch/arm/src/stm32l4: Add USB FS device support.
This commit is contained in:
Juha Niskanen
Gregory Nutt
parent
357641ec74
commit
d02ec6373c
@ -5055,15 +5055,15 @@ static int stm32_pullup(struct usbdev_s *dev, bool enable)
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if (enable)
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{
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/* Connect the device by clearing the soft disconnect bit in the DCTL
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* register
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* register.
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*/
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regval &= ~OTG_DCTL_SDIS;
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}
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else
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{
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/* Connect the device by setting the soft disconnect bit in the DCTL
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* register
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/* Disconnect the device by setting the soft disconnect bit in the DCTL
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* register.
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*/
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regval |= OTG_DCTL_SDIS;
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@ -4926,15 +4926,15 @@ static int stm32_pullup(struct usbdev_s *dev, bool enable)
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if (enable)
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{
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/* Connect the device by clearing the soft disconnect bit in the DCTL
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* register
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* register.
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*/
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regval &= ~OTG_DCTL_SDIS;
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}
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else
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{
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/* Connect the device by setting the soft disconnect bit in the DCTL
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* register
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/* Disconnect the device by setting the soft disconnect bit in the DCTL
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* register.
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*/
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regval |= OTG_DCTL_SDIS;
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@ -459,6 +459,7 @@ config STM32L4_STM32L4X2
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bool
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default n
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select STM32L4_STM32L4X3
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select STM32L4_HAVE_USBFS
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config STM32L4_STM32L4X3
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# STM32L4 devices documented in RM0394, regardless of what ST's
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@ -956,6 +957,10 @@ config STM32L4_HAVE_OTGFS
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bool
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default n
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config STM32L4_HAVE_USBFS
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bool
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default n
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config STM32L4_HAVE_SAI1
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bool
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default n
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@ -1448,6 +1453,12 @@ config STM32L4_LPTIM2
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select STM32L4_LPTIM
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depends on STM32L4_HAVE_LPTIM2
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config STM32L4_USBFS
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bool "USB FS"
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default n
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depends on STM32L4_HAVE_USBFS
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select USBDEV
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comment "APB2 Peripherals"
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config STM32L4_SYSCFG
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@ -142,6 +142,9 @@ CHIP_CSRCS += stm32l4_dma.c
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endif
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ifeq ($(CONFIG_USBDEV),y)
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ifeq ($(CONFIG_STM32L4_USBFS),y)
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CHIP_CSRCS += stm32l4_usbdev.c
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endif
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ifeq ($(CONFIG_STM32L4_OTGFS),y)
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CHIP_CSRCS += stm32l4_otgfsdev.c
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endif
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264
arch/arm/src/stm32l4/chip/stm32l4_usbdev.h
Normal file
264
arch/arm/src/stm32l4/chip/stm32l4_usbdev.h
Normal file
@ -0,0 +1,264 @@
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/************************************************************************************
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* arch/arm/src/stm32l4/chip/stm32l4_usbdev.h
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*
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* Copyright (C) 2009, 2011, 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_USBDEV_H
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#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_USBDEV_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <chip.h>
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#if defined(CONFIG_STM32L4_STM32L4X2)
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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/* Endpoint Registers */
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#define STM32L4_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */
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#define STM32L4_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */
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#define STM32L4_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */
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#define STM32L4_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */
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#define STM32L4_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */
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#define STM32L4_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */
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#define STM32L4_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */
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#define STM32L4_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */
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#define STM32L4_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */
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/* Common Registers */
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#define STM32L4_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */
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#define STM32L4_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */
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#define STM32L4_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */
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#define STM32L4_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */
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#define STM32L4_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */
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#define STM32L4_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */
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#define STM32L4_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */
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/* Buffer Descriptor Table (Relatative to BTABLE address) */
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#define STM32L4_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */
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#define STM32L4_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */
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#define STM32L4_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */
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#define STM32L4_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */
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#define STM32L4_USB_BTABLE_RADDR(ep,o) ((((uint32_t)getreg16(STM32L4_USB_BTABLE) + ((ep) << 3)) + (o)) << 1)
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#define STM32L4_USB_ADDR_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET)
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#define STM32L4_USB_COUNT_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET)
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#define STM32L4_USB_ADDR_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET)
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#define STM32L4_USB_COUNT_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET)
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/* Register Addresses ***************************************************************/
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/* Endpoint Registers */
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#define STM32L4_USB_EPR(n) (STM32L4_USB_FS_BASE+STM32L4_USB_EPR_OFFSET(n))
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#define STM32L4_USB_EP0R (STM32L4_USB_FS_BASE+STM32L4_USB_EP0R_OFFSET)
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#define STM32L4_USB_EP1R (STM32L4_USB_FS_BASE+STM32L4_USB_EP1R_OFFSET)
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#define STM32L4_USB_EP2R (STM32L4_USB_FS_BASE+STM32L4_USB_EP2R_OFFSET)
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#define STM32L4_USB_EP3R (STM32L4_USB_FS_BASE+STM32L4_USB_EP3R_OFFSET)
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#define STM32L4_USB_EP4R (STM32L4_USB_FS_BASE+STM32L4_USB_EP4R_OFFSET)
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#define STM32L4_USB_EP5R (STM32L4_USB_FS_BASE+STM32L4_USB_EP5R_OFFSET)
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#define STM32L4_USB_EP6R (STM32L4_USB_FS_BASE+STM32L4_USB_EP6R_OFFSET)
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#define STM32L4_USB_EP7R (STM32L4_USB_FS_BASE+STM32L4_USB_EP7R_OFFSET)
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/* Common Registers */
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#define STM32L4_USB_CNTR (STM32L4_USB_FS_BASE+STM32L4_USB_CNTR_OFFSET)
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#define STM32L4_USB_ISTR (STM32L4_USB_FS_BASE+STM32L4_USB_ISTR_OFFSET)
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#define STM32L4_USB_FNR (STM32L4_USB_FS_BASE+STM32L4_USB_FNR_OFFSET)
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#define STM32L4_USB_DADDR (STM32L4_USB_FS_BASE+STM32L4_USB_DADDR_OFFSET)
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#define STM32L4_USB_BTABLE (STM32L4_USB_FS_BASE+STM32L4_USB_BTABLE_OFFSET)
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#define STM32L4_USB_LPMCSR (STM32L4_USB_FS_BASE+STM32L4_USB_LPMCSR_OFFSET)
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#define STM32L4_USB_BCDR (STM32L4_USB_FS_BASE+STM32L4_USB_BCDR_OFFSET)
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/* Buffer Descriptor Table (Relatative to BTABLE address) */
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#define STM32L4_USB_BTABLE_ADDR(ep,o) (STM32L4_USB_SRAM_BASE+STM32L4_USB_BTABLE_RADDR(ep,o))
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#define STM32L4_USB_ADDR_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET)
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#define STM32L4_USB_COUNT_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET)
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#define STM32L4_USB_ADDR_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET)
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#define STM32L4_USB_COUNT_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* USB endpoint register */
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#define USB_EPR_EA_SHIFT (0) /* Bits 3:0 [3:0]: Endpoint Address */
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#define USB_EPR_EA_MASK (0x0f << USB_EPR_EA_SHIFT)
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#define USB_EPR_STATTX_SHIFT (4) /* Bits 5-4: Status bits, for transmission transfers */
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#define USB_EPR_STATTX_MASK (3 << USB_EPR_STATTX_SHIFT)
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# define USB_EPR_STATTX_DIS (0 << USB_EPR_STATTX_SHIFT) /* EndPoint TX DISabled */
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# define USB_EPR_STATTX_STALL (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX STALLed */
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# define USB_EPR_STATTX_NAK (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX NAKed */
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# define USB_EPR_STATTX_VALID (3 << USB_EPR_STATTX_SHIFT) /* EndPoint TX VALID */
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# define USB_EPR_STATTX_DTOG1 (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit1 */
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# define USB_EPR_STATTX_DTOG2 (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit2 */
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#define USB_EPR_DTOG_TX (1 << 6) /* Bit 6: Data Toggle, for transmission transfers */
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#define USB_EPR_CTR_TX (1 << 7) /* Bit 7: Correct Transfer for transmission */
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#define USB_EPR_EP_KIND (1 << 8) /* Bit 8: Endpoint Kind */
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#define USB_EPR_EPTYPE_SHIFT (9) /* Bits 10-9: Endpoint type */
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#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT)
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# define USB_EPR_EPTYPE_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* EndPoint BULK */
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# define USB_EPR_EPTYPE_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* EndPoint CONTROL */
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# define USB_EPR_EPTYPE_ISOC (2 << USB_EPR_EPTYPE_SHIFT) /* EndPoint ISOCHRONOUS */
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# define USB_EPR_EPTYPE_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* EndPoint INTERRUPT */
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#define USB_EPR_SETUP (1 << 11) /* Bit 11: Setup transaction completed */
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#define USB_EPR_STATRX_SHIFT (12) /* Bits 13-12: Status bits, for reception transfers */
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#define USB_EPR_STATRX_MASK (3 << USB_EPR_STATRX_SHIFT)
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# define USB_EPR_STATRX_DIS (0 << USB_EPR_STATRX_SHIFT) /* EndPoint RX DISabled */
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# define USB_EPR_STATRX_STALL (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX STALLed */
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# define USB_EPR_STATRX_NAK (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX NAKed */
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# define USB_EPR_STATRX_VALID (3 << USB_EPR_STATRX_SHIFT) /* EndPoint RX VALID */
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# define USB_EPR_STATRX_DTOG1 (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */
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# define USB_EPR_STATRX_DTOG2 (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit2 */
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#define USB_EPR_DTOG_RX (1 << 14) /* Bit 14: Data Toggle, for reception transfers */
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#define USB_EPR_CTR_RX (1 << 15) /* Bit 15: Correct Transfer for reception */
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/* USB control register */
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#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force USB Reset */
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#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */
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#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */
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#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */
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#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */
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#define USB_CNTR_L1RESUME (1 << 5) /* Bit 5: LPM L1 Resume request */
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#define USB_CNTR_L1REQM (1 << 7) /* Bit 7: LPM L1 State Request Interrupt Mask */
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#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected Start Of Frame Interrupt Mask */
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#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start Of Frame Interrupt Mask */
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#define USB_CNTR_RESETM (1 << 10) /* Bit 10: USB Reset Interrupt Mask */
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#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */
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#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wakeup Interrupt Mask */
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#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error Interrupt Mask */
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#define USB_CNTR_PMAOVRNM (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */
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#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */
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#define USB_CNTR_ALLINTS (USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|USB_CNTR_SUSPM|\
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USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_PMAOVRNM|USB_CNTR_CTRM)
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/* USB interrupt status register */
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#define USB_ISTR_EPID_SHIFT (0) /* Bits 3-0: Endpoint Identifier */
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#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT)
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#define USB_ISTR_DIR (1 << 4) /* Bit 4: Direction of transaction */
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#define USB_ISTR_L1REQ (1 << 7) /* Bit 7: LPM L1 state request */
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#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */
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#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */
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#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request */
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#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend mode request */
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#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wake up */
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#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */
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#define USB_ISTR_PMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */
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#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */
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#define USB_ISTR_ALLINTS (USB_ISTR_L1REQ|USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|\
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USB_ISTR_SUSP|USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_PMAOVRN|\
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USB_ISTR_CTR)
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/* USB frame number register */
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#define USB_FNR_FN_SHIFT (0) /* Bits 10-0: Frame Number */
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#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT)
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#define USB_FNR_LSOF_SHIFT (11) /* Bits 12-11: Lost SOF */
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#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT)
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#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */
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#define USB_FNR_RXDM (1 << 14) /* Bit 14: Receive Data - Line Status */
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#define USB_FNR_RXDP (1 << 15) /* Bit 15: Receive Data + Line Status */
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/* USB device address */
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#define USB_DADDR_ADD_SHIFT (0) /* Bits 6-0: Device Address */
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#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT)
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#define USB_DADDR_EF (1 << 7) /* Bit 7: Enable Function */
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/* Buffer table address */
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#define USB_BTABLE_SHIFT (3) /* Bits 15:3: Buffer Table */
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#define USB_BTABLE_MASK (0x1fff << USB_BTABLE_SHIFT)
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/* Transmission buffer address */
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#define USB_ADDR_TX_ZERO (1 << 0) /* Bit 0 Must always be written as ‘0’ */
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#define USB_ADDR_TX_SHIFT (1) /* Bits 15-1: Transmission Buffer Address */
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#define USB_ADDR_TX_MASK (0x7fff << USB_ADDR_ADDR_TX_SHIFT)
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/* Transmission byte count */
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#define USB_COUNT_TX_SHIFT (0) /* Bits 9-0: Transmission Byte Count */
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#define USB_COUNT_TX_MASK (0x03ff << USB_COUNT_COUNT_TX_SHIFT)
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/* Reception buffer address */
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#define USB_ADDR_RX_ZERO (1 << 0) /* Bit 0 This bit must always be written as ‘0’ */
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#define USB_ADDR_RX_SHIFT (1) /* Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address */
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#define USB_ADDR_RX_MASK (0x7fff << USB_ADDR_RX_SHIFT)
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/* Reception byte count */
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#define USB_COUNT_RX_BL_SIZE (1 << 15) /* Bit 15: BLock SIZE. */
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#define USB_COUNT_RX_NUM_BLOCK_SHIFT (10) /* Bits 14-10: Number of blocks */
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#define USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT)
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#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */
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#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT)
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/* LPM control and status register */
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#define USB_LPMCSR_LPMEN (1 << 0) /* Bit 0: LPM support enable */
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#define USB_LPMCSR_LPMACK (1 << 1) /* Bit 1: LPM Token acknowledge enable */
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#define USB_LPMCSR_REMWAKE (1 << 2) /* Bit 2: bRemoteWake value */
|
||||
#define USB_LPMCSR_BESL_SHIFT (4) /* Bits 7-4: BESL value */
|
||||
#define USB_LPMCSR_BESL_MASK (0x0f << USB_LPMCSR_BESL_SHIFT)
|
||||
|
||||
/* Battery charging detector */
|
||||
|
||||
#define USB_BCDR_BCDEN (1 << 0) /* Bit 0: Battery charging detector (BCD) enable */
|
||||
#define USB_BCDR_DCDEN (1 << 1) /* Bit 1: Data contact detection (DCD) mode enable */
|
||||
#define USB_BCDR_PDEN (1 << 2) /* Bit 2: Primary detection (PD) mode enable */
|
||||
#define USB_BCDR_SDEN (1 << 3) /* Bit 3: Secondary detection (SD) mode enable */
|
||||
#define USB_BCDR_DCDET (1 << 4) /* Bit 4: Data contact detection (DCD) status */
|
||||
#define USB_BCDR_PDET (1 << 5) /* Bit 5: Primary detection (PD) status */
|
||||
#define USB_BCDR_SDET (1 << 6) /* Bit 6: Secondary detection (SD) status */
|
||||
#define USB_BCDR_PS2DET (1 << 7) /* Bit 7: DM pull-up detection status */
|
||||
#define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */
|
||||
|
||||
#endif /* CONFIG_STM32L4_STM32L4X2 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_USBDEV_H */
|
||||
|
||||
3881
arch/arm/src/stm32l4/stm32l4_usbdev.c
Normal file
3881
arch/arm/src/stm32l4/stm32l4_usbdev.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,85 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32l4/stm32l4_usbdev.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011, 2015, 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USBDEV_H
|
||||
#define __ARCH_ARM_SRC_STM32L4_STM32L4_USBDEV_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/usb/usbdev.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/stm32l4_usbdev.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32l4_usbsuspend
|
||||
*
|
||||
* Description:
|
||||
* Board logic must provide the stm32l4_usbsuspend logic if the USBDEV driver is
|
||||
* used. This function is called whenever the USB enters or leaves suspend mode.
|
||||
* This is an opportunity for the board logic to shutdown clocks, power, etc.
|
||||
* while the USB is suspended.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32l4_usbsuspend(FAR struct usbdev_s *dev, bool resume);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_USBDEV_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user