diff --git a/arch/arm/src/cxd56xx/cxd56_adc.c b/arch/arm/src/cxd56xx/cxd56_adc.c index 69687774c2..b06fa91ccc 100644 --- a/arch/arm/src/cxd56xx/cxd56_adc.c +++ b/arch/arm/src/cxd56xx/cxd56_adc.c @@ -223,6 +223,7 @@ static struct cxd56adc_dev_s g_lpadc0priv = .wm = NULL, .filter = NULL, .notify = NULL, + .lock = NXMUTEX_INITIALIZER, .crefs = 0, }; #endif @@ -239,6 +240,7 @@ static struct cxd56adc_dev_s g_lpadc1priv = .wm = NULL, .filter = NULL, .notify = NULL, + .lock = NXMUTEX_INITIALIZER, .crefs = 0, }; #endif @@ -255,6 +257,7 @@ static struct cxd56adc_dev_s g_lpadc2priv = .wm = NULL, .filter = NULL, .notify = NULL, + .lock = NXMUTEX_INITIALIZER, .crefs = 0, }; #endif @@ -271,6 +274,7 @@ static struct cxd56adc_dev_s g_lpadc3priv = .wm = NULL, .filter = NULL, .notify = NULL, + .lock = NXMUTEX_INITIALIZER, .crefs = 0, }; #endif @@ -287,6 +291,7 @@ static struct cxd56adc_dev_s g_hpadc0priv = .wm = NULL, .filter = NULL, .notify = NULL, + .lock = NXMUTEX_INITIALIZER, .crefs = 0, }; #endif @@ -303,6 +308,7 @@ static struct cxd56adc_dev_s g_hpadc1priv = .wm = NULL, .filter = NULL, .notify = NULL, + .lock = NXMUTEX_INITIALIZER, .crefs = 0, }; #endif @@ -1107,9 +1113,8 @@ int cxd56_adcinitialize(void) aerr("Failed to register driver(lpadc0): %d\n", ret); return ret; } - - nxmutex_init(&g_lpadc0priv.lock); #endif + #if defined (CONFIG_CXD56_LPADC1) || defined (CONFIG_CXD56_LPADC0_1) || defined (CONFIG_CXD56_LPADC_ALL) ret = register_driver("/dev/lpadc1", &g_adcops, 0666, &g_lpadc1priv); if (ret < 0) @@ -1117,9 +1122,8 @@ int cxd56_adcinitialize(void) aerr("Failed to register driver(lpadc1): %d\n", ret); return ret; } - - nxmutex_init(&g_lpadc1priv.lock); #endif + #if defined (CONFIG_CXD56_LPADC2) || defined (CONFIG_CXD56_LPADC_ALL) ret = register_driver("/dev/lpadc2", &g_adcops, 0666, &g_lpadc2priv); if (ret < 0) @@ -1127,9 +1131,8 @@ int cxd56_adcinitialize(void) aerr("Failed to register driver(lpadc2): %d\n", ret); return ret; } - - nxmutex_init(&g_lpadc2priv.lock); #endif + #if defined (CONFIG_CXD56_LPADC3) || defined (CONFIG_CXD56_LPADC_ALL) ret = register_driver("/dev/lpadc3", &g_adcops, 0666, &g_lpadc3priv); if (ret < 0) @@ -1137,9 +1140,8 @@ int cxd56_adcinitialize(void) aerr("Failed to register driver(lpadc3): %d\n", ret); return ret; } - - nxmutex_init(&g_lpadc3priv.lock); #endif + #ifdef CONFIG_CXD56_HPADC0 ret = register_driver("/dev/hpadc0", &g_adcops, 0666, &g_hpadc0priv); if (ret < 0) @@ -1147,9 +1149,8 @@ int cxd56_adcinitialize(void) aerr("Failed to register driver(hpadc0): %d\n", ret); return ret; } - - nxmutex_init(&g_hpadc0priv.lock); #endif + #ifdef CONFIG_CXD56_HPADC1 ret = register_driver("/dev/hpadc1", &g_adcops, 0666, &g_hpadc1priv); if (ret < 0) @@ -1157,8 +1158,6 @@ int cxd56_adcinitialize(void) aerr("Failed to register driver(hpadc1): %d\n", ret); return ret; } - - nxmutex_init(&g_hpadc1priv.lock); #endif return ret; diff --git a/arch/arm/src/cxd56xx/cxd56_charger.c b/arch/arm/src/cxd56xx/cxd56_charger.c index 325eb27ff5..90cac9db53 100644 --- a/arch/arm/src/cxd56xx/cxd56_charger.c +++ b/arch/arm/src/cxd56xx/cxd56_charger.c @@ -103,7 +103,10 @@ static const struct file_operations g_chargerops = #endif }; -static struct charger_dev_s g_chargerdev; +static struct charger_dev_s g_chargerdev = +{ + .batlock = NXMUTEX_INITIALIZER, +}; /**************************************************************************** * Private Functions @@ -621,10 +624,6 @@ int cxd56_charger_initialize(const char *devpath) struct charger_dev_s *priv = &g_chargerdev; int ret; - /* Initialize the CXD5247 device structure */ - - nxmutex_init(&priv->batlock); - /* Register battery driver */ ret = register_driver(devpath, &g_chargerops, 0666, priv); diff --git a/arch/arm/src/cxd56xx/cxd56_dmac.c b/arch/arm/src/cxd56xx/cxd56_dmac.c index 80cab93047..a54c245786 100644 --- a/arch/arm/src/cxd56xx/cxd56_dmac.c +++ b/arch/arm/src/cxd56xx/cxd56_dmac.c @@ -290,7 +290,7 @@ struct dma_channel_s /* This is the array of all DMA channels */ static struct dma_channel_s g_dmach[NCHANNELS]; -static mutex_t g_dmalock; +static mutex_t g_dmalock = NXMUTEX_INITIALIZER; static int dma_init(int ch); static int dma_uninit(int ch); @@ -726,8 +726,6 @@ void weak_function arm_dma_initialize(void) g_dmach[i].chan = i; up_enable_irq(irq_map[i]); } - - nxmutex_init(&g_dmalock); } /**************************************************************************** diff --git a/arch/arm/src/cxd56xx/cxd56_emmc.c b/arch/arm/src/cxd56xx/cxd56_emmc.c index 5fcaf58619..dfb72a25a9 100644 --- a/arch/arm/src/cxd56xx/cxd56_emmc.c +++ b/arch/arm/src/cxd56xx/cxd56_emmc.c @@ -137,8 +137,11 @@ static const struct block_operations g_bops = NULL /* ioctl */ }; -static sem_t g_waitsem; -struct cxd56_emmc_state_s g_emmcdev; +static sem_t g_waitsem = SEM_INITIALIZER(0); +struct cxd56_emmc_state_s g_emmcdev = +{ + .lock = NXMUTEX_INITIALIZER, +}; /**************************************************************************** * Private Functions @@ -939,10 +942,6 @@ int cxd56_emmcinitialize(void) priv = &g_emmcdev; - memset(priv, 0, sizeof(struct cxd56_emmc_state_s)); - nxmutex_init(&priv->lock); - nxsem_init(&g_waitsem, 0, 0); - ret = emmc_hwinitialize(); if (ret != OK) { diff --git a/arch/arm/src/cxd56xx/cxd56_farapi.c b/arch/arm/src/cxd56xx/cxd56_farapi.c index ec53266f57..70d29c71eb 100644 --- a/arch/arm/src/cxd56xx/cxd56_farapi.c +++ b/arch/arm/src/cxd56xx/cxd56_farapi.c @@ -113,8 +113,8 @@ extern struct modulelist_s _image_modlist_base[]; * Private Data ****************************************************************************/ -static sem_t g_farwait; -static mutex_t g_farlock; +static sem_t g_farwait = SEM_INITIALIZER(0); +static mutex_t g_farlock = NXMUTEX_INITIALIZER; static struct pm_cpu_wakelock_s g_wlock = { .count = 0, @@ -288,10 +288,7 @@ void cxd56_farapiinitialize(void) PANIC(); # endif } - #endif - nxmutex_init(&g_farlock); - nxsem_init(&g_farwait, 0, 0); cxd56_iccinit(CXD56_PROTO_MBX); cxd56_iccinit(CXD56_PROTO_FLG); diff --git a/arch/arm/src/cxd56xx/cxd56_gauge.c b/arch/arm/src/cxd56xx/cxd56_gauge.c index dc73d50240..c5db2383fc 100644 --- a/arch/arm/src/cxd56xx/cxd56_gauge.c +++ b/arch/arm/src/cxd56xx/cxd56_gauge.c @@ -88,7 +88,10 @@ static const struct file_operations g_gaugeops = #endif }; -static struct bat_gauge_dev_s g_gaugedev; +static struct bat_gauge_dev_s g_gaugedev = +{ + .batlock = NXMUTEX_INITIALIZER, +}; /**************************************************************************** * Private Functions @@ -345,10 +348,6 @@ int cxd56_gauge_initialize(const char *devpath) struct bat_gauge_dev_s *priv = &g_gaugedev; int ret; - /* Initialize the CXD5247 device structure */ - - nxmutex_init(&priv->batlock); - /* Register battery driver */ ret = register_driver(devpath, &g_gaugeops, 0666, priv); diff --git a/arch/arm/src/cxd56xx/cxd56_ge2d.c b/arch/arm/src/cxd56xx/cxd56_ge2d.c index 182a5f8af9..eda8aeca6f 100644 --- a/arch/arm/src/cxd56xx/cxd56_ge2d.c +++ b/arch/arm/src/cxd56xx/cxd56_ge2d.c @@ -64,8 +64,8 @@ static const struct file_operations g_ge2dfops = .ioctl = ge2d_ioctl }; -static sem_t g_wait; -static mutex_t g_lock; +static sem_t g_wait = SEM_INITIALIZER(0); +static mutex_t g_lock = NXMUTEX_INITIALIZER; /**************************************************************************** * Private Functions @@ -184,9 +184,6 @@ int cxd56_ge2dinitialize(const char *devname) { int ret; - nxmutex_init(&g_lock); - nxsem_init(&g_wait, 0, 0); - ret = register_driver(devname, &g_ge2dfops, 0666, NULL); if (ret != 0) { @@ -215,9 +212,5 @@ void cxd56_ge2duninitialize(const char *devname) irq_detach(CXD56_IRQ_GE2D); cxd56_img_ge2d_clock_disable(); - - nxmutex_destroy(&g_lock); - nxsem_destroy(&g_wait); - unregister_driver(devname); } diff --git a/arch/arm/src/cxd56xx/cxd56_hostif.c b/arch/arm/src/cxd56xx/cxd56_hostif.c index 85563c843c..d9cc850e4f 100644 --- a/arch/arm/src/cxd56xx/cxd56_hostif.c +++ b/arch/arm/src/cxd56xx/cxd56_hostif.c @@ -130,7 +130,10 @@ static int hif_unlink(struct inode *inode); /* Host interface driver */ -static struct cxd56_hifdrv_s g_hifdrv; +static struct cxd56_hifdrv_s g_hifdrv = +{ + .sync = SEM_INITIALIZER(0), +}; /* Host interface operations */ @@ -379,8 +382,6 @@ static int hif_initialize(struct hostif_buff_s *buffer) DEBUGASSERT(buffer); - memset(drv, 0, sizeof(struct cxd56_hifdrv_s)); - /* Get the number of devices */ for (num = 0; num < MAX_BUFFER_NUM; num++) @@ -441,8 +442,6 @@ static int hif_initialize(struct hostif_buff_s *buffer) cxd56_iccinit(CXD56_PROTO_HOSTIF); - nxsem_init(&drv->sync, 0, 0); - ret = cxd56_iccregisterhandler(CXD56_PROTO_HOSTIF, hif_rxhandler, NULL); return ret; diff --git a/arch/arm/src/cxd56xx/cxd56_powermgr.c b/arch/arm/src/cxd56xx/cxd56_powermgr.c index 155a7b5ff1..1341c68dd0 100644 --- a/arch/arm/src/cxd56xx/cxd56_powermgr.c +++ b/arch/arm/src/cxd56xx/cxd56_powermgr.c @@ -166,10 +166,10 @@ static int cxd56_pmmsghandler(int cpuid, int protoid, uint32_t pdata, static struct cxd56_pm_target_id_s g_target_id_table; static struct file g_queuedesc; -static sem_t g_bootsync; -static mutex_t g_regcblock; -static mutex_t g_freqlock; -static sem_t g_freqlockwait; +static sem_t g_bootsync = SEM_INITIALIZER(0); +static mutex_t g_regcblock = NXMUTEX_INITIALIZER; +static mutex_t g_freqlock = NXMUTEX_INITIALIZER; +static sem_t g_freqlockwait = SEM_INITIALIZER(0); static dq_queue_t g_cbqueue; static sq_queue_t g_freqlockqueue; static sq_queue_t g_wakelockqueue; @@ -818,36 +818,11 @@ int cxd56_pm_hotsleep(int idletime) int cxd56_pm_initialize(void) { int taskid; - int ret; dq_init(&g_cbqueue); sq_init(&g_freqlockqueue); sq_init(&g_wakelockqueue); - ret = nxmutex_init(&g_regcblock); - if (ret < 0) - { - return ret; - } - - ret = nxmutex_init(&g_freqlock); - if (ret < 0) - { - return ret; - } - - ret = nxsem_init(&g_freqlockwait, 0, 0); - if (ret < 0) - { - return ret; - } - - ret = nxsem_init(&g_bootsync, 0, 0); - if (ret < 0) - { - return ret; - } - taskid = task_create("cxd56_pm_task", CXD56_PM_TASK_PRIO, CXD56_PM_TASK_STACKSIZE, cxd56_pm_maintask, NULL); diff --git a/arch/arm/src/cxd56xx/cxd56_scu.c b/arch/arm/src/cxd56xx/cxd56_scu.c index 6983eb0933..3eefe823fc 100644 --- a/arch/arm/src/cxd56xx/cxd56_scu.c +++ b/arch/arm/src/cxd56xx/cxd56_scu.c @@ -315,7 +315,17 @@ static void seq_handleisopdoneintr(struct cxd56_scudev_s *priv, * Private Data ****************************************************************************/ -struct cxd56_scudev_s g_scudev; +struct cxd56_scudev_s g_scudev = +{ + .syncwait = SEM_INITIALIZER(0), + .synclock = NXMUTEX_INITIALIZER, + .oneshotwait = + { + SEM_INITIALIZER(0), + SEM_INITIALIZER(0), + SEM_INITIALIZER(0), + }, +}; /**************************************************************************** * Public Data @@ -3417,23 +3427,10 @@ void seq_close(struct seq_s *seq) void scu_initialize(void) { - struct cxd56_scudev_s *priv = &g_scudev; - int i; - #ifdef CONFIG_CXD56_UDMAC cxd56_udmainitialize(); #endif - memset(priv, 0, sizeof(struct cxd56_scudev_s)); - - nxmutex_init(&priv->synclock); - nxsem_init(&priv->syncwait, 0, 0); - - for (i = 0; i < 3; i++) - { - nxsem_init(&priv->oneshotwait[i], 0, 0); - } - scufifo_initialize(); /** @@ -3486,9 +3483,6 @@ void scu_initialize(void) void scu_uninitialize(void) { - struct cxd56_scudev_s *priv = &g_scudev; - int i; - /* Request don't sleep */ seq_inhibitrequest(REQ_SLEEP, true); @@ -3496,12 +3490,4 @@ void scu_uninitialize(void) up_disable_irq(CXD56_IRQ_SCU_3); cxd56_scuseq_clock_disable(); - - nxsem_destroy(&priv->syncwait); - nxmutex_destroy(&priv->synclock); - - for (i = 0; i < 3; i++) - { - nxsem_destroy(&priv->oneshotwait[i]); - } } diff --git a/arch/arm/src/cxd56xx/cxd56_sdhci.c b/arch/arm/src/cxd56xx/cxd56_sdhci.c index 38a6fa868a..9c442356a5 100644 --- a/arch/arm/src/cxd56xx/cxd56_sdhci.c +++ b/arch/arm/src/cxd56xx/cxd56_sdhci.c @@ -464,6 +464,7 @@ struct cxd56_sdiodev_s g_sdhcdev = .dmasendsetup = cxd56_sdio_sendsetup, #endif }, + .waitsem = SEM_INITIALIZER(0), }; /* Register logging support */ @@ -1315,10 +1316,6 @@ static void cxd56_sdio_sdhci_reset(struct sdio_dev_s *dev) /* Initialize the SDHC slot structure data structure */ - /* Initialize semaphores */ - - nxsem_init(&priv->waitsem, 0, 0); - /* The next phase of the hardware reset would be to set the SYSCTRL INITA * bit to send 80 clock ticks for card to power up and then reset the card * with CMD0. This is done elsewhere. diff --git a/arch/arm/src/cxd56xx/cxd56_spi.c b/arch/arm/src/cxd56xx/cxd56_spi.c index d9e7882915..e1df6b3d03 100644 --- a/arch/arm/src/cxd56xx/cxd56_spi.c +++ b/arch/arm/src/cxd56xx/cxd56_spi.c @@ -77,7 +77,6 @@ struct cxd56_spidev_s uint8_t port; /* Port number */ int initialized; /* Initialized flag */ #ifdef CONFIG_CXD56_DMAC - bool dmaenable; /* Use DMA or not */ DMA_HANDLE rxdmach; /* RX DMA channel handle */ DMA_HANDLE txdmach; /* TX DMA channel handle */ sem_t dmasem; /* Wait for DMA to complete */ @@ -188,6 +187,10 @@ static struct cxd56_spidev_s g_spi4dev = .initialized = 0, #ifdef CONFIG_CXD56_SPI_INTERRUPTS .spiirq = CXD56_IRQ_IMG_SPI, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_CXD56_DMAC + .dmasem = SEM_INITIALIZER(0), #endif }; @@ -231,6 +234,10 @@ static struct cxd56_spidev_s g_spi5dev = .initialized = 0, #ifdef CONFIG_CXD56_SPI_INTERRUPTS .spiirq = CXD56_IRQ_IMG_WSPI, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_CXD56_DMAC + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -273,6 +280,10 @@ static struct cxd56_spidev_s g_spi0dev = .initialized = 0, #ifdef CONFIG_CXD56_SPI_INTERRUPTS .spiirq = CXD56_IRQ_SPIM, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_CXD56_DMAC + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -315,6 +326,10 @@ static struct cxd56_spidev_s g_spi3dev = .initialized = 0, #ifdef CONFIG_CXD56_SPI_INTERRUPTS .spiirq = CXD56_IRQ_SCU_SPI, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_CXD56_DMAC + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -863,15 +878,13 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { #ifdef CONFIG_CXD56_DMAC - struct cxd56_spidev_s *priv = (struct cxd56_spidev_s *)dev; - #ifdef CONFIG_CXD56_SPI_DMATHRESHOLD size_t dmath = CONFIG_CXD56_SPI_DMATHRESHOLD; #else size_t dmath = 0; #endif - if (priv->dmaenable && dmath < nwords) + if (dmath < nwords) { spi_dmaexchange(dev, txbuffer, rxbuffer, nwords); } @@ -1204,7 +1217,6 @@ struct spi_dev_s *cxd56_spibus_initialize(int port) /* DMA settings */ #ifdef CONFIG_CXD56_DMAC - priv->dmaenable = false; priv->txdmach = NULL; priv->rxdmach = NULL; #endif @@ -1244,10 +1256,6 @@ struct spi_dev_s *cxd56_spibus_initialize(int port) spi_setfrequency((struct spi_dev_s *)priv, 400000); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_CXD56_SPI3_SCUSEQ /* Enable the SPI, but not enable port 3 when SCU support enabled. * Because this enabler will be controlled by SCU. @@ -1328,12 +1336,6 @@ void cxd56_spi_dmaconfig(int port, int chtype, DMA_HANDLE handle, priv->txdmach = handle; memcpy(&priv->txconfig, conf, sizeof(dma_config_t)); - - if (!priv->dmaenable) - { - nxsem_init(&priv->dmasem, 0, 0); - priv->dmaenable = true; - } } else if ((chtype == CXD56_SPI_DMAC_CHTYPE_RX) && (!priv->rxdmach)) { @@ -1341,12 +1343,6 @@ void cxd56_spi_dmaconfig(int port, int chtype, DMA_HANDLE handle, priv->rxdmach = handle; memcpy(&priv->rxconfig, conf, sizeof(dma_config_t)); - - if (!priv->dmaenable) - { - nxsem_init(&priv->dmasem, 0, 0); - priv->dmaenable = true; - } } } } diff --git a/arch/arm/src/cxd56xx/cxd56_sysctl.c b/arch/arm/src/cxd56xx/cxd56_sysctl.c index 56c73c46e2..34b5e4a538 100644 --- a/arch/arm/src/cxd56xx/cxd56_sysctl.c +++ b/arch/arm/src/cxd56xx/cxd56_sysctl.c @@ -66,8 +66,8 @@ static int sysctl_rxhandler(int cpuid, int protoid, * Private Data ****************************************************************************/ -static mutex_t g_lock; -static sem_t g_sync; +static mutex_t g_lock = NXMUTEX_INITIALIZER; +static sem_t g_sync = SEM_INITIALIZER(0); static int g_errcode = 0; static const struct file_operations g_sysctlfops = @@ -159,11 +159,6 @@ int cxd56_sysctlcmd(uint8_t id, uint32_t data) void cxd56_sysctlinitialize(void) { cxd56_iccinit(CXD56_PROTO_SYSCTL); - - nxmutex_init(&g_lock); - nxsem_init(&g_sync, 0, 0); - cxd56_iccregisterhandler(CXD56_PROTO_SYSCTL, sysctl_rxhandler, NULL); - register_driver("/dev/sysctl", &g_sysctlfops, 0666, NULL); } diff --git a/arch/arm/src/cxd56xx/cxd56_uart0.c b/arch/arm/src/cxd56xx/cxd56_uart0.c index 9b0a2fb1b4..6a7f55a68d 100644 --- a/arch/arm/src/cxd56xx/cxd56_uart0.c +++ b/arch/arm/src/cxd56xx/cxd56_uart0.c @@ -97,7 +97,7 @@ static const struct file_operations g_uart0fops = .write = uart0_write }; -static mutex_t g_lock; +static mutex_t g_lock = NXMUTEX_INITIALIZER; /**************************************************************************** * Private Functions @@ -233,8 +233,6 @@ int cxd56_uart0initialize(const char *devname) { int ret; - nxmutex_init(&g_lock); - ret = register_driver(devname, &g_uart0fops, 0666, NULL); if (ret != 0) { @@ -251,7 +249,6 @@ int cxd56_uart0initialize(const char *devname) void cxd56_uart0uninitialize(const char *devname) { unregister_driver(devname); - nxmutex_destroy(&g_lock); } #endif /* CONFIG_CXD56_UART0 */ diff --git a/arch/arm/src/cxd56xx/cxd56_udmac.c b/arch/arm/src/cxd56xx/cxd56_udmac.c index 1d1a89389d..a072e29a52 100644 --- a/arch/arm/src/cxd56xx/cxd56_udmac.c +++ b/arch/arm/src/cxd56xx/cxd56_udmac.c @@ -78,7 +78,11 @@ struct dma_controller_s /* This is the overall state of the DMA controller */ -static struct dma_controller_s g_dmac; +static struct dma_controller_s g_dmac = +{ + .lock = NXMUTEX_INITIALIZER, + .chansem = SEM_INITIALIZER(CXD56_DMA_NCHANNELS), +}; /* This is the array of all DMA channels */ @@ -239,9 +243,6 @@ void cxd56_udmainitialize(void) /* Initialize the channel list */ - nxmutex_init(&g_dmac.lock); - nxsem_init(&g_dmac.chansem, 0, CXD56_DMA_NCHANNELS); - for (i = 0; i < CXD56_DMA_NCHANNELS; i++) { g_dmach[i].chan = i; diff --git a/arch/arm/src/efm32/efm32_dma.c b/arch/arm/src/efm32/efm32_dma.c index 37976b1941..b6ce2db879 100644 --- a/arch/arm/src/efm32/efm32_dma.c +++ b/arch/arm/src/efm32/efm32_dma.c @@ -78,7 +78,11 @@ struct dma_controller_s /* This is the overall state of the DMA controller */ -static struct dma_controller_s g_dmac; +static struct dma_controller_s g_dmac = +{ + .lock = NXMUTEX_INITIALIZER, + .chansem = SEM_INITIALIZER(EFM32_DMA_NCHANNELS), +}; /* This is the array of all DMA channels */ @@ -266,9 +270,6 @@ void weak_function arm_dma_initialize(void) /* Initialize the channel list */ - nxmutex_init(&g_dmac.lock); - nxsem_init(&g_dmac.chansem, 0, EFM32_DMA_NCHANNELS); - for (i = 0; i < EFM32_DMA_NCHANNELS; i++) { g_dmach[i].chan = i; diff --git a/arch/arm/src/efm32/efm32_spi.c b/arch/arm/src/efm32/efm32_spi.c index 4d2ce69121..cae525c87e 100644 --- a/arch/arm/src/efm32/efm32_spi.c +++ b/arch/arm/src/efm32/efm32_spi.c @@ -226,7 +226,15 @@ static const struct spi_ops_s g_spiops = #ifdef CONFIG_EFM32_USART0_ISSPI /* Support for SPI on USART0 */ -static struct efm32_spidev_s g_spi0dev; +static struct efm32_spidev_s g_spi0dev = +{ +#ifdef CONFIG_EFM32_SPI_DMA + .rxdmasem = SEM_INITIALIZER(0), + .txdmasem = SEM_INITIALIZER(0), +#endif + .lock = NXMUTEX_INITIALIZER, +}; + static const struct efm32_spiconfig_s g_spi0config = { .base = EFM32_USART0_BASE, @@ -249,7 +257,15 @@ static const struct efm32_spiconfig_s g_spi0config = #ifdef CONFIG_EFM32_USART1_ISSPI /* Support for SPI on USART1 */ -static struct efm32_spidev_s g_spi1dev; +static struct efm32_spidev_s g_spi1dev = +{ +#ifdef CONFIG_EFM32_SPI_DMA + .rxdmasem = SEM_INITIALIZER(0), + .txdmasem = SEM_INITIALIZER(0), +#endif + .lock = NXMUTEX_INITIALIZER, +}; + static const struct efm32_spiconfig_s g_spi1config = { .base = EFM32_USART1_BASE, @@ -272,7 +288,15 @@ static const struct efm32_spiconfig_s g_spi1config = #ifdef CONFIG_EFM32_USART2_ISSPI /* Support for SPI on USART2 */ -static struct efm32_spidev_s g_spi2dev; +static struct efm32_spidev_s g_spi2dev = +{ +#ifdef CONFIG_EFM32_SPI_DMA + .rxdmasem = SEM_INITIALIZER(0), + .txdmasem = SEM_INITIALIZER(0), +#endif + .lock = NXMUTEX_INITIALIZER, +}; + static const struct efm32_spiconfig_s g_spi2config = { .base = EFM32_USART2_BASE, @@ -1577,10 +1601,6 @@ static int spi_portinitialize(struct efm32_spidev_s *priv) spi_putreg(config, EFM32_USART_CMD_OFFSET, USART_CMD_MASTEREN); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_EFM32_SPI_DMA /* Allocate two DMA channels... one for the RX and one for the TX side of * the transfer. @@ -1601,12 +1621,6 @@ static int spi_portinitialize(struct efm32_spidev_s *priv) port); goto errout_with_rxdmach; } - - /* Initialized semaphores used to wait for DMA completion */ - - nxsem_init(&priv->rxdmasem, 0, 0); - nxsem_init(&priv->txdmasem, 0, 0); - #endif /* Enable SPI */ diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c index 1e4ffad448..258ece1f09 100644 --- a/arch/arm/src/efm32/efm32_usbhost.c +++ b/arch/arm/src/efm32/efm32_usbhost.c @@ -484,7 +484,11 @@ static inline int efm32_hw_initialize(struct efm32_usbhost_s *priv); * single global instance. */ -static struct efm32_usbhost_s g_usbhost; +static struct efm32_usbhost_s g_usbhost = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), +}; /* This is the connection/enumeration interface */ @@ -5259,11 +5263,6 @@ static inline void efm32_sw_initialize(struct efm32_usbhost_s *priv) usbhost_devaddr_initialize(&priv->rhport); - /* Initialize semaphores & mutex */ - - nxsem_init(&priv->pscsem, 0, 0); - nxmutex_init(&priv->lock); - /* Initialize the driver state data */ priv->smstate = SMSTATE_DETACHED; diff --git a/arch/arm/src/gd32f4/gd32f4xx_dma.c b/arch/arm/src/gd32f4/gd32f4xx_dma.c index 8d4ed14bbf..67cdef1481 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_dma.c +++ b/arch/arm/src/gd32f4/gd32f4xx_dma.c @@ -90,82 +90,98 @@ static struct gd32_dma_channel_s g_dmachan[DMA_NCHANNELS] = { .chan_num = GD32_DMA_CH0, .irq = GD32_IRQ_DMA0_CHANNEL0, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA0, }, { .chan_num = GD32_DMA_CH1, .irq = GD32_IRQ_DMA0_CHANNEL1, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA0, }, { .chan_num = GD32_DMA_CH2, .irq = GD32_IRQ_DMA0_CHANNEL2, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA0, }, { .chan_num = GD32_DMA_CH3, .irq = GD32_IRQ_DMA0_CHANNEL3, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA0, }, { .chan_num = GD32_DMA_CH4, .irq = GD32_IRQ_DMA0_CHANNEL4, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA0, }, { .chan_num = GD32_DMA_CH5, .irq = GD32_IRQ_DMA0_CHANNEL5, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA0, }, { .chan_num = GD32_DMA_CH6, .irq = GD32_IRQ_DMA0_CHANNEL6, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA0, }, { .chan_num = GD32_DMA_CH7, .irq = GD32_IRQ_DMA0_CHANNEL7, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA0, }, { .chan_num = GD32_DMA_CH0, .irq = GD32_IRQ_DMA1_CHANNEL0, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA1, }, { .chan_num = GD32_DMA_CH1, .irq = GD32_IRQ_DMA1_CHANNEL1, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA1, }, { .chan_num = GD32_DMA_CH2, .irq = GD32_IRQ_DMA1_CHANNEL2, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA1, }, { .chan_num = GD32_DMA_CH3, .irq = GD32_IRQ_DMA1_CHANNEL3, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA1, }, { .chan_num = GD32_DMA_CH4, .irq = GD32_IRQ_DMA1_CHANNEL4, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA1, }, { .chan_num = GD32_DMA_CH5, .irq = GD32_IRQ_DMA1_CHANNEL5, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA1, }, { .chan_num = GD32_DMA_CH6, .irq = GD32_IRQ_DMA1_CHANNEL6, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA1, }, { .chan_num = GD32_DMA_CH7, .irq = GD32_IRQ_DMA1_CHANNEL7, + .chsem = SEM_INITIALIZER(1), .dmabase = GD32_DMA1, }, }; @@ -517,8 +533,6 @@ void weak_function arm_dma_initialize(void) DEBUGASSERT(dmachan != NULL); - nxsem_init(&dmachan->chsem, 0, 1); - /* Attach DMA interrupt vectors */ irq_attach(dmachan->irq, gd32_dma_interrupt, dmachan); diff --git a/arch/arm/src/gd32f4/gd32f4xx_spi.c b/arch/arm/src/gd32f4/gd32f4xx_spi.c index fee72e36bc..75c941c5ab 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_spi.c +++ b/arch/arm/src/gd32f4/gd32f4xx_spi.c @@ -298,6 +298,7 @@ static struct gd32_spidev_s g_spi0dev = }, .spibase = GD32_SPI0, .spiclock = GD32_PCLK2_FREQUENCY, + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_GD32F4_SPI_INTERRUPT .spiirq = GD32_IRQ_SPI0, #endif @@ -314,6 +315,8 @@ static struct gd32_spidev_s g_spi0dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif }; #endif @@ -363,6 +366,7 @@ static struct gd32_spidev_s g_spi1dev = }, .spibase = GD32_SPI1, .spiclock = GD32_PCLK1_FREQUENCY, + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_GD32F4_SPI_INTERRUPT .spiirq = GD32_IRQ_SPI1, #endif @@ -379,6 +383,8 @@ static struct gd32_spidev_s g_spi1dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif }; #endif @@ -428,6 +434,7 @@ static struct gd32_spidev_s g_spi2dev = }, .spibase = GD32_SPI2, .spiclock = GD32_PCLK1_FREQUENCY, + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_GD32F4_SPI_INTERRUPT .spiirq = GD32_IRQ_SPI2, #endif @@ -444,6 +451,8 @@ static struct gd32_spidev_s g_spi2dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif }; #endif @@ -493,6 +502,7 @@ static struct gd32_spidev_s g_spi3dev = }, .spibase = GD32_SPI3, .spiclock = GD32_PCLK2_FREQUENCY, + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_GD32F4_SPI_INTERRUPT .spiirq = GD32_IRQ_SPI3, #endif @@ -509,6 +519,8 @@ static struct gd32_spidev_s g_spi3dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif }; #endif @@ -558,6 +570,7 @@ static struct gd32_spidev_s g_spi4dev = }, .spibase = GD32_SPI4, .spiclock = GD32_PCLK2_FREQUENCY, + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_GD32F4_SPI_INTERRUPT .spiirq = GD32_IRQ_SPI4, #endif @@ -574,6 +587,8 @@ static struct gd32_spidev_s g_spi4dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif }; #endif @@ -623,6 +638,7 @@ static struct gd32_spidev_s g_spi5dev = }, .spibase = GD32_SPI5, .spiclock = GD32_PCLK2_FREQUENCY, + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_GD32F5_SPI_INTERRUPT .spiirq = GD32_IRQ_SPI5, #endif @@ -639,6 +655,8 @@ static struct gd32_spidev_s g_spi5dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif }; #endif @@ -2041,23 +2059,11 @@ static void spi_bus_initialize(struct gd32_spidev_s *priv) spi_setfrequency((struct spi_dev_s *)priv, 400000); - /* Initialize the SPI lock that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_GD32F4_SPI_DMA - /* Initialize the SPI semaphores that is used to wait for DMA completion. - * This semaphore is used for signaling and, hence, should not have - * priority inheritance enabled. - */ - if (priv->rxch && priv->txch) { if (priv->txdma == NULL && priv->rxdma == NULL) { - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); - /* Get DMA channels */ priv->rxdma = gd32_dma_channel_alloc(priv->rxch); diff --git a/arch/arm/src/imx1/imx_spi.c b/arch/arm/src/imx1/imx_spi.c index 1f6512bf66..080bcb946d 100644 --- a/arch/arm/src/imx1/imx_spi.c +++ b/arch/arm/src/imx1/imx_spi.c @@ -209,7 +209,9 @@ static struct imx_spidev_s g_spidev[] = { .ops = &g_spiops, .base = IMX_CSPI1_VBASE, + .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_SPI_POLLWAIT + .waitsem = SEM_INITIALIZER(0), .irq = IMX_IRQ_CSPI1, #endif }, @@ -218,7 +220,9 @@ static struct imx_spidev_s g_spidev[] = { .ops = &g_spiops, .base = IMX_CSPI2_VBASE, + .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_SPI_POLLWAIT + .waitsem = SEM_INITIALIZER(0), .irq = IMX_IRQ_CSPI2, #endif }, @@ -1108,11 +1112,6 @@ struct spi_dev_s *imx_spibus_initialize(int port) /* Initialize the state structure */ -#ifndef CONFIG_SPI_POLLWAIT - nxsem_init(&priv->waitsem, 0, 0); -#endif - nxmutex_init(&priv->lock); - /* Initialize control register: * min frequency, ignore ready, master mode, mode=0, 8-bit */ diff --git a/arch/arm/src/imx6/imx_ecspi.c b/arch/arm/src/imx6/imx_ecspi.c index 6a74f73fa1..49455a8c2e 100644 --- a/arch/arm/src/imx6/imx_ecspi.c +++ b/arch/arm/src/imx6/imx_ecspi.c @@ -268,7 +268,9 @@ static struct imx_spidev_s g_spidev[] = .ops = &g_spiops, .base = IMX_ECSPI1_VBASE, .spindx = SPI1_NDX, + .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_SPI_POLLWAIT + .waitsem = SEM_INITIALIZER(0), .irq = IMX_IRQ_ECSPI1, #endif .select = imx_spi1select, @@ -284,7 +286,9 @@ static struct imx_spidev_s g_spidev[] = .ops = &g_spiops, .base = IMX_ECSPI2_VBASE, .spindx = SPI2_NDX, + .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_SPI_POLLWAIT + .waitsem = SEM_INITIALIZER(0), .irq = IMX_IRQ_ECSPI2, #endif .select = imx_spi2select, @@ -300,7 +304,9 @@ static struct imx_spidev_s g_spidev[] = .ops = &g_spiops, .base = IMX_ECSPI3_VBASE, .spindx = SPI3_NDX, + .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_SPI_POLLWAIT + .waitsem = SEM_INITIALIZER(0), .irq = IMX_IRQ_ECSPI3, #endif .select = imx_spi3select, @@ -316,7 +322,9 @@ static struct imx_spidev_s g_spidev[] = .ops = &g_spiops, .base = IMX_ECSPI4_VBASE, .spindx = SPI4_NDX, + .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_SPI_POLLWAIT + .waitsem = SEM_INITIALIZER(0), .irq = IMX_IRQ_ECSPI4, #endif .select = imx_spi4select, @@ -332,7 +340,9 @@ static struct imx_spidev_s g_spidev[] = .ops = &g_spiops, .base = IMX_ECSPI5_VBASE, .spindx = SPI5_NDX, + .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_SPI_POLLWAIT + .waitsem = SEM_INITIALIZER(0), .irq = IMX_IRQ_ECSPI5, #endif .select = imx_spi5select, @@ -1282,13 +1292,6 @@ struct spi_dev_s *imx_spibus_initialize(int port) /* Initialize the state structure */ - /* Initialize Semaphores */ - -#ifndef CONFIG_SPI_POLLWAIT - nxsem_init(&priv->waitsem, 0, 0); -#endif - nxmutex_init(&priv->lock); - /* Initialize control register: * min frequency, ignore ready, master mode, mode=0, 8-bit */ diff --git a/arch/arm/src/imxrt/imxrt_edma.c b/arch/arm/src/imxrt/imxrt_edma.c index d4bd9866d2..b5c58278ff 100644 --- a/arch/arm/src/imxrt/imxrt_edma.c +++ b/arch/arm/src/imxrt/imxrt_edma.c @@ -155,7 +155,13 @@ struct imxrt_edma_s /* The state of the eDMA */ -static struct imxrt_edma_s g_edma; +static struct imxrt_edma_s g_edma = +{ + .chlock = NXMUTEX_INITIALIZER, +#if CONFIG_IMXRT_EDMA_NTCD > 0 + .dsem = SEM_INITIALIZER(CONFIG_IMXRT_EDMA_NTCD), +#endif +}; #if CONFIG_IMXRT_EDMA_NTCD > 0 /* This is a singly-linked list of free TCDs */ @@ -740,18 +746,12 @@ void weak_function arm_dma_initialize(void) /* Initialize data structures */ - memset(&g_edma, 0, sizeof(struct imxrt_edma_s)); for (i = 0; i < IMXRT_EDMA_NCHANNELS; i++) { g_edma.dmach[i].chan = i; } - /* Initialize mutex & semaphores */ - - nxmutex_init(&g_edma.chlock); #if CONFIG_IMXRT_EDMA_NTCD > 0 - nxsem_init(&g_edma.dsem, 0, CONFIG_IMXRT_EDMA_NTCD); - /* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */ imxrt_tcd_initialize(); diff --git a/arch/arm/src/imxrt/imxrt_ehci.c b/arch/arm/src/imxrt/imxrt_ehci.c index 87985e8931..4e2bd8edf3 100644 --- a/arch/arm/src/imxrt/imxrt_ehci.c +++ b/arch/arm/src/imxrt/imxrt_ehci.c @@ -567,7 +567,12 @@ static int imxrt_reset(void); * single global instance. */ -static struct imxrt_ehci_s g_ehci; +static struct imxrt_ehci_s g_ehci = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), + .ep0.iocsem = SEM_INITIALIZER(1), +}; /* This is the connection/enumeration interface */ @@ -4993,15 +4998,6 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller) usbhost_vtrace1(EHCI_VTRACE1_INITIALIZING, 0); - /* Initialize the EHCI state data structure */ - - nxmutex_init(&g_ehci.lock); - nxsem_init(&g_ehci.pscsem, 0, 0); - - /* Initialize EP0 */ - - nxsem_init(&g_ehci.ep0.iocsem, 0, 1); - /* Initialize the root hub port structures */ for (i = 0; i < IMXRT_EHCI_NRHPORT; i++) diff --git a/arch/arm/src/imxrt/imxrt_enc.c b/arch/arm/src/imxrt/imxrt_enc.c index 92ed32915d..2e6f201e7d 100644 --- a/arch/arm/src/imxrt/imxrt_enc.c +++ b/arch/arm/src/imxrt/imxrt_enc.c @@ -403,6 +403,7 @@ static struct imxrt_enc_lowerhalf_s imxrt_enc1_priv = .ops = &g_qecallbacks, .config = &imxrt_enc1_config, .data = &imxrt_enc1_data, + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -441,6 +442,7 @@ static struct imxrt_enc_lowerhalf_s imxrt_enc2_priv = .ops = &g_qecallbacks, .config = &imxrt_enc2_config, .data = &imxrt_enc2_data, + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -479,6 +481,7 @@ static struct imxrt_enc_lowerhalf_s imxrt_enc3_priv = .ops = &g_qecallbacks, .config = &imxrt_enc3_config, .data = &imxrt_enc3_data, + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -517,6 +520,7 @@ static struct imxrt_enc_lowerhalf_s imxrt_enc4_priv = .ops = &g_qecallbacks, .config = &imxrt_enc4_config, .data = &imxrt_enc4_data, + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -1225,10 +1229,6 @@ int imxrt_qeinitialize(const char *devpath, int enc) return -ENODEV; } - /* Initialize private data */ - - nxmutex_init(&priv->lock); - /* Register the upper-half driver */ int ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv); diff --git a/arch/arm/src/imxrt/imxrt_flexspi.c b/arch/arm/src/imxrt/imxrt_flexspi.c index 60473461d5..070c6f5afb 100644 --- a/arch/arm/src/imxrt/imxrt_flexspi.c +++ b/arch/arm/src/imxrt/imxrt_flexspi.c @@ -113,6 +113,7 @@ static struct imxrt_flexspidev_s g_flexspi0dev = .ops = &g_flexspi0ops, }, .base = (struct flexspi_type_s *) IMXRT_FLEXSPIC_BASE, + .lock = NXMUTEX_INITIALIZER, }; #define FREQ_1MHz (1000000ul) @@ -1268,12 +1269,6 @@ struct flexspi_dev_s *imxrt_flexspi_initialize(int intf) { /* No perform one time initialization */ - /* Initialize the FlexSPI mutex that enforces mutually exclusive - * access to the FlexSPI registers. - */ - - nxmutex_init(&priv->lock); - /* Perform hardware initialization. Puts the FlexSPI into an active * state. */ diff --git a/arch/arm/src/imxrt/imxrt_lpspi.c b/arch/arm/src/imxrt/imxrt_lpspi.c index da5ee76a7b..c478a28048 100644 --- a/arch/arm/src/imxrt/imxrt_lpspi.c +++ b/arch/arm/src/imxrt/imxrt_lpspi.c @@ -248,9 +248,12 @@ static struct imxrt_lpspidev_s g_lpspi1dev = #ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS .spiirq = IMXRT_IRQ_LPSPI1, #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_IMXRT_LPSPI1_DMA .rxch = IMXRT_DMACHAN_LPSPI1_RX, .txch = IMXRT_DMACHAN_LPSPI1_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif }; #endif @@ -294,9 +297,12 @@ static struct imxrt_lpspidev_s g_lpspi2dev = #ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS .spiirq = IMXRT_IRQ_LPSPI2, #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_IMXRT_LPSPI2_DMA .rxch = IMXRT_DMACHAN_LPSPI2_RX, .txch = IMXRT_DMACHAN_LPSPI2_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif }; #endif @@ -340,9 +346,12 @@ static struct imxrt_lpspidev_s g_lpspi3dev = #ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS .spiirq = IMXRT_IRQ_LPSPI3, #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_IMXRT_LPSPI3_DMA .rxch = IMXRT_DMACHAN_LPSPI3_RX, .txch = IMXRT_DMACHAN_LPSPI3_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif }; #endif @@ -386,9 +395,12 @@ static struct imxrt_lpspidev_s g_lpspi4dev = #ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS .spiirq = IMXRT_IRQ_LPSPI4, #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_IMXRT_LPSPI4_DMA .rxch = IMXRT_DMACHAN_LPSPI4_RX, .txch = IMXRT_DMACHAN_LPSPI4_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif }; #endif @@ -1691,10 +1703,6 @@ static void imxrt_lpspi_bus_initialize(struct imxrt_lpspidev_s *priv) imxrt_lpspi_setmode((struct spi_dev_s *)priv, SPIDEV_MODE0); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - /* Enable LPSPI */ imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); @@ -2021,18 +2029,10 @@ struct spi_dev_s *imxrt_lpspibus_initialize(int bus) } #ifdef CONFIG_IMXRT_LPSPI_DMA - /* Initialize the SPI semaphores that is used to wait for DMA completion. - * This semaphore is used for signaling and, hence, should not have - * priority inheritance enabled. - */ - if (priv->rxch && priv->txch) { if (priv->txdma == NULL && priv->rxdma == NULL) { - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); - priv->txdma = imxrt_dmach_alloc(priv->txch | DMAMUX_CHCFG_ENBL, 0); priv->rxdma = imxrt_dmach_alloc(priv->rxch | DMAMUX_CHCFG_ENBL, diff --git a/arch/arm/src/imxrt/imxrt_rtc_lowerhalf.c b/arch/arm/src/imxrt/imxrt_rtc_lowerhalf.c index bbf765f8f9..2ed3717f11 100644 --- a/arch/arm/src/imxrt/imxrt_rtc_lowerhalf.c +++ b/arch/arm/src/imxrt/imxrt_rtc_lowerhalf.c @@ -128,7 +128,8 @@ static const struct rtc_ops_s g_rtc_ops = static struct imxrt_lowerhalf_s g_rtc_lowerhalf = { - .ops = &g_rtc_ops, + .ops = &g_rtc_ops, + .devlock = NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -514,7 +515,6 @@ static int imxrt_rdalarm(struct rtc_lowerhalf_s *lower, struct rtc_lowerhalf_s *imxrt_rtc_lowerhalf(void) { - nxmutex_init(&g_rtc_lowerhalf.devlock); return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/imxrt/imxrt_serial.c b/arch/arm/src/imxrt/imxrt_serial.c index 6503a585fc..3d24db6e00 100644 --- a/arch/arm/src/imxrt/imxrt_serial.c +++ b/arch/arm/src/imxrt/imxrt_serial.c @@ -846,6 +846,7 @@ static struct imxrt_uart_s g_lpuart1priv = #ifdef CONFIG_LPUART1_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART1_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_LPUART1_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART1_RX, @@ -914,6 +915,7 @@ static struct imxrt_uart_s g_lpuart2priv = #ifdef CONFIG_LPUART2_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART2_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_LPUART2_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART2_RX, @@ -980,6 +982,7 @@ static struct imxrt_uart_s g_lpuart3priv = #ifdef CONFIG_LPUART3_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART3_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_LPUART3_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART3_RX, @@ -1046,6 +1049,7 @@ static struct imxrt_uart_s g_lpuart4priv = #ifdef CONFIG_LPUART4_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART4_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_LPUART4_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART4_RX, @@ -1112,6 +1116,7 @@ static struct imxrt_uart_s g_lpuart5priv = #ifdef CONFIG_LPUART5_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART5_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_LPUART5_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART5_RX, @@ -1178,6 +1183,7 @@ static struct imxrt_uart_s g_lpuart6priv = #ifdef CONFIG_LPUART6_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART6_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_LPUART6_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART6_RX, @@ -1244,6 +1250,7 @@ static struct imxrt_uart_s g_lpuart7priv = #ifdef CONFIG_LPUART7_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART7_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_LPUART7_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART7_RX, @@ -1310,6 +1317,7 @@ static struct imxrt_uart_s g_lpuart8priv = #ifdef CONFIG_LPUART8_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART8_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_LPUART8_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART8_RX, @@ -1457,8 +1465,6 @@ static int imxrt_dma_setup(struct uart_dev_s *dev) { return -EBUSY; } - - nxsem_init(&priv->txdmasem, 0, 1); } /* Enable Tx DMA for the UART */ @@ -1659,7 +1665,6 @@ static void imxrt_dma_shutdown(struct uart_dev_s *dev) imxrt_dmach_free(priv->txdma); priv->txdma = NULL; - nxsem_destroy(&priv->txdmasem); } #endif } diff --git a/arch/arm/src/imxrt/imxrt_usdhc.c b/arch/arm/src/imxrt/imxrt_usdhc.c index 0f2c2679a8..03aef2d8dc 100644 --- a/arch/arm/src/imxrt/imxrt_usdhc.c +++ b/arch/arm/src/imxrt/imxrt_usdhc.c @@ -422,7 +422,8 @@ struct imxrt_dev_s g_sdhcdev[IMXRT_MAX_SDHC_DEV_SLOTS] = .dmasendsetup = imxrt_sendsetup, #endif #endif - } + }, + .waitsem = SEM_INITIALIZER(0), }, #endif @@ -479,7 +480,8 @@ struct imxrt_dev_s g_sdhcdev[IMXRT_MAX_SDHC_DEV_SLOTS] = .dmarecvsetup = imxrt_recvsetup, .dmasendsetup = imxrt_sendsetup, #endif - } + }, + .waitsem = SEM_INITIALIZER(0), } #endif #endif @@ -3215,11 +3217,8 @@ struct sdio_dev_s *imxrt_usdhc_initialize(int slotno) DEBUGASSERT(slotno < IMXRT_MAX_SDHC_DEV_SLOTS); struct imxrt_dev_s *priv = &g_sdhcdev[slotno]; - /* Initialize the USDHC slot structure data structure - * Initialize semaphores - */ + /* Initialize the USDHC slot structure data structure */ - nxsem_init(&priv->waitsem, 0, 0); switch (priv->addr) { case IMXRT_USDHC1_BASE: diff --git a/arch/arm/src/kinetis/kinetis_edma.c b/arch/arm/src/kinetis/kinetis_edma.c index 2cbabd41b0..6120e94d60 100644 --- a/arch/arm/src/kinetis/kinetis_edma.c +++ b/arch/arm/src/kinetis/kinetis_edma.c @@ -157,7 +157,13 @@ struct kinetis_edma_s /* The state of the eDMA */ -static struct kinetis_edma_s g_edma; +static struct kinetis_edma_s g_edma = +{ + .chlock = NXMUTEX_INITIALIZER, +#if CONFIG_KINETIS_EDMA_NTCD > 0 + .dsem = SEM_INITIALIZER(CONFIG_KINETIS_EDMA_NTCD), +#endif +}; #if CONFIG_KINETIS_EDMA_NTCD > 0 /* This is a singly-linked list of free TCDs */ @@ -721,18 +727,12 @@ void weak_function arm_dma_initialize(void) /* Initialize data structures */ - memset(&g_edma, 0, sizeof(struct kinetis_edma_s)); for (i = 0; i < KINETIS_EDMA_NCHANNELS; i++) { g_edma.dmach[i].chan = i; } - /* Initialize mutex & semaphore */ - - nxmutex_init(&g_edma.chlock); #if CONFIG_KINETIS_EDMA_NTCD > 0 - nxsem_init(&g_edma.dsem, 0, CONFIG_KINETIS_EDMA_NTCD); - /* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */ kinetis_tcd_initialize(); diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c index ab2c9d663c..4f7cdffa36 100644 --- a/arch/arm/src/kinetis/kinetis_sdhc.c +++ b/arch/arm/src/kinetis/kinetis_sdhc.c @@ -397,6 +397,7 @@ struct kinetis_dev_s g_sdhcdev = #endif #endif }, + .waitsem = SEM_INITIALIZER(0), }; /* Register logging support */ @@ -2851,10 +2852,6 @@ struct sdio_dev_s *sdhc_initialize(int slotno) /* Initialize the SDHC slot structure data structure */ - /* Initialize semaphores */ - - nxsem_init(&priv->waitsem, 0, 0); - /* In addition to the system clock, the SDHC module needs a clock for the * base for the external card clock. There are four possible sources for * this clock, selected by the SIM's SOPT2 register: diff --git a/arch/arm/src/kinetis/kinetis_spi.c b/arch/arm/src/kinetis/kinetis_spi.c index 33f8ac0a7e..7843d33ded 100644 --- a/arch/arm/src/kinetis/kinetis_spi.c +++ b/arch/arm/src/kinetis/kinetis_spi.c @@ -226,6 +226,7 @@ static struct kinetis_spidev_s g_spi0dev = &g_spi0ops }, .spibase = KINETIS_SPI0_BASE, + .lock = NXMUTEX_INITIALIZER, .ctarsel = KINETIS_SPI_CTAR0_OFFSET, #ifdef CONFIG_KINETIS_SPI_DMA # ifdef CONFIG_KINETIS_SPI0_DMA @@ -235,6 +236,8 @@ static struct kinetis_spidev_s g_spi0dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif }; #endif @@ -275,6 +278,7 @@ static struct kinetis_spidev_s g_spi1dev = &g_spi1ops }, .spibase = KINETIS_SPI1_BASE, + .lock = NXMUTEX_INITIALIZER, .ctarsel = KINETIS_SPI_CTAR0_OFFSET, #ifdef CONFIG_KINETIS_SPI_DMA # ifdef CONFIG_KINETIS_SPI1_DMA @@ -284,6 +288,8 @@ static struct kinetis_spidev_s g_spi1dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif }; #endif @@ -324,6 +330,7 @@ static struct kinetis_spidev_s g_spi2dev = &g_spi2ops }, .spibase = KINETIS_SPI2_BASE, + .lock = NXMUTEX_INITIALIZER, .ctarsel = KINETIS_SPI_CTAR0_OFFSET, #ifdef CONFIG_KINETIS_SPI_DMA # ifdef CONFIG_KINETIS_SPI2_DMA @@ -333,6 +340,8 @@ static struct kinetis_spidev_s g_spi2dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif }; #endif @@ -1666,22 +1675,11 @@ struct spi_dev_s *kinetis_spibus_initialize(int port) priv->frequency = 0; spi_setfrequency(&priv->spidev, KINETIS_SPI_CLK_INIT); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); #ifdef CONFIG_KINETIS_SPI_DMA - /* Initialize the SPI semaphores that is used to wait for DMA completion. - * This semaphore is used for signaling and, hence, should not have - * priority inheritance enabled. - */ - if (priv->rxch && priv->txch) { if (priv->txdma == NULL && priv->rxdma == NULL) { - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); - priv->txdma = kinetis_dmach_alloc(priv->txch | DMAMUX_CHCFG_ENBL, 0); priv->rxdma = kinetis_dmach_alloc(priv->rxch | DMAMUX_CHCFG_ENBL, diff --git a/arch/arm/src/kinetis/kinetis_usbhshost.c b/arch/arm/src/kinetis/kinetis_usbhshost.c index d0415e0f2b..fdf1baebaf 100644 --- a/arch/arm/src/kinetis/kinetis_usbhshost.c +++ b/arch/arm/src/kinetis/kinetis_usbhshost.c @@ -588,7 +588,12 @@ static int kinetis_reset(void); * single global instance. */ -static struct kinetis_ehci_s g_ehci; +static struct kinetis_ehci_s g_ehci = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), + .ep0.iocsem = SEM_INITIALIZER(1), +}; /* This is the connection/enumeration interface */ @@ -5067,15 +5072,6 @@ struct usbhost_connection_s *kinetis_ehci_initialize(int controller) usbhost_vtrace1(EHCI_VTRACE1_INITIALIZING, 0); - /* Initialize the EHCI state data structure */ - - nxmutex_init(&g_ehci.lock); - nxsem_init(&g_ehci.pscsem, 0, 0); - - /* Initialize EP0 */ - - nxsem_init(&g_ehci.ep0.iocsem, 0, 1); - /* Initialize the root hub port structures */ for (i = 0; i < KINETIS_EHCI_NRHPORT; i++) diff --git a/arch/arm/src/kl/kl_spi.c b/arch/arm/src/kl/kl_spi.c index 248614b081..18e0777b14 100644 --- a/arch/arm/src/kl/kl_spi.c +++ b/arch/arm/src/kl/kl_spi.c @@ -126,6 +126,7 @@ static struct kl_spidev_s g_spi0dev = &g_spi0ops }, .spibase = KL_SPI0_BASE, + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -158,6 +159,7 @@ static struct kl_spidev_s g_spi1dev = &g_spi1ops }, .spibase = KL_SPI1_BASE, + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -688,10 +690,6 @@ struct spi_dev_s *kl_spibus_initialize(int port) /* Select a default frequency of approx. 400KHz */ spi_setfrequency((struct spi_dev_s *)priv, 400000); - - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); return &priv->spidev; } diff --git a/arch/arm/src/lc823450/lc823450_dma.c b/arch/arm/src/lc823450/lc823450_dma.c index 777eb5b4f5..499bede1de 100644 --- a/arch/arm/src/lc823450/lc823450_dma.c +++ b/arch/arm/src/lc823450/lc823450_dma.c @@ -122,7 +122,10 @@ static int phydmastart(struct lc823450_phydmach_s *pdmach); * Private Data ****************************************************************************/ -static struct lc823450_dma_s g_dma; +static struct lc823450_dma_s g_dma = +{ + .lock = NXMUTEX_INITIALIZER, +}; volatile uint8_t g_dma_inprogress; /**************************************************************************** @@ -342,8 +345,6 @@ void arm_dma_initialize(void) sq_init(&g_dma.phydmach[i].req_q); } - nxmutex_init(&g_dma.lock); - if (irq_attach(LC823450_IRQ_DMAC, dma_interrupt, NULL) != 0) { return; diff --git a/arch/arm/src/lc823450/lc823450_i2s.c b/arch/arm/src/lc823450/lc823450_i2s.c index 48af12ccb1..f6b7a62f3d 100644 --- a/arch/arm/src/lc823450/lc823450_i2s.c +++ b/arch/arm/src/lc823450/lc823450_i2s.c @@ -234,12 +234,12 @@ static const struct i2s_ops_s g_i2sops = }; static DMA_HANDLE _hrxdma; -static sem_t _sem_rxdma; -static sem_t _sem_buf_over; +static sem_t _sem_rxdma = SEM_INITIALIZER(0); +static sem_t _sem_buf_over = SEM_INITIALIZER(0); static DMA_HANDLE _htxdma; -static sem_t _sem_txdma; -static sem_t _sem_buf_under; +static sem_t _sem_txdma = SEM_INITIALIZER(0); +static sem_t _sem_buf_under = SEM_INITIALIZER(0); /**************************************************************************** * Public Data @@ -1034,12 +1034,7 @@ struct i2s_dev_s *lc823450_i2sdev_initialize(void) #endif _hrxdma = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL); - nxsem_init(&_sem_rxdma, 0, 0); - nxsem_init(&_sem_buf_over, 0, 0); - _htxdma = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL); - nxsem_init(&_sem_txdma, 0, 0); - nxsem_init(&_sem_buf_under, 0, 0); #ifdef CONFIG_SMP cpu_set_t cpuset0; diff --git a/arch/arm/src/lc823450/lc823450_sddrv_dep.c b/arch/arm/src/lc823450/lc823450_sddrv_dep.c index 17dbfbc390..8e84a05768 100644 --- a/arch/arm/src/lc823450/lc823450_sddrv_dep.c +++ b/arch/arm/src/lc823450/lc823450_sddrv_dep.c @@ -81,9 +81,17 @@ #ifdef CONFIG_LC823450_SDC_DMA static DMA_HANDLE _hrdma[2]; -static sem_t _sem_rwait[2]; +static sem_t _sem_rwait[2] = +{ + SEM_INITIALIZER(0), + SEM_INITIALIZER(0), +}; static DMA_HANDLE _hwdma[2]; -static sem_t _sem_wwait[2]; +static sem_t _sem_wwait[2] = +{ + SEM_INITIALIZER(0), + SEM_INITIALIZER(0), +}; #endif /* CONFIG_LC823450_SDC_DMA */ static uint64_t _sddep_timeout = (10 * 100); /* 10sec (in tick) */ @@ -281,9 +289,7 @@ SINT_T sddep_os_init(struct sddrcfg_s *cfg) #ifdef CONFIG_LC823450_SDC_DMA _hrdma[ch] = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL); - nxsem_init(&_sem_rwait[ch], 0, 0); _hwdma[ch] = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL); - nxsem_init(&_sem_wwait[ch], 0, 0); #endif /* CONFIG_LC823450_SDC_DMA */ return 0; } diff --git a/arch/arm/src/lc823450/lc823450_serial.c b/arch/arm/src/lc823450/lc823450_serial.c index 464cc037e7..37836c9706 100644 --- a/arch/arm/src/lc823450/lc823450_serial.c +++ b/arch/arm/src/lc823450/lc823450_serial.c @@ -253,6 +253,10 @@ static struct up_dev_s g_uart0priv = .parity = CONFIG_UART0_PARITY, .bits = CONFIG_UART0_BITS, .stopbits2 = CONFIG_UART0_2STOP, +#ifdef CONFIG_HSUART + .rxdma_wait = SEM_INITIALIZER(0), + .txdma_wait = SEM_INITIALIZER(1), +#endif }; static uart_dev_t g_uart0port = @@ -283,6 +287,10 @@ static struct up_dev_s g_uart1priv = .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, .stopbits2 = CONFIG_UART1_2STOP, +#ifdef CONFIG_HSUART + .rxdma_wait = SEM_INITIALIZER(0), + .txdma_wait = SEM_INITIALIZER(1), +#endif }; static uart_dev_t g_uart1port = @@ -313,6 +321,10 @@ static struct up_dev_s g_uart2priv = .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, .stopbits2 = CONFIG_UART2_2STOP, +#ifdef CONFIG_HSUART + .rxdma_wait = SEM_INITIALIZER(0), + .txdma_wait = SEM_INITIALIZER(1), +#endif }; static uart_dev_t g_uart2port = @@ -1329,11 +1341,9 @@ void arm_serialinit(void) #ifdef TTYS1_DEV uart_register("/dev/ttyS1", &TTYS1_DEV); #ifdef CONFIG_HSUART - nxsem_init(&g_uart1priv.txdma_wait, 0, 1); g_uart1priv.htxdma = lc823450_dmachannel(DMA_CHANNEL_UART1TX); lc823450_dmarequest(g_uart1priv.htxdma, DMA_REQUEST_UART1TX); - nxsem_init(&g_uart1priv.rxdma_wait, 0, 0); g_uart1priv.hrxdma = lc823450_dmachannel(DMA_CHANNEL_UART1RX); lc823450_dmarequest(g_uart1priv.hrxdma, DMA_REQUEST_UART1RX); diff --git a/arch/arm/src/lc823450/lc823450_spi.c b/arch/arm/src/lc823450/lc823450_spi.c index 660a4b4106..3f1144c8fd 100644 --- a/arch/arm/src/lc823450/lc823450_spi.c +++ b/arch/arm/src/lc823450/lc823450_spi.c @@ -130,6 +130,12 @@ static struct lc823450_spidev_s g_spidev = { &g_spiops }, +#ifndef CONFIG_SPI_OWNBUS + .lock = NXMUTEX_INITIALIZER, +#endif +#ifdef CONFIG_LC823450_SPI_DMA + .dma_wait = SEM_INITIALIZER(0), +#endif }; /**************************************************************************** @@ -523,10 +529,6 @@ struct spi_dev_s *lc823450_spibus_initialize(int port) modifyreg32(MCLKCNTAPB, 0, MCLKCNTAPB_PORT5_CLKEN); modifyreg32(MRSTCNTAPB, 0, MRSTCNTAPB_PORT5_RSTB); -#ifndef CONFIG_SPI_OWNBUS - nxmutex_init(&priv->lock); -#endif - /* Initialize SPI mode. It must be done before starting SPI transfer */ /* PO: SPI Mode3 (default) */ @@ -543,7 +545,6 @@ struct spi_dev_s *lc823450_spibus_initialize(int port) lc823450_spiinitialize(); #ifdef CONFIG_LC823450_SPI_DMA - nxsem_init(&priv->dma_wait, 0, 0); priv->hdma = lc823450_dmachannel(DMA_CHANNEL_SIOTX); lc823450_dmarequest(priv->hdma, DMA_REQUEST_SIOTX); diff --git a/arch/arm/src/lc823450/lc823450_usbdev.c b/arch/arm/src/lc823450/lc823450_usbdev.c index a3189a83cb..2ba3860ba9 100644 --- a/arch/arm/src/lc823450/lc823450_usbdev.c +++ b/arch/arm/src/lc823450/lc823450_usbdev.c @@ -189,7 +189,7 @@ extern int lc823450_dvfs_boost(int timeout); static struct lc823450_usbdev_s g_usbdev; static DMA_HANDLE g_hdma; -static sem_t dma_wait; +static sem_t dma_wait = SEM_INITIALIZER(0); #ifdef CONFIG_USBMSC_OPT static struct lc823450_dma_llist g_dma_list[16]; @@ -1453,7 +1453,6 @@ void arm_usbinitialize(void) return; } - nxsem_init(&dma_wait, 0, 0); g_hdma = lc823450_dmachannel(DMA_CHANNEL_USBDEV); lc823450_dmarequest(g_hdma, DMA_REQUEST_USBDEV); @@ -1722,7 +1721,6 @@ void usbdev_msc_read_enter() privep->epcmd &= ~USB_EPCMD_EMPTY_EN; epcmd_write(CONFIG_USBMSC_EPBULKIN, (privep->epcmd)); lc823450_dmareauest_dir(g_hdma, DMA_REQUEST_USBDEV, 1); - nxsem_init(&dma_wait, 0, 0); } /**************************************************************************** @@ -1825,7 +1823,6 @@ void usbdev_msc_write_enter0(void) privep->epcmd &= ~USB_EPCMD_READY_EN; epcmd_write(CONFIG_USBMSC_EPBULKOUT, (privep->epcmd)); lc823450_dmareauest_dir(g_hdma, DMA_REQUEST_USBDEV, 0); - nxsem_init(&dma_wait, 0, 0); } /**************************************************************************** diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c index 850064cacb..80261388f3 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c @@ -84,7 +84,10 @@ struct lpc17_40_gpdma_s /* The state of the LPC17 DMA block */ -static struct lpc17_40_gpdma_s g_gpdma; +static struct lpc17_40_gpdma_s g_gpdma = +{ + .lock = NXMUTEX_INITIALIZER, +}; /**************************************************************************** * Public Data @@ -291,8 +294,6 @@ void weak_function arm_dma_initialize(void) /* Initialize the DMA state structure */ - nxmutex_init(&g_gpdma.lock); - for (i = 0; i < LPC17_40_NDMACH; i++) { g_gpdma.dmach[i].chn = i; /* Channel number */ diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c index 2b4377509f..cf57a0decc 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c @@ -147,13 +147,25 @@ static int lpc17_40_i2c_reset(struct i2c_master_s * dev); ****************************************************************************/ #ifdef CONFIG_LPC17_40_I2C0 -static struct lpc17_40_i2cdev_s g_i2c0dev; +static struct lpc17_40_i2cdev_s g_i2c0dev = +{ + .lock = NXMUTEX_INITIALIZER, + .wait = SEM_INITIALIZER(0), +}; #endif #ifdef CONFIG_LPC17_40_I2C1 -static struct lpc17_40_i2cdev_s g_i2c1dev; +static struct lpc17_40_i2cdev_s g_i2c1dev = +{ + .lock = NXMUTEX_INITIALIZER, + .wait = SEM_INITIALIZER(0), +}; #endif #ifdef CONFIG_LPC17_40_I2C2 -static struct lpc17_40_i2cdev_s g_i2c2dev; +static struct lpc17_40_i2cdev_s g_i2c2dev = +{ + .lock = NXMUTEX_INITIALIZER, + .wait = SEM_INITIALIZER(0), +}; #endif struct i2c_ops_s lpc17_40_i2c_ops = @@ -617,11 +629,6 @@ struct i2c_master_s *lpc17_40_i2cbus_initialize(int port) putreg32(I2C_CONSET_I2EN, priv->base + LPC17_40_I2C_CONSET_OFFSET); - /* Initialize mutex & semaphores */ - - nxmutex_init(&priv->lock); - nxsem_init(&priv->wait, 0, 0); - /* Attach Interrupt Handler */ irq_attach(priv->irqid, lpc17_40_i2c_interrupt, priv); @@ -652,11 +659,6 @@ int lpc17_40_i2cbus_uninitialize(struct i2c_master_s * dev) putreg32(I2C_CONCLRT_I2ENC, priv->base + LPC17_40_I2C_CONCLR_OFFSET); - /* Reset data structures */ - - nxmutex_destroy(&priv->lock); - nxsem_destroy(&priv->wait); - /* Cancel the watchdog timer */ wd_cancel(&priv->timeout); diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c index dcd4f15bb3..060abced66 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c @@ -444,6 +444,7 @@ struct lpc17_40_dev_s g_scard_dev = #endif #endif }, + .waitsem = SEM_INITIALIZER(0), }; /* Register logging support */ @@ -2719,10 +2720,6 @@ struct sdio_dev_s *sdio_initialize(int slotno) /* Initialize the SD card slot structure */ - /* Initialize semaphores */ - - nxsem_init(&priv->waitsem, 0, 0); - #ifdef CONFIG_LPC17_40_SDCARD_DMA /* Configure the SDCARD DMA request */ diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c index 5ce5a18c9b..88b3ee8be7 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c @@ -142,6 +142,7 @@ static struct lpc17_40_spidev_s g_spidev = { &g_spiops }, + .lock = NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -563,10 +564,6 @@ struct spi_dev_s *lpc17_40_spibus_initialize(int port) /* Select a default frequency of approx. 400KHz */ spi_setfrequency((struct spi_dev_s *)priv, 400000); - - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); return &priv->spidev; } diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c index 39dbb6a4b3..f5977a4be7 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c @@ -184,6 +184,7 @@ static struct lpc17_40_sspdev_s g_ssp0dev = #ifdef CONFIG_LPC17_40_SSP_INTERRUPTS .sspirq = LPC17_40_IRQ_SSP0, #endif + .lock = NXMUTEX_INITIALIZER, }; #endif /* CONFIG_LPC17_40_SSP0 */ @@ -219,6 +220,7 @@ static struct lpc17_40_sspdev_s g_ssp1dev = #ifdef CONFIG_LPC17_40_SSP_INTERRUPTS .sspirq = LPC17_40_IRQ_SSP1, #endif + .lock = NXMUTEX_INITIALIZER, }; #endif /* CONFIG_LPC17_40_SSP1 */ @@ -254,6 +256,7 @@ static struct lpc17_40_sspdev_s g_ssp2dev = #ifdef CONFIG_LPC17_40_SSP_INTERRUPTS .sspirq = LPC17_40_IRQ_SSP2, #endif + .lock = NXMUTEX_INITIALIZER, }; #endif /* CONFIG_LPC17_40_SSP2 */ @@ -993,10 +996,6 @@ struct spi_dev_s *lpc17_40_sspbus_initialize(int port) ssp_setfrequency((struct spi_dev_s *)priv, 400000); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - /* Enable the SPI */ regval = ssp_getreg(priv, LPC17_40_SSP_CR1_OFFSET); diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c index d5db4b1a38..116634245d 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c @@ -411,7 +411,11 @@ static inline void lpc17_40_ep0init(struct lpc17_40_usbhost_s *priv); * single global instance. */ -static struct lpc17_40_usbhost_s g_usbhost; +static struct lpc17_40_usbhost_s g_usbhost = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), +}; /* This is the connection/enumeration interface */ @@ -3736,11 +3740,6 @@ struct usbhost_connection_s *lpc17_40_usbhost_initialize(int controller) usbhost_devaddr_initialize(&priv->rhport); - /* Initialize semaphores & mutex */ - - nxsem_init(&priv->pscsem, 0, 0); - nxmutex_init(&priv->lock); - #ifndef CONFIG_USBHOST_INT_DISABLE priv->ininterval = MAX_PERINTERVAL; priv->outinterval = MAX_PERINTERVAL; diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.c b/arch/arm/src/lpc2378/lpc23xx_i2c.c index 9a00ad9258..d87c22101a 100644 --- a/arch/arm/src/lpc2378/lpc23xx_i2c.c +++ b/arch/arm/src/lpc2378/lpc23xx_i2c.c @@ -153,13 +153,25 @@ static int lpc2378_i2c_reset(struct i2c_master_s * dev); ****************************************************************************/ #ifdef CONFIG_LPC2378_I2C0 -static struct lpc2378_i2cdev_s g_i2c0dev; +static struct lpc2378_i2cdev_s g_i2c0dev = +{ + .lock = NXMUTEX_INITIALIZER, + .wait = SEM_INITIALIZER(0), +}; #endif #ifdef CONFIG_LPC2378_I2C1 -static struct lpc2378_i2cdev_s g_i2c1dev; +static struct lpc2378_i2cdev_s g_i2c1dev = +{ + .lock = NXMUTEX_INITIALIZER, + .wait = SEM_INITIALIZER(0), +}; #endif #ifdef CONFIG_LPC2378_I2C2 -static struct lpc2378_i2cdev_s g_i2c2dev; +static struct lpc2378_i2cdev_s g_i2c2dev = +{ + .lock = NXMUTEX_INITIALIZER, + .wait = SEM_INITIALIZER(0), +}; #endif struct i2c_ops_s lpc2378_i2c_ops = @@ -580,11 +592,6 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port) putreg32(I2C_CONSET_I2EN, priv->base + I2C_CONSET_OFFSET); - /* Initialize mutex & semaphores */ - - nxmutex_init(&priv->lock); - nxsem_init(&priv->wait, 0, 0); - /* Attach Interrupt Handler */ irq_attach(priv->irqid, lpc2378_i2c_interrupt, priv); @@ -615,11 +622,6 @@ int lpc2378_i2cbus_uninitialize(struct i2c_master_s * dev) putreg32(I2C_CONCLRT_I2ENC, priv->base + I2C_CONCLR_OFFSET); - /* Reset data structures */ - - nxmutex_destroy(&priv->lock); - nxsem_destroy(&priv->wait); - /* Cancel the watchdog timer */ wd_cancel(&priv->timeout); diff --git a/arch/arm/src/lpc2378/lpc23xx_spi.c b/arch/arm/src/lpc2378/lpc23xx_spi.c index d31abe09cd..85e0985ba8 100644 --- a/arch/arm/src/lpc2378/lpc23xx_spi.c +++ b/arch/arm/src/lpc2378/lpc23xx_spi.c @@ -161,6 +161,7 @@ static struct lpc23xx_spidev_s g_spidev = { &g_spiops }, + .lock = NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -588,10 +589,6 @@ struct spi_dev_s *lpc23_spibus_initialize(int port) /* Select a default frequency of approx. 400KHz */ spi_setfrequency((struct spi_dev_s *)priv, 400000); - - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); return &priv->spidev; } diff --git a/arch/arm/src/lpc31xx/lpc31_ehci.c b/arch/arm/src/lpc31xx/lpc31_ehci.c index cd72270202..5734ae6027 100644 --- a/arch/arm/src/lpc31xx/lpc31_ehci.c +++ b/arch/arm/src/lpc31xx/lpc31_ehci.c @@ -565,7 +565,12 @@ static int lpc31_reset(void); * global instance. */ -static struct lpc31_ehci_s g_ehci; +static struct lpc31_ehci_s g_ehci = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), + .ep0.iocsem = SEM_INITIALIZER(1), +}; /* This is the connection/enumeration interface */ @@ -5016,15 +5021,6 @@ struct usbhost_connection_s *lpc31_ehci_initialize(int controller) usbhost_vtrace1(EHCI_VTRACE1_INITIALIZING, 0); - /* Initialize the EHCI state data structure */ - - nxmutex_init(&g_ehci.lock); - nxsem_init(&g_ehci.pscsem, 0, 0); - - /* Initialize EP0 */ - - nxsem_init(&g_ehci.ep0.iocsem, 0, 1); - /* Initialize the root hub port structures */ for (i = 0; i < LPC31_EHCI_NRHPORT; i++) diff --git a/arch/arm/src/lpc31xx/lpc31_i2c.c b/arch/arm/src/lpc31xx/lpc31_i2c.c index b541c99862..8979cda244 100644 --- a/arch/arm/src/lpc31xx/lpc31_i2c.c +++ b/arch/arm/src/lpc31xx/lpc31_i2c.c @@ -90,7 +90,17 @@ struct lpc31_i2cdev_s #define I2C_STATE_HEADER 2 #define I2C_STATE_TRANSFER 3 -static struct lpc31_i2cdev_s i2cdevices[2]; +static struct lpc31_i2cdev_s i2cdevices[2] = +{ + { + .lock = NXMUTEX_INITIALIZER, + .wait = SEM_INITIALIZER(0), + }, + { + .lock = NXMUTEX_INITIALIZER, + .wait = SEM_INITIALIZER(0), + }, +}; /**************************************************************************** * Private Function Prototypes @@ -556,11 +566,6 @@ struct i2c_master_s *lpc31_i2cbus_initialize(int port) priv->rstid = (port == 0) ? RESETID_I2C0RST : RESETID_I2C1RST; priv->irqid = (port == 0) ? LPC31_IRQ_I2C0 : LPC31_IRQ_I2C1; - /* Initialize mutex & semaphores */ - - nxmutex_init(&priv->lock); - nxsem_init(&priv->wait, 0, 0); - /* Enable I2C system clocks */ lpc31_enableclock(priv->clkid); diff --git a/arch/arm/src/lpc31xx/lpc31_spi.c b/arch/arm/src/lpc31xx/lpc31_spi.c index 74df6b7655..3519b9fe8d 100644 --- a/arch/arm/src/lpc31xx/lpc31_spi.c +++ b/arch/arm/src/lpc31xx/lpc31_spi.c @@ -157,6 +157,7 @@ static struct lpc31_spidev_s g_spidev = { &g_spiops }, + .lock = NXMUTEX_INITIALIZER, }; #ifdef CONFIG_LPC31_SPI_REGDEBUG @@ -964,10 +965,6 @@ struct spi_dev_s *lpc31_spibus_initialize(int port) lpc31_softreset(RESETID_SPIRSTAPB); lpc31_softreset(RESETID_SPIRSTIP); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - /* Reset the SPI block */ spi_putreg(SPI_CONFIG_SOFTRST, LPC31_SPI_CONFIG); diff --git a/arch/arm/src/lpc43xx/lpc43_ehci.c b/arch/arm/src/lpc43xx/lpc43_ehci.c index 454d6be585..0aadcdfeb2 100644 --- a/arch/arm/src/lpc43xx/lpc43_ehci.c +++ b/arch/arm/src/lpc43xx/lpc43_ehci.c @@ -555,7 +555,12 @@ static int lpc43_reset(void); * global instance. */ -static struct lpc43_ehci_s g_ehci; +static struct lpc43_ehci_s g_ehci = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), + .ep0.iocsem = SEM_INITIALIZER(1), +}; /* This is the connection/enumeration interface */ @@ -4840,15 +4845,6 @@ struct usbhost_connection_s *lpc43_ehci_initialize(int controller) usbhost_vtrace1(EHCI_VTRACE1_INITIALIZING, 0); - /* Initialize the EHCI state data structure */ - - nxmutex_init(&g_ehci.lock); - nxsem_init(&g_ehci.pscsem, 0, 0); - - /* Initialize EP0 */ - - nxsem_init(&g_ehci.ep0.iocsem, 0, 1); - /* Initialize the root hub port structures */ for (i = 0; i < LPC43_EHCI_NRHPORT; i++) diff --git a/arch/arm/src/lpc43xx/lpc43_gpdma.c b/arch/arm/src/lpc43xx/lpc43_gpdma.c index 201e68c4b2..1d03c7b943 100644 --- a/arch/arm/src/lpc43xx/lpc43_gpdma.c +++ b/arch/arm/src/lpc43xx/lpc43_gpdma.c @@ -84,7 +84,10 @@ struct lpc43_gpdma_s /* The state of the LPC43 DMA block */ -static struct lpc43_gpdma_s g_gpdma; +static struct lpc43_gpdma_s g_gpdma = +{ + .lock = NXMUTEX_INITIALIZER, +}; /**************************************************************************** * Public Data @@ -291,8 +294,6 @@ void weak_function arm_dma_initialize(void) /* Initialize the DMA state structure */ - nxmutex_init(&g_gpdma.lock); - for (i = 0; i < LPC43_NDMACH; i++) { g_gpdma.dmach[i].chn = i; /* Channel number */ diff --git a/arch/arm/src/lpc43xx/lpc43_i2c.c b/arch/arm/src/lpc43xx/lpc43_i2c.c index 8315ccb14d..016f25a11e 100644 --- a/arch/arm/src/lpc43xx/lpc43_i2c.c +++ b/arch/arm/src/lpc43xx/lpc43_i2c.c @@ -118,10 +118,18 @@ struct lpc43_i2cdev_s }; #ifdef CONFIG_LPC43_I2C0 -static struct lpc43_i2cdev_s g_i2c0dev; +static struct lpc43_i2cdev_s g_i2c0dev = +{ + .lock = NXMUTEX_INITIALIZER, + .wait = SEM_INITIALIZER(0), +}; #endif #ifdef CONFIG_LPC43_I2C1 -static struct lpc43_i2cdev_s g_i2c1dev; +static struct lpc43_i2cdev_s g_i2c1dev = +{ + .lock = NXMUTEX_INITIALIZER, + .wait = SEM_INITIALIZER(0), +}; #endif /**************************************************************************** @@ -528,11 +536,6 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port) putreg32(I2C_CONSET_I2EN, priv->base + LPC43_I2C_CONSET_OFFSET); - /* Initialize mutex & semaphores */ - - nxmutex_init(&priv->lock); - nxsem_init(&priv->wait, 0, 0); - /* Attach Interrupt Handler */ irq_attach(priv->irqid, lpc43_i2c_interrupt, priv); diff --git a/arch/arm/src/lpc43xx/lpc43_sdmmc.c b/arch/arm/src/lpc43xx/lpc43_sdmmc.c index 23e953ad53..d9bdacff26 100644 --- a/arch/arm/src/lpc43xx/lpc43_sdmmc.c +++ b/arch/arm/src/lpc43xx/lpc43_sdmmc.c @@ -380,6 +380,7 @@ struct lpc43_dev_s g_scard_dev = .dmasendsetup = lpc43_dmasendsetup, #endif }, + .waitsem = SEM_INITIALIZER(0), }; #ifdef CONFIG_LPC43_SDMMC_DMA @@ -2824,10 +2825,6 @@ struct sdio_dev_s *lpc43_sdmmc_initialize(int slotno) lpc43_putreg(LPC43_SDMMC_DELAY_DEFAULT, LPC43_SDMMC_DELAY); - /* Initialize semaphores */ - - nxsem_init(&priv->waitsem, 0, 0); - /* Configure GPIOs for 4-bit, wide-bus operation */ lpc43_pin_config(GPIO_SD_D0); diff --git a/arch/arm/src/lpc43xx/lpc43_spi.c b/arch/arm/src/lpc43xx/lpc43_spi.c index 35095c290d..de44591550 100644 --- a/arch/arm/src/lpc43xx/lpc43_spi.c +++ b/arch/arm/src/lpc43xx/lpc43_spi.c @@ -133,6 +133,7 @@ static struct lpc43_spidev_s g_spidev = { &g_spiops }, + .lock = NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -532,10 +533,6 @@ static struct spi_dev_s *lpc43_spiport_initialize(int port) /* Select a default frequency of approx. 400KHz */ spi_setfrequency((struct spi_dev_s *)priv, 400000); - - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); return &priv->spidev; } #endif /* CONFIG_LPC43_SPI */ diff --git a/arch/arm/src/lpc43xx/lpc43_ssp.c b/arch/arm/src/lpc43xx/lpc43_ssp.c index 90e0c88f1f..4f1025c5a3 100644 --- a/arch/arm/src/lpc43xx/lpc43_ssp.c +++ b/arch/arm/src/lpc43xx/lpc43_ssp.c @@ -148,10 +148,11 @@ static struct lpc43_sspdev_s g_ssp0dev = &g_spi0ops }, .sspbase = LPC43_SSP0_BASE, - .sspbasefreq = BOARD_SSP0_BASEFREQ + .sspbasefreq = BOARD_SSP0_BASEFREQ, #ifdef CONFIG_LPC43_SSP_INTERRUPTS .sspirq = LPC43_IRQ_SSP0, #endif + .lock = NXMUTEX_INITIALIZER, }; #endif /* CONFIG_LPC43_SSP0 */ @@ -188,10 +189,11 @@ static struct lpc43_sspdev_s g_ssp1dev = &g_spi1ops }, .sspbase = LPC43_SSP1_BASE, - .sspbasefreq = BOARD_SSP1_BASEFREQ + .sspbasefreq = BOARD_SSP1_BASEFREQ, #ifdef CONFIG_LPC43_SSP_INTERRUPTS .sspirq = LPC43_IRQ_SSP1, #endif + .lock = NXMUTEX_INITIALIZER, }; #endif /* CONFIG_LPC43_SSP1 */ @@ -827,10 +829,6 @@ struct spi_dev_s *lpc43_sspbus_initialize(int port) ssp_setfrequency((struct spi_dev_s *)priv, 400000); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - /* Enable the SPI */ regval = ssp_getreg(priv, LPC43_SSP_CR1_OFFSET); diff --git a/arch/arm/src/lpc54xx/lpc54_dma.c b/arch/arm/src/lpc54xx/lpc54_dma.c index 39ad7a8269..aa262f6c22 100644 --- a/arch/arm/src/lpc54xx/lpc54_dma.c +++ b/arch/arm/src/lpc54xx/lpc54_dma.c @@ -73,7 +73,10 @@ struct lpc54_dma_s /* The state of the LPC54 DMA block */ -static struct lpc54_dma_s g_dma; +static struct lpc54_dma_s g_dma = +{ + .lock = NXMUTEX_INITIALIZER, +}; /* The SRAMBASE register must be configured with an address (preferably in * on-chip SRAM) where DMA descriptors will be stored. Each DMA channel has @@ -232,10 +235,6 @@ void weak_function arm_dma_initialize(void) putreg32(DMA_ALL_CHANNELS, LPC54_DMA_INTA0); putreg32(DMA_ALL_CHANNELS, LPC54_DMA_INTB0); - /* Initialize the DMA state structure */ - - nxmutex_init(&g_dma.lock); - /* Set the SRAMBASE to the beginning a array of DMA descriptors, one for * each DMA channel. */ diff --git a/arch/arm/src/lpc54xx/lpc54_i2c_master.c b/arch/arm/src/lpc54xx/lpc54_i2c_master.c index f9935e97d5..3515ddd168 100644 --- a/arch/arm/src/lpc54xx/lpc54_i2c_master.c +++ b/arch/arm/src/lpc54xx/lpc54_i2c_master.c @@ -185,34 +185,103 @@ struct i2c_ops_s lpc54_i2c_ops = }; #ifdef CONFIG_LPC54_I2C0_MASTER -static struct lpc54_i2cdev_s g_i2c0_dev; +static struct lpc54_i2cdev_s g_i2c0_dev = +{ + .lock = NXMUTEX_INITIALIZER, +# ifndef CONFIG_I2C_POLLED + .waitsem = SEM_INITIALIZER(0), +# endif +}; #endif + #ifdef CONFIG_LPC54_I2C1_MASTER -static struct lpc54_i2cdev_s g_i2c1_dev; +static struct lpc54_i2cdev_s g_i2c1_dev = +{ + .lock = NXMUTEX_INITIALIZER, +# ifndef CONFIG_I2C_POLLED + .waitsem = SEM_INITIALIZER(0), +# endif +}; #endif + #ifdef CONFIG_LPC54_I2C2_MASTER -static struct lpc54_i2cdev_s g_i2c2_dev; +static struct lpc54_i2cdev_s g_i2c2_dev = +{ + .lock = NXMUTEX_INITIALIZER, +# ifndef CONFIG_I2C_POLLED + .waitsem = SEM_INITIALIZER(0), +# endif +}; #endif + #ifdef CONFIG_LPC54_I2C3_MASTER -static struct lpc54_i2cdev_s g_i2c3_dev; +static struct lpc54_i2cdev_s g_i2c3_dev = +{ + .lock = NXMUTEX_INITIALIZER, +# ifndef CONFIG_I2C_POLLED + .waitsem = SEM_INITIALIZER(0), +# endif +}; #endif + #ifdef CONFIG_LPC54_I2C4_MASTER -static struct lpc54_i2cdev_s g_i2c4_dev; +static struct lpc54_i2cdev_s g_i2c4_dev = +{ + .lock = NXMUTEX_INITIALIZER, +# ifndef CONFIG_I2C_POLLED + .waitsem = SEM_INITIALIZER(0), +# endif +}; #endif + #ifdef CONFIG_LPC54_I2C5_MASTER -static struct lpc54_i2cdev_s g_i2c5_dev; +static struct lpc54_i2cdev_s g_i2c5_dev = +{ + .lock = NXMUTEX_INITIALIZER, +# ifndef CONFIG_I2C_POLLED + .waitsem = SEM_INITIALIZER(0), +# endif +}; #endif + #ifdef CONFIG_LPC54_I2C6_MASTER -static struct lpc54_i2cdev_s g_i2c6_dev; +static struct lpc54_i2cdev_s g_i2c6_dev = +{ + .lock = NXMUTEX_INITIALIZER, +# ifndef CONFIG_I2C_POLLED + .waitsem = SEM_INITIALIZER(0), +# endif +}; #endif + #ifdef CONFIG_LPC54_I2C7_MASTER -static struct lpc54_i2cdev_s g_i2c7_dev; +static struct lpc54_i2cdev_s g_i2c7_dev = +{ + .lock = NXMUTEX_INITIALIZER, +# ifndef CONFIG_I2C_POLLED + .waitsem = SEM_INITIALIZER(0), +# endif +}; #endif + #ifdef CONFIG_LPC54_I2C8_MASTER -static struct lpc54_i2cdev_s g_i2c8_dev; +static struct lpc54_i2cdev_s g_i2c8_dev = +{ + .lock = NXMUTEX_INITIALIZER, +# ifndef CONFIG_I2C_POLLED + .waitsem = SEM_INITIALIZER(0), +# endif +}; #endif + #ifdef CONFIG_LPC54_I2C9_MASTER -static struct lpc54_i2cdev_s g_i2c9_dev; +static struct lpc54_i2cdev_s g_i2c9_dev = +{ + .lock = NXMUTEX_INITIALIZER, +# ifndef CONFIG_I2C_POLLED + .waitsem = SEM_INITIALIZER(0), +# endif +}; #endif /**************************************************************************** @@ -1207,13 +1276,6 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) lpc54_i2c_setfrequency(priv, I2C_DEFAULT_FREQUENCY); - /* Initialize mutex & semaphores */ - - nxmutex_init(&priv->lock); -#ifndef CONFIG_I2C_POLLED - nxsem_init(&priv->waitsem, 0, 0); -#endif - #ifndef CONFIG_I2C_POLLED /* Attach Interrupt Handler */ diff --git a/arch/arm/src/lpc54xx/lpc54_rng.c b/arch/arm/src/lpc54xx/lpc54_rng.c index 65ff4fa2fc..cd06eb0885 100644 --- a/arch/arm/src/lpc54xx/lpc54_rng.c +++ b/arch/arm/src/lpc54xx/lpc54_rng.c @@ -55,7 +55,10 @@ struct rng_dev_s * Private Data ****************************************************************************/ -static struct rng_dev_s g_rngdev; +static struct rng_dev_s g_rngdev = +{ + .rd_devlock = NXMUTEX_INITIALIZER, +}; static const struct file_operations g_rngops = { @@ -145,7 +148,6 @@ static ssize_t lpc54_read(struct file *filep, char *buffer, size_t buflen) #ifdef CONFIG_DEV_RANDOM void devrandom_register(void) { - nxmutex_init(&g_rngdev.rd_devlock); register_driver("/dev/random", &g_rngops, 0444, NULL); } #endif @@ -167,9 +169,6 @@ void devrandom_register(void) #ifdef CONFIG_DEV_URANDOM_ARCH void devurandom_register(void) { -#ifndef CONFIG_DEV_RANDOM - nxmutex_init(&g_rngdev.rd_devlock); -#endif register_driver("/dev/urandom", &g_rngops, 0444, NULL); } #endif diff --git a/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c b/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c index b8c4bfc9a0..ebc11162a5 100644 --- a/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c +++ b/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c @@ -146,6 +146,7 @@ static const struct rtc_ops_s g_rtc_ops = static struct lpc54_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, + .devlock = NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -639,7 +640,6 @@ static int lpc54_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) struct rtc_lowerhalf_s *lpc54_rtc_lowerhalf(void) { - nxmutex_init(&g_rtc_lowerhalf.devlock); return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/lpc54xx/lpc54_sdmmc.c b/arch/arm/src/lpc54xx/lpc54_sdmmc.c index f0a6fb9b32..b7d7ad293a 100644 --- a/arch/arm/src/lpc54xx/lpc54_sdmmc.c +++ b/arch/arm/src/lpc54xx/lpc54_sdmmc.c @@ -380,6 +380,7 @@ struct lpc54_dev_s g_scard_dev = .dmasendsetup = lpc54_dmasendsetup, #endif }, + .waitsem = SEM_INITIALIZER(0), }; #ifdef CONFIG_LPC54_SDMMC_DMA @@ -2827,10 +2828,6 @@ struct sdio_dev_s *lpc54_sdmmc_initialize(int slotno) lpc54_sdmmc_enableclk(); - /* Initialize semaphores */ - - nxsem_init(&priv->waitsem, 0, 0); - /* Configure GPIOs for 4-bit, wide-bus operation */ lpc54_gpio_config(GPIO_SD_D0); diff --git a/arch/arm/src/lpc54xx/lpc54_spi_master.c b/arch/arm/src/lpc54xx/lpc54_spi_master.c index e2d7f0dc56..5aea8195df 100644 --- a/arch/arm/src/lpc54xx/lpc54_spi_master.c +++ b/arch/arm/src/lpc54xx/lpc54_spi_master.c @@ -237,7 +237,10 @@ static const struct spi_ops_s g_spi0_ops = #endif }; -static struct lpc54_spidev_s g_spi0_dev; +static struct lpc54_spidev_s g_spi0_dev = +{ + .lock = NXMUTEX_INITIALIZER, +}; #endif #ifdef CONFIG_LPC54_SPI1_MASTER @@ -269,7 +272,10 @@ static const struct spi_ops_s g_spi1_ops = #endif }; -static struct lpc54_spidev_s g_spi1_dev; +static struct lpc54_spidev_s g_spi1_dev = +{ + .lock = NXMUTEX_INITIALIZER, +}; #endif #ifdef CONFIG_LPC54_SPI2_MASTER @@ -301,7 +307,10 @@ static const struct spi_ops_s g_spi2_ops = #endif }; -static struct lpc54_spidev_s g_spi2_dev; +static struct lpc54_spidev_s g_spi2_dev = +{ + .lock = NXMUTEX_INITIALIZER, +}; #endif #ifdef CONFIG_LPC54_SPI3_MASTER @@ -333,7 +342,10 @@ static const struct spi_ops_s g_spi3_ops = #endif }; -static struct lpc54_spidev_s g_spi3_dev; +static struct lpc54_spidev_s g_spi3_dev = +{ + .lock = NXMUTEX_INITIALIZER, +}; #endif #ifdef CONFIG_LPC54_SPI4_MASTER @@ -365,7 +377,10 @@ static const struct spi_ops_s g_spi4_ops = #endif }; -static struct lpc54_spidev_s g_spi4_dev; +static struct lpc54_spidev_s g_spi4_dev = +{ + .lock = NXMUTEX_INITIALIZER, +}; #endif #ifdef CONFIG_LPC54_SPI5_MASTER @@ -397,7 +412,10 @@ static const struct spi_ops_s g_spi5_ops = #endif }; -static struct lpc54_spidev_s g_spi5_dev; +static struct lpc54_spidev_s g_spi5_dev = +{ + .lock = NXMUTEX_INITIALIZER, +}; #endif #ifdef CONFIG_LPC54_SPI6_MASTER @@ -429,7 +447,10 @@ static const struct spi_ops_s g_spi6_ops = #endif }; -static struct lpc54_spidev_s g_spi6_dev; +static struct lpc54_spidev_s g_spi6_dev = +{ + .lock = NXMUTEX_INITIALIZER, +}; #endif #ifdef CONFIG_LPC54_SPI7_MASTER @@ -461,7 +482,10 @@ static const struct spi_ops_s g_spi7_ops = #endif }; -static struct lpc54_spidev_s g_spi7_dev; +static struct lpc54_spidev_s g_spi7_dev = +{ + .lock = NXMUTEX_INITIALIZER, +}; #endif #ifdef CONFIG_LPC54_SPI8_MASTER @@ -493,7 +517,10 @@ static const struct spi_ops_s g_spi8_ops = #endif }; -static struct lpc54_spidev_s g_spi8_dev; +static struct lpc54_spidev_s g_spi8_dev = +{ + .lock = NXMUTEX_INITIALIZER, +}; #endif #ifdef CONFIG_LPC54_SPI9_MASTER @@ -525,7 +552,10 @@ static const struct spi_ops_s g_spi9_ops = #endif }; -static struct lpc54_spidev_s g_spi9_dev; +static struct lpc54_spidev_s g_spi9_dev = +{ + .lock = NXMUTEX_INITIALIZER, +}; #endif /**************************************************************************** @@ -2016,10 +2046,6 @@ struct spi_dev_s *lpc54_spibus_initialize(int port) priv->nbits = 8; priv->mode = SPIDEV_MODE0; - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - /* Configure master mode in mode 0: * * ENABLE - Disabled for now (0) diff --git a/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c b/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c index 7fca28fe48..6c47ceb055 100644 --- a/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c +++ b/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c @@ -500,7 +500,11 @@ static inline void lpc54_ep0init(struct lpc54_usbhost_s *priv); * single global instance. */ -static struct lpc54_usbhost_s g_usbhost; +static struct lpc54_usbhost_s g_usbhost = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), +}; /* This is the connection/enumeration interface */ @@ -3822,11 +3826,6 @@ struct usbhost_connection_s *lpc54_usbhost_initialize(int controller) usbhost_devaddr_initialize(&priv->rhport); - /* Initialize semaphores & mutex */ - - nxsem_init(&priv->pscsem, 0, 0); - nxmutex_init(&priv->lock); - #ifndef CONFIG_OHCI_INT_DISABLE priv->ininterval = MAX_PERINTERVAL; priv->outinterval = MAX_PERINTERVAL; diff --git a/arch/arm/src/max326xx/common/max326_rtc_lowerhalf.c b/arch/arm/src/max326xx/common/max326_rtc_lowerhalf.c index 46cf0d4c5c..60a4bb9100 100644 --- a/arch/arm/src/max326xx/common/max326_rtc_lowerhalf.c +++ b/arch/arm/src/max326xx/common/max326_rtc_lowerhalf.c @@ -152,6 +152,7 @@ static const struct rtc_ops_s g_rtc_ops = static struct max326_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, + .devlock = NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -747,7 +748,6 @@ static int max326_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) struct rtc_lowerhalf_s *max326_rtc_lowerhalf(void) { - nxmutex_init(&g_rtc_lowerhalf.devlock); return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/max326xx/max32660/max32660_spim.c b/arch/arm/src/max326xx/max32660/max32660_spim.c index 4cb783f8fe..af974fe415 100644 --- a/arch/arm/src/max326xx/max32660/max32660_spim.c +++ b/arch/arm/src/max326xx/max32660/max32660_spim.c @@ -236,6 +236,7 @@ static struct max326_spidev_s g_spi0dev = &g_sp0iops }, .base = MAX326_SPI0_BASE, + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_MAX326_SPI_INTERRUPTS .irq = MAX326_IRQ_SPI, #endif @@ -1433,10 +1434,6 @@ static void spi_bus_initialize(struct max326_spidev_s *priv) regval = priv->wire3 ? SPI_CTRL2_DATWIDTH_SINGLE : SPI_CTRL2_DATWIDTH_DUAL; spi_modify_ctrl2(priv, regval, SPI_CTRL2_DATWIDTH_MASK); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - /* Disable all interrupts at the peripheral */ spi_putreg(priv, MAX326_SPI_INTEN_OFFSET, 0); diff --git a/arch/arm/src/nrf52/nrf52_radio.c b/arch/arm/src/nrf52/nrf52_radio.c index b18f6e81af..f400877a5c 100644 --- a/arch/arm/src/nrf52/nrf52_radio.c +++ b/arch/arm/src/nrf52/nrf52_radio.c @@ -143,6 +143,8 @@ struct nrf52_radio_dev_s g_nrf52_radio_dev_1 = .txbuf_len = NRF52_RADIO_TXBUFFER, .rxbuf = g_nrf52_radio_dev_rx1, .txbuf = g_nrf52_radio_dev_tx1, + .lock = NXMUTEX_INITIALIZER, + .sem_isr = SEM_INITIALIZER(0), }; /**************************************************************************** @@ -1160,11 +1162,6 @@ nrf52_radio_initialize(int intf, struct nrf52_radio_board_s *board) irq_attach(dev->irq, nrf52_radio_isr, dev); up_enable_irq(dev->irq); - /* Initialize mutex */ - - nxmutex_init(&dev->lock); - nxsem_init(&dev->sem_isr, 0, 0); - /* Connect board-specific data */ dev->board = board; diff --git a/arch/arm/src/nrf52/nrf52_rng.c b/arch/arm/src/nrf52/nrf52_rng.c index da4261158d..cc4f31541c 100644 --- a/arch/arm/src/nrf52/nrf52_rng.c +++ b/arch/arm/src/nrf52/nrf52_rng.c @@ -72,7 +72,11 @@ struct rng_dev_s * Private Data ****************************************************************************/ -static struct rng_dev_s g_rngdev; +static struct rng_dev_s g_rngdev = +{ + .rd_sem = SEM_INITIALIZER(0), + .lock = NXMUTEX_INITIALIZER, +}; static const struct file_operations g_rngops = { @@ -124,13 +128,6 @@ static int nrf52_rng_initialize(void) first_flag = false; - _info("Initializing RNG\n"); - - memset(&g_rngdev, 0, sizeof(struct rng_dev_s)); - - nxsem_init(&g_rngdev.rd_sem, 0, 0); - nxmutex_init(&g_rngdev.lock); - _info("Ready to stop\n"); nrf52_rng_stop(); diff --git a/arch/arm/src/nrf52/nrf52_sdc.c b/arch/arm/src/nrf52/nrf52_sdc.c index 6152f51ab4..c48a92379d 100644 --- a/arch/arm/src/nrf52/nrf52_sdc.c +++ b/arch/arm/src/nrf52/nrf52_sdc.c @@ -171,7 +171,10 @@ static const mpsl_clock_lfclk_cfg_t g_clock_config = .skip_wait_lfclk_started = false }; -static struct nrf52_sdc_dev_s g_sdc_dev; +static struct nrf52_sdc_dev_s g_sdc_dev = +{ + .lock = NXMUTEX_INITIALIZER, +}; /**************************************************************************** * Private Functions @@ -499,11 +502,6 @@ int nrf52_sdc_initialize(void) int32_t required_memory; sdc_cfg_t cfg; - /* Initialize device data */ - - memset(&g_sdc_dev, 0, sizeof(g_sdc_dev)); - nxmutex_init(&g_sdc_dev.lock); - /* Register interrupt handler for normal-priority events. SWI5 will be * used by MPSL to delegate low-priority work */ diff --git a/arch/arm/src/nrf52/nrf52_spi.c b/arch/arm/src/nrf52/nrf52_spi.c index 42baa16ace..b706f28ca8 100644 --- a/arch/arm/src/nrf52/nrf52_spi.c +++ b/arch/arm/src/nrf52/nrf52_spi.c @@ -202,7 +202,9 @@ static struct nrf52_spidev_s g_spi0dev = }, .base = NRF52_SPIM0_BASE, + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS + .sem_isr = SEM_INITIALIZER(0), .irq = NRF52_IRQ_SPI_TWI_0, #endif .sck_pin = BOARD_SPI0_SCK_PIN, @@ -253,7 +255,9 @@ static struct nrf52_spidev_s g_spi1dev = }, .base = NRF52_SPIM1_BASE, + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS + .sem_isr = SEM_INITIALIZER(0), .irq = NRF52_IRQ_SPI_TWI_1, #endif .sck_pin = BOARD_SPI1_SCK_PIN, @@ -304,7 +308,9 @@ static struct nrf52_spidev_s g_spi2dev = }, .base = NRF52_SPIM2_BASE, + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS + .sem_isr = SEM_INITIALIZER(0), .irq = NRF52_IRQ_SPI2, #endif .sck_pin = BOARD_SPI2_SCK_PIN, @@ -355,7 +361,9 @@ static struct nrf52_spidev_s g_spi3dev = }, .base = NRF52_SPIM3_BASE, + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS + .sem_isr = SEM_INITIALIZER(0), .irq = NRF52_IRQ_SPI3, #endif .sck_pin = BOARD_SPI3_SCK_PIN, @@ -1470,13 +1478,7 @@ struct spi_dev_s *nrf52_spibus_initialize(int port) priv->initialized = true; - /* Initialize the SPI mutex */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS - nxsem_init(&priv->sem_isr, 0, 0); - /* Attach SPI interrupt */ irq_attach(priv->irq, nrf52_spi_isr, priv); diff --git a/arch/arm/src/rp2040/rp2040_dmac.c b/arch/arm/src/rp2040/rp2040_dmac.c index 115209df7e..c8ba891905 100644 --- a/arch/arm/src/rp2040/rp2040_dmac.c +++ b/arch/arm/src/rp2040/rp2040_dmac.c @@ -72,7 +72,11 @@ struct dma_controller_s /* This is the overall state of the DMA controller */ -static struct dma_controller_s g_dmac; +static struct dma_controller_s g_dmac = +{ + .lock = NXMUTEX_INITIALIZER, + .chansem = SEM_INITIALIZER(RP2040_DMA_NCHANNELS), +}; /* This is the array of all DMA channels */ @@ -161,9 +165,6 @@ void weak_function arm_dma_initialize(void) /* Initialize the channel list */ - nxmutex_init(&g_dmac.lock); - nxsem_init(&g_dmac.chansem, 0, RP2040_DMA_NCHANNELS); - for (i = 0; i < RP2040_DMA_NCHANNELS; i++) { g_dmach[i].chan = i; diff --git a/arch/arm/src/rp2040/rp2040_flash_mtd.c b/arch/arm/src/rp2040/rp2040_flash_mtd.c index cef367e116..74554cd2c6 100644 --- a/arch/arm/src/rp2040/rp2040_flash_mtd.c +++ b/arch/arm/src/rp2040/rp2040_flash_mtd.c @@ -165,7 +165,8 @@ static struct rp2040_flash_dev_s my_dev = #endif rp2040_flash_ioctl, "rp_flash" - } + }, + .lock = NXMUTEX_INITIALIZER, }; static bool initialized = false; @@ -503,8 +504,6 @@ struct mtd_dev_s *rp2040_flash_mtd_initialize(void) initialized = true; - nxmutex_init(&my_dev.lock); - if (FLASH_BLOCK_COUNT < 4) { errno = ENOMEM; diff --git a/arch/arm/src/rp2040/rp2040_spi.c b/arch/arm/src/rp2040/rp2040_spi.c index 0711120469..02d682cd6b 100644 --- a/arch/arm/src/rp2040/rp2040_spi.c +++ b/arch/arm/src/rp2040/rp2040_spi.c @@ -186,6 +186,10 @@ static struct rp2040_spidev_s g_spi0dev = .initialized = 0, #ifdef CONFIG_RP2040_SPI_INTERRUPTS .spiirq = RP2040_SPI0_IRQ, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_RP2040_SPI_DMA + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -231,6 +235,10 @@ static struct rp2040_spidev_s g_spi1dev = .initialized = 0, #ifdef CONFIG_RP2040_SPI_INTERRUPTS .spiirq = RP2040_SPI1_IRQ, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_RP2040_SPI_DMA + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -817,8 +825,6 @@ struct spi_dev_s *rp2040_spibus_initialize(int port) /* DMA settings */ #ifdef CONFIG_RP2040_SPI_DMA - nxsem_init(&priv->dmasem, 0, 0); - priv->txdmach = rp2040_dmachannel(); txconf.size = RP2040_DMA_SIZE_BYTE; txconf.noincr = false; @@ -857,10 +863,6 @@ struct spi_dev_s *rp2040_spibus_initialize(int port) spi_setfrequency((struct spi_dev_s *)priv, 400000); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - regval = spi_getreg(priv, RP2040_SPI_SSPCR1_OFFSET); spi_putreg(priv, RP2040_SPI_SSPCR1_OFFSET, regval | RP2040_SPI_SSPCR1_SSE); diff --git a/arch/arm/src/s32k1xx/s32k1xx_edma.c b/arch/arm/src/s32k1xx/s32k1xx_edma.c index 5d2728b917..27c0a22ccf 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_edma.c +++ b/arch/arm/src/s32k1xx/s32k1xx_edma.c @@ -155,7 +155,13 @@ struct s32k1xx_edma_s /* The state of the eDMA */ -static struct s32k1xx_edma_s g_edma; +static struct s32k1xx_edma_s g_edma = +{ + .chlock = NXMUTEX_INITIALIZER, +#if CONFIG_S32K1XX_EDMA_NTCD > 0 + .dsem = SEM_INITIALIZER(CONFIG_S32K1XX_EDMA_NTCD), +#endif +}; #if CONFIG_S32K1XX_EDMA_NTCD > 0 /* This is a singly-linked list of free TCDs */ @@ -706,18 +712,12 @@ void weak_function arm_dma_initialize(void) /* Initialize data structures */ - memset(&g_edma, 0, sizeof(struct s32k1xx_edma_s)); for (i = 0; i < S32K1XX_EDMA_NCHANNELS; i++) { g_edma.dmach[i].chan = i; } - /* Initialize mutex & semaphores */ - - nxmutex_init(&g_edma.chlock); #if CONFIG_S32K1XX_EDMA_NTCD > 0 - nxsem_init(&g_edma.dsem, 0, CONFIG_S32K1XX_EDMA_NTCD); - /* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */ s32k1xx_tcd_initialize(); diff --git a/arch/arm/src/s32k1xx/s32k1xx_lpspi.c b/arch/arm/src/s32k1xx/s32k1xx_lpspi.c index a80636d368..58ffd13476 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_lpspi.c +++ b/arch/arm/src/s32k1xx/s32k1xx_lpspi.c @@ -261,6 +261,7 @@ static struct s32k1xx_lpspidev_s g_lpspi0dev = #ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS .spiirq = S32K1XX_IRQ_LPSPI0, #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_S32K1XX_LPSPI_DMA .rxch = DMAMAP_LPSPI0_RX, .txch = DMAMAP_LPSPI0_TX, @@ -311,6 +312,7 @@ static struct s32k1xx_lpspidev_s g_lpspi1dev = #ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS .spiirq = S32K1XX_IRQ_LPSPI1, #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_S32K1XX_LPSPI_DMA .rxch = DMAMAP_LPSPI1_RX, .txch = DMAMAP_LPSPI1_TX, @@ -361,6 +363,7 @@ static struct s32k1xx_lpspidev_s g_lpspi2dev = #ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS .spiirq = S32K1XX_IRQ_LPSPI2, #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_S32K1XX_LPSPI_DMA .rxch = DMAMAP_LPSPI2_RX, .txch = DMAMAP_LPSPI2_TX, @@ -1714,10 +1717,6 @@ static void s32k1xx_lpspi_bus_initialize(struct s32k1xx_lpspidev_s *priv) s32k1xx_lpspi_setmode((struct spi_dev_s *)priv, SPIDEV_MODE0); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - /* Enable LPSPI */ s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); diff --git a/arch/arm/src/s32k3xx/s32k3xx_edma.c b/arch/arm/src/s32k3xx/s32k3xx_edma.c index 34b45e3208..9d0b9908bd 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_edma.c +++ b/arch/arm/src/s32k3xx/s32k3xx_edma.c @@ -203,7 +203,13 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] = /* The state of the eDMA */ -static struct s32k3xx_edma_s g_edma; +static struct s32k3xx_edma_s g_edma = +{ + .chlock = NXMUTEX_INITIALIZER, +#if CONFIG_S32K3XX_EDMA_NTCD > 0 + .dsem = SEM_INITIALIZER(CONFIG_S32K3XX_EDMA_NTCD), +#endif +}; #if CONFIG_S32K3XX_EDMA_NTCD > 0 /* This is a singly-linked list of free TCDs */ @@ -916,18 +922,12 @@ void weak_function arm_dma_initialize(void) /* Initialize data structures */ - memset(&g_edma, 0, sizeof(struct s32k3xx_edma_s)); for (i = 0; i < S32K3XX_EDMA_NCHANNELS; i++) { g_edma.dmach[i].chan = i; } - /* Initialize mutex & semaphore */ - - nxmutex_init(&g_edma.chlock); #if CONFIG_S32K3XX_EDMA_NTCD > 0 - nxsem_init(&g_edma.dsem, 0, CONFIG_S32K3XX_EDMA_NTCD); - /* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */ s32k3xx_tcd_initialize(); diff --git a/arch/arm/src/s32k3xx/s32k3xx_lpspi.c b/arch/arm/src/s32k3xx/s32k3xx_lpspi.c index 8bce87ab79..1d0b234662 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_lpspi.c +++ b/arch/arm/src/s32k3xx/s32k3xx_lpspi.c @@ -252,9 +252,12 @@ static struct s32k3xx_lpspidev_s g_lpspi0dev = #ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS .spiirq = S32K3XX_IRQ_LPSPI0, #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_S32K3XX_LPSPI0_DMA .rxch = DMA_REQ_LPSPI0_RX, .txch = DMA_REQ_LPSPI0_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif .pincfg = CONFIG_S32K3XX_LPSPI0_PINCFG, }; @@ -299,9 +302,12 @@ static struct s32k3xx_lpspidev_s g_lpspi1dev = #ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS .spiirq = S32K3XX_IRQ_LPSPI1, #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_S32K3XX_LPSPI1_DMA .rxch = DMA_REQ_LPSPI1_RX, .txch = DMA_REQ_LPSPI1_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif .pincfg = CONFIG_S32K3XX_LPSPI1_PINCFG, }; @@ -346,9 +352,12 @@ static struct s32k3xx_lpspidev_s g_lpspi2dev = #ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS .spiirq = S32K3XX_IRQ_LPSPI2, #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_S32K3XX_LPSPI2_DMA .rxch = DMA_REQ_LPSPI2_RX, .txch = DMA_REQ_LPSPI2_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif .pincfg = CONFIG_S32K3XX_LPSPI2_PINCFG, }; @@ -393,9 +402,12 @@ static struct s32k3xx_lpspidev_s g_lpspi3dev = #ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS .spiirq = S32K3XX_IRQ_LPSPI3, #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_S32K3XX_LPSPI3_DMA .rxch = DMA_REQ_LPSPI3_RX, .txch = DMA_REQ_LPSPI3_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif .pincfg = CONFIG_S32K3XX_LPSPI3_PINCFG, }; @@ -440,9 +452,12 @@ static struct s32k3xx_lpspidev_s g_lpspi4dev = #ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS .spiirq = S32K3XX_IRQ_LPSPI4, #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_S32K3XX_LPSPI4_DMA .rxch = DMA_REQ_LPSPI4_RX, .txch = DMA_REQ_LPSPI4_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif .pincfg = CONFIG_S32K3XX_LPSPI4_PINCFG, }; @@ -487,9 +502,12 @@ static struct s32k3xx_lpspidev_s g_lpspi5dev = #ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS .spiirq = S32K3XX_IRQ_LPSPI5, #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_S32K3XX_LPSPI5_DMA .rxch = DMA_REQ_LPSPI5_RX, .txch = DMA_REQ_LPSPI5_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif .pincfg = CONFIG_S32K3XX_LPSPI5_PINCFG, }; @@ -2013,10 +2031,6 @@ static void s32k3xx_lpspi_bus_initialize(struct s32k3xx_lpspidev_s *priv) s32k3xx_lpspi_setmode((struct spi_dev_s *)priv, SPIDEV_MODE0); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - /* Enable LPSPI */ s32k3xx_lpspi_modifyreg32(priv, S32K3XX_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); @@ -2369,17 +2383,10 @@ struct spi_dev_s *s32k3xx_lpspibus_initialize(int bus) } #ifdef CONFIG_S32K3XX_LPSPI_DMA - /* Initialize the SPI semaphores that is used to wait for DMA completion. - * This semaphore is used for signaling and, hence, should not have - * priority inheritance enabled. - */ - if (priv->rxch && priv->txch) { if (priv->txdma == NULL && priv->rxdma == NULL) { - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); priv->txdma = s32k3xx_dmach_alloc(priv->txch | DMAMUX_CHCFG_ENBL, 0); priv->rxdma = s32k3xx_dmach_alloc(priv->rxch | DMAMUX_CHCFG_ENBL, diff --git a/arch/arm/src/s32k3xx/s32k3xx_qspi.c b/arch/arm/src/s32k3xx/s32k3xx_qspi.c index b10db79495..d9be63a0a7 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_qspi.c +++ b/arch/arm/src/s32k3xx/s32k3xx_qspi.c @@ -226,14 +226,18 @@ static struct s32k3xx_qspidev_s g_qspi0dev = .ops = &g_qspi0ops, }, .base = S32K3XX_QSPI_BASE, + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_S32K3XX_QSPI_INTERRUPTS .handler = qspi_interrupt, .irq = S32K3XX_IRQ_QSPI, + .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, #ifdef CONFIG_S32K3XX_QSPI_DMA .rxch = DMA_REQ_QSPI_RX, .txch = DMA_REQ_QSPI_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif }; @@ -1785,13 +1789,7 @@ struct qspi_dev_s *s32k3xx_qspi_initialize(int intf) if (!priv->initialized) { - /* Now perform one time initialization. - * - * Initialize the QSPI semaphore that enforces mutually exclusive - * access to the QSPI registers. - */ - - nxmutex_init(&priv->lock); + /* Now perform one time initialization. */ #ifdef CONFIG_S32K3XX_QSPI_INTERRUPTS /* Attach the interrupt handler */ @@ -1801,8 +1799,6 @@ struct qspi_dev_s *s32k3xx_qspi_initialize(int intf) { spierr("ERROR: Failed to attach irq %d\n", priv->irq); } - - nxsem_init(&priv->op_sem, 0, 0); #endif /* Perform hardware initialization. Puts the QSPI into an active @@ -1824,17 +1820,12 @@ struct qspi_dev_s *s32k3xx_qspi_initialize(int intf) #endif #ifdef CONFIG_S32K3XX_QSPI_DMA - /* Initialize the QSPI semaphores that is used to wait for DMA completion. - * This semaphore is used for signaling and, hence, should not have - * priority inheritance enabled. - */ + /* Initialize the QSPI dma channel. */ if (priv->rxch && priv->txch) { if (priv->txdma == NULL && priv->rxdma == NULL) { - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); priv->txdma = s32k3xx_dmach_alloc(priv->txch | DMAMUX_CHCFG_ENBL, 0); priv->rxdma = s32k3xx_dmach_alloc(priv->rxch @@ -1851,9 +1842,6 @@ struct qspi_dev_s *s32k3xx_qspi_initialize(int intf) } return &priv->qspi; - - nxmutex_destroy(&priv->lock); - return NULL; } #endif /* CONFIG_S32K3XX_QSPI */ diff --git a/arch/arm/src/sam34/sam_aes.c b/arch/arm/src/sam34/sam_aes.c index c5bb2f2d6f..ab24477596 100644 --- a/arch/arm/src/sam34/sam_aes.c +++ b/arch/arm/src/sam34/sam_aes.c @@ -59,7 +59,7 @@ * Private Data ****************************************************************************/ -static mutex_t g_samaes_lock; +static mutex_t g_samaes_lock = NXMUTEX_INITIALIZER; static bool g_samaes_initdone = false; /**************************************************************************** @@ -159,7 +159,6 @@ static int samaes_setup_mr(uint32_t keysize, int mode, int encrypt) static int samaes_initialize(void) { - nxmutex_init(&g_samaes_lock); sam_aes_enableclk(); putreg32(AES_CR_SWRST, SAM_AES_CR); return OK; diff --git a/arch/arm/src/sam34/sam_dmac.c b/arch/arm/src/sam34/sam_dmac.c index 109d22bae7..43546a76c5 100644 --- a/arch/arm/src/sam34/sam_dmac.c +++ b/arch/arm/src/sam34/sam_dmac.c @@ -104,8 +104,8 @@ struct sam_dma_s /* These mutex protect the DMA channel and descriptor tables */ -static mutex_t g_chlock; -static sem_t g_dsem; +static mutex_t g_chlock = NXMUTEX_INITIALIZER; +static sem_t g_dsem = SEM_INITIALIZER(CONFIG_SAM34_NLLDESC); /* CTRLA field lookups */ @@ -1340,11 +1340,6 @@ void weak_function arm_dma_initialize(void) /* Enable the DMA controller */ putreg32(DMAC_EN_ENABLE, SAM_DMAC_EN); - - /* Initialize mutex & semaphores */ - - nxmutex_init(&g_chlock); - nxsem_init(&g_dsem, 0, CONFIG_SAM34_NLLDESC); } /**************************************************************************** diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c index d20540c956..fb808d3d14 100644 --- a/arch/arm/src/sam34/sam_hsmci.c +++ b/arch/arm/src/sam34/sam_hsmci.c @@ -542,6 +542,7 @@ struct sam_dev_s g_sdiodev = .dmasendsetup = sam_dmasendsetup, #endif }, + .waitsem = SEM_INITIALIZER(0), }; /* Register logging support */ @@ -2699,9 +2700,6 @@ struct sdio_dev_s *sdio_initialize(int slotno) /* Initialize the HSMCI slot structure */ - /* Initialize semaphores */ - - nxsem_init(&priv->waitsem, 0, 0); #ifdef CONFIG_SAM34_DMAC0 /* Allocate a DMA channel. A FIFO size of 8 is sufficient. */ diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c index c5294e7eb4..5e35a71d0c 100644 --- a/arch/arm/src/sam34/sam_spi.c +++ b/arch/arm/src/sam34/sam_spi.c @@ -322,6 +322,7 @@ static const struct spi_ops_s g_spi0ops = static struct sam_spidev_s g_spi0dev = { .base = SAM_SPI0_BASE, + .spilock = NXMUTEX_INITIALIZER, .select = sam_spi0select, #ifdef CONFIG_SAM34_SPI_DMA .rxintf = DMACHAN_INTF_SPI0RX, @@ -359,6 +360,7 @@ static const struct spi_ops_s g_spi1ops = static struct sam_spidev_s g_spi1dev = { .base = SAM_SPI1_BASE, + .spilock = NXMUTEX_INITIALIZER, .select = sam_spi1select, #ifdef CONFIG_SAM34_SPI_DMA .rxintf = DMACHAN_INTF_SPI1RX, @@ -1857,11 +1859,6 @@ struct spi_dev_s *sam_spibus_initialize(int port) spi_getreg(spi, SAM_SPI_SR_OFFSET); spi_getreg(spi, SAM_SPI_RDR_OFFSET); - /* Initialize the SPI mutex that enforces mutually exclusive - * access to the SPI registers. - */ - - nxmutex_init(&spi->spilock); spi->initialized = true; #ifdef CONFIG_SAM34_SPI_DMA diff --git a/arch/arm/src/sam34/sam_twi.c b/arch/arm/src/sam34/sam_twi.c index 032391e8dc..93ae0abc9d 100644 --- a/arch/arm/src/sam34/sam_twi.c +++ b/arch/arm/src/sam34/sam_twi.c @@ -187,21 +187,43 @@ static void twi_hw_initialize(struct twi_dev_s *priv, unsigned int pid, * Private Data ****************************************************************************/ +static const struct i2c_ops_s g_twiops = +{ + .transfer = twi_transfer, +#ifdef CONFIG_I2C_RESET + .reset = twi_reset +#endif +}; + #ifdef CONFIG_SAM34_TWIM0 -static struct twi_dev_s g_twi0; +static struct twi_dev_s g_twi0 = +{ + .dev = + { + .ops = g_twiops, + }, + .base = SAM_TWI0_BASE, + .irq = SAM_IRQ_TWI0, + .twi = 0, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef CONFIG_SAM34_TWIM1 -static struct twi_dev_s g_twi1; -#endif - -static const struct i2c_ops_s g_twiops = +static struct twi_dev_s g_twi1 = { - .transfer = twi_transfer -#ifdef CONFIG_I2C_RESET - , .reset = twi_reset -#endif + .dev = + { + .ops = g_twiops, + }, + .base = SAM_TWI1_BASE, + .irq = SAM_IRQ_TWI1, + .twi = 1, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), }; +#endif /**************************************************************************** * Private Functions @@ -891,12 +913,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) #ifdef CONFIG_SAM34_TWIM0 if (bus == 0) { - /* Set up TWI0 register base address and IRQ number */ - - priv = &g_twi0; - priv->base = SAM_TWI0_BASE; - priv->irq = SAM_IRQ_TWI0; - priv->twi = 0; + priv = &g_twi0; /* Enable peripheral clocking */ @@ -917,12 +934,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) #ifdef CONFIG_SAM34_TWIM1 if (bus == 1) { - /* Set up TWI1 register base address and IRQ number */ - - priv = &g_twi1; - priv->base = SAM_TWI1_BASE; - priv->irq = SAM_IRQ_TWI1; - priv->twi = 1; + priv = &g_twi1; /* Enable peripheral clocking */ @@ -946,15 +958,6 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) return NULL; } - /* Initialize the device structure */ - - priv->dev.ops = &g_twiops; - - /* Initialize mutex & semaphores */ - - nxmutex_init(&priv->lock); - nxsem_init(&priv->waitsem, 0, 0); - /* Configure and enable the TWI hardware */ priv->pid = pid; @@ -989,11 +992,6 @@ int sam_i2cbus_uninitialize(struct i2c_master_s * dev) up_disable_irq(priv->irq); - /* Reset data structures */ - - nxmutex_destroy(&priv->lock); - nxsem_destroy(&priv->waitsem); - /* Cancel the watchdog timer */ wd_cancel(&priv->timeout); diff --git a/arch/arm/src/sama5/sam_adc.c b/arch/arm/src/sama5/sam_adc.c index 8ad945879c..6399524627 100644 --- a/arch/arm/src/sama5/sam_adc.c +++ b/arch/arm/src/sama5/sam_adc.c @@ -497,11 +497,20 @@ static const struct adc_ops_s g_adcops = /* ADC internal state */ -static struct sam_adc_s g_adcpriv; +static struct sam_adc_s g_adcpriv = +{ + .lock = NXMUTEX_INITIALIZER, +}; /* ADC device instance */ -static struct adc_dev_s g_adcdev; +static struct adc_dev_s g_adcdev = +{ +#ifdef SAMA5_ADC_HAVE_CHANNELS + .ad_ops = &g_adcops, +#endif + .ad_priv = &g_adcpriv, +}; /**************************************************************************** * Private Functions @@ -2041,17 +2050,9 @@ struct adc_dev_s *sam_adc_initialize(void) /* Initialize the public ADC device data structure */ #ifdef SAMA5_ADC_HAVE_CHANNELS - g_adcdev.ad_ops = &g_adcops; priv->dev = &g_adcdev; #endif - g_adcdev.ad_priv = priv; - - /* Initialize the private ADC device data structure */ - - nxmutex_init(&priv->lock); - priv->cb = NULL; - #ifdef CONFIG_SAMA5_ADC_DMA /* Allocate a DMA channel from DMAC1 */ diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c index 4f2b1c58c3..55e0b29584 100644 --- a/arch/arm/src/sama5/sam_can.c +++ b/arch/arm/src/sama5/sam_can.c @@ -287,8 +287,17 @@ static const struct sam_config_s g_can0const = }, }; -static struct sam_can_s g_can0priv; -static struct can_dev_s g_can0dev; +static struct sam_can_s g_can0priv = +{ + .config = &g_can0const, + .freemb = CAN_ALL_MAILBOXES, + .lock = NXMUTEX_INITIALIZER, +}; +static struct can_dev_s g_can0dev = +{ + .cd_ops = &g_canops, + .cd_priv = &g_can0priv, +}; #endif #ifdef CONFIG_SAMA5_CAN1 @@ -322,8 +331,17 @@ static const struct sam_config_s g_can1const = }, }; -static struct sam_can_s g_can1priv; -static struct can_dev_s g_can1dev; +static struct sam_can_s g_can1priv = +{ + .config = &g_can1const, + .freemb = CAN_ALL_MAILBOXES, + .lock = NXMUTEX_INITIALIZER, +}; +static struct can_dev_s g_can1dev = +{ + .cd_ops = &g_canops, + .cd_priv = &g_can1priv, +}; #endif /**************************************************************************** @@ -1902,7 +1920,6 @@ struct can_dev_s *sam_caninitialize(int port) { struct can_dev_s *dev; struct sam_can_s *priv; - const struct sam_config_s *config; caninfo("CAN%d\n", port); @@ -1915,9 +1932,8 @@ struct can_dev_s *sam_caninitialize(int port) { /* Select the CAN0 device structure */ - dev = &g_can0dev; - priv = &g_can0priv; - config = &g_can0const; + dev = &g_can0dev; + priv = &g_can0priv; } else #endif @@ -1926,9 +1942,8 @@ struct can_dev_s *sam_caninitialize(int port) { /* Select the CAN1 device structure */ - dev = &g_can1dev; - priv = &g_can1priv; - config = &g_can1const; + dev = &g_can1dev; + priv = &g_can1priv; } else #endif @@ -1943,16 +1958,8 @@ struct can_dev_s *sam_caninitialize(int port) { /* Yes, then perform one time data initialization */ - memset(priv, 0, sizeof(struct sam_can_s)); - priv->config = config; - priv->freemb = CAN_ALL_MAILBOXES; priv->initialized = true; - nxmutex_init(&priv->lock); - - dev->cd_ops = &g_canops; - dev->cd_priv = (void *)priv; - /* And put the hardware in the initial state */ can_reset(dev); diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c index 0f698494b8..b70a09fa4c 100644 --- a/arch/arm/src/sama5/sam_dmac.c +++ b/arch/arm/src/sama5/sam_dmac.c @@ -342,6 +342,9 @@ static struct sam_dmach_s g_dmach0[SAM_NDMACHAN] = static struct sam_dmac_s g_dmac0 = { + .chlock = NXMUTEX_INITIALIZER, + .dsem = SEM_INITIALIZER(SAM_NDMACHAN), + /* DMAC 0 base address */ .base = SAM_DMAC0_VBASE, @@ -444,6 +447,9 @@ static struct sam_dmach_s g_dmach1[SAM_NDMACHAN] = static struct sam_dmac_s g_dmac1 = { + .chlock = NXMUTEX_INITIALIZER, + .dsem = SEM_INITIALIZER(SAM_NDMACHAN), + /* DMAC 0 base address */ .base = SAM_DMAC1_VBASE, @@ -1854,11 +1860,6 @@ void sam_dmainitialize(struct sam_dmac_s *dmac) /* Enable the DMA controller */ sam_putdmac(dmac, DMAC_EN_ENABLE, SAM_DMAC_EN_OFFSET); - - /* Initialize muttex & semaphores */ - - nxmutex_init(&dmac->chlock); - nxsem_init(&dmac->dsem, 0, SAM_NDMACHAN); } /**************************************************************************** diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c index 0829e77db0..030aac185b 100644 --- a/arch/arm/src/sama5/sam_ehci.c +++ b/arch/arm/src/sama5/sam_ehci.c @@ -435,7 +435,12 @@ static int sam_reset(void); * global instance. */ -static struct sam_ehci_s g_ehci; +static struct sam_ehci_s g_ehci = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), + .ep0.iocsem = SEM_INITIALIZER(1), +}; /* This is the connection/enumeration interface */ @@ -4820,15 +4825,6 @@ struct usbhost_connection_s *sam_ehci_initialize(int controller) usbhost_vtrace1(EHCI_VTRACE1_INITIALIZING, 0); - /* Initialize the EHCI state data structure */ - - nxmutex_init(&g_ehci.lock); - nxsem_init(&g_ehci.pscsem, 0, 0); - - /* Initialize EP0 */ - - nxsem_init(&g_ehci.ep0.iocsem, 0, 1); - /* Initialize the root hub port structures */ for (i = 0; i < SAM_EHCI_NRHPORT; i++) diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c index 11dc5b5e3d..d76405de0e 100644 --- a/arch/arm/src/sama5/sam_hsmci.c +++ b/arch/arm/src/sama5/sam_hsmci.c @@ -596,57 +596,145 @@ static void sam_callback(void *arg); * Private Data ****************************************************************************/ -/* Callbacks */ - -static const struct sdio_dev_s g_callbacks = -{ - .reset = sam_reset, - .capabilities = sam_capabilities, - .status = sam_status, - .widebus = sam_widebus, - .clock = sam_clock, - .attach = sam_attach, - .sendcmd = sam_sendcmd, - .blocksetup = sam_blocksetup, - .recvsetup = sam_recvsetup, - .sendsetup = sam_sendsetup, - .cancel = sam_cancel, - .waitresponse = sam_waitresponse, - .recv_r1 = sam_recvshort, - .recv_r2 = sam_recvlong, - .recv_r3 = sam_recvshort, - .recv_r4 = sam_recvnotimpl, - .recv_r5 = sam_recvnotimpl, - .recv_r6 = sam_recvshort, - .recv_r7 = sam_recvshort, - .waitenable = sam_waitenable, - .eventwait = sam_eventwait, - .callbackenable = sam_callbackenable, - .registercallback = sam_registercallback, -#ifdef CONFIG_SDIO_DMA -#ifndef HSCMI_NORXDMA - .dmarecvsetup = sam_dmarecvsetup, -#else - .dmarecvsetup = sam_recvsetup, -#endif -#ifndef HSCMI_NOTXDMA - .dmasendsetup = sam_dmasendsetup, -#else - .dmasendsetup = sam_sendsetup, -#endif -#endif -}; - /* Pre-allocate memory for each HSMCI device */ #ifdef CONFIG_SAMA5_HSMCI0 -static struct sam_dev_s g_hsmci0; +static struct sam_dev_s g_hsmci0 = +{ + .dev = + { + .reset = sam_reset, + .capabilities = sam_capabilities, + .status = sam_status, + .widebus = sam_widebus, + .clock = sam_clock, + .attach = sam_attach, + .sendcmd = sam_sendcmd, + .blocksetup = sam_blocksetup, + .recvsetup = sam_recvsetup, + .sendsetup = sam_sendsetup, + .cancel = sam_cancel, + .waitresponse = sam_waitresponse, + .recv_r1 = sam_recvshort, + .recv_r2 = sam_recvlong, + .recv_r3 = sam_recvshort, + .recv_r4 = sam_recvnotimpl, + .recv_r5 = sam_recvnotimpl, + .recv_r6 = sam_recvshort, + .recv_r7 = sam_recvshort, + .waitenable = sam_waitenable, + .eventwait = sam_eventwait, + .callbackenable = sam_callbackenable, + .registercallback = sam_registercallback, +#ifdef CONFIG_SDIO_DMA +#ifndef HSCMI_NORXDMA + .dmarecvsetup = sam_dmarecvsetup, +#else + .dmarecvsetup = sam_recvsetup, +#endif +#ifndef HSCMI_NOTXDMA + .dmasendsetup = sam_dmasendsetup, +#else + .dmasendsetup = sam_sendsetup, +#endif +#endif + }, + .waitsem = SEM_INITIALIZER(0), + .base = SAM_HSMCI0_VBASE, + .hsmci = 0, +}; #endif #ifdef CONFIG_SAMA5_HSMCI1 -static struct sam_dev_s g_hsmci1; +static struct sam_dev_s g_hsmci1 = +{ + .dev = + { + .reset = sam_reset, + .capabilities = sam_capabilities, + .status = sam_status, + .widebus = sam_widebus, + .clock = sam_clock, + .attach = sam_attach, + .sendcmd = sam_sendcmd, + .blocksetup = sam_blocksetup, + .recvsetup = sam_recvsetup, + .sendsetup = sam_sendsetup, + .cancel = sam_cancel, + .waitresponse = sam_waitresponse, + .recv_r1 = sam_recvshort, + .recv_r2 = sam_recvlong, + .recv_r3 = sam_recvshort, + .recv_r4 = sam_recvnotimpl, + .recv_r5 = sam_recvnotimpl, + .recv_r6 = sam_recvshort, + .recv_r7 = sam_recvshort, + .waitenable = sam_waitenable, + .eventwait = sam_eventwait, + .callbackenable = sam_callbackenable, + .registercallback = sam_registercallback, +#ifdef CONFIG_SDIO_DMA +#ifndef HSCMI_NORXDMA + .dmarecvsetup = sam_dmarecvsetup, +#else + .dmarecvsetup = sam_recvsetup, +#endif +#ifndef HSCMI_NOTXDMA + .dmasendsetup = sam_dmasendsetup, +#else + .dmasendsetup = sam_sendsetup, +#endif +#endif + }, + .waitsem = SEM_INITIALIZER(0), + .base = SAM_HSMCI0_VBASE, + .hsmci = 0, +}; #endif #ifdef CONFIG_SAMA5_HSMCI2 -static struct sam_dev_s g_hsmci2; +static struct sam_dev_s g_hsmci2 = +{ + .dev = + { + .reset = sam_reset, + .capabilities = sam_capabilities, + .status = sam_status, + .widebus = sam_widebus, + .clock = sam_clock, + .attach = sam_attach, + .sendcmd = sam_sendcmd, + .blocksetup = sam_blocksetup, + .recvsetup = sam_recvsetup, + .sendsetup = sam_sendsetup, + .cancel = sam_cancel, + .waitresponse = sam_waitresponse, + .recv_r1 = sam_recvshort, + .recv_r2 = sam_recvlong, + .recv_r3 = sam_recvshort, + .recv_r4 = sam_recvnotimpl, + .recv_r5 = sam_recvnotimpl, + .recv_r6 = sam_recvshort, + .recv_r7 = sam_recvshort, + .waitenable = sam_waitenable, + .eventwait = sam_eventwait, + .callbackenable = sam_callbackenable, + .registercallback = sam_registercallback, +#ifdef CONFIG_SDIO_DMA +#ifndef HSCMI_NORXDMA + .dmarecvsetup = sam_dmarecvsetup, +#else + .dmarecvsetup = sam_recvsetup, +#endif +#ifndef HSCMI_NOTXDMA + .dmasendsetup = sam_dmasendsetup, +#else + .dmasendsetup = sam_sendsetup, +#endif +#endif + }, + .waitsem = SEM_INITIALIZER(0), + .base = SAM_HSMCI0_VBASE, + .hsmci = 0, +}; #endif /**************************************************************************** @@ -3193,11 +3281,6 @@ struct sdio_dev_s *sdio_initialize(int slotno) priv = &g_hsmci0; - /* HSMCI0 Initialization */ - - priv->base = SAM_HSMCI0_VBASE; - priv->hsmci = 0; - /* Configure PIOs for 4-bit, wide-bus operation. NOTE: (1) the chip * is capable of 8-bit wide bus operation but D4-D7 are not configured, * (2) any card detection PIOs must be set up in board-specific logic. @@ -3232,11 +3315,6 @@ struct sdio_dev_s *sdio_initialize(int slotno) priv = &g_hsmci1; - /* HSMCI1 Initialization */ - - priv->base = SAM_HSMCI1_VBASE; - priv->hsmci = 1; - /* Configure PIOs for 4-bit, wide-bus operation. NOTE: (1) the chip * is capable of 8-bit wide bus operation but D4-D7 are not configured, * (2) any card detection PIOs must be set up in board-specific logic. @@ -3271,11 +3349,6 @@ struct sdio_dev_s *sdio_initialize(int slotno) priv = &g_hsmci2; - /* HSMCI2 Initialization */ - - priv->base = SAM_HSMCI2_VBASE; - priv->hsmci = 2; - /* Configure PIOs for 4-bit, wide-bus operation. NOTE: (1) the chip * is capable of 8-bit wide bus operation but D4-D7 are not configured, * (2) any card detection PIOs must be set up in board-specific logic. @@ -3312,16 +3385,6 @@ struct sdio_dev_s *sdio_initialize(int slotno) " hsmci: %d dmac: %d pid: %" PRId32 "\n", priv, priv->base, priv->hsmci, dmac, pid); - /* Initialize the HSMCI slot structure */ - - /* Initialize semaphores */ - - nxsem_init(&priv->waitsem, 0, 0); - - /* Initialize the callbacks */ - - memcpy(&priv->dev, &g_callbacks, sizeof(struct sdio_dev_s)); - /* Allocate a DMA channel */ priv->dma = sam_dmachannel(dmac, DMA_FLAGS(pid)); diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c index 1b88c9bdea..588417fcca 100644 --- a/arch/arm/src/sama5/sam_nand.c +++ b/arch/arm/src/sama5/sam_nand.c @@ -272,16 +272,36 @@ static void nand_reset(struct sam_nandcs_s *priv); */ #ifdef CONFIG_SAMA5_EBICS0_NAND -static struct sam_nandcs_s g_cs0nand; +static struct sam_nandcs_s g_cs0nand = +{ +#ifdef CONFIG_SAMA5_NAND_DMA + .waitsem = SEM_INITIALIZER(0) +#endif +}; #endif #ifdef CONFIG_SAMA5_EBICS1_NAND -static struct sam_nandcs_s g_cs1nand; +static struct sam_nandcs_s g_cs1nand = +{ +#ifdef CONFIG_SAMA5_NAND_DMA + .waitsem = SEM_INITIALIZER(0) +#endif +}; #endif #ifdef CONFIG_SAMA5_EBICS2_NAND -static struct sam_nandcs_s g_cs2nand; +static struct sam_nandcs_s g_cs2nand = +{ +#ifdef CONFIG_SAMA5_NAND_DMA + .waitsem = SEM_INITIALIZER(0) +#endif +}; #endif #ifdef CONFIG_SAMA5_EBICS3_NAND -static struct sam_nandcs_s g_cs3nand; +static struct sam_nandcs_s g_cs3nand = +{ +#ifdef CONFIG_SAMA5_NAND_DMA + .waitsem = SEM_INITIALIZER(0) +#endif +}; #endif /**************************************************************************** @@ -290,7 +310,15 @@ static struct sam_nandcs_s g_cs3nand; /* NAND global state */ -struct sam_nand_s g_nand; +struct sam_nand_s g_nand = +{ +#if NAND_NBANKS > 1 + .lock = NXMUTEX_INITIALIZER, +#endif +#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS + .waitsem = SEM_INITIALIZER(0), +#endif +}; /**************************************************************************** * Private Functions @@ -2966,7 +2994,6 @@ struct mtd_dev_s *sam_nand_initialize(int cs) /* Initialize the device structure */ - memset(priv, 0, sizeof(struct sam_nandcs_s)); priv->raw.cmdaddr = cmdaddr; priv->raw.addraddr = addraddr; priv->raw.dataaddr = dataaddr; @@ -2980,34 +3007,15 @@ struct mtd_dev_s *sam_nand_initialize(int cs) #endif priv->cs = cs; -#ifdef CONFIG_SAMA5_NAND_DMA - nxsem_init(&priv->waitsem, 0, 0); -#endif - /* Perform one-time, global NFC/PMECC initialization */ if (!g_nand.initialized) { - /* Initialize the global nand state structure */ - -#if NAND_NBANKS > 1 - nxmutex_init(&g_nand.lock); -#endif - -#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS - nxsem_init(&g_nand.waitsem, 0, 0); -#endif - /* Enable the NAND FLASH Controller (The NFC is always used) */ nand_putreg(SAM_HSMC_CTRL, HSMC_CTRL_NFCEN); -#ifdef CONFIG_SAMA5_HAVE_PMECC - /* Perform one-time initialization of the PMECC */ - - pmecc_initialize(); - -#else +#ifndef CONFIG_SAMA5_HAVE_PMECC /* Disable the PMECC if it is not being used */ nand_putreg(SAM_HSMC_PMECCTRL, HSMC_PMECCTRL_RST); diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c index b7b27cd0d1..34da2bee1b 100644 --- a/arch/arm/src/sama5/sam_ohci.c +++ b/arch/arm/src/sama5/sam_ohci.c @@ -461,7 +461,11 @@ static void sam_disconnect(struct usbhost_driver_s *drvr, * single global instance. */ -static struct sam_ohci_s g_ohci; +static struct sam_ohci_s g_ohci = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), +}; /* This is the connection/enumeration interface */ @@ -3954,11 +3958,6 @@ struct usbhost_connection_s *sam_ohci_initialize(int controller) DEBUGASSERT(sizeof(struct sam_ed_s) == SIZEOF_SAM_ED_S); DEBUGASSERT(sizeof(struct sam_gtd_s) == SIZEOF_SAM_TD_S); - /* Initialize the state data structure */ - - nxsem_init(&g_ohci.pscsem, 0, 0); - nxmutex_init(&g_ohci.lock); - #ifndef CONFIG_USBHOST_INT_DISABLE g_ohci.ininterval = MAX_PERINTERVAL; g_ohci.outinterval = MAX_PERINTERVAL; diff --git a/arch/arm/src/sama5/sam_pmecc.c b/arch/arm/src/sama5/sam_pmecc.c index 7d886b2754..280d31cd90 100644 --- a/arch/arm/src/sama5/sam_pmecc.c +++ b/arch/arm/src/sama5/sam_pmecc.c @@ -172,7 +172,10 @@ static uint32_t pmecc_correctionalgo(uint32_t isr, uintptr_t data); /* PMECC state data */ -static struct sam_pmecc_s g_pmecc; +static struct sam_pmecc_s g_pmecc = +{ + .lock = NXMUTEX_INITIALIZER, +}; /* Maps BCH_ERR correctability register value to number of errors per * sector. @@ -999,28 +1002,6 @@ static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize) * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: pmecc_initialize - * - * Description: - * Perform one-time PMECC initialization. This must be called before any - * other PMECC interfaces are used. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if NAND_NPMECC_BANKS > 1 -void pmecc_initialize(void) -{ - nxmutex_init(&g_pmecc.lock); -} -#endif - /**************************************************************************** * Name: pmecc_configure * diff --git a/arch/arm/src/sama5/sam_pmecc.h b/arch/arm/src/sama5/sam_pmecc.h index bfea5407b8..355dce4f27 100644 --- a/arch/arm/src/sama5/sam_pmecc.h +++ b/arch/arm/src/sama5/sam_pmecc.h @@ -294,27 +294,6 @@ void pmecc_enable(void); void pmecc_disable(void); -/**************************************************************************** - * Name: pmecc_initialize - * - * Description: - * Perform one-time PMECC initialization. This must be called before any - * other PMECC interfaces are used. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if NAND_NPMECC_BANKS > 1 -void pmecc_initialize(void); -#else -# define pmecc_initialize() -#endif - /**************************************************************************** * Name: pmecc_configure * @@ -417,7 +396,6 @@ void pmecc_buildgf(uint32_t mm, int16_t *indexof, int16_t *alphato); # define pmecc_unlock() # define pmecc_enable() # define pmecc_disable() -# define pmecc_initialize() # define pmecc_configure(a,b) (0) # define pmecc_get_eccsize() (0) # define pmecc_get_pagesize() (0) diff --git a/arch/arm/src/sama5/sam_sdmmc.c b/arch/arm/src/sama5/sam_sdmmc.c index 37098b781f..d1db6a9af8 100644 --- a/arch/arm/src/sama5/sam_sdmmc.c +++ b/arch/arm/src/sama5/sam_sdmmc.c @@ -425,7 +425,8 @@ struct sam_dev_s g_sdmmcdev[SAM_MAX_SDMMC_DEV_SLOTS] = .dmasendsetup = sam_sendsetup, #endif #endif - } + }, + .waitsem = SEM_INITIALIZER(0), }, #endif @@ -482,7 +483,8 @@ struct sam_dev_s g_sdmmcdev[SAM_MAX_SDMMC_DEV_SLOTS] = .dmarecvsetup = sam_recvsetup, .dmasendsetup = sam_sendsetup, #endif - } + }, + .waitsem = SEM_INITIALIZER(0), } #endif #endif @@ -3588,11 +3590,7 @@ struct sdio_dev_s *sam_sdmmc_sdio_initialize(int slotno) struct sam_dev_s *priv = &g_sdmmcdev[slotno]; - /* Initialize the SDMMC slot structure data structure - * Initialize semaphores - */ - - nxsem_init(&priv->waitsem, 0, 0); + /* Initialize the SDMMC slot structure data structure */ switch (priv->addr) { diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c index aafff4b772..e7b7746415 100644 --- a/arch/arm/src/sama5/sam_spi.c +++ b/arch/arm/src/sama5/sam_spi.c @@ -309,6 +309,7 @@ static const struct spi_ops_s g_spi0ops = static struct sam_spidev_s g_spi0dev = { .base = SAM_SPI0_VBASE, + .spilock = NXMUTEX_INITIALIZER, .select = sam_spi0select, #ifdef CONFIG_SAMA5_SPI_DMA .pid = SAM_PID_SPI0, @@ -345,6 +346,7 @@ static const struct spi_ops_s g_spi1ops = static struct sam_spidev_s g_spi1dev = { .base = SAM_SPI1_VBASE, + .spilock = NXMUTEX_INITIALIZER, .select = sam_spi1select, #ifdef CONFIG_SAMA5_SPI_DMA .pid = SAM_PID_SPI1, @@ -1783,11 +1785,6 @@ struct spi_dev_s *sam_spibus_initialize(int port) spi_getreg(spi, SAM_SPI_SR_OFFSET); spi_getreg(spi, SAM_SPI_RDR_OFFSET); - /* Initialize the SPI mutex that enforces mutually exclusive - * access to the SPI registers. - */ - - nxmutex_init(&spi->spilock); spi->initialized = true; #ifdef CONFIG_SAMA5_SPI_DMA diff --git a/arch/arm/src/sama5/sam_tc.c b/arch/arm/src/sama5/sam_tc.c index 40d49b030b..31a3ad9406 100644 --- a/arch/arm/src/sama5/sam_tc.c +++ b/arch/arm/src/sama5/sam_tc.c @@ -98,10 +98,7 @@ struct sam_chconfig_s struct sam_tcconfig_s { - uintptr_t base; /* TC register base address */ - uint8_t pid; /* Peripheral ID */ uint8_t chfirst; /* First channel number */ - uint8_t tc; /* Timer/counter number */ /* Channels */ @@ -201,10 +198,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel); #ifdef CONFIG_SAMA5_TC0 static const struct sam_tcconfig_s g_tc012config = { - .base = SAM_TC012_VBASE, - .pid = SAM_PID_TC0, .chfirst = 0, - .tc = 0, .channel = { [0] = @@ -271,10 +265,7 @@ static const struct sam_tcconfig_s g_tc012config = #ifdef CONFIG_SAMA5_TC1 static const struct sam_tcconfig_s g_tc345config = { - .base = SAM_TC345_VBASE, - .pid = SAM_PID_TC1, .chfirst = 3, - .tc = 1, .channel = { [0] = @@ -341,10 +332,7 @@ static const struct sam_tcconfig_s g_tc345config = #ifdef CONFIG_SAMA5_TC2 static const struct sam_tcconfig_s g_tc678config = { - .base = SAM_TC678_VBASE, - .pid = SAM_PID_TC2, .chfirst = 6, - .tc = 2, .channel = { [0] = @@ -411,15 +399,33 @@ static const struct sam_tcconfig_s g_tc678config = /* Timer/counter state */ #ifdef CONFIG_SAMA5_TC0 -static struct sam_tc_s g_tc012; +static struct sam_tc_s g_tc012 = +{ + .lock = NXMUTEX_INITIALIZER, + .base = SAM_TC012_VBASE, + .pid = SAM_PID_TC0, + .tc = 0, +}; #endif #ifdef CONFIG_SAMA5_TC1 -static struct sam_tc_s g_tc345; +static struct sam_tc_s g_tc345 = +{ + .lock = NXMUTEX_INITIALIZER, + .base = SAM_TC345_VBASE, + .pid = SAM_PID_TC1, + .tc = 1, +}; #endif #ifdef CONFIG_SAMA5_TC2 -static struct sam_tc_s g_tc678; +static struct sam_tc_s g_tc678 = +{ + .lock = NXMUTEX_INITIALIZER, + .base = SAM_TC678_VBASE, + .pid = SAM_PID_TC2, + .tc = 2, +}; #endif /* TC frequency data. @@ -954,19 +960,11 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) flags = enter_critical_section(); if (!tc->initialized) { - /* Initialize the timer counter data structure. */ - - memset(tc, 0, sizeof(struct sam_tc_s)); - nxmutex_init(&tc->lock); - tc->base = tcconfig->base; - tc->tc = channel < 3 ? 0 : 1; - tc->pid = tcconfig->pid; - /* Initialize the channels */ for (i = 0, ch = tcconfig->chfirst; i < SAM_TC_NCHANNELS; i++) { - tmrerr("ERROR: Initializing TC%d channel %d\n", tcconfig->tc, ch); + tmrerr("ERROR: Initializing TC%d channel %d\n", tc->tc, ch); /* Initialize the channel data structure */ @@ -1008,7 +1006,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) /* Set the maximum TC peripheral clock frequency */ - regval = PMC_PCR_PID(tcconfig->pid) | PMC_PCR_CMD | PMC_PCR_EN; + regval = PMC_PCR_PID(tc->pid) | PMC_PCR_CMD | PMC_PCR_EN; #ifdef SAMA5_HAVE_PMC_PCR_DIV /* Set the MCK divider (if any) */ @@ -1020,7 +1018,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) /* Enable clocking to the timer counter */ - sam_enableperiph0(tcconfig->pid); + sam_enableperiph0(tc->pid); /* Attach the timer interrupt handler and enable the timer interrupts */ diff --git a/arch/arm/src/sama5/sam_trng.c b/arch/arm/src/sama5/sam_trng.c index ae0ef9acf1..547f3d272d 100644 --- a/arch/arm/src/sama5/sam_trng.c +++ b/arch/arm/src/sama5/sam_trng.c @@ -74,7 +74,11 @@ struct trng_dev_s * Private Data ****************************************************************************/ -static struct trng_dev_s g_trngdev; +static struct trng_dev_s g_trngdev = +{ + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; static const struct file_operations g_trngops = { @@ -333,15 +337,6 @@ static int sam_rng_initialize(void) finfo("Initializing TRNG hardware\n"); - /* Initialize the device structure */ - - memset(&g_trngdev, 0, sizeof(struct trng_dev_s)); - - /* Initialize mutex & semphores */ - - nxmutex_init(&g_trngdev.lock); - nxsem_init(&g_trngdev.waitsem, 0, 0); - /* Enable clocking to the TRNG */ sam_trng_enableclk(); diff --git a/arch/arm/src/sama5/sam_tsd.c b/arch/arm/src/sama5/sam_tsd.c index e4e17a5571..800a414bae 100644 --- a/arch/arm/src/sama5/sam_tsd.c +++ b/arch/arm/src/sama5/sam_tsd.c @@ -245,7 +245,12 @@ static const struct file_operations g_tsdops = /* The driver state structure is pre-allocated. */ -static struct sam_tsd_s g_tsd; +static struct sam_tsd_s g_tsd = +{ + .threshx = INVALID_THRESHOLD, + .threshy = INVALID_THRESHOLD, + .waitsem = SEM_INITIALIZER(0), +}; /**************************************************************************** * Private Functions @@ -1650,11 +1655,7 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor) /* Initialize the touchscreen device driver instance */ - memset(priv, 0, sizeof(struct sam_tsd_s)); - priv->adc = adc; /* Save the ADC device handle */ - priv->threshx = INVALID_THRESHOLD; /* Initialize thresholding logic */ - priv->threshy = INVALID_THRESHOLD; /* Initialize thresholding logic */ - nxsem_init(&priv->waitsem, 0, 0); + priv->adc = adc; /* Save the ADC device handle */ /* Register the device as an input device */ @@ -1665,7 +1666,7 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor) if (ret < 0) { ierr("ERROR: register_driver() failed: %d\n", ret); - goto errout_with_priv; + return ret; } /* And return success. The hardware will be initialized as soon as the @@ -1673,10 +1674,6 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor) */ return OK; - -errout_with_priv: - nxsem_destroy(&priv->waitsem); - return ret; } /**************************************************************************** diff --git a/arch/arm/src/sama5/sam_twi.c b/arch/arm/src/sama5/sam_twi.c index a908777ccb..507692a29b 100644 --- a/arch/arm/src/sama5/sam_twi.c +++ b/arch/arm/src/sama5/sam_twi.c @@ -229,6 +229,14 @@ static void twi_hw_initialize(struct twi_dev_s *priv, uint32_t frequency); * Private Data ****************************************************************************/ +static const struct i2c_ops_s g_twiops = +{ + .transfer = twi_transfer, +#ifdef CONFIG_I2C_RESET + .reset = twi_reset +#endif +}; + #ifdef CONFIG_SAMA5_TWI0 static const struct twi_attr_s g_twi0attr = { @@ -240,7 +248,16 @@ static const struct twi_attr_s g_twi0attr = .base = SAM_TWI0_VBASE, }; -static struct twi_dev_s g_twi0; +static struct twi_dev_s g_twi0 = +{ + .dev = + { + .ops = &g_twiops, + }, + .attr = &g_twi0attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef CONFIG_SAMA5_TWI1 @@ -254,7 +271,16 @@ static const struct twi_attr_s g_twi1attr = .base = SAM_TWI1_VBASE, }; -static struct twi_dev_s g_twi1; +static struct twi_dev_s g_twi1 = +{ + .dev = + { + .ops = &g_twiops, + }, + .attr = &g_twi1attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef CONFIG_SAMA5_TWI2 @@ -268,7 +294,16 @@ static const struct twi_attr_s g_twi2attr = .base = SAM_TWI2_VBASE, }; -static struct twi_dev_s g_twi2; +static struct twi_dev_s g_twi2 = +{ + .dev = + { + .ops = &g_twiops, + }, + .attr = &g_twi2attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef CONFIG_SAMA5_TWI3 @@ -282,16 +317,17 @@ static const struct twi_attr_s g_twi3attr = .base = SAM_TWI3_VBASE, }; -static struct twi_dev_s g_twi3; -#endif - -static const struct i2c_ops_s g_twiops = +static struct twi_dev_s g_twi3 = { - .transfer = twi_transfer -#ifdef CONFIG_I2C_RESET - , .reset = twi_reset -#endif + .dev = + { + .ops = &g_twiops, + }, + .attr = &g_twi3attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), }; +#endif /**************************************************************************** * Private Functions @@ -1177,13 +1213,9 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) #ifdef CONFIG_SAMA5_TWI0 if (bus == 0) { - /* Select up TWI0 and setup invariant attributes */ - - priv = &g_twi0; - priv->attr = &g_twi0attr; - - /* Select the (initial) TWI frequency */ + /* Select up TWI0 and the (initial) TWI frequency */ + priv = &g_twi0; frequency = CONFIG_SAMA5_TWI0_FREQUENCY; } else @@ -1191,13 +1223,9 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) #ifdef CONFIG_SAMA5_TWI1 if (bus == 1) { - /* Select up TWI1 and setup invariant attributes */ - - priv = &g_twi1; - priv->attr = &g_twi1attr; - - /* Select the (initial) TWI frequency */ + /* Select up TWI1 and the (initial) TWI frequency */ + priv = &g_twi1; frequency = CONFIG_SAMA5_TWI1_FREQUENCY; } else @@ -1205,13 +1233,9 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) #ifdef CONFIG_SAMA5_TWI2 if (bus == 2) { - /* Select up TWI2 and setup invariant attributes */ - - priv = &g_twi2; - priv->attr = &g_twi2attr; - - /* Select the (initial) TWI frequency */ + /* Select up TWI2 and the (initial) TWI frequency */ + priv = &g_twi2; frequency = CONFIG_SAMA5_TWI2_FREQUENCY; } else @@ -1219,13 +1243,9 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) #ifdef CONFIG_SAMA5_TWI3 if (bus == 3) { - /* Select up TWI3 and setup invariant attributes */ - - priv = &g_twi3; - priv->attr = &g_twi3attr; - - /* Select the (initial) TWI frequency */ + /* Select up TWI3 and the (initial) TWI frequency */ + priv = &g_twi3; frequency = CONFIG_SAMA5_TWI3_FREQUENCY; } else @@ -1248,15 +1268,6 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) goto errout_with_lock; } - /* Initialize the TWI driver structure */ - - priv->dev.ops = &g_twiops; - - /* Initialize mutex & semaphores */ - - nxmutex_init(&priv->lock); - nxsem_init(&priv->waitsem, 0, 0); - /* Perform repeatable TWI hardware initialization */ twi_hw_initialize(priv, frequency); @@ -1286,11 +1297,6 @@ int sam_i2cbus_uninitialize(struct i2c_master_s *dev) up_disable_irq(priv->attr->irq); - /* Reset data structures */ - - nxmutex_destroy(&priv->lock); - nxsem_destroy(&priv->waitsem); - /* Cancel the watchdog timer */ wd_cancel(&priv->timeout); diff --git a/arch/arm/src/sama5/sam_xdmac.c b/arch/arm/src/sama5/sam_xdmac.c index 418b5de031..d8510f84f4 100644 --- a/arch/arm/src/sama5/sam_xdmac.c +++ b/arch/arm/src/sama5/sam_xdmac.c @@ -539,6 +539,9 @@ static struct sam_xdmach_s g_xdmach0[SAM_NDMACHAN] = static struct sam_xdmac_s g_xdmac0 = { + .chlock = NXMUTEX_INITIALIZER, + .dsem = SEM_INITIALIZER(SAM_NDMACHAN), + /* XDMAC 0 base address */ .base = SAM_XDMAC0_VBASE, @@ -713,6 +716,9 @@ static struct sam_xdmach_s g_xdmach1[SAM_NDMACHAN] = static struct sam_xdmac_s g_xdmac1 = { + .chlock = NXMUTEX_INITIALIZER, + .dsem = SEM_INITIALIZER(SAM_NDMACHAN), + /* XDMAC 0 base address */ .base = SAM_XDMAC1_VBASE, @@ -1979,11 +1985,6 @@ void sam_dmainitialize(struct sam_xdmac_s *xdmac) /* Disable all DMA channels */ sam_putdmac(xdmac, XDMAC_CHAN_ALL, SAM_XDMAC_GD_OFFSET); - - /* Initialize mutex & semaphores */ - - nxmutex_init(&xdmac->chlock); - nxsem_init(&xdmac->dsem, 0, SAM_NDMACHAN); } /**************************************************************************** diff --git a/arch/arm/src/samd2l2/sam_dmac.c b/arch/arm/src/samd2l2/sam_dmac.c index 496136c253..3a5808eb08 100644 --- a/arch/arm/src/samd2l2/sam_dmac.c +++ b/arch/arm/src/samd2l2/sam_dmac.c @@ -123,9 +123,9 @@ static int sam_rxbuffer(struct sam_dmach_s *dmach, uint32_t paddr, /* These mutex protect the DMA channel and descriptor tables */ -static mutex_t g_chlock; +static mutex_t g_chlock = NXMUTEX_INITIALIZER; #if CONFIG_SAMD2L2_DMAC_NDESC > 0 -static sem_t g_dsem; +static sem_t g_dsem = SEM_INITIALIZER(CONFIG_SAMD2L2_DMAC_NDESC); #endif /* This array describes the state of each DMA channel */ @@ -751,13 +751,6 @@ void weak_function arm_dma_initialize(void) dmainfo("Initialize DMAC\n"); int i; - /* Initialize global lock and semaphores */ - - nxmutex_init(&g_chlock); -#if CONFIG_SAMD2L2_DMAC_NDESC > 0 - nxsem_init(&g_dsem, 0, CONFIG_SAMD2L2_DMAC_NDESC); -#endif - /* Initialized the DMA channel table */ for (i = 0; i < SAMD2L2_NDMACHAN; i++) diff --git a/arch/arm/src/samd2l2/sam_i2c_master.c b/arch/arm/src/samd2l2/sam_i2c_master.c index b591e1f1a2..b571270be6 100644 --- a/arch/arm/src/samd2l2/sam_i2c_master.c +++ b/arch/arm/src/samd2l2/sam_i2c_master.c @@ -255,6 +255,14 @@ static void i2c_pad_configure(struct sam_i2c_dev_s *priv); * Private Data ****************************************************************************/ +static const struct i2c_ops_s g_i2cops = +{ + .transfer = sam_i2c_transfer, +#ifdef CONFIG_I2C_RESET + .reset = sam_i2c_reset, +#endif +}; + #ifdef SAMD2L2_HAVE_I2C0 static const struct i2c_attr_s g_i2c0attr = { @@ -270,7 +278,16 @@ static const struct i2c_attr_s g_i2c0attr = .base = SAM_SERCOM0_BASE, }; -static struct sam_i2c_dev_s g_i2c0; +static struct sam_i2c_dev_s g_i2c0 = +{ + .dev = + { + .ops = &g_i2cops, + }, + .attr = &g_i2c0attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef SAMD2L2_HAVE_I2C1 static const struct i2c_attr_s g_i2c1attr = @@ -287,7 +304,16 @@ static const struct i2c_attr_s g_i2c1attr = .base = SAM_SERCOM1_BASE, }; -static struct sam_i2c_dev_s g_i2c1; +static struct sam_i2c_dev_s g_i2c1 = +{ + .dev = + { + .ops = &g_i2cops, + }, + .attr = &g_i2c1attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef SAMD2L2_HAVE_I2C2 @@ -305,7 +331,16 @@ static const struct i2c_attr_s g_i2c2attr = .base = SAM_SERCOM2_BASE, }; -static struct sam_i2c_dev_s g_i2c2; +static struct sam_i2c_dev_s g_i2c2 = +{ + .dev = + { + .ops = &g_i2cops, + }, + .attr = &g_i2c2attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef SAMD2L2_HAVE_I2C3 @@ -323,7 +358,16 @@ static const struct i2c_attr_s g_i2c3attr = .base = SAM_SERCOM3_BASE, }; -static struct sam_i2c_dev_s g_i2c3; +static struct sam_i2c_dev_s g_i2c3 = +{ + .dev = + { + .ops = &g_i2cops, + }, + .attr = &g_i2c3attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef SAMD2L2_HAVE_I2C4 @@ -341,7 +385,16 @@ static const struct i2c_attr_s g_i2c4attr = .base = SAM_SERCOM4_BASE, }; -static struct sam_i2c_dev_s g_i2c4; +static struct sam_i2c_dev_s g_i2c4 = +{ + .dev = + { + .ops = &g_i2cops, + }, + .attr = &g_i2c4attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef SAMD2L2_HAVE_I2C5 @@ -359,16 +412,17 @@ static const struct i2c_attr_s g_i2c5attr = .base = SAM_SERCOM5_BASE, }; -static struct sam_i2c_dev_s g_i2c5; -#endif - -struct i2c_ops_s g_i2cops = +static struct sam_i2c_dev_s g_i2c5 = { - .transfer = sam_i2c_transfer, -#ifdef CONFIG_I2C_RESET - .reset = sam_i2c_reset, -#endif + .dev = + { + .ops = &g_i2cops, + }, + .attr = &g_i2c5attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), }; +#endif /**************************************************************************** * Private Functions @@ -1253,13 +1307,9 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) #ifdef SAMD2L2_HAVE_I2C0 if (bus == 0) { - /* Select up I2C0 and setup invariant attributes */ + /* Select up I2C0 and the (initial) I2C frequency */ priv = &g_i2c0; - priv->attr = &g_i2c0attr; - - /* Select the (initial) I2C frequency */ - frequency = CONFIG_SAM_I2C0_FREQUENCY; } else @@ -1267,13 +1317,9 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) #ifdef SAMD2L2_HAVE_I2C1 if (bus == 1) { - /* Select up I2C1 and setup invariant attributes */ + /* Select up I2C1 and the (initial) I2C frequency */ priv = &g_i2c1; - priv->attr = &g_i2c1attr; - - /* Select the (initial) I2C frequency */ - frequency = CONFIG_SAM_I2C1_FREQUENCY; } else @@ -1281,13 +1327,9 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) #ifdef SAMD2L2_HAVE_I2C2 if (bus == 2) { - /* Select up I2C2 and setup invariant attributes */ + /* Select up I2C2 and the (initial) I2C frequency */ priv = &g_i2c2; - priv->attr = &g_i2c2attr; - - /* Select the (initial) I2C frequency */ - frequency = CONFIG_SAM_I2C2_FREQUENCY; } else @@ -1295,13 +1337,9 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) #ifdef SAMD2L2_HAVE_I2C3 if (bus == 3) { - /* Select up I2C3 and setup invariant attributes */ + /* Select up I2C3 and the (initial) I2C frequency */ priv = &g_i2c3; - priv->attr = &g_i2c3attr; - - /* Select the (initial) I2C frequency */ - frequency = CONFIG_SAM_I2C3_FREQUENCY; } else @@ -1309,13 +1347,9 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) #ifdef SAMD2L2_HAVE_I2C4 if (bus == 4) { - /* Select up I2C4 and setup invariant attributes */ + /* Select up I2C4 and the (initial) I2C frequency */ priv = &g_i2c4; - priv->attr = &g_i2c4attr; - - /* Select the (initial) I2C frequency */ - frequency = CONFIG_SAM_I2C4_FREQUENCY; } else @@ -1323,13 +1357,9 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) #ifdef SAMD2L2_HAVE_I2C5 if (bus == 5) { - /* Select up I2C5 and setup invariant attributes */ + /* Select up I2C5 and the (initial) I2C frequency */ priv = &g_i2c5; - priv->attr = &g_i2c5attr; - - /* Select the (initial) I2C frequency */ - frequency = CONFIG_SAM_I2C5_FREQUENCY; } else @@ -1353,14 +1383,6 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) return NULL; } - /* Initialize the I2C driver structure */ - - priv->dev.ops = &g_i2cops; - priv->flags = 0; - - nxmutex_init(&priv->lock); - nxsem_init(&priv->waitsem, 0, 0); - /* Perform repeatable I2C hardware initialization */ i2c_hw_initialize(priv, frequency); @@ -1386,11 +1408,6 @@ int sam_i2c_uninitialize(struct i2c_master_s *dev) up_disable_irq(priv->attr->irq); - /* Reset data structures */ - - nxmutex_destroy(&priv->lock); - nxsem_destroy(&priv->waitsem); - /* Detach Interrupt Handler */ irq_detach(priv->attr->irq); diff --git a/arch/arm/src/samd2l2/sam_spi.c b/arch/arm/src/samd2l2/sam_spi.c index 5e8f604cfa..4eac237cfa 100644 --- a/arch/arm/src/samd2l2/sam_spi.c +++ b/arch/arm/src/samd2l2/sam_spi.c @@ -242,6 +242,7 @@ static struct sam_spidev_s g_spi0dev = #ifdef CONFIG_SAMD2L2_SPI_DMA .dma_tx_trig = DMAC_TRIGSRC_SERCOM0_TX, .dma_rx_trig = DMAC_TRIGSRC_SERCOM0_RX, + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -292,6 +293,7 @@ static struct sam_spidev_s g_spi1dev = #ifdef CONFIG_SAMD2L2_SPI_DMA .dma_tx_trig = DMAC_TRIGSRC_SERCOM1_TX, .dma_rx_trig = DMAC_TRIGSRC_SERCOM1_RX, + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -342,6 +344,7 @@ static struct sam_spidev_s g_spi2dev = #ifdef CONFIG_SAMD2L2_SPI_DMA .dma_tx_trig = DMAC_TRIGSRC_SERCOM2_TX, .dma_rx_trig = DMAC_TRIGSRC_SERCOM2_RX, + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -392,6 +395,7 @@ static struct sam_spidev_s g_spi3dev = #ifdef CONFIG_SAMD2L2_SPI_DMA .dma_tx_trig = DMAC_TRIGSRC_SERCOM3_TX, .dma_rx_trig = DMAC_TRIGSRC_SERCOM3_RX, + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -442,6 +446,7 @@ static struct sam_spidev_s g_spi4dev = #ifdef CONFIG_SAMD2L2_SPI_DMA .dma_tx_trig = DMAC_TRIGSRC_SERCOM4_TX, .dma_rx_trig = DMAC_TRIGSRC_SERCOM4_RX, + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -492,6 +497,7 @@ static struct sam_spidev_s g_spi5dev = #ifdef CONFIG_SAMD2L2_SPI_DMA .dma_tx_trig = DMAC_TRIGSRC_SERCOM5_TX, .dma_rx_trig = DMAC_TRIGSRC_SERCOM5_RX, + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -1430,10 +1436,6 @@ static void spi_dma_setup(struct sam_spidev_s *priv) priv->dma_tx = sam_dmachannel(DMACH_FLAG_BEATSIZE_BYTE | DMACH_FLAG_MEM_INCREMENT | DMACH_FLAG_PERIPH_TXTRIG(priv->dma_tx_trig)); - - /* Initialize the semaphore used to notify when DMA is complete */ - - nxsem_init(&priv->dmasem, 0, 0); } #endif diff --git a/arch/arm/src/samd5e5/sam_dmac.c b/arch/arm/src/samd5e5/sam_dmac.c index a8ff9854e1..10433fa71c 100644 --- a/arch/arm/src/samd5e5/sam_dmac.c +++ b/arch/arm/src/samd5e5/sam_dmac.c @@ -125,9 +125,9 @@ static int sam_rxbuffer(struct sam_dmach_s *dmach, uint32_t paddr, /* These mutex protect the DMA channel and descriptor tables */ -static mutex_t g_chlock; +static mutex_t g_chlock = NXMUTEX_INITIALIZER; #if CONFIG_SAMD5E5_DMAC_NDESC > 0 -static sem_t g_dsem; +static sem_t g_dsem = SEM_INITIALIZER(CONFIG_SAMD5E5_DMAC_NDESC); #endif /* This array describes the state of each DMA channel */ @@ -724,13 +724,6 @@ void weak_function arm_dma_initialize(void) dmainfo("Initialize DMAC\n"); int i; - /* Initialize global mutex & semaphore */ - - nxmutex_init(&g_chlock); -#if CONFIG_SAMD5E5_DMAC_NDESC > 0 - nxsem_init(&g_dsem, 0, CONFIG_SAMD5E5_DMAC_NDESC); -#endif - /* Initialized the DMA channel table */ for (i = 0; i < SAMD5E5_NDMACHAN; i++) diff --git a/arch/arm/src/samd5e5/sam_i2c_master.c b/arch/arm/src/samd5e5/sam_i2c_master.c index 7920af236c..1e14554af2 100644 --- a/arch/arm/src/samd5e5/sam_i2c_master.c +++ b/arch/arm/src/samd5e5/sam_i2c_master.c @@ -243,6 +243,14 @@ static void i2c_pad_configure(struct sam_i2c_dev_s *priv); * Private Data ****************************************************************************/ +static static struct i2c_ops_s g_i2cops = +{ + .transfer = sam_i2c_transfer, +#ifdef CONFIG_I2C_RESET + .reset = sam_i2c_reset, +#endif +}; + #ifdef SAMD5E5_HAVE_I2C0_MASTER static const struct i2c_attr_s g_i2c0attr = { @@ -258,7 +266,16 @@ static const struct i2c_attr_s g_i2c0attr = .base = SAM_SERCOM0_BASE, }; -static struct sam_i2c_dev_s g_i2c0; +static struct sam_i2c_dev_s g_i2c0 = +{ + .dev = + { + .ops = &g_i2cops, + }, + .attr = &g_i2c0attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef SAMD5E5_HAVE_I2C1_MASTER @@ -276,7 +293,16 @@ static const struct i2c_attr_s g_i2c1attr = .base = SAM_SERCOM1_BASE, }; -static struct sam_i2c_dev_s g_i2c1; +static struct sam_i2c_dev_s g_i2c1 = +{ + .dev = + { + .ops = &g_i2cops, + }, + .attr = &g_i2c1attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef SAMD5E5_HAVE_I2C2_MASTER @@ -294,7 +320,16 @@ static const struct i2c_attr_s g_i2c2attr = .base = SAM_SERCOM2_BASE, }; -static struct sam_i2c_dev_s g_i2c2; +static struct sam_i2c_dev_s g_i2c2 = +{ + .dev = + { + .ops = &g_i2cops, + }, + .attr = &g_i2c2attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef SAMD5E5_HAVE_I2C3_MASTER @@ -312,7 +347,16 @@ static const struct i2c_attr_s g_i2c3attr = .base = SAM_SERCOM3_BASE, }; -static struct sam_i2c_dev_s g_i2c3; +static struct sam_i2c_dev_s g_i2c3 = +{ + .dev = + { + .ops = &g_i2cops, + }, + .attr = &g_i2c3attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef SAMD5E5_HAVE_I2C4_MASTER @@ -330,7 +374,16 @@ static const struct i2c_attr_s g_i2c4attr = .base = SAM_SERCOM4_BASE, }; -static struct sam_i2c_dev_s g_i2c4; +static struct sam_i2c_dev_s g_i2c4 = +{ + .dev = + { + .ops = &g_i2cops, + }, + .attr = &g_i2c4attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef SAMD5E5_HAVE_I2C5_MASTER @@ -348,7 +401,16 @@ static const struct i2c_attr_s g_i2c5attr = .base = SAM_SERCOM5_BASE, }; -static struct sam_i2c_dev_s g_i2c5; +static struct sam_i2c_dev_s g_i2c5 = +{ + .dev = + { + .ops = &g_i2cops, + }, + .attr = &g_i2c5attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef SAMD5E5_HAVE_I2C6_MASTER @@ -366,7 +428,16 @@ static const struct i2c_attr_s g_i2c6attr = .base = SAM_SERCOM6_BASE, }; -static struct sam_i2c_dev_s g_i2c6; +static struct sam_i2c_dev_s g_i2c6 = +{ + .dev = + { + .ops = &g_i2cops, + }, + .attr = &g_i2c6attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; #endif #ifdef SAMD5E5_HAVE_I2C7_MASTER @@ -384,16 +455,17 @@ static const struct i2c_attr_s g_i2c7attr = .base = SAM_SERCOM7_BASE, }; -static struct sam_i2c_dev_s g_i2c7; -#endif - -struct i2c_ops_s g_i2cops = +static struct sam_i2c_dev_s g_i2c7 = { - .transfer = sam_i2c_transfer, -#ifdef CONFIG_I2C_RESET - .reset = sam_i2c_reset, -#endif + .dev = + { + .ops = &g_i2cops, + }, + .attr = &g_i2c7attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), }; +#endif /**************************************************************************** * Low-level Helpers @@ -1275,13 +1347,9 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) #ifdef SAMD5E5_HAVE_I2C0_MASTER if (bus == 0) { - /* Select up I2C0 and setup invariant attributes */ + /* Select up I2C0 and the (initial) I2C frequency */ priv = &g_i2c0; - priv->attr = &g_i2c0attr; - - /* Select the (initial) I2C frequency */ - frequency = CONFIG_SAM_I2C0_FREQUENCY; } else @@ -1289,13 +1357,9 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) #ifdef SAMD5E5_HAVE_I2C1_MASTER if (bus == 1) { - /* Select up I2C1 and setup invariant attributes */ + /* Select up I2C1 and the (initial) I2C frequency */ priv = &g_i2c1; - priv->attr = &g_i2c1attr; - - /* Select the (initial) I2C frequency */ - frequency = CONFIG_SAM_I2C1_FREQUENCY; } else @@ -1303,13 +1367,9 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) #ifdef SAMD5E5_HAVE_I2C2_MASTER if (bus == 2) { - /* Select up I2C2 and setup invariant attributes */ + /* Select up I2C2 and the (initial) I2C frequency */ priv = &g_i2c2; - priv->attr = &g_i2c2attr; - - /* Select the (initial) I2C frequency */ - frequency = CONFIG_SAM_I2C2_FREQUENCY; } else @@ -1317,13 +1377,9 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) #ifdef SAMD5E5_HAVE_I2C3_MASTER if (bus == 3) { - /* Select up I2C3 and setup invariant attributes */ + /* Select up I2C3 and the (initial) I2C frequency */ priv = &g_i2c3; - priv->attr = &g_i2c3attr; - - /* Select the (initial) I2C frequency */ - frequency = CONFIG_SAM_I2C3_FREQUENCY; } else @@ -1331,13 +1387,9 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) #ifdef SAMD5E5_HAVE_I2C4_MASTER if (bus == 4) { - /* Select up I2C4 and setup invariant attributes */ + /* Select up I2C4 and the (initial) I2C frequency */ priv = &g_i2c4; - priv->attr = &g_i2c4attr; - - /* Select the (initial) I2C frequency */ - frequency = CONFIG_SAM_I2C4_FREQUENCY; } else @@ -1345,13 +1397,9 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) #ifdef SAMD5E5_HAVE_I2C5_MASTER if (bus == 5) { - /* Select up I2C5 and setup invariant attributes */ + /* Select up I2C5 and the (initial) I2C frequency */ priv = &g_i2c5; - priv->attr = &g_i2c5attr; - - /* Select the (initial) I2C frequency */ - frequency = CONFIG_SAM_I2C5_FREQUENCY; } else @@ -1359,13 +1407,9 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) #ifdef SAMD5E5_HAVE_I2C6_MASTER if (bus == 6) { - /* Select up I2C6 and setup invariant attributes */ + /* Select up I2C6 and the (initial) I2C frequency */ priv = &g_i2c6; - priv->attr = &g_i2c6attr; - - /* Select the (initial) I2C frequency */ - frequency = CONFIG_SAM_I2C6_FREQUENCY; } else @@ -1373,13 +1417,9 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) #ifdef SAMD5E5_HAVE_I2C7_MASTER if (bus == 7) { - /* Select up I2C7 and setup invariant attributes */ + /* Select up I2C7 and the (initial) I2C frequency */ priv = &g_i2c7; - priv->attr = &g_i2c7attr; - - /* Select the (initial) I2C frequency */ - frequency = CONFIG_SAM_I2C7_FREQUENCY; } else @@ -1411,14 +1451,6 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) return NULL; } - /* Initialize the I2C driver structure */ - - priv->dev.ops = &g_i2cops; - priv->flags = 0; - - nxmutex_init(&priv->lock); - nxsem_init(&priv->waitsem, 0, 0); - /* Perform repeatable I2C hardware initialization */ i2c_hw_initialize(priv, frequency); @@ -1445,11 +1477,6 @@ int sam_i2c_uninitialize(struct i2c_master_s *dev) up_disable_irq(priv->attr->irq); up_disable_irq(priv->attr->irq + 1); - /* Reset data structures */ - - nxmutex_destroy(&priv->lock); - nxsem_destroy(&priv->waitsem); - /* Detach Interrupt Handler */ irq_detach(priv->attr->irq); diff --git a/arch/arm/src/samd5e5/sam_progmem.c b/arch/arm/src/samd5e5/sam_progmem.c index dd280b959d..ea3b384abe 100644 --- a/arch/arm/src/samd5e5/sam_progmem.c +++ b/arch/arm/src/samd5e5/sam_progmem.c @@ -155,7 +155,7 @@ ****************************************************************************/ static uint32_t g_page_buffer[SAMD5E5_PAGE_WORDS]; -static mutex_t g_page_lock; +static mutex_t g_page_lock = NXMUTEX_INITIALIZER; /**************************************************************************** * Private Functions @@ -350,12 +350,6 @@ void sam_progmem_initialize(void) NVMCTRL_CTRLA_WMODE_MAN | NVMCTRL_CTRLA_AUTOWS; putreg16(ctrla, SAM_NVMCTRL_CTRLA); - - /* Initialize the mutex that manages exclusive access to the global - * page buffer. - */ - - nxmutex_init(&g_page_lock); } /**************************************************************************** diff --git a/arch/arm/src/samd5e5/sam_spi.c b/arch/arm/src/samd5e5/sam_spi.c index 902559aacc..72772a4092 100644 --- a/arch/arm/src/samd5e5/sam_spi.c +++ b/arch/arm/src/samd5e5/sam_spi.c @@ -236,6 +236,7 @@ static struct sam_spidev_s g_spi0dev = #ifdef CONFIG_SAMD5E5SPI_DMA .dma_tx_trig = DMAC_TRIGSRC_SERCOM0_TX, .dma_rx_trig = DMAC_TRIGSRC_SERCOM0_RX, + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -286,6 +287,7 @@ static struct sam_spidev_s g_spi1dev = #ifdef CONFIG_SAMD5E5SPI_DMA .dma_tx_trig = DMAC_TRIGSRC_SERCOM1_TX, .dma_rx_trig = DMAC_TRIGSRC_SERCOM1_RX, + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -336,6 +338,7 @@ static struct sam_spidev_s g_spi2dev = #ifdef CONFIG_SAMD5E5SPI_DMA .dma_tx_trig = DMAC_TRIGSRC_SERCOM2_TX, .dma_rx_trig = DMAC_TRIGSRC_SERCOM2_RX, + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -386,6 +389,7 @@ static struct sam_spidev_s g_spi3dev = #ifdef CONFIG_SAMD5E5SPI_DMA .dma_tx_trig = DMAC_TRIGSRC_SERCOM3_TX, .dma_rx_trig = DMAC_TRIGSRC_SERCOM3_RX, + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -436,6 +440,7 @@ static struct sam_spidev_s g_spi4dev = #ifdef CONFIG_SAMD5E5SPI_DMA .dma_tx_trig = DMAC_TRIGSRC_SERCOM4_TX, .dma_rx_trig = DMAC_TRIGSRC_SERCOM4_RX, + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -486,6 +491,7 @@ static struct sam_spidev_s g_spi5dev = #ifdef CONFIG_SAMD5E5SPI_DMA .dma_tx_trig = DMAC_TRIGSRC_SERCOM5_TX, .dma_rx_trig = DMAC_TRIGSRC_SERCOM5_RX, + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -536,6 +542,7 @@ static struct sam_spidev_s g_spi6dev = #ifdef CONFIG_SAMD5E5SPI_DMA .dma_tx_trig = DMAC_TRIGSRC_SERCOM6_TX, .dma_rx_trig = DMAC_TRIGSRC_SERCOM6_RX, + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -586,6 +593,7 @@ static struct sam_spidev_s g_spi7dev = #ifdef CONFIG_SAMD5E5SPI_DMA .dma_tx_trig = DMAC_TRIGSRC_SERCOM7_TX, .dma_rx_trig = DMAC_TRIGSRC_SERCOM7_RX, + .dmasem = SEM_INITIALIZER(0), #endif }; #endif @@ -1519,10 +1527,6 @@ static void spi_dma_setup(struct sam_spidev_s *priv) priv->dma_tx = sam_dmachannel(DMACH_FLAG_BEATSIZE_BYTE | DMACH_FLAG_MEM_INCREMENT | DMACH_FLAG_PERIPH_TXTRIG(priv->dma_tx_trig)); - - /* Initialize the semaphore used to notify when DMA is complete */ - - nxsem_init(&priv->dmasem, 0, 0); } #endif diff --git a/arch/arm/src/samd5e5/sam_tc.c b/arch/arm/src/samd5e5/sam_tc.c index 4a9f6881ad..1fbaac1a20 100644 --- a/arch/arm/src/samd5e5/sam_tc.c +++ b/arch/arm/src/samd5e5/sam_tc.c @@ -85,8 +85,9 @@ static const struct tc_attr_s g_tc0attr = }; static struct sam_tc_dev_s g_tc0 = { - .initialized = false, - .inuse = false, + .attr = &g_tc0attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), }; #endif @@ -103,8 +104,9 @@ static const struct tc_attr_s g_tc1attr = }; static struct sam_tc_dev_s g_tc1 = { - .initialized = false, - .inuse = false, + .attr = &g_tc0attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), }; #endif @@ -121,8 +123,9 @@ static const struct tc_attr_s g_tc2attr = }; static struct sam_tc_dev_s g_tc2 = { - .initialized = false, - .inuse = false, + .attr = &g_tc0attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), }; #endif @@ -139,8 +142,9 @@ static const struct tc_attr_s g_tc3attr = }; static struct sam_tc_dev_s g_tc3 = { - .initialized = false, - .inuse = false, + .attr = &g_tc0attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), }; #endif @@ -157,8 +161,9 @@ static const struct tc_attr_s g_tc4attr = }; static struct sam_tc_dev_s g_tc4 = { - .initialized = false, - .inuse = false, + .attr = &g_tc0attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), }; #endif @@ -175,8 +180,9 @@ static const struct tc_attr_s g_tc5attr = }; static struct sam_tc_dev_s g_tc5 = { - .initialized = false, - .inuse = false, + .attr = &g_tc0attr, + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), }; #endif @@ -481,60 +487,54 @@ static inline struct sam_tc_dev_s *sam_tc_initialize(int tc) #ifdef CONFIG_SAMD5E5_TC0 if (tc == 0) { - /* Select up TC0 and setup invariant attributes */ + /* Select up TC0 */ priv = &g_tc0; - priv->attr = &g_tc0attr; } else #endif #ifdef CONFIG_SAMD5E5_TC1 if (tc == 1) { - /* Select up TC1 and setup invariant attributes */ + /* Select up TC1 */ priv = &g_tc1; - priv->attr = &g_tc1attr; } else #endif #ifdef CONFIG_SAMD5E5_TC2 if (tc == 2) { - /* Select up TC2 and setup invariant attributes */ + /* Select up TC2 */ priv = &g_tc2; - priv->attr = &g_tc2attr; } else #endif #ifdef CONFIG_SAMD5E5_TC3 if (tc == 3) { - /* Select up TC3 and setup invariant attributes */ + /* Select up TC3 */ priv = &g_tc3; - priv->attr = &g_tc3attr; } else #endif #ifdef CONFIG_SAMD5E5_TC4 if (tc == 4) { - /* Select up TC4 and setup invariant attributes */ + /* Select up TC4 */ priv = &g_tc4; - priv->attr = &g_tc4attr; } else #endif #ifdef CONFIG_SAMD5E5_TC5 if (tc == 5) { - /* Select up TC5 and setup invariant attributes */ + /* Select up TC5 */ priv = &g_tc5; - priv->attr = &g_tc5attr; } else #endif @@ -617,11 +617,6 @@ TC_HANDLE sam_tc_allocate(int tc, int frequency) tmrinfo("TC%d attached irq %d\n", tc, priv->attr->irq); - /* Initialize the TC driver structure */ - - priv->flags = 0; - nxmutex_init(&priv->lock); - /* Enable clocking to the TC module in PCHCTRL */ tc_bridge_enable(priv->attr->tc); diff --git a/arch/arm/src/samd5e5/sam_usb.c b/arch/arm/src/samd5e5/sam_usb.c index 447cfaff13..6408a411b3 100644 --- a/arch/arm/src/samd5e5/sam_usb.c +++ b/arch/arm/src/samd5e5/sam_usb.c @@ -1002,7 +1002,11 @@ static void sam_add_sof_user(struct sam_usbhost_s *priv); * instance. */ -static struct sam_usbhost_s g_usbhost; +static struct sam_usbhost_s g_usbhost = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), +}; /* This is the connection/enumeration interface */ @@ -8449,13 +8453,6 @@ static inline void sam_sw_initialize(struct sam_usbhost_s *priv) struct usbhost_hubport_s *hport; int epno; - /* Initialize the device state structure. NOTE: many fields - * have the initial value of zero and, hence, are not explicitly - * initialized here. - */ - - memset(priv, 0, sizeof(struct sam_usbhost_s)); - /* Initialize the device operations */ drvr = &priv->drvr; @@ -8510,17 +8507,6 @@ static inline void sam_sw_initialize(struct sam_usbhost_s *priv) sam_reset_pipes(priv, false); - /* Initialize semaphore & mutex */ - - nxsem_init(&priv->pscsem, 0, 0); - nxmutex_init(&priv->lock); - - /* The pscsem semaphore is used for signaling and, hence, should not have - * priority inheritance enabled. - */ - - sem_setprotocol(&priv->pscsem, SEM_PRIO_NONE); - /* Initialize the driver state data */ priv->smstate = SMSTATE_DETACHED; diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c index c801d29032..6df4d27b9b 100644 --- a/arch/arm/src/samv7/sam_hsmci.c +++ b/arch/arm/src/samv7/sam_hsmci.c @@ -532,51 +532,53 @@ static void sam_callback(void *arg); * Private Data ****************************************************************************/ -/* Callbacks */ - -static const struct sdio_dev_s g_callbacks = -{ - .reset = sam_reset, - .capabilities = sam_capabilities, - .status = sam_status, - .widebus = sam_widebus, - .clock = sam_clock, - .attach = sam_attach, - .sendcmd = sam_sendcmd, - .blocksetup = sam_blocksetup, - .recvsetup = sam_recvsetup, - .sendsetup = sam_sendsetup, - .cancel = sam_cancel, - .waitresponse = sam_waitresponse, - .recv_r1 = sam_recvshort, - .recv_r2 = sam_recvlong, - .recv_r3 = sam_recvshort, - .recv_r4 = sam_recvnotimpl, - .recv_r5 = sam_recvnotimpl, - .recv_r6 = sam_recvshort, - .recv_r7 = sam_recvshort, - .waitenable = sam_waitenable, - .eventwait = sam_eventwait, - .callbackenable = sam_callbackenable, - .registercallback = sam_registercallback, -#ifdef CONFIG_SDIO_DMA -#ifndef HSCMI_NORXDMA - .dmarecvsetup = sam_dmarecvsetup, -#else - .dmarecvsetup = sam_recvsetup, -#endif -#ifndef HSCMI_NOTXDMA - .dmasendsetup = sam_dmasendsetup, -#else - .dmasendsetup = sam_sendsetup, -#endif -#endif -}; - /* Pre-allocate memory for each HSMCI device */ #ifdef CONFIG_SAMV7_HSMCI0 -static struct sam_dev_s g_hsmci0; +static struct sam_dev_s g_hsmci0 = +{ + .dev = + { + .reset = sam_reset, + .capabilities = sam_capabilities, + .status = sam_status, + .widebus = sam_widebus, + .clock = sam_clock, + .attach = sam_attach, + .sendcmd = sam_sendcmd, + .blocksetup = sam_blocksetup, + .recvsetup = sam_recvsetup, + .sendsetup = sam_sendsetup, + .cancel = sam_cancel, + .waitresponse = sam_waitresponse, + .recv_r1 = sam_recvshort, + .recv_r2 = sam_recvlong, + .recv_r3 = sam_recvshort, + .recv_r4 = sam_recvnotimpl, + .recv_r5 = sam_recvnotimpl, + .recv_r6 = sam_recvshort, + .recv_r7 = sam_recvshort, + .waitenable = sam_waitenable, + .eventwait = sam_eventwait, + .callbackenable = sam_callbackenable, + .registercallback = sam_registercallback, +#ifdef CONFIG_SDIO_DMA +#ifndef HSCMI_NORXDMA + .dmarecvsetup = sam_dmarecvsetup, +#else + .dmarecvsetup = sam_recvsetup, +#endif +#ifndef HSCMI_NOTXDMA + .dmasendsetup = sam_dmasendsetup, +#else + .dmasendsetup = sam_sendsetup, +#endif +#endif + }, + .waitsem = SEM_INITIALIZER(0), + .base = SAM_HSMCI0_BASE, + .hsmci = 0, +}; #endif /**************************************************************************** @@ -3270,11 +3272,6 @@ struct sdio_dev_s *sdio_initialize(int slotno) priv = &g_hsmci0; - /* HSMCI0 Initialization */ - - priv->base = SAM_HSMCI0_BASE; - priv->hsmci = 0; - /* Configure PIOs for 4-bit, wide-bus operation. NOTE: (1) the chip * is capable of 8-bit wide bus operation but D4-D7 are not configured, * (2) any card detection PIOs must be set up in board-specific logic. @@ -3309,16 +3306,6 @@ struct sdio_dev_s *sdio_initialize(int slotno) mcinfo("priv: %p base: %08" PRIx32 " hsmci: %d pid: %" PRId32 "\n", priv, priv->base, priv->hsmci, pid); - /* Initialize the HSMCI slot structure */ - - /* Initialize semaphores */ - - nxsem_init(&priv->waitsem, 0, 0); - - /* Initialize the callbacks */ - - memcpy(&priv->dev, &g_callbacks, sizeof(struct sdio_dev_s)); - /* Allocate a DMA channel */ priv->dma = sam_dmachannel(0, DMA_FLAGS(pid)); diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index 582924ce3b..7cbc94e337 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -1077,8 +1077,18 @@ static struct sam_config_s g_mcan0const = /* MCAN0 variable driver state */ -static struct sam_mcan_s g_mcan0priv; -static struct can_dev_s g_mcan0dev; +static struct sam_mcan_s g_mcan0priv = +{ + .config = &g_mcan1const, + .lock = NXMUTEX_INITIALIZER, + .txfsem = SEM_INITIALIZER(CONFIG_SAMV7_MCAN0_TXFIFOQ_SIZE), +}; + +static struct can_dev_s g_mcan0dev = +{ + .cd_ops = &g_mcanops, + .cd_priv = &g_mcan0priv, +}; #endif /* CONFIG_SAMV7_MCAN0 */ @@ -1164,8 +1174,18 @@ static struct sam_config_s g_mcan1const = /* MCAN0 variable driver state */ -static struct sam_mcan_s g_mcan1priv; -static struct can_dev_s g_mcan1dev; +static struct sam_mcan_s g_mcan1priv = +{ + .config = &g_mcan1const, + .lock = NXMUTEX_INITIALIZER, + .txfsem = SEM_INITIALIZER(CONFIG_SAMV7_MCAN0_TXFIFOQ_SIZE), +}; + +static struct can_dev_s g_mcan1dev = +{ + .cd_ops = &g_mcanops, + .cd_priv = &g_mcan1priv, +}; #endif /* CONFIG_SAMV7_MCAN1 */ @@ -2354,14 +2374,9 @@ static void mcan_reset(struct can_dev_s *dev) mcan_putreg(priv, SAM_MCAN_IE_OFFSET, 0); mcan_putreg(priv, SAM_MCAN_TXBTIE_OFFSET, 0); - /* Make sure that all buffers are released. - * - * REVISIT: What if a thread is waiting for a buffer? The following - * will not wake up any waiting threads. - */ + /* Make sure that all buffers are released. */ - nxsem_destroy(&priv->txfsem); - nxsem_init(&priv->txfsem, 0, config->ntxfifoq); + nxsem_reset(&priv->txfsem, config->ntxfifoq); /* Disable peripheral clocking to the MCAN controller */ @@ -4213,9 +4228,7 @@ static int mcan_hw_initialize(struct sam_mcan_s *priv) struct can_dev_s *sam_mcan_initialize(int port) { - struct can_dev_s *dev; struct sam_mcan_s *priv; - const struct sam_config_s *config; uint32_t regval; caninfo("MCAN%d\n", port); @@ -4239,9 +4252,7 @@ struct can_dev_s *sam_mcan_initialize(int port) { /* Select the MCAN0 device structure */ - dev = &g_mcan0dev; - priv = &g_mcan0priv; - config = &g_mcan0const; + priv = &g_mcan0priv; /* Configure MCAN0 Message RAM Base Address */ @@ -4258,9 +4269,7 @@ struct can_dev_s *sam_mcan_initialize(int port) { /* Select the MCAN1 device structure */ - dev = &g_mcan1dev; - priv = &g_mcan1priv; - config = &g_mcan1const; + priv = &g_mcan1priv; /* Configure MCAN1 Message RAM Base Address */ @@ -4283,10 +4292,7 @@ struct can_dev_s *sam_mcan_initialize(int port) { /* Yes, then perform one time data initialization */ - memset(priv, 0, sizeof(struct sam_mcan_s)); - priv->config = config; - - /* Get the revision of the chip (A or B ) */ + /* Get the revision of the chip (A or B) */ regval = getreg32(SAM_CHIPID_CIDR); priv->rev = regval & CHIPID_CIDR_VERSION_MASK; @@ -4299,15 +4305,15 @@ struct can_dev_s *sam_mcan_initialize(int port) { /* Revision A */ - priv->btp = config->btp; - priv->fbtp = config->fbtp; + priv->btp = priv->config->btp; + priv->fbtp = priv->config->fbtp; } else if (priv->rev == 1) { /* Revision B */ - priv->btp = config->nbtp; - priv->fbtp = config->dbtp; + priv->btp = priv->config->nbtp; + priv->fbtp = priv->config->dbtp; } else { @@ -4315,14 +4321,6 @@ struct can_dev_s *sam_mcan_initialize(int port) return NULL; } - /* Initialize mutex & semaphores */ - - nxmutex_init(&priv->lock); - nxsem_init(&priv->txfsem, 0, config->ntxfifoq); - - dev->cd_ops = &g_mcanops; - dev->cd_priv = (void *)priv; - /* And put the hardware in the initial state */ mcan_reset(dev); diff --git a/arch/arm/src/samv7/sam_progmem.c b/arch/arm/src/samv7/sam_progmem.c index 7575c75078..4e85806bc0 100644 --- a/arch/arm/src/samv7/sam_progmem.c +++ b/arch/arm/src/samv7/sam_progmem.c @@ -153,7 +153,7 @@ ****************************************************************************/ static uint32_t g_page_buffer[SAMV7_PAGE_WORDS]; -static mutex_t g_page_lock; +static mutex_t g_page_lock = NXMUTEX_INITIALIZER; /**************************************************************************** * Private Functions @@ -190,12 +190,6 @@ void sam_progmem_initialize(void) regval = getreg32(SAM_EEFC_FMR); regval &= ~EEFC_FMR_FRDY; sam_eefc_writefmr(regval); - - /* Initialize the mutex that manages exclusive access to the global - * page buffer. - */ - - nxmutex_init(&g_page_lock); } /**************************************************************************** diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index b9d8a96ef3..e8d1f45f68 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -314,10 +314,12 @@ static struct sam_qspidev_s g_qspi0dev = #ifdef QSPI_USE_INTERRUPTS .irq = SAM_IRQ_QSPI, #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_SAMV7_QSPI_DMA .candma = SAMV7_QSPI0_DMA, .rxintf = XDMACH_QSPI_RX, .txintf = XDMACH_QSPI_TX, + .dmawait = SEM_INITIALIZER(0), #endif }; #endif /* CONFIG_SAMV7_QSPI */ @@ -1756,12 +1758,6 @@ struct qspi_dev_s *sam_qspi_initialize(int intf) { /* No perform one time initialization */ - /* Initialize the QSPI mutex that enforces mutually exclusive - * access to the QSPI registers. - */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_SAMV7_QSPI_DMA /* Pre-allocate DMA channels. */ @@ -1774,8 +1770,6 @@ struct qspi_dev_s *sam_qspi_initialize(int intf) priv->candma = false; } } - - nxsem_init(&priv->dmawait, 0, 0); #endif #ifdef QSPI_USE_INTERRUPTS @@ -1785,7 +1779,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf) if (ret < 0) { spierr("ERROR: Failed to attach irq %d\n", priv->irq); - goto errout_with_dmawait; + goto errout_with_dmach; } #endif @@ -1814,10 +1808,9 @@ errout_with_irq: #ifdef QSPI_USE_INTERRUPTS irq_detach(priv->irq); -errout_with_dmawait: +errout_with_dmach: #endif #ifdef CONFIG_SAMV7_QSPI_DMA - nxsem_destroy(&priv->dmawait); if (priv->dmach) { sam_dmafree(priv->dmach); @@ -1825,7 +1818,6 @@ errout_with_dmawait: } #endif - nxmutex_destroy(&priv->lock); return NULL; } #endif /* CONFIG_SAMV7_QSPI */ diff --git a/arch/arm/src/samv7/sam_qspi_spi.c b/arch/arm/src/samv7/sam_qspi_spi.c index dc6086ffab..fcc6d4f356 100644 --- a/arch/arm/src/samv7/sam_qspi_spi.c +++ b/arch/arm/src/samv7/sam_qspi_spi.c @@ -154,6 +154,7 @@ static const struct spi_ops_s g_spiops = static struct sam_spidev_s g_spidev = { .base = SAM_QSPI_BASE, + .spilock = NXMUTEX_INITIALIZER, .select = sam_qspi_select, }; @@ -832,12 +833,6 @@ struct spi_dev_s *sam_qspi_spi_initialize(int intf) qspi_getreg(spi, SAM_QSPI_SR_OFFSET); qspi_getreg(spi, SAM_QSPI_RDR_OFFSET); - /* Initialize the SPI mutex that enforces mutually exclusive - * access to the SPI registers. - */ - - nxmutex_init(&spi->spilock); - spi->escape_lastxfer = false; spi->initialized = true; } diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index 98fa07ed2f..f70dff06fa 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -336,6 +336,7 @@ static const struct spi_ops_s g_spi0ops = static struct sam_spidev_s g_spi0dev = { .base = SAM_SPI0_BASE, + .spilock = NXMUTEX_INITIALIZER, .select = sam_spi0select, #ifdef CONFIG_SAMV7_SPI_DMA .pid = SAM_PID_SPI0, @@ -375,6 +376,7 @@ static const struct spi_ops_s g_spi1ops = static struct sam_spidev_s g_spi1dev = { .base = SAM_SPI1_BASE, + .spilock = NXMUTEX_INITIALIZER, .select = sam_spi1select, #ifdef CONFIG_SAMV7_SPI_DMA .pid = SAM_PID_SPI1, @@ -2156,12 +2158,6 @@ struct spi_dev_s *sam_spibus_initialize(int port) spi_getreg(spi, SAM_SPI_SR_OFFSET); spi_getreg(spi, SAM_SPI_RDR_OFFSET); - /* Initialize the SPI mutex that enforces mutually exclusive - * access to the SPI registers. - */ - - nxmutex_init(&spi->spilock); - spi->escape_lastxfer = false; spi->initialized = true; #ifdef CONFIG_SAMV7_SPI_DMA diff --git a/arch/arm/src/samv7/sam_spi_slave.c b/arch/arm/src/samv7/sam_spi_slave.c index c4647610bc..4ca7208ca0 100644 --- a/arch/arm/src/samv7/sam_spi_slave.c +++ b/arch/arm/src/samv7/sam_spi_slave.c @@ -180,13 +180,37 @@ static const struct spi_slave_ctrlrops_s g_ctrlr_ops = #ifdef CONFIG_SAMV7_SPI0_SLAVE /* This is the overall state of the SPI0 controller */ -static struct sam_spidev_s g_spi0_ctrlr; +static struct sam_spidev_s g_spi0_ctrlr = +{ + .ctrlr = + { + .ops = g_ctrlr_ops, + }, + .base = SAM_SPI0_BASE, + .spilock = NXMUTEX_INITIALIZER, + .irq = SAM_IRQ_SPI0, + .nbits = 8, + .spino = 0, + .nss = true, +}; #endif #ifdef CONFIG_SAMV7_SPI1_SLAVE /* This is the overall state of the SPI0 controller */ -static struct sam_spidev_s g_spi1_ctrlr; +static struct sam_spidev_s g_spi1_ctrlr = +{ + .ctrlr = + { + .ops = g_ctrlr_ops, + }, + .base = SAM_SPI1_BASE, + .spilock = NXMUTEX_INITIALIZER, + .irq = SAM_IRQ_SPI0, + .nbits = 8, + .spino = 1, + .nss = true, +}; #endif /**************************************************************************** @@ -1097,20 +1121,6 @@ struct spi_slave_ctrlr_s *sam_spi_slave_initialize(int port) priv = &g_spi1_ctrlr; #endif - /* Set up the initial state for this chip select structure. Other fields - * are zeroed. - */ - - memset(priv, 0, sizeof(struct sam_spidev_s)); - - /* Initialize the SPI operations */ - - priv->ctrlr.ops = &g_ctrlr_ops; - - /* Save the SPI controller number */ - - priv->spino = spino; - /* Has the SPI hardware been initialized? */ if (!priv->initialized) @@ -1123,11 +1133,6 @@ struct spi_slave_ctrlr_s *sam_spi_slave_initialize(int port) #endif #if defined(CONFIG_SAMV7_SPI0_SLAVE) { - /* Set the SPI0 register base address and interrupt information */ - - priv->base = SAM_SPI0_BASE, - priv->irq = SAM_IRQ_SPI0; - /* Enable peripheral clocking to SPI0 */ sam_spi0_enableclk(); @@ -1145,11 +1150,6 @@ struct spi_slave_ctrlr_s *sam_spi_slave_initialize(int port) #endif #if defined(CONFIG_SAMV7_SPI1_SLAVE) { - /* Set the SPI1 register base address and interrupt information */ - - priv->base = SAM_SPI1_BASE, - priv->irq = SAM_IRQ_SPI1; - /* Enable peripheral clocking to SPI1 */ sam_spi1_enableclk(); @@ -1187,12 +1187,6 @@ struct spi_slave_ctrlr_s *sam_spi_slave_initialize(int port) spi_getreg(priv, SAM_SPI_SR_OFFSET); spi_getreg(priv, SAM_SPI_RDR_OFFSET); - /* Initialize the SPI mutex that enforces mutually exclusive - * access to the SPI registers. - */ - - nxmutex_init(&priv->spilock); - priv->nss = true; priv->initialized = true; /* Disable all SPI interrupts at the SPI peripheral */ @@ -1214,7 +1208,6 @@ struct spi_slave_ctrlr_s *sam_spi_slave_initialize(int port) regval |= (SPI_CSR_NCPHA | SPI_CSR_BITS(8)); spi_putreg(priv, regval, SAM_SPI_CSR0_OFFSET); - priv->nbits = 8; spiinfo("csr[offset=%02x]=%08x\n", offset, regval); return &priv->ctrlr; diff --git a/arch/arm/src/samv7/sam_tc.c b/arch/arm/src/samv7/sam_tc.c index ca68a9b86a..ca06910078 100644 --- a/arch/arm/src/samv7/sam_tc.c +++ b/arch/arm/src/samv7/sam_tc.c @@ -102,9 +102,6 @@ struct sam_chconfig_s struct sam_tcconfig_s { - uintptr_t base; /* TC register base address */ - uint8_t tc; /* Timer/counter number */ - /* Channels */ struct sam_chconfig_s channel[SAM_TC_NCHANNELS]; @@ -198,8 +195,6 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel); #ifdef CONFIG_SAMV7_TC0 static const struct sam_tcconfig_s g_tc012config = { - .base = SAM_TC012_BASE, - .tc = 0, .channel = { [0] = @@ -275,8 +270,6 @@ static const struct sam_tcconfig_s g_tc012config = #ifdef CONFIG_SAMV7_TC1 static const struct sam_tcconfig_s g_tc345config = { - .base = SAM_TC345_BASE, - .tc = 1, .channel = { [0] = @@ -352,8 +345,6 @@ static const struct sam_tcconfig_s g_tc345config = #ifdef CONFIG_SAMV7_TC2 static const struct sam_tcconfig_s g_tc678config = { - .base = SAM_TC678_BASE, - .tc = 2, .channel = { [0] = @@ -429,8 +420,6 @@ static const struct sam_tcconfig_s g_tc678config = #ifdef CONFIG_SAMV7_TC3 static const struct sam_tcconfig_s g_tc901config = { - .base = SAM_TC901_BASE, - .tc = 3, .channel = { [0] = @@ -506,19 +495,39 @@ static const struct sam_tcconfig_s g_tc901config = /* Timer/counter state */ #ifdef CONFIG_SAMV7_TC0 -static struct sam_tc_s g_tc012; +static struct sam_tc_s g_tc012 = +{ + .lock = NXMUTEX_INITIALIZER, + .base = SAM_TC012_BASE, + .tc = 0, +}; #endif #ifdef CONFIG_SAMV7_TC1 -static struct sam_tc_s g_tc345; +static struct sam_tc_s g_tc345 = +{ + .lock = NXMUTEX_INITIALIZER, + .base = SAM_TC345_BASE, + .tc = 1, +}; #endif #ifdef CONFIG_SAMV7_TC2 -static struct sam_tc_s g_tc678; +static struct sam_tc_s g_tc678 = +{ + .lock = NXMUTEX_INITIALIZER, + .base = SAM_TC789_BASE, + .tc = 2, +}; #endif #ifdef CONFIG_SAMV7_TC3 -static struct sam_tc_s g_tc901; +static struct sam_tc_s g_tc901 = +{ + .lock = NXMUTEX_INITIALIZER, + .base = SAM_TC901_BASE, + .tc = 3, +}; #endif /* TC frequency data. This table provides the frequency for each @@ -1055,13 +1064,6 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) flags = enter_critical_section(); if (!tc->initialized) { - /* Initialize the timer counter data structure. */ - - memset(tc, 0, sizeof(struct sam_tc_s)); - nxmutex_init(&tc->lock); - tc->base = tcconfig->base; - tc->tc = tcconfig->tc; - /* Initialize the channels */ for (chndx = 0, ch = chfirst; chndx < SAM_TC_NCHANNELS; chndx++) diff --git a/arch/arm/src/samv7/sam_trng.c b/arch/arm/src/samv7/sam_trng.c index 69b11418d5..8a977aa597 100644 --- a/arch/arm/src/samv7/sam_trng.c +++ b/arch/arm/src/samv7/sam_trng.c @@ -74,7 +74,11 @@ struct trng_dev_s * Private Data ****************************************************************************/ -static struct trng_dev_s g_trngdev; +static struct trng_dev_s g_trngdev = +{ + .lock = NXMUTEX_INITIALIZER, + .waitsem = SEM_INITIALIZER(0), +}; static const struct file_operations g_trngops = { @@ -335,15 +339,6 @@ static int sam_rng_initialize(void) finfo("Initializing TRNG hardware\n"); - /* Initialize the device structure */ - - memset(&g_trngdev, 0, sizeof(struct trng_dev_s)); - - /* Initialize mutex & semaphores */ - - nxmutex_init(&g_trngdev.lock); - nxsem_init(&g_trngdev.waitsem, 0, 0); - /* Enable clocking to the TRNG */ sam_trng_enableclk(); diff --git a/arch/arm/src/samv7/sam_xdmac.c b/arch/arm/src/samv7/sam_xdmac.c index d55f3edf5f..d94177be5d 100644 --- a/arch/arm/src/samv7/sam_xdmac.c +++ b/arch/arm/src/samv7/sam_xdmac.c @@ -343,7 +343,11 @@ static struct sam_xdmach_s g_xdmach[SAMV7_NDMACHAN] = /* This describes the overall state of DMA controller */ -static struct sam_xdmac_s g_xdmac; +static struct sam_xdmac_s g_xdmac = +{ + .chlock = NXMUTEX_INITIALIZER, + .dsem = SEM_INITIALIZER(SAMV7_NDMACHAN), +}; /**************************************************************************** * Private Functions @@ -1561,11 +1565,6 @@ void sam_dmainitialize(struct sam_xdmac_s *xdmac) /* Disable all DMA channels */ sam_putdmac(xdmac, XDMAC_CHAN_ALL, SAM_XDMAC_GD_OFFSET); - - /* Initialize mutex & semaphores */ - - nxmutex_init(&xdmac->chlock); - nxsem_init(&xdmac->dsem, 0, SAMV7_NDMACHAN); } /**************************************************************************** diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index 62e39b205e..3bfdfbe116 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -697,7 +697,8 @@ static const struct stm32_adc_ops_s g_adc_llops = struct adccmn_data_s g_adc123_cmn = { - .refcount = 0 + .refcount = 0, + .lock = NXMUTEX_INITIALIZER, }; # elif defined(HAVE_IP_ADC_V2) @@ -711,7 +712,8 @@ struct adccmn_data_s g_adc123_cmn = struct adccmn_data_s g_adc12_cmn = { - .refcount = 0 + .refcount = 0, + .lock = NXMUTEX_INITIALIZER, }; # endif @@ -721,7 +723,8 @@ struct adccmn_data_s g_adc12_cmn = struct adccmn_data_s g_adc34_cmn = { - .refcount = 0 + .refcount = 0, + .lock = NXMUTEX_INITIALIZER, }; # endif @@ -4755,10 +4758,6 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, priv->adc_channels = ADC_CHANNELS_NUMBER; #endif -#ifdef ADC_HAVE_CB - priv->cb = NULL; -#endif - #ifdef CONFIG_STM32_ADC_LL_OPS /* Store reference to the upper-half ADC device */ @@ -4772,16 +4771,6 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, ainfo("intf: %d cr_channels: %d\n", intf, priv->cr_channels); #endif -#ifdef HAVE_ADC_CMN_DATA - /* Initialize the ADC common data semaphore. - * - * REVISIT: This will be done several times for each initialzied ADC in - * the ADC block. - */ - - nxmutex_init(&priv->cmn->lock); -#endif - return dev; } diff --git a/arch/arm/src/stm32/stm32_aes.c b/arch/arm/src/stm32/stm32_aes.c index b322ec928c..059cf88be2 100644 --- a/arch/arm/src/stm32/stm32_aes.c +++ b/arch/arm/src/stm32/stm32_aes.c @@ -68,7 +68,7 @@ static int stm32aes_setup_cr(int mode, int encrypt); * Private Data ****************************************************************************/ -static mutex_t g_stm32aes_lock; +static mutex_t g_stm32aes_lock = NXMUTEX_INITIALIZER; static bool g_stm32aes_initdone = false; /**************************************************************************** @@ -231,8 +231,6 @@ int stm32_aesinitialize(void) { uint32_t regval; - nxmutex_init(&g_stm32aes_lock); - regval = getreg32(STM32_RCC_AHBENR); regval |= RCC_AHBENR_AESEN; putreg32(regval, STM32_RCC_AHBENR); @@ -252,7 +250,6 @@ int stm32_aesuninitialize(void) regval &= ~RCC_AHBENR_AESEN; putreg32(regval, STM32_RCC_AHBENR); - nxmutex_destroy(&g_stm32aes_lock); return OK; } diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/stm32/stm32_dma2d.c index 53a9defed5..9055c1170e 100644 --- a/arch/arm/src/stm32/stm32_dma2d.c +++ b/arch/arm/src/stm32/stm32_dma2d.c @@ -250,11 +250,11 @@ static uint32_t g_clut[STM32_DMA2D_NCLUT * /* The DMA2D mutex that enforces mutually exclusive access */ -static mutex_t g_lock; +static mutex_t g_lock = NXMUTEX_INITIALIZER; /* Semaphore for interrupt handling */ -static sem_t g_semirq; +static sem_t g_semirq = SEM_INITIALIZER(0); /* This structure provides irq handling */ @@ -1095,13 +1095,6 @@ int stm32_dma2dinitialize(void) * arch/arm/src/stm32/stm32f40xxx_rcc.c */ - /* Initialize the DMA2D mutex that enforces mutually exclusive - * access to the driver - */ - - nxmutex_init(&g_lock); - nxsem_init(g_interrupt.sem, 0, 0); - #ifdef CONFIG_STM32_FB_CMAP /* Enable dma2d transfer and clut loading interrupts only */ diff --git a/arch/arm/src/stm32/stm32_dma_v1.c b/arch/arm/src/stm32/stm32_dma_v1.c index e28d7275e4..4aca2a4cd5 100644 --- a/arch/arm/src/stm32/stm32_dma_v1.c +++ b/arch/arm/src/stm32/stm32_dma_v1.c @@ -105,6 +105,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 0, .irq = STM32_IRQ_DMA1CH1, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, #endif /* DMA1_NCHANNELS > 0 */ @@ -112,6 +113,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 1, .irq = STM32_IRQ_DMA1CH2, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, #endif /* DMA1_NCHANNELS > 1 */ @@ -119,6 +121,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 2, .irq = STM32_IRQ_DMA1CH3, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, #endif /* DMA1_NCHANNELS > 2 */ @@ -126,6 +129,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 3, .irq = STM32_IRQ_DMA1CH4, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, #endif /* DMA1_NCHANNELS > 3 */ @@ -133,6 +137,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 4, .irq = STM32_IRQ_DMA1CH5, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, #endif /* DMA1_NCHANNELS > 4 */ @@ -140,6 +145,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 5, .irq = STM32_IRQ_DMA1CH6, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, #endif /* DMA1_NCHANNELS > 5 */ @@ -147,6 +153,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 6, .irq = STM32_IRQ_DMA1CH7, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, #endif /* DMA1_NCHANNELS > 6 */ @@ -154,6 +161,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 7, .irq = STM32_IRQ_DMA1CH8, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(7), }, #endif /* DMA1_NCHANNELS > 7 */ @@ -162,6 +170,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 0, .irq = STM32_IRQ_DMA2CH1, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, #endif /* DMA2_NCHANNELS > 0 */ @@ -169,6 +178,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 1, .irq = STM32_IRQ_DMA2CH2, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, #endif /* DMA2_NCHANNELS > 1 */ @@ -176,6 +186,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 2, .irq = STM32_IRQ_DMA2CH3, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, #endif /* DMA2_NCHANNELS > 2 */ @@ -189,6 +200,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = #else .irq = STM32_IRQ_DMA2CH45, #endif + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, #endif /* DMA2_NCHANNELS > 3 */ @@ -202,6 +214,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = #else .irq = STM32_IRQ_DMA2CH45, #endif + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, #endif /* DMA2_NCHANNELS > 4 */ @@ -209,6 +222,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 5, .irq = STM32_IRQ_DMA2CH5, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), }, #endif /* DMA2_NCHANNELS > 5 */ @@ -216,6 +230,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 6, .irq = STM32_IRQ_DMA2CH6, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), }, #endif /* DMA2_NCHANNELS > 6 */ @@ -223,6 +238,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 7, .irq = STM32_IRQ_DMA2CH7, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(7), }, #endif /* DMA2_NCHANNELS > 7 */ @@ -401,7 +417,6 @@ void weak_function arm_dma_initialize(void) for (chndx = 0; chndx < DMA_NCHANNELS; chndx++) { dmach = &g_dma[chndx]; - nxsem_init(&dmach->sem, 0, 1); /* Attach DMA interrupt vectors */ diff --git a/arch/arm/src/stm32/stm32_dma_v2.c b/arch/arm/src/stm32/stm32_dma_v2.c index f3d383f77e..638ca18f6e 100644 --- a/arch/arm/src/stm32/stm32_dma_v2.c +++ b/arch/arm/src/stm32/stm32_dma_v2.c @@ -92,48 +92,56 @@ static struct stm32_dma_s g_dma[DMA_NSTREAMS] = .stream = 0, .irq = STM32_IRQ_DMA1S0, .shift = DMA_INT_STREAM0_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(0), }, { .stream = 1, .irq = STM32_IRQ_DMA1S1, .shift = DMA_INT_STREAM1_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(1), }, { .stream = 2, .irq = STM32_IRQ_DMA1S2, .shift = DMA_INT_STREAM2_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(2), }, { .stream = 3, .irq = STM32_IRQ_DMA1S3, .shift = DMA_INT_STREAM3_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(3), }, { .stream = 4, .irq = STM32_IRQ_DMA1S4, .shift = DMA_INT_STREAM4_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(4), }, { .stream = 5, .irq = STM32_IRQ_DMA1S5, .shift = DMA_INT_STREAM5_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(5), }, { .stream = 6, .irq = STM32_IRQ_DMA1S6, .shift = DMA_INT_STREAM6_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(6), }, { .stream = 7, .irq = STM32_IRQ_DMA1S7, .shift = DMA_INT_STREAM7_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(7), }, #if STM32_NDMA > 1 @@ -141,47 +149,55 @@ static struct stm32_dma_s g_dma[DMA_NSTREAMS] = .stream = 0, .irq = STM32_IRQ_DMA2S0, .shift = DMA_INT_STREAM0_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(0), }, { .stream = 1, .irq = STM32_IRQ_DMA2S1, .shift = DMA_INT_STREAM1_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(1), }, { .stream = 2, .irq = STM32_IRQ_DMA2S2, .shift = DMA_INT_STREAM2_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(2), }, { .stream = 3, .irq = STM32_IRQ_DMA2S3, .shift = DMA_INT_STREAM3_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(3), }, { .stream = 4, .irq = STM32_IRQ_DMA2S4, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(4), }, { .stream = 5, .irq = STM32_IRQ_DMA2S5, .shift = DMA_INT_STREAM5_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(5), }, { .stream = 6, .irq = STM32_IRQ_DMA2S6, .shift = DMA_INT_STREAM6_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(6), }, { .stream = 7, .irq = STM32_IRQ_DMA2S7, .shift = DMA_INT_STREAM7_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(7), }, #endif @@ -438,7 +454,6 @@ void weak_function arm_dma_initialize(void) for (stream = 0; stream < DMA_NSTREAMS; stream++) { dmast = &g_dma[stream]; - nxsem_init(&dmast->sem, 0, 1); /* Attach DMA interrupt vectors */ diff --git a/arch/arm/src/stm32/stm32_foc.c b/arch/arm/src/stm32/stm32_foc.c index c202eef1ef..c26a9a3a02 100644 --- a/arch/arm/src/stm32/stm32_foc.c +++ b/arch/arm/src/stm32/stm32_foc.c @@ -816,7 +816,8 @@ static void stm32_foc_hw_config_get(struct foc_dev_s *dev); static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 = { - .cntr = 0 + .cntr = 0, + .lock = NXMUTEX_INITIALIZER, }; # endif /* CONFIG_STM32_HAVE_IP_ADC_V1 */ @@ -826,7 +827,8 @@ static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 = static struct stm32_foc_adccmn_s g_stm32_foc_adccmn12 = { - .cntr = 0 + .cntr = 0, + .lock = NXMUTEX_INITIALIZER, }; # endif /* CONFIG_STM32_HAVE_ADC1 || CONFIG_STM32_HAVE_ADC2 */ # if defined(CONFIG_STM32_HAVE_ADC3) || defined(CONFIG_STM32_HAVE_ADC4) @@ -834,7 +836,8 @@ static struct stm32_foc_adccmn_s g_stm32_foc_adccmn12 = static struct stm32_foc_adccmn_s g_stm32_foc_adccmn34 = { - .cntr = 0 + .cntr = 0, + .lock = NXMUTEX_INITIALIZER, }; # endif /* CONFIG_STM32_HAVE_ADC3 || CONFIG_STM32_HAVE_ADC4 */ # endif /* CONFIG_STM32_HAVE_IP_ADC_V2 */ @@ -2355,12 +2358,6 @@ stm32_foc_initialize(int inst, struct stm32_foc_board_s *board) modifyreg32(FOC_PWM_FZ_REG, 0, pwmfzbit); -#ifdef FOC_ADC_HAVE_CMN - /* Initialize ADC common data mutex */ - - nxmutex_init(&foc_priv->adc_cmn->lock); -#endif - /* Initialize calibration semaphore */ nxsem_init(&foc_priv->cal_done_sem, 0, 0); diff --git a/arch/arm/src/stm32/stm32_hciuart.c b/arch/arm/src/stm32/stm32_hciuart.c index bda132ac83..227782155b 100644 --- a/arch/arm/src/stm32/stm32_hciuart.c +++ b/arch/arm/src/stm32/stm32_hciuart.c @@ -358,7 +358,11 @@ static uint8_t g_usart1_rxdmabuffer[RXDMA_BUFFER_SIZE]; /* HCI USART1 variable state information */ -static struct hciuart_state_s g_hciusart1_state; +static struct hciuart_state_s g_hciusart1_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; /* HCI USART1 constant configuration information */ @@ -418,7 +422,11 @@ static uint8_t g_usart2_rxdmabuffer[RXDMA_BUFFER_SIZE]; /* HCI USART2 variable state information */ -static struct hciuart_state_s g_hciusart2_state; +static struct hciuart_state_s g_hciusart2_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; /* HCI USART2 constant configuration information */ @@ -474,7 +482,11 @@ static uint8_t g_usart3_rxdmabuffer[RXDMA_BUFFER_SIZE]; /* HCI USART3 variable state information */ -static struct hciuart_state_s g_hciusart3_state; +static struct hciuart_state_s g_hciusart3_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; /* HCI USART3 constant configuration information */ @@ -532,7 +544,11 @@ static uint8_t g_usart6_rxdmabuffer[RXDMA_BUFFER_SIZE]; /* HCI USART6 variable state information */ -static struct hciuart_state_s g_hciusart6_state; +static struct hciuart_state_s g_hciusart6_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; /* HCI USART6 constant configuration information */ @@ -588,7 +604,11 @@ static uint8_t g_uart7_rxdmabuffer[RXDMA_BUFFER_SIZE]; /* HCI UART7 variable state information */ -static struct hciuart_state_s g_hciuart7_state; +static struct hciuart_state_s g_hciuart7_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; /* HCI UART7 constant configuration information */ @@ -644,7 +664,11 @@ static uint8_t g_uart8_rxdmabuffer[RXDMA_BUFFER_SIZE]; /* HCI UART8 variable state information */ -static struct hciuart_state_s g_hciuart8_state; +static struct hciuart_state_s g_hciuart8_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; /* HCI UART8 constant configuration information */ @@ -2586,11 +2610,6 @@ void hciuart_initialize(void) hciuart_disableints(config, HCIUART_ALLINTS); - /* Initialize signalling semaphores */ - - nxsem_init(&state->rxwait, 0, 0); - nxsem_init(&state->txwait, 0, 0); - /* Attach and enable the HCI UART IRQ */ ret = irq_attach(config->irq, hciuart_interrupt, (void *)config); diff --git a/arch/arm/src/stm32/stm32_ltdc.c b/arch/arm/src/stm32/stm32_ltdc.c index 55686ee618..2dc5b39d64 100644 --- a/arch/arm/src/stm32/stm32_ltdc.c +++ b/arch/arm/src/stm32/stm32_ltdc.c @@ -808,11 +808,11 @@ static uint8_t g_transpclut[STM32_LTDC_NCLUT]; /* The LTDC mutex that enforces mutually exclusive access */ -static mutex_t g_lock; +static mutex_t g_lock = NXMUTEX_INITIALIZER; /* The semaphore for interrupt handling */ -static sem_t g_semirq; +static sem_t g_semirq = SEM_INITIALIZER(0); /* This structure provides irq handling */ @@ -1608,11 +1608,6 @@ static int stm32_ltdc_reload(uint8_t value, bool waitvblank) static void stm32_ltdc_irqconfig(void) { - /* Initialize the LTDC mutex that enforces mutually exclusive access */ - - nxmutex_init(&g_lock); - nxsem_init(g_interrupt.sem, 0, 0); - /* Attach LTDC interrupt vector */ irq_attach(g_interrupt.irq, stm32_ltdcirq, NULL); diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c index cdbec9f682..12e51bff72 100644 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ b/arch/arm/src/stm32/stm32_otgfshost.c @@ -474,7 +474,11 @@ static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv); * single global instance. */ -static struct stm32_usbhost_s g_usbhost; +static struct stm32_usbhost_s g_usbhost = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), +}; /* This is the connection/enumeration interface */ @@ -5250,11 +5254,6 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv) usbhost_devaddr_initialize(&priv->rhport); - /* Initialize semaphores & mutex */ - - nxsem_init(&priv->pscsem, 0, 0); - nxmutex_init(&priv->lock); - /* Initialize the driver state data */ priv->smstate = SMSTATE_DETACHED; diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c index eec79b1906..7d595c0971 100644 --- a/arch/arm/src/stm32/stm32_otghshost.c +++ b/arch/arm/src/stm32/stm32_otghshost.c @@ -479,7 +479,11 @@ static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv); * single global instance. */ -static struct stm32_usbhost_s g_usbhost; +static struct stm32_usbhost_s g_usbhost = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), +}; /* This is the connection/enumeration interface */ @@ -5249,11 +5253,6 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv) usbhost_devaddr_initialize(&priv->rhport); - /* Initialize semaphores & mutex */ - - nxsem_init(&priv->pscsem, 0, 0); - nxmutex_init(&priv->lock); - /* Initialize the driver state data */ priv->smstate = SMSTATE_DETACHED; diff --git a/arch/arm/src/stm32/stm32_rng.c b/arch/arm/src/stm32/stm32_rng.c index 18a1bb67b2..39166e3737 100644 --- a/arch/arm/src/stm32/stm32_rng.c +++ b/arch/arm/src/stm32/stm32_rng.c @@ -70,7 +70,11 @@ struct rng_dev_s * Private Data ****************************************************************************/ -static struct rng_dev_s g_rngdev; +static struct rng_dev_s g_rngdev = +{ + .rd_devlock = NXMUTEX_INITIALIZER, + .rd_readsem = SEM_INITIALIZER(0), +}; static const struct file_operations g_rngops = { @@ -100,10 +104,6 @@ static int stm32_rng_initialize(void) _info("Initializing RNG\n"); - memset(&g_rngdev, 0, sizeof(struct rng_dev_s)); - - nxmutex_init(&g_rngdev.rd_devlock); - if (irq_attach(STM32_IRQ_RNG, stm32_rng_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -241,7 +241,11 @@ static ssize_t stm32_rng_read(struct file *filep, char *buffer, /* We've got the mutex. */ - nxsem_init(&g_rngdev.rd_readsem, 0, 0); + /* Reset the operation semaphore with 0 for blocking until the + * buffer is filled from interrupts. + */ + + nxsem_reset(&g_rngdev.rd_readsem, 0); g_rngdev.rd_buflen = buflen; g_rngdev.rd_buf = buffer; diff --git a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c b/arch/arm/src/stm32/stm32_rtc_lowerhalf.c index 1f5859cd77..e192e67a70 100644 --- a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c +++ b/arch/arm/src/stm32/stm32_rtc_lowerhalf.c @@ -159,6 +159,7 @@ static const struct rtc_ops_s g_rtc_ops = static struct stm32_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, + .devlock = NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -918,7 +919,6 @@ static int stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void) { - nxmutex_init(&g_rtc_lowerhalf.devlock); return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c index 4c0460bc37..e6ab5a26f5 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/stm32/stm32_sdio.c @@ -549,6 +549,7 @@ struct stm32_dev_s g_sdiodev = #endif #endif }, + .waitsem = SEM_INITIALIZER(0), }; /* Register logging support */ @@ -3019,12 +3020,6 @@ struct sdio_dev_s *sdio_initialize(int slotno) struct stm32_dev_s *priv = &g_sdiodev; - /* Initialize the SDIO slot structure */ - - /* Initialize semaphores */ - - nxsem_init(&priv->waitsem, 0, 0); - /* Allocate a DMA channel */ #ifdef CONFIG_STM32_SDIO_DMA diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/stm32/stm32_spi.c index 5f2c21e950..2490e7e112 100644 --- a/arch/arm/src/stm32/stm32_spi.c +++ b/arch/arm/src/stm32/stm32_spi.c @@ -370,7 +370,10 @@ static struct stm32_spidev_s g_spi1dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -435,7 +438,10 @@ static struct stm32_spidev_s g_spi2dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -500,7 +506,10 @@ static struct stm32_spidev_s g_spi3dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -565,7 +574,10 @@ static struct stm32_spidev_s g_spi4dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -630,7 +642,10 @@ static struct stm32_spidev_s g_spi5dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -695,7 +710,10 @@ static struct stm32_spidev_s g_spi6dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -2088,16 +2106,9 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_STM32_SPI_DMA if (priv->rxch && priv->txch) { - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); - /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the * DMA channel. If the channel is not available, then * stm32_dmachannel() will block and wait until the channel becomes diff --git a/arch/arm/src/stm32f0l0g0/stm32_aes.c b/arch/arm/src/stm32f0l0g0/stm32_aes.c index 62478a499d..8a1bac4290 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_aes.c +++ b/arch/arm/src/stm32f0l0g0/stm32_aes.c @@ -68,8 +68,8 @@ static int stm32aes_setup_cr(int mode, int encrypt); * Private Data ****************************************************************************/ -static mutex_t g_stm32aes_lock; -static bool g_stm32aes_initdone = false; +static mutex_t g_stm32aes_lock = NXMUTEX_INITIALIZER; +static bool g_stm32aes_initdone; /**************************************************************************** * Public Data @@ -231,8 +231,6 @@ int stm32_aesinitialize(void) { uint32_t regval; - nxmutex_init(&g_stm32aes_lock); - regval = getreg32(STM32_RCC_AHBENR); regval |= RCC_AHBENR_AESEN; putreg32(regval, STM32_RCC_AHBENR); @@ -252,7 +250,6 @@ int stm32_aesuninitialize(void) regval &= ~RCC_AHBENR_AESEN; putreg32(regval, STM32_RCC_AHBENR); - nxmutex_destroy(&g_stm32aes_lock); return OK; } diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c index fc8b6719f9..a0b96db9f7 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c @@ -100,62 +100,74 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { .chan = 0, .irq = STM32_IRQ_DMA1CH1, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, { .chan = 1, .irq = STM32_IRQ_DMA1CH2, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, { .chan = 2, .irq = STM32_IRQ_DMA1CH3, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, { .chan = 3, .irq = STM32_IRQ_DMA1CH4, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, { .chan = 4, .irq = STM32_IRQ_DMA1CH5, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, { .chan = 5, .irq = STM32_IRQ_DMA1CH6, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, { .chan = 6, .irq = STM32_IRQ_DMA1CH7, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, #if STM32_NDMA > 1 { .chan = 0, .irq = STM32_IRQ_DMA2CH1, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, { .chan = 1, .irq = STM32_IRQ_DMA2CH2, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, { .chan = 2, .irq = STM32_IRQ_DMA2CH3, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, { .chan = 3, .irq = STM32_IRQ_DMA2CH4, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, { .chan = 4, .irq = STM32_IRQ_DMA2CH5, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, #endif @@ -308,7 +320,6 @@ void weak_function arm_dma_initialize(void) for (chndx = 0; chndx < DMA_NCHANNELS; chndx++) { dmach = &g_dma[chndx]; - nxsem_init(&dmach->sem, 0, 1); /* Attach DMA interrupt vectors */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_rng.c b/arch/arm/src/stm32f0l0g0/stm32_rng.c index 7905bf75ed..d492778145 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_rng.c +++ b/arch/arm/src/stm32f0l0g0/stm32_rng.c @@ -70,7 +70,11 @@ struct rng_dev_s * Private Data ****************************************************************************/ -static struct rng_dev_s g_rngdev; +static struct rng_dev_s g_rngdev = +{ + .rd_devlock = NXMUTEX_INITIALIZER, + .rd_readsem = SEM_INITIALIZER(0), +}; static const struct file_operations g_rngops = { @@ -100,9 +104,6 @@ static int stm32_rng_initialize(void) _info("Initializing RNG\n"); - memset(&g_rngdev, 0, sizeof(struct rng_dev_s)); - nxmutex_init(&g_rngdev.rd_devlock); - if (irq_attach(STM32_IRQ_RNG, stm32_rng_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -240,7 +241,11 @@ static ssize_t stm32_rng_read(struct file *filep, /* We've got the semaphore. */ - nxsem_init(&g_rngdev.rd_readsem, 0, 0); + /* Reset the operation semaphore with 0 for blocking until the + * buffer is filled from interrupts. + */ + + nxsem_reset(&g_rngdev.rd_readsem, 0); g_rngdev.rd_buflen = buflen; g_rngdev.rd_buf = buffer; diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/stm32f0l0g0/stm32_spi.c index 4bb55658e2..3d85ee99da 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.c +++ b/arch/arm/src/stm32f0l0g0/stm32_spi.c @@ -325,7 +325,10 @@ static struct stm32_spidev_s g_spi1dev = .rxch = DMACHAN_SPI1_RX, .txch = DMACHAN_SPI1_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -379,7 +382,10 @@ static struct stm32_spidev_s g_spi2dev = #ifdef CONFIG_STM32F0L0G0_SPI2_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -433,7 +439,10 @@ static struct stm32_spidev_s g_spi3dev = #ifdef CONFIG_STM32F0L0G0_SPI3_DMA .rxch = DMACHAN_SPI3_RX, .txch = DMACHAN_SPI3_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -1946,20 +1955,9 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_STM32F0L0G0_SPI_DMA if (priv->rxch && priv->txch) { - /* Initialize the SPI semaphores that is used to wait for DMA - * completion - */ - - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); - /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the * DMA channel. If the channel is not available, then * stm32_dmachannel() will block and wait until the channel becomes diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c index 495571a77a..7f9e802bd2 100644 --- a/arch/arm/src/stm32f7/stm32_adc.c +++ b/arch/arm/src/stm32f7/stm32_adc.c @@ -439,7 +439,8 @@ static const struct stm32_adc_ops_s g_adc_llops = struct adccmn_data_s g_adc123_cmn = { - .refcount = 0 + .refcount = 0, + .lock = NXMUTEX_INITIALIZER, }; /* ADC1 state */ @@ -3031,10 +3032,6 @@ struct adc_dev_s *stm32_adc_initialize(int intf, priv->adc_channels = ADC_CHANNELS_NUMBER; #endif -#ifdef ADC_HAVE_CB - priv->cb = NULL; -#endif - #ifdef CONFIG_STM32F7_ADC_LL_OPS /* Store reference to the upper-half ADC device */ @@ -3048,13 +3045,6 @@ struct adc_dev_s *stm32_adc_initialize(int intf, ainfo("intf: %d cr_channels: %d\n", intf, priv->cr_channels); #endif - /* Initialize the ADC common data semaphore. - * - * REVISIT: This will be done several times for each initialzied ADC in - * the ADC block. - */ - - nxmutex_init(&priv->cmn->lock); return dev; } diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index 3ff569ae90..65a20d3b3f 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -94,48 +94,56 @@ static struct stm32_dma_s g_dma[DMA_NSTREAMS] = .stream = 0, .irq = STM32_IRQ_DMA1S0, .shift = DMA_INT_STREAM0_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(0), }, { .stream = 1, .irq = STM32_IRQ_DMA1S1, .shift = DMA_INT_STREAM1_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(1), }, { .stream = 2, .irq = STM32_IRQ_DMA1S2, .shift = DMA_INT_STREAM2_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(2), }, { .stream = 3, .irq = STM32_IRQ_DMA1S3, .shift = DMA_INT_STREAM3_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(3), }, { .stream = 4, .irq = STM32_IRQ_DMA1S4, .shift = DMA_INT_STREAM4_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(4), }, { .stream = 5, .irq = STM32_IRQ_DMA1S5, .shift = DMA_INT_STREAM5_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(5), }, { .stream = 6, .irq = STM32_IRQ_DMA1S6, .shift = DMA_INT_STREAM6_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(6), }, { .stream = 7, .irq = STM32_IRQ_DMA1S7, .shift = DMA_INT_STREAM7_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(7), }, #if STM32F7_NDMA > 1 @@ -143,47 +151,55 @@ static struct stm32_dma_s g_dma[DMA_NSTREAMS] = .stream = 0, .irq = STM32_IRQ_DMA2S0, .shift = DMA_INT_STREAM0_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(0), }, { .stream = 1, .irq = STM32_IRQ_DMA2S1, .shift = DMA_INT_STREAM1_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(1), }, { .stream = 2, .irq = STM32_IRQ_DMA2S2, .shift = DMA_INT_STREAM2_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(2), }, { .stream = 3, .irq = STM32_IRQ_DMA2S3, .shift = DMA_INT_STREAM3_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(3), }, { .stream = 4, .irq = STM32_IRQ_DMA2S4, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(4), }, { .stream = 5, .irq = STM32_IRQ_DMA2S5, .shift = DMA_INT_STREAM5_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(5), }, { .stream = 6, .irq = STM32_IRQ_DMA2S6, .shift = DMA_INT_STREAM6_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(6), }, { .stream = 7, .irq = STM32_IRQ_DMA2S7, .shift = DMA_INT_STREAM7_SHIFT, + .sem = SEM_INITIALIZER(1), .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(7), }, #endif @@ -440,7 +456,6 @@ void weak_function arm_dma_initialize(void) for (stream = 0; stream < DMA_NSTREAMS; stream++) { dmast = &g_dma[stream]; - nxsem_init(&dmast->sem, 0, 1); /* Attach DMA interrupt vectors */ diff --git a/arch/arm/src/stm32f7/stm32_dma2d.c b/arch/arm/src/stm32f7/stm32_dma2d.c index 0e2138059b..3c29fecda4 100644 --- a/arch/arm/src/stm32f7/stm32_dma2d.c +++ b/arch/arm/src/stm32f7/stm32_dma2d.c @@ -249,11 +249,11 @@ static uint32_t g_clut[STM32_DMA2D_NCLUT * /* The DMA2D mutex that enforces mutually exclusive access */ -static mutex_t g_lock; +static mutex_t g_lock = NXMUTEX_INITIALIZER; /* Semaphore for interrupt handling */ -static sem_t g_semirq; +static sem_t g_semirq = SEM_INITIALIZER(0); /* This structure provides irq handling */ @@ -1092,13 +1092,6 @@ int stm32_dma2dinitialize(void) * arch/arm/src/stm32f7/stm32f7xxxx_rcc.c */ - /* Initialize the DMA2D mutex that enforces mutually exclusive - * access to the driver - */ - - nxmutex_init(&g_lock); - nxsem_init(g_interrupt.sem, 0, 0); - #ifdef CONFIG_STM32F7_FB_CMAP /* Enable dma2d transfer and clut loading interrupts only */ diff --git a/arch/arm/src/stm32f7/stm32_foc.c b/arch/arm/src/stm32f7/stm32_foc.c index 8b6ea5ea6a..7034fff68b 100644 --- a/arch/arm/src/stm32f7/stm32_foc.c +++ b/arch/arm/src/stm32f7/stm32_foc.c @@ -533,7 +533,7 @@ struct stm32_foc_dev_s struct stm32_foc_adccmn_s { uint8_t cntr; /* ADC common counter */ - sem_t lock; /* Lock data */ + mutex_t lock; /* Lock data */ }; /* STM32 FOC volatile data */ @@ -639,7 +639,8 @@ static void stm32_foc_hw_config_get(struct foc_dev_s *dev); static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 = { - .cntr = 0 + .cntr = 0, + .lock = NXMUTEX_INITIALIZER, }; /* STM32 specific FOC data */ @@ -2086,10 +2087,6 @@ stm32_foc_initialize(int inst, struct stm32_foc_board_s *board) modifyreg32(FOC_PWM_FZ_REG, 0, pwmfzbit); - /* Initialize ADC common data mutex */ - - nxmutex_init(&foc_priv->adc_cmn->lock); - /* Initialize calibration semaphore */ nxsem_init(&foc_priv->cal_done_sem, 0, 0); diff --git a/arch/arm/src/stm32f7/stm32_ltdc.c b/arch/arm/src/stm32f7/stm32_ltdc.c index 1fa548827f..41df28c1f6 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.c +++ b/arch/arm/src/stm32f7/stm32_ltdc.c @@ -809,11 +809,11 @@ static uint8_t g_transpclut[STM32_LTDC_NCLUT]; /* The LTDC mutex that enforces mutually exclusive access */ -static mutex_t g_lock; +static mutex_t g_lock = NXMUTEX_INITIALIZER; /* The semaphore for interrupt handling */ -static sem_t g_semirq; +static sem_t g_semirq = SEM_INITIALIZER(0); /* This structure provides irq handling */ @@ -1611,11 +1611,6 @@ static int stm32_ltdc_reload(uint8_t value, bool waitvblank) static void stm32_ltdc_irqconfig(void) { - /* Initialize the LTDC mutex that enforces mutually exclusive access */ - - nxmutex_init(&g_lock); - nxsem_init(g_interrupt.sem, 0, 0); - /* Attach LTDC interrupt vector */ irq_attach(g_interrupt.irq, stm32_ltdcirq, NULL); diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c index 3a4a55dd23..c8b7bc3279 100644 --- a/arch/arm/src/stm32f7/stm32_otghost.c +++ b/arch/arm/src/stm32f7/stm32_otghost.c @@ -473,7 +473,11 @@ static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv); * single global instance. */ -static struct stm32_usbhost_s g_usbhost; +static struct stm32_usbhost_s g_usbhost = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), +}; /* This is the connection/enumeration interface */ @@ -5222,11 +5226,6 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv) usbhost_devaddr_initialize(&priv->rhport); - /* Initialize semaphores & mutex */ - - nxsem_init(&priv->pscsem, 0, 0); - nxmutex_init(&priv->lock); - /* Initialize the driver state data */ priv->smstate = SMSTATE_DETACHED; diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c index 9c5f9241fc..833178bcf7 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.c +++ b/arch/arm/src/stm32f7/stm32_qspi.c @@ -340,13 +340,16 @@ static struct stm32f7_qspidev_s g_qspi0dev = .ops = &g_qspi0ops, }, .base = STM32_QUADSPI_BASE, + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_STM32F7_QSPI_INTERRUPTS .handler = qspi0_interrupt, .irq = STM32_IRQ_QUADSPI, + .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, #ifdef CONFIG_STM32F7_QSPI_DMA .candma = true, + .dmawait = SEM_INITIALIZER(0), #endif }; @@ -2556,13 +2559,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) if (!priv->initialized) { - /* Now perform one time initialization. - * - * Initialize the QSPI mutex that enforces mutually exclusive - * access to the QSPI registers. - */ - - nxmutex_init(&priv->lock); + /* Now perform one time initialization. */ #ifdef CONFIG_STM32F7_QSPI_DMA /* Pre-allocate DMA channels. */ @@ -2576,8 +2573,6 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) priv->candma = false; } } - - nxsem_init(&priv->dmawait, 0, 0); #endif #ifdef CONFIG_STM32F7_QSPI_INTERRUPTS @@ -2587,10 +2582,8 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) if (ret < 0) { spierr("ERROR: Failed to attach irq %d\n", priv->irq); - goto errout_with_dmawait; + goto errout_with_dmach; } - - nxsem_init(&priv->op_sem, 0, 0); #endif /* Perform hardware initialization. Puts the QSPI into an active @@ -2619,10 +2612,9 @@ errout_with_irq: #ifdef CONFIG_STM32F7_QSPI_INTERRUPTS irq_detach(priv->irq); -errout_with_dmawait: +errout_with_dmach: #endif #ifdef CONFIG_STM32F7_QSPI_DMA - nxsem_destroy(&priv->dmawait); if (priv->dmach) { stm32_dmafree(priv->dmach); @@ -2630,7 +2622,6 @@ errout_with_dmawait: } #endif - nxmutex_destroy(&priv->lock); return NULL; } diff --git a/arch/arm/src/stm32f7/stm32_rng.c b/arch/arm/src/stm32f7/stm32_rng.c index aae5fd0358..7d8e3117ce 100644 --- a/arch/arm/src/stm32f7/stm32_rng.c +++ b/arch/arm/src/stm32f7/stm32_rng.c @@ -69,7 +69,11 @@ struct rng_dev_s * Private Data ****************************************************************************/ -static struct rng_dev_s g_rngdev; +static struct rng_dev_s g_rngdev = +{ + .rd_devlock = NXMUTEX_INITIALIZER, + .rd_readsem = SEM_INITIALIZER(0), +}; static const struct file_operations g_rngops = { @@ -97,10 +101,6 @@ static int stm32_rng_initialize(void) { _info("Initializing RNG\n"); - memset(&g_rngdev, 0, sizeof(struct rng_dev_s)); - - nxmutex_init(&g_rngdev.rd_devlock); - if (irq_attach(STM32_IRQ_RNG, stm32_rnginterrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -259,7 +259,11 @@ static ssize_t stm32_rngread(struct file *filep, char *buffer, size_t buflen) /* We've got the device semaphore, proceed with reading */ - nxsem_init(&g_rngdev.rd_readsem, 0, 0); + /* Reset the operation semaphore with 0 for blocking until the + * buffer is filled from interrupts. + */ + + nxsem_reset(&g_rngdev.rd_readsem, 0); g_rngdev.rd_buflen = buflen; g_rngdev.rd_buf = buffer; @@ -272,10 +276,6 @@ static ssize_t stm32_rngread(struct file *filep, char *buffer, size_t buflen) ret = nxsem_wait(&g_rngdev.rd_readsem); - /* Done with the operation semaphore */ - - nxsem_destroy(&g_rngdev.rd_readsem); - /* Free RNG via the device mutex for next use */ nxmutex_unlock(&g_rngdev.rd_devlock); diff --git a/arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c b/arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c index c9da58ac8a..8aa12bee23 100644 --- a/arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c +++ b/arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c @@ -154,7 +154,8 @@ static const struct rtc_ops_s g_rtc_ops = static struct stm32_lowerhalf_s g_rtc_lowerhalf = { - .ops = &g_rtc_ops, + .ops = &g_rtc_ops, + .devlock = NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -738,7 +739,6 @@ static int stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void) { - nxmutex_init(&g_rtc_lowerhalf.devlock); return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c index 1b9cf96a3b..8b08fa06cc 100644 --- a/arch/arm/src/stm32f7/stm32_sai.c +++ b/arch/arm/src/stm32f7/stm32_sai.c @@ -277,6 +277,7 @@ static struct stm32f7_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, .base = STM32F7_SAI1_A_BASE, + .lock = NXMUTEX_INITIALIZER, .frequency = STM32F7_SAI1_FREQUENCY, #ifdef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, @@ -288,6 +289,7 @@ static struct stm32f7_sai_s g_sai1a_priv = #endif .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), }; #endif @@ -296,6 +298,7 @@ static struct stm32f7_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, .base = STM32F7_SAI1_B_BASE, + .lock = NXMUTEX_INITIALIZER, .frequency = STM32F7_SAI1_FREQUENCY, #ifdef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, @@ -307,6 +310,7 @@ static struct stm32f7_sai_s g_sai1b_priv = #endif .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), }; #endif @@ -317,6 +321,7 @@ static struct stm32f7_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, .base = STM32F7_SAI2_A_BASE, + .lock = NXMUTEX_INITIALIZER, .frequency = STM32F7_SAI2_FREQUENCY, #ifdef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, @@ -328,6 +333,7 @@ static struct stm32f7_sai_s g_sai2a_priv = #endif .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), }; #endif @@ -336,6 +342,7 @@ static struct stm32f7_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, .base = STM32F7_SAI2_B_BASE, + .lock = NXMUTEX_INITIALIZER, .frequency = STM32F7_SAI2_FREQUENCY, #ifdef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, @@ -347,6 +354,7 @@ static struct stm32f7_sai_s g_sai2b_priv = #endif .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), }; #endif @@ -1473,8 +1481,6 @@ static void sai_buf_initialize(struct stm32f7_sai_s *priv) int i; priv->freelist = NULL; - nxsem_init(&priv->bufsem, 0, CONFIG_STM32F7_SAI_MAXINFLIGHT); - for (i = 0; i < CONFIG_STM32F7_SAI_MAXINFLIGHT; i++) { sai_buf_free(priv, &priv->containers[i]); @@ -1499,8 +1505,6 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv) { sai_dump_regs(priv, "Before initialization"); - nxmutex_init(&priv->lock); - /* Initialize buffering */ sai_buf_initialize(priv); diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 77b8aad1d3..241563c06e 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -637,7 +637,7 @@ struct stm32_dev_s g_sdmmcdev1 = #ifdef CONFIG_STM32F7_SDMMC1_DMAPRIO .dmapri = CONFIG_STM32F7_SDMMC1_DMAPRIO, #endif - + .waitsem = SEM_INITIALIZER(0), #ifdef HAVE_SDMMC_SDIO_MODE #ifdef CONFIG_SDMMC1_SDIO_MODE .sdiomode = true, @@ -697,7 +697,7 @@ struct stm32_dev_s g_sdmmcdev2 = #ifdef CONFIG_STM32F7_SDMMC2_DMAPRIO .dmapri = CONFIG_STM32F7_SDMMC2_DMAPRIO, #endif - + .waitsem = SEM_INITIALIZER(0), #ifdef HAVE_SDMMC_SDIO_MODE #ifdef CONFIG_SDMMC2_SDIO_MODE .sdiomode = true, @@ -3386,12 +3386,6 @@ struct sdio_dev_s *sdio_initialize(int slotno) return NULL; } - /* Initialize the SDIO slot structure */ - - /* Initialize semaphores */ - - nxsem_init(&priv->waitsem, 0, 0); - #ifdef CONFIG_STM32F7_SDMMC_DMA /* Allocate a DMA channel */ diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c index c77a5475a7..40af5410e5 100644 --- a/arch/arm/src/stm32f7/stm32_spi.c +++ b/arch/arm/src/stm32f7/stm32_spi.c @@ -350,7 +350,10 @@ static struct stm32_spidev_s g_spi1dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -418,7 +421,10 @@ static struct stm32_spidev_s g_spi2dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -486,7 +492,10 @@ static struct stm32_spidev_s g_spi3dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -554,7 +563,10 @@ static struct stm32_spidev_s g_spi4dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -622,7 +634,10 @@ static struct stm32_spidev_s g_spi5dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -690,7 +705,10 @@ static struct stm32_spidev_s g_spi6dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -2153,16 +2171,9 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); - /* Initialize the SPI mutex that enforces mutually exclusive access. */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_STM32F7_SPI_DMA if (priv->rxch && priv->txch) { - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); - /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the * DMA channel. If the channel is not available, then * stm32_dmachannel() will block and wait until the channel becomes diff --git a/arch/arm/src/stm32h7/stm32_otghost.c b/arch/arm/src/stm32h7/stm32_otghost.c index 81378dab49..48e14e6b30 100644 --- a/arch/arm/src/stm32h7/stm32_otghost.c +++ b/arch/arm/src/stm32h7/stm32_otghost.c @@ -475,7 +475,11 @@ static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv); * single global instance. */ -static struct stm32_usbhost_s g_usbhost; +static struct stm32_usbhost_s g_usbhost = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), +}; /* This is the connection/enumeration interface */ @@ -5226,11 +5230,6 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv) usbhost_devaddr_initialize(&priv->rhport); - /* Initialize semaphores & mutex */ - - nxsem_init(&priv->pscsem, 0, 0); - nxmutex_init(&priv->lock); - /* Initialize the driver state data */ priv->smstate = SMSTATE_DETACHED; diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c index 7f313473a7..d073889af9 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.c +++ b/arch/arm/src/stm32h7/stm32_qspi.c @@ -365,13 +365,16 @@ static struct stm32h7_qspidev_s g_qspi0dev = .ops = &g_qspi0ops, }, .base = STM32_QUADSPI_BASE, + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_STM32H7_QSPI_INTERRUPTS .handler = qspi0_interrupt, .irq = STM32_IRQ_QUADSPI, + .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, #ifdef CONFIG_STM32H7_QSPI_DMA .candma = true, + .dmawait = SEM_INITIALIZER(0), #endif }; @@ -2614,13 +2617,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) if (!priv->initialized) { - /* Now perform one time initialization. - * - * Initialize the QSPI mutex that enforces mutually exclusive - * access to the QSPI registers. - */ - - nxmutex_init(&priv->lock); + /* Now perform one time initialization. */ #ifdef CONFIG_STM32H7_QSPI_DMA /* Pre-allocate DMA channels. */ @@ -2634,8 +2631,6 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) priv->candma = false; } } - - nxsem_init(&priv->dmawait, 0, 0); #endif #ifdef CONFIG_STM32H7_QSPI_INTERRUPTS @@ -2645,10 +2640,8 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) if (ret < 0) { spierr("ERROR: Failed to attach irq %d\n", priv->irq); - goto errout_with_dmawait; + goto errout_with_dmach; } - - nxsem_init(&priv->op_sem, 0, 0); #endif /* Perform hardware initialization. Puts the QSPI into an active @@ -2677,10 +2670,9 @@ errout_with_irq: #ifdef CONFIG_STM32H7_QSPI_INTERRUPTS irq_detach(priv->irq); -errout_with_dmawait: +errout_with_dmach: #endif #ifdef CONFIG_STM32H7_QSPI_DMA - nxsem_destroy(&priv->dmawait); if (priv->dmach) { stm32_dmafree(priv->dmach); @@ -2688,7 +2680,6 @@ errout_with_dmawait: } #endif - nxmutex_destroy(&priv->lock); return NULL; } diff --git a/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c b/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c index 9addd887be..700080cafb 100644 --- a/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c @@ -156,6 +156,7 @@ static const struct rtc_ops_s g_rtc_ops = static struct stm32_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, + .devlock = NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -739,7 +740,6 @@ static int stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void) { - nxmutex_init(&g_rtc_lowerhalf.devlock); return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c index 92038d2ea3..d2a23c7c1a 100644 --- a/arch/arm/src/stm32h7/stm32_sdmmc.c +++ b/arch/arm/src/stm32h7/stm32_sdmmc.c @@ -593,6 +593,7 @@ struct stm32_dev_s g_sdmmcdev1 = #if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE) .d0_gpio = SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0), #endif + .waitsem = SEM_INITIALIZER(0), #if defined(HAVE_SDMMC_SDIO_MODE) && defined(CONFIG_SDMMC1_SDIO_MODE) .sdiomode = true, #endif @@ -647,6 +648,7 @@ struct stm32_dev_s g_sdmmcdev2 = #if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE) .d0_gpio = SDMMC2_SDIO_PULL(GPIO_SDMMC2_D0), #endif + .waitsem = SEM_INITIALIZER(0), #if defined(HAVE_SDMMC_SDIO_MODE) && defined(CONFIG_SDMMC2_SDIO_MODE) .sdiomode = true, #endif @@ -3484,12 +3486,6 @@ struct sdio_dev_s *sdio_initialize(int slotno) return NULL; } - /* Initialize the SDIO slot structure */ - - /* Initialize semaphores */ - - nxsem_init(&priv->waitsem, 0, 0); - /* Reset the card and assure that it is in the initial, unconfigured * state. */ diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index fe4a333e30..7a8ea71f12 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -965,6 +965,7 @@ static struct up_dev_s g_usart1priv = #endif #ifdef CONFIG_USART1_TXDMA .txdma_channel = DMAMAP_USART1_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_USART1_RXDMA .rxdma_channel = DMAMAP_USART1_RX, @@ -1034,6 +1035,7 @@ static struct up_dev_s g_usart2priv = #endif #ifdef CONFIG_USART2_TXDMA .txdma_channel = DMAMAP_USART2_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_USART2_RXDMA .rxdma_channel = DMAMAP_USART2_RX, @@ -1103,6 +1105,7 @@ static struct up_dev_s g_usart3priv = #endif #ifdef CONFIG_USART3_TXDMA .txdma_channel = DMAMAP_USART3_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_USART3_RXDMA .rxdma_channel = DMAMAP_USART3_RX, @@ -1172,6 +1175,7 @@ static struct up_dev_s g_uart4priv = .rx_gpio = GPIO_UART4_RX, #ifdef CONFIG_UART4_TXDMA .txdma_channel = DMAMAP_UART4_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_UART4_RXDMA .rxdma_channel = DMAMAP_UART4_RX, @@ -1241,6 +1245,7 @@ static struct up_dev_s g_uart5priv = .rx_gpio = GPIO_UART5_RX, #ifdef CONFIG_UART5_TXDMA .txdma_channel = DMAMAP_UART5_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_UART5_RXDMA .rxdma_channel = DMAMAP_UART5_RX, @@ -1310,6 +1315,7 @@ static struct up_dev_s g_usart6priv = #endif #ifdef CONFIG_USART6_TXDMA .txdma_channel = DMAMAP_USART6_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_USART6_RXDMA .rxdma_channel = DMAMAP_USART6_RX, @@ -1379,6 +1385,7 @@ static struct up_dev_s g_uart7priv = #endif #ifdef CONFIG_UART7_TXDMA .txdma_channel = DMAMAP_UART7_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_UART7_RXDMA .rxdma_channel = DMAMAP_UART7_RX, @@ -1448,6 +1455,7 @@ static struct up_dev_s g_uart8priv = #endif #ifdef CONFIG_UART8_TXDMA .txdma_channel = DMAMAP_UART8_TX, + .txdmasem = SEM_INITIALIZER(1), #endif #ifdef CONFIG_UART8_RXDMA .rxdma_channel = DMAMAP_UART8_RX, @@ -2224,8 +2232,6 @@ static int up_dma_setup(struct uart_dev_s *dev) { priv->txdma = stm32_dmachannel(priv->txdma_channel); - nxsem_init(&priv->txdmasem, 0, 1); - /* Enable receive Tx DMA for the UART */ modifyreg32(priv->usartbase + STM32_USART_CR3_OFFSET, diff --git a/arch/arm/src/stm32h7/stm32_spi.c b/arch/arm/src/stm32h7/stm32_spi.c index d920a9fda1..59d0ef5fce 100644 --- a/arch/arm/src/stm32h7/stm32_spi.c +++ b/arch/arm/src/stm32h7/stm32_spi.c @@ -409,7 +409,10 @@ static struct stm32_spidev_s g_spi1dev = .txbuf = g_spi1_txbuf, .buflen = SPI1_DMABUFSIZE_ADJUSTED, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -478,7 +481,10 @@ static struct stm32_spidev_s g_spi2dev = .txbuf = g_spi2_txbuf, .buflen = SPI2_DMABUFSIZE_ADJUSTED, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -547,7 +553,10 @@ static struct stm32_spidev_s g_spi3dev = .txbuf = g_spi3_txbuf, .buflen = SPI3_DMABUFSIZE_ADJUSTED, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -616,7 +625,10 @@ static struct stm32_spidev_s g_spi4dev = .txbuf = g_spi4_txbuf, .buflen = SPI4_DMABUFSIZE_ADJUSTED, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -685,7 +697,10 @@ static struct stm32_spidev_s g_spi5dev = .txbuf = g_spi5_txbuf, .buflen = SPI5_DMABUFSIZE_ADJUSTED, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -755,7 +770,10 @@ static struct stm32_spidev_s g_spi6dev = .txbuf = g_spi6_txbuf, .buflen = SPI6_DMABUFSIZE_ADJUSTED, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -2497,14 +2515,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); - /* Initialize the SPI mutex that enforces mutually exclusive access. */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_STM32H7_SPI_DMA - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); - /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. WARNING: If you diff --git a/arch/arm/src/stm32h7/stm32_spi_slave.c b/arch/arm/src/stm32h7/stm32_spi_slave.c index 9d0b09b8eb..833af6703b 100644 --- a/arch/arm/src/stm32h7/stm32_spi_slave.c +++ b/arch/arm/src/stm32h7/stm32_spi_slave.c @@ -313,6 +313,8 @@ static const struct spi_slave_ctrlrops_s g_ctrlr_ops = #define SPI_SLAVE_INIT_DMA(x) \ .rxch = DMAMAP_SPI##x##_RX, \ .txch = DMAMAP_SPI##x##_TX, \ + .rxsem = SEM_INITIALIZER(0), \ + .txsem = SEM_INITIALIZER(0), \ .outq = SPI_SLAVE_OUTQ(x), \ .inq = SPI_SLAVE_INQ(x), #else @@ -334,6 +336,7 @@ static const struct spi_slave_ctrlrops_s g_ctrlr_ops = .irq = STM32_IRQ_SPI##x, \ SPI_SLAVE_INIT_DMA(x) \ .initialized = false, \ + .lock = NXMUTEX_INITIALIZER, \ SPI_SLAVE_INIT_PM_PREPARE \ .config = CONFIG_STM32H7_SPI##x##_COMMTYPE, \ } @@ -1648,10 +1651,6 @@ static void spi_slave_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); - /* Initialize the SPI mutex that enforces mutually exclusive access. */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_STM32H7_SPI_DMA /* DMA will be started in the interrupt handler, synchronized to the master * nss @@ -1659,17 +1658,6 @@ static void spi_slave_initialize(struct stm32_spidev_s *priv) priv->dmarunning = false; - /* Initialize the SPI semaphores that is used to wait for DMA completion. - * This semaphore is used for signaling and, hence, should not have - * priority inheritance enabled. - */ - - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); - - sem_setprotocol(&priv->rxsem, SEM_PRIO_NONE); - sem_setprotocol(&priv->txsem, SEM_PRIO_NONE); - if (priv->config != SIMPLEX_TX) { priv->rxdma = stm32_dmachannel(priv->rxch); diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c index 7d9a278f70..6fc6a8b598 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c @@ -483,7 +483,11 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv); * single global instance. */ -static struct stm32l4_usbhost_s g_usbhost; +static struct stm32l4_usbhost_s g_usbhost = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), +}; /* This is the connection/enumeration interface */ @@ -5263,11 +5267,6 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) usbhost_devaddr_initialize(&priv->rhport); - /* Initialize semaphores & mutex */ - - nxsem_init(&priv->pscsem, 0, 0); - nxmutex_init(&priv->lock); - /* Initialize the driver state data */ priv->smstate = SMSTATE_DETACHED; diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index bd91d21a5c..606dbfb172 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -338,13 +338,16 @@ static struct stm32l4_qspidev_s g_qspi0dev = .ops = &g_qspi0ops, }, .base = STM32L4_QSPI_BASE, + .lock = NXMUTEX_INITIALIZER, #ifdef STM32L4_QSPI_INTERRUPTS .handler = qspi0_interrupt, .irq = STM32L4_IRQ_QUADSPI, + .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, #ifdef CONFIG_STM32L4_QSPI_DMA .candma = true, + .dmawait = SEM_INITIALIZER(0), #endif }; @@ -2499,12 +2502,6 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) { /* Now perform one time initialization */ - /* Initialize the QSPI mutex that enforces mutually exclusive - * access to the QSPI registers. - */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_STM32L4_QSPI_DMA /* Pre-allocate DMA channels. */ @@ -2517,8 +2514,6 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) priv->candma = false; } } - - nxsem_init(&priv->dmawait, 0, 0); #endif #ifdef STM32L4_QSPI_INTERRUPTS @@ -2528,10 +2523,8 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) if (ret < 0) { spierr("ERROR: Failed to attach irq %d\n", priv->irq); - goto errout_with_dmawait; + goto errout_with_dmach; } - - nxsem_init(&priv->op_sem, 0, 0); #endif /* Perform hardware initialization. Puts the QSPI into an active @@ -2560,10 +2553,9 @@ errout_with_irq: #ifdef STM32L4_QSPI_INTERRUPTS irq_detach(priv->irq); -errout_with_dmawait: +errout_with_dmach: #endif #ifdef CONFIG_STM32L4_QSPI_DMA - nxsem_destroy(&priv->dmawait); if (priv->dmach) { stm32l4_dmafree(priv->dmach); @@ -2571,7 +2563,6 @@ errout_with_dmawait: } #endif - nxmutex_destroy(&priv->lock); return NULL; } diff --git a/arch/arm/src/stm32l4/stm32l4_rng.c b/arch/arm/src/stm32l4/stm32l4_rng.c index c3eb86eece..3bf6e45959 100644 --- a/arch/arm/src/stm32l4/stm32l4_rng.c +++ b/arch/arm/src/stm32l4/stm32l4_rng.c @@ -70,7 +70,11 @@ struct rng_dev_s * Private Data ****************************************************************************/ -static struct rng_dev_s g_rngdev; +static struct rng_dev_s g_rngdev = +{ + .rd_devlock = NXMUTEX_INITIALIZER, + .rd_readsem = SEM_INITIALIZER(0), +}; static const struct file_operations g_rngops = { @@ -94,10 +98,6 @@ static int stm32l4_rng_initialize(void) { _info("Initializing RNG\n"); - memset(&g_rngdev, 0, sizeof(struct rng_dev_s)); - - nxmutex_init(&g_rngdev.rd_devlock); - if (irq_attach(STM32L4_IRQ_RNG, stm32l4_rnginterrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -245,7 +245,11 @@ static ssize_t stm32l4_rngread(struct file *filep, /* We've got the device semaphore, proceed with reading */ - nxsem_init(&g_rngdev.rd_readsem, 0, 0); + /* Reset the operation semaphore with 0 for blocking until the + * buffer is filled from interrupts. + */ + + nxsem_reset(&g_rngdev.rd_readsem, 0); g_rngdev.rd_buflen = buflen; g_rngdev.rd_buf = buffer; @@ -258,10 +262,6 @@ static ssize_t stm32l4_rngread(struct file *filep, nxsem_wait(&g_rngdev.rd_readsem); - /* Done with the operation semaphore */ - - nxsem_destroy(&g_rngdev.rd_readsem); - /* Free RNG via the device mutex for next use */ nxmutex_unlock(&g_rngdev.rd_devlock); diff --git a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c index 8337fd0bb9..2e2d18281f 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c @@ -155,6 +155,7 @@ static const struct rtc_ops_s g_rtc_ops = static struct stm32l4_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, + .devlock = NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -707,7 +708,6 @@ static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) struct rtc_lowerhalf_s *stm32l4_rtc_lowerhalf(void) { - nxmutex_init(&g_rtc_lowerhalf.devlock); return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/stm32l4/stm32l4_sai.c b/arch/arm/src/stm32l4/stm32l4_sai.c index 406ef0caca..2f62990f37 100644 --- a/arch/arm/src/stm32l4/stm32l4_sai.c +++ b/arch/arm/src/stm32l4/stm32l4_sai.c @@ -233,6 +233,7 @@ static struct stm32l4_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, .base = STM32L4_SAI1_A_BASE, + .lock = NXMUTEX_INITIALIZER, .frequency = STM32L4_SAI1_FREQUENCY, #ifdef CONFIG_STM32L4_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_SYNC_INT, @@ -244,6 +245,7 @@ static struct stm32l4_sai_s g_sai1a_priv = #endif .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, .samplerate = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT), }; #endif @@ -252,6 +254,7 @@ static struct stm32l4_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, .base = STM32L4_SAI1_B_BASE, + .lock = NXMUTEX_INITIALIZER, .frequency = STM32L4_SAI1_FREQUENCY, #ifdef CONFIG_STM32L4_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_SYNC_INT, @@ -263,6 +266,7 @@ static struct stm32l4_sai_s g_sai1b_priv = #endif .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, .samplerate = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT), }; #endif @@ -273,6 +277,7 @@ static struct stm32l4_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, .base = STM32L4_SAI2_A_BASE, + .lock = NXMUTEX_INITIALIZER, .frequency = STM32L4_SAI2_FREQUENCY, #ifdef CONFIG_STM32L4_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_SYNC_INT, @@ -284,6 +289,7 @@ static struct stm32l4_sai_s g_sai2a_priv = #endif .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, .samplerate = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT), }; #endif @@ -292,6 +298,7 @@ static struct stm32l4_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, .base = STM32L4_SAI2_B_BASE, + .lock = NXMUTEX_INITIALIZER, .frequency = STM32L4_SAI2_FREQUENCY, #ifdef CONFIG_STM32L4_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_SYNC_INT, @@ -303,6 +310,7 @@ static struct stm32l4_sai_s g_sai2b_priv = #endif .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, .samplerate = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT), }; #endif @@ -1222,8 +1230,6 @@ static void sai_buf_initialize(struct stm32l4_sai_s *priv) int i; priv->freelist = NULL; - nxsem_init(&priv->bufsem, 0, CONFIG_STM32L4_SAI_MAXINFLIGHT); - for (i = 0; i < CONFIG_STM32L4_SAI_MAXINFLIGHT; i++) { sai_buf_free(priv, &priv->containers[i]); @@ -1248,8 +1254,6 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv) { sai_dump_regs(priv, "Before initialization"); - nxmutex_init(&priv->lock); - /* Initialize buffering */ sai_buf_initialize(priv); diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index 176c5ea606..8a8bf1da7c 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -567,6 +567,7 @@ struct stm32_dev_s g_sdmmcdev1 = #ifdef CONFIG_STM32L4_SDMMC1_DMAPRIO .dmapri = CONFIG_STM32L4_SDMMC1_DMAPRIO, #endif + .waitsem = SEM_INITIALIZER(0), }; #endif #ifdef CONFIG_STM32L4_SDMMC2 @@ -620,6 +621,7 @@ struct stm32_dev_s g_sdmmcdev2 = #ifdef CONFIG_STM32L4_SDMMC2_DMAPRIO .dmapri = CONFIG_STM32L4_SDMMC2_DMAPRIO, #endif + .waitsem = SEM_INITIALIZER(0), }; #endif @@ -3094,12 +3096,6 @@ struct sdio_dev_s *sdio_initialize(int slotno) return NULL; } - /* Initialize the SDIO slot structure */ - - /* Initialize semaphores */ - - nxsem_init(&priv->waitsem, 0, 0); - #ifdef CONFIG_STM32L4_SDMMC_DMA /* Allocate a DMA channel */ diff --git a/arch/arm/src/stm32l4/stm32l4_spi.c b/arch/arm/src/stm32l4/stm32l4_spi.c index ddc1fcecee..d5b0810ec6 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.c +++ b/arch/arm/src/stm32l4/stm32l4_spi.c @@ -293,7 +293,10 @@ static struct stm32l4_spidev_s g_spi1dev = .rxch = DMACHAN_SPI1_RX, .txch = DMACHAN_SPI1_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -346,7 +349,10 @@ static struct stm32l4_spidev_s g_spi2dev = #ifdef CONFIG_STM32L4_SPI_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -399,7 +405,10 @@ static struct stm32l4_spidev_s g_spi3dev = #ifdef CONFIG_STM32L4_SPI_DMA .rxch = DMACHAN_SPI3_RX, .txch = DMACHAN_SPI3_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -1745,16 +1754,7 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) spi_putreg(priv, STM32L4_SPI_CRCPR_OFFSET, 7); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_STM32L4_SPI_DMA - /* Initialize the SPI semaphores that is used to wait for DMA completion */ - - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); - /* Get DMA channels. NOTE: stm32l4_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32l4_dmachannel() * will block and wait until the channel becomes available. WARNING: If diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c index 6843de6a78..f11d7f79ba 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c @@ -85,72 +85,86 @@ static struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = { .chan = 0, .irq = STM32L4_IRQ_DMA1CH1, + .sem = SEM_INITIALIZER(1), .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(0), }, { .chan = 1, .irq = STM32L4_IRQ_DMA1CH2, + .sem = SEM_INITIALIZER(1), .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(1), }, { .chan = 2, .irq = STM32L4_IRQ_DMA1CH3, + .sem = SEM_INITIALIZER(1), .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(2), }, { .chan = 3, .irq = STM32L4_IRQ_DMA1CH4, + .sem = SEM_INITIALIZER(1), .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(3), }, { .chan = 4, .irq = STM32L4_IRQ_DMA1CH5, + .sem = SEM_INITIALIZER(1), .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(4), }, { .chan = 5, .irq = STM32L4_IRQ_DMA1CH6, + .sem = SEM_INITIALIZER(1), .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(5), }, { .chan = 6, .irq = STM32L4_IRQ_DMA1CH7, + .sem = SEM_INITIALIZER(1), .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(6), }, #if STM32L4_NDMA > 1 { .chan = 0, .irq = STM32L4_IRQ_DMA2CH1, + .sem = SEM_INITIALIZER(1), .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(0), }, { .chan = 1, .irq = STM32L4_IRQ_DMA2CH2, + .sem = SEM_INITIALIZER(1), .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(1), }, { .chan = 2, .irq = STM32L4_IRQ_DMA2CH3, + .sem = SEM_INITIALIZER(1), .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(2), }, { .chan = 3, .irq = STM32L4_IRQ_DMA2CH4, + .sem = SEM_INITIALIZER(1), .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(3), }, { .chan = 4, .irq = STM32L4_IRQ_DMA2CH5, + .sem = SEM_INITIALIZER(1), .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(4), }, { .chan = 5, .irq = STM32L4_IRQ_DMA2CH6, + .sem = SEM_INITIALIZER(1), .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(5), }, { .chan = 6, .irq = STM32L4_IRQ_DMA2CH7, + .sem = SEM_INITIALIZER(1), .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(6), }, #endif @@ -307,7 +321,6 @@ void weak_function arm_dma_initialize(void) for (chndx = 0; chndx < DMA_NCHANNELS; chndx++) { dmach = &g_dma[chndx]; - nxsem_init(&dmach->sem, 0, 1); /* Attach DMA interrupt vectors */ diff --git a/arch/arm/src/stm32l5/stm32l5_spi.c b/arch/arm/src/stm32l5/stm32l5_spi.c index 4c2b75a0fd..0a01960ffb 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.c +++ b/arch/arm/src/stm32l5/stm32l5_spi.c @@ -293,7 +293,10 @@ static struct stm32l5_spidev_s g_spi1dev = .rxch = DMACHAN_SPI1_RX, .txch = DMACHAN_SPI1_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -346,7 +349,10 @@ static struct stm32l5_spidev_s g_spi2dev = #ifdef CONFIG_STM32L5_SPI_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -399,7 +405,10 @@ static struct stm32l5_spidev_s g_spi3dev = #ifdef CONFIG_STM32L5_SPI_DMA .rxch = DMACHAN_SPI3_RX, .txch = DMACHAN_SPI3_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -1737,23 +1746,7 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) spi_putreg(priv, STM32L5_SPI_CRCPR_OFFSET, 7); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_STM32L5_SPI_DMA - /* Initialize the SPI semaphores that is used to wait for DMA completion */ - - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); - - /* These semaphores are used for signaling and, hence, should not have - * priority inheritance enabled. - */ - - nxsem_setprotocol(&priv->rxsem, SEM_PRIO_NONE); - nxsem_setprotocol(&priv->txsem, SEM_PRIO_NONE); - /* Get DMA channels. * NOTE: stm32l5_dmachannel() will always assign the DMA channel. * If the channel is not available, then stm32l5_dmachannel() will diff --git a/arch/arm/src/stm32u5/stm32_spi.c b/arch/arm/src/stm32u5/stm32_spi.c index a4b779a9c6..9ca4003b5d 100644 --- a/arch/arm/src/stm32u5/stm32_spi.c +++ b/arch/arm/src/stm32u5/stm32_spi.c @@ -361,7 +361,10 @@ static struct stm32_spidev_s g_spi1dev = .txbuf = g_spi1_txbuf, .buflen = SPI1_DMABUFSIZE_ADJUSTED, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -430,7 +433,10 @@ static struct stm32_spidev_s g_spi2dev = .txbuf = g_spi2_txbuf, .buflen = SPI2_DMABUFSIZE_ADJUSTED, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -499,7 +505,10 @@ static struct stm32_spidev_s g_spi3dev = .txbuf = g_spi3_txbuf, .buflen = SPI3_DMABUFSIZE_ADJUSTED, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -2239,14 +2248,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); - /* Initialize the SPI mutex that enforces mutually exclusive access. */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_STM32U5_SPI_DMA - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); - /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. WARNING: If you diff --git a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c index 3f346a5b9b..4bf9f2ceec 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c @@ -154,6 +154,7 @@ static const struct rtc_ops_s g_rtc_ops = static struct stm32wb_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, + .devlock = NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -705,7 +706,6 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) struct rtc_lowerhalf_s *stm32wb_rtc_lowerhalf(void) { - nxmutex_init(&g_rtc_lowerhalf.devlock); return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/stm32wb/stm32wb_spi.c b/arch/arm/src/stm32wb/stm32wb_spi.c index 3844507ee5..f99da36da7 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.c +++ b/arch/arm/src/stm32wb/stm32wb_spi.c @@ -289,7 +289,10 @@ static struct stm32wb_spidev_s g_spi1dev = .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -342,7 +345,10 @@ static struct stm32wb_spidev_s g_spi2dev = #ifdef CONFIG_STM32WB_SPI_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif @@ -1680,16 +1686,7 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) spi_putreg(priv, STM32WB_SPI_CRCPR_OFFSET, 7); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_STM32WB_SPI_DMA - /* Initialize the SPI semaphores that is used to wait for DMA completion */ - - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); - /* Get DMA channels. NOTE: stm32wb_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32wb_dmachannel() * will block and wait until the channel becomes available. WARNING: If diff --git a/arch/arm/src/stm32wl5/stm32wl5_spi.c b/arch/arm/src/stm32wl5/stm32wl5_spi.c index 6cec9c2955..30e1e6c112 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_spi.c +++ b/arch/arm/src/stm32wl5/stm32wl5_spi.c @@ -332,7 +332,10 @@ static struct stm32wl5_spidev_s g_spi1dev = .rxch = 0, .txch = 0, # endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -1728,16 +1731,9 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) spi_putreg(priv, STM32WL5_SPI_CRCPR_OFFSET, 7); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_STM32WL5_SPI_DMA if (priv->rxch && priv->txch) { - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); - /* Get DMA channels. NOTE: stm32wl5_dmachannel() will always assign * the DMA channel. If the channel is not available, then * stm32wl5_dmachannel() will block and wait until the channel becomes diff --git a/arch/arm/src/tiva/common/tiva_adclow.c b/arch/arm/src/tiva/common/tiva_adclow.c index 453999ffb8..b51b6b3692 100644 --- a/arch/arm/src/tiva/common/tiva_adclow.c +++ b/arch/arm/src/tiva/common/tiva_adclow.c @@ -204,20 +204,50 @@ static void tiva_adc_dump_dev(void); static struct adc_dev_s dev0; static struct tiva_adc_s adc0; -static struct tiva_adc_sse_s sse00; -static struct tiva_adc_sse_s sse01; -static struct tiva_adc_sse_s sse02; -static struct tiva_adc_sse_s sse03; +static struct tiva_adc_sse_s sse00 = +{ + .lock = NXMUTEX_INITIALIZER, +}; + +static struct tiva_adc_sse_s sse01 = +{ + .lock = NXMUTEX_INITIALIZER, +}; + +static struct tiva_adc_sse_s sse02 = +{ + .lock = NXMUTEX_INITIALIZER, +}; + +static struct tiva_adc_sse_s sse03 = +{ + .lock = NXMUTEX_INITIALIZER, +}; #endif #ifdef CONFIG_TIVA_ADC1 static struct adc_dev_s dev1; static struct tiva_adc_s adc1; -static struct tiva_adc_sse_s sse10; -static struct tiva_adc_sse_s sse11; -static struct tiva_adc_sse_s sse12; -static struct tiva_adc_sse_s sse13; +static struct tiva_adc_sse_s sse10 = +{ + .lock = NXMUTEX_INITIALIZER, +}; + +static struct tiva_adc_sse_s sse11 = +{ + .lock = NXMUTEX_INITIALIZER, +}; + +static struct tiva_adc_sse_s sse12 = +{ + .lock = NXMUTEX_INITIALIZER, +}; + +static struct tiva_adc_sse_s sse13 = +{ + .lock = NXMUTEX_INITIALIZER, +}; #endif /* Offer run-time ADC objects in array form to help reduce the reliance on @@ -812,7 +842,6 @@ static struct tiva_adc_s *tiva_adc_struct_init(struct tiva_adc_cfg_s *cfg) { sse->adc = cfg->adc; sse->num = s; - nxmutex_init(&sse->lock); sse->ena = false; sse->cfg = true; } diff --git a/arch/arm/src/tiva/common/tiva_can.c b/arch/arm/src/tiva/common/tiva_can.c index 32a77da346..f498a21582 100644 --- a/arch/arm/src/tiva/common/tiva_can.c +++ b/arch/arm/src/tiva/common/tiva_can.c @@ -276,8 +276,11 @@ static struct tiva_canmod_s g_tivacan0priv = { .modnum = 0, .base = TIVA_CAN_BASE(0), + .rxsem = SEM_INITIALIZER(0), + .thd_iface_lock = NXMUTEX_INITIALIZER, .thd_iface_base = TIVA_CAN_IFACE_BASE(0, 0), .isr_iface_base = TIVA_CAN_IFACE_BASE(0, 1), + .fifo_lock = NXMUTEX_INITIALIZER, .rxdefault_fifo = NULL, }; @@ -293,8 +296,11 @@ static struct tiva_canmod_s g_tivacan1priv = { .modnum = 1, .base = TIVA_CAN_BASE(1), + .rxsem = SEM_INITIALIZER(0), + .thd_iface_lock = NXMUTEX_INITIALIZER, .thd_iface_base = TIVA_CAN_IFACE_BASE(1, 0), .isr_iface_base = TIVA_CAN_IFACE_BASE(1, 1), + .fifo_lock = NXMUTEX_INITIALIZER, .rxdefault_fifo = NULL, }; @@ -394,13 +400,6 @@ static int tivacan_setup(struct can_dev_s *dev) char *kthd_argv[2]; kthd_argv[1] = NULL; - ret = nxsem_init(&canmod->rxsem, 0, 0); - - if (ret < 0) - { - return ret; - } - switch (canmod->modnum) { #ifdef CONFIG_TIVA_CAN0 @@ -2377,22 +2376,6 @@ int tiva_can_initialize(char *devpath, int modnum) canmod = dev->cd_priv; - /* Initialize concurrancy objects for accessing interfaces */ - - ret = nxmutex_init(&canmod->thd_iface_lock); - if (ret < 0) - { - canerr("ERROR: failed to initialize mutex: %d\n", ret); - return ret; - } - - ret = nxmutex_init(&canmod->fifo_lock); - if (ret < 0) - { - canerr("ERROR: failed to initialize mutex: %d\n", ret); - return ret; - } - /* Register the driver */ ret = can_register(devpath, dev); diff --git a/arch/arm/src/tiva/common/tiva_hciuart.c b/arch/arm/src/tiva/common/tiva_hciuart.c index d3344c19dc..3e203ed169 100644 --- a/arch/arm/src/tiva/common/tiva_hciuart.c +++ b/arch/arm/src/tiva/common/tiva_hciuart.c @@ -182,7 +182,11 @@ static uint8_t g_uart0_txbuffer[CONFIG_TIVA_HCIUART0_TXBUFSIZE]; /* HCI UART0 variable state information */ -static struct hciuart_state_s g_hciuart0_state; +static struct hciuart_state_s g_hciuart0_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; /* HCI UART0 constant configuration information */ @@ -228,7 +232,11 @@ static uint8_t g_uart1_txbuffer[CONFIG_TIVA_HCIUART1_TXBUFSIZE]; /* HCI UART1 variable state information */ -static struct hciuart_state_s g_hciuart1_state; +static struct hciuart_state_s g_hciuart1_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; /* HCI UART1 constant configuration information */ @@ -274,7 +282,11 @@ static uint8_t g_uart2_txbuffer[CONFIG_TIVA_HCIUART2_TXBUFSIZE]; /* HCI UART2 variable state information */ -static struct hciuart_state_s g_hciuart2_state; +static struct hciuart_state_s g_hciuart2_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; /* HCI UART2 constant configuration information */ @@ -320,7 +332,11 @@ static uint8_t g_uart3_txbuffer[CONFIG_TIVA_HCIUART3_TXBUFSIZE]; /* HCI UART3 variable state information */ -static struct hciuart_state_s g_hciuart3_state; +static struct hciuart_state_s g_hciuart3_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; /* HCI UART3 constant configuration information */ @@ -367,6 +383,10 @@ static uint8_t g_uart4_txbuffer[CONFIG_TIVA_HCIUART4_TXBUFSIZE]; /* HCI UART4 variable state information */ static struct hciuart_state_s g_hciuart4_state; +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; /* HCI UART4 constant configuration information */ @@ -412,7 +432,11 @@ static uint8_t g_uart5_txbuffer[CONFIG_TIVA_HCIUART5_TXBUFSIZE]; /* HCI UART5 variable state information */ -static struct hciuart_state_s g_hciuart5_state; +static struct hciuart_state_s g_hciuart5_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; /* HCI UART5 constant configuration information */ @@ -458,7 +482,11 @@ static uint8_t g_uart6_txbuffer[CONFIG_TIVA_HCIUART6_TXBUFSIZE]; /* HCI UART6 variable state information */ -static struct hciuart_state_s g_hciuart6_state; +static struct hciuart_state_s g_hciuart6_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; /* HCI UART6 constant configuration information */ @@ -504,7 +532,11 @@ static uint8_t g_uart7_txbuffer[CONFIG_TIVA_HCIUART7_TXBUFSIZE]; /* HCI UART7 variable state information */ -static struct hciuart_state_s g_hciuart7_state; +static struct hciuart_state_s g_hciuart7_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; /* HCI UART7 constant configuration information */ @@ -1843,11 +1875,6 @@ void hciuart_initialize(void) hciuart_disableints(config, HCIUART_ALLINTS); - /* Initialize signalling semaphores */ - - nxsem_init(&state->rxwait, 0, 0); - nxsem_init(&state->txwait, 0, 0); - /* Attach and enable the HCI UART IRQ */ ret = irq_attach(config->irq, hciuart_interrupt, (void *)config); diff --git a/arch/arm/src/tiva/common/tiva_ssi.c b/arch/arm/src/tiva/common/tiva_ssi.c index 497975f402..8464d335a9 100644 --- a/arch/arm/src/tiva/common/tiva_ssi.c +++ b/arch/arm/src/tiva/common/tiva_ssi.c @@ -312,9 +312,13 @@ static struct tiva_ssidev_s g_ssidev[] = #if NSSI_ENABLED > 1 .base = TIVA_SSI0_BASE, #endif +#ifndef CONFIG_SSI_POLLWAIT + .xfrsem = SEM_INITIALIZER(0), +#endif #if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 .irq = TIVA_IRQ_SSI0, #endif + .lock = NXMUTEX_INITIALIZER, }, #endif #ifdef CONFIG_TIVA_SSI1 @@ -323,9 +327,13 @@ static struct tiva_ssidev_s g_ssidev[] = #if NSSI_ENABLED > 1 .base = TIVA_SSI1_BASE, #endif +#ifndef CONFIG_SSI_POLLWAIT + .xfrsem = SEM_INITIALIZER(0), +#endif #if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 .irq = TIVA_IRQ_SSI1, #endif + .lock = NXMUTEX_INITIALIZER, }, #endif #ifdef CONFIG_TIVA_SSI2 @@ -334,9 +342,13 @@ static struct tiva_ssidev_s g_ssidev[] = #if NSSI_ENABLED > 1 .base = TIVA_SSI2_BASE, #endif +#ifndef CONFIG_SSI_POLLWAIT + .xfrsem = SEM_INITIALIZER(0), +#endif #if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 .irq = TIVA_IRQ_SSI2, #endif + .lock = NXMUTEX_INITIALIZER, }, #endif #ifdef CONFIG_TIVA_SSI3 @@ -345,9 +357,13 @@ static struct tiva_ssidev_s g_ssidev[] = #if NSSI_ENABLED > 1 .base = TIVA_SSI3_BASE, #endif +#ifndef CONFIG_SSI_POLLWAIT + .xfrsem = SEM_INITIALIZER(0), +#endif #if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 .irq = TIVA_IRQ_SSI3, #endif + .lock = NXMUTEX_INITIALIZER, }, #endif }; @@ -1598,11 +1614,6 @@ struct spi_dev_s *tiva_ssibus_initialize(int port) /* Initialize the state structure */ -#ifndef CONFIG_SSI_POLLWAIT - nxsem_init(&priv->xfrsem, 0, 0); -#endif - nxmutex_init(&priv->lock); - /* Set all CR1 fields to reset state. This will be master mode. */ ssi_putreg(priv, TIVA_SSI_CR1_OFFSET, 0); diff --git a/arch/arm/src/xmc4/xmc4_spi.c b/arch/arm/src/xmc4/xmc4_spi.c index 4a065b1fb1..3396a05beb 100644 --- a/arch/arm/src/xmc4/xmc4_spi.c +++ b/arch/arm/src/xmc4/xmc4_spi.c @@ -325,6 +325,7 @@ static const struct spi_ops_s g_spi0ops = static struct xmc4_spidev_s g_spi0dev = { .base = XMC4_USIC0_CH0_BASE, + .spilock = NXMUTEX_INITIALIZER, .select = xmc4_spi0select, #ifdef CONFIG_XMC4_SPI_DMA .rxintf = DMACHAN_INTF_SPI0RX, @@ -362,6 +363,7 @@ static const struct spi_ops_s g_spi1ops = static struct xmc4_spidev_s g_spi1dev = { .base = XMC4_USIC0_CH1_BASE, + .spilock = NXMUTEX_INITIALIZER, .select = xmc4_spi1select, #ifdef CONFIG_XMC4_SPI_DMA .rxintf = DMACHAN_INTF_SPI1RX, @@ -399,6 +401,7 @@ static const struct spi_ops_s g_spi2ops = static struct xmc4_spidev_s g_spi2dev = { .base = XMC4_USIC1_CH0_BASE, + .spilock = NXMUTEX_INITIALIZER, .select = xmc4_spi2select, #ifdef CONFIG_XMC4_SPI_DMA .rxintf = DMACHAN_INTF_SPI2RX, @@ -436,6 +439,7 @@ static const struct spi_ops_s g_spi3ops = static struct xmc4_spidev_s g_spi3dev = { .base = XMC4_USIC1_CH1_BASE, + .spilock = NXMUTEX_INITIALIZER, .select = xmc4_spi3select, #ifdef CONFIG_XMC4_SPI_DMA .rxintf = DMACHAN_INTF_SPI3RX, @@ -473,6 +477,7 @@ static const struct spi_ops_s g_spi4ops = static struct xmc4_spidev_s g_spi4dev = { .base = XMC4_USIC2_CH0_BASE, + .spilock = NXMUTEX_INITIALIZER, .select = xmc4_spi4select, #ifdef CONFIG_XMC4_SPI_DMA .rxintf = DMACHAN_INTF_SPI4RX, @@ -511,6 +516,7 @@ static const struct spi_ops_s g_spi5ops = static struct xmc4_spidev_s g_spi5dev = { .base = XMC4_USIC2_CH1_BASE, + .spilock = NXMUTEX_INITIALIZER, .select = xmc4_spi5select, #ifdef CONFIG_XMC4_SPI_DMA .rxintf = DMACHAN_INTF_SPI5RX, @@ -2057,11 +2063,6 @@ struct spi_dev_s *xmc4_spibus_initialize(int channel) spi_putreg(spi, 0, XMC4_USIC_CCR_OFFSET); - /* Initialize the SPI mutex that enforces mutually exclusive - * access to the SPI registers. - */ - - nxmutex_init(&spi->spilock); spi->initialized = true; #ifdef CONFIG_XMC4_SPI_DMA diff --git a/arch/avr/src/avr/up_spi.c b/arch/avr/src/avr/up_spi.c index 2a35b22ae4..38166b61cb 100644 --- a/arch/avr/src/avr/up_spi.c +++ b/arch/avr/src/avr/up_spi.c @@ -108,6 +108,7 @@ static struct avr_spidev_s g_spidev = { &g_spiops }, + .lock = NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -481,10 +482,6 @@ FAR struct spi_dev_s *avr_spibus_initialize(int port) spi_setfrequency((FAR struct spi_dev_s *)priv, 400000); - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - leave_critical_section(flags); return &priv->spidev; } diff --git a/arch/mips/src/pic32mx/pic32mx_spi.c b/arch/mips/src/pic32mx/pic32mx_spi.c index 133b0e6016..d22b823a06 100644 --- a/arch/mips/src/pic32mx/pic32mx_spi.c +++ b/arch/mips/src/pic32mx/pic32mx_spi.c @@ -147,6 +147,7 @@ static struct pic32mx_dev_s g_spi1dev = .rxirq = PIC32MX_IRQSRC_SPI1RX, .txirq = PIC32MX_IRQSRC_SPI1TX, #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -185,6 +186,7 @@ static struct pic32mx_dev_s g_spi2dev = .rxirq = PIC32MX_IRQSRC_SPI2RX, .txirq = PIC32MX_IRQSRC_SPI2TX, #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -223,6 +225,7 @@ static struct pic32mx_dev_s g_spi3dev = .rxirq = PIC32MX_IRQSRC_SPI3RX, .txirq = PIC32MX_IRQSRC_SPI3TX, #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -261,6 +264,7 @@ static struct pic32mx_dev_s g_spi4dev = .rxirq = PIC32MX_IRQSRC_SPI4RX, .txirq = PIC32MX_IRQSRC_SPI4TX, #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -963,10 +967,6 @@ struct spi_dev_s *pic32mx_spibus_initialize(int port) priv->nbits = 8; priv->mode = SPIDEV_MODE0; - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_PIC32MX_SPI_INTERRUPTS /* Enable interrupts at the SPI controller */ diff --git a/arch/mips/src/pic32mz/pic32mz_dma.c b/arch/mips/src/pic32mz/pic32mz_dma.c index d9263618d0..dfbffee556 100644 --- a/arch/mips/src/pic32mz/pic32mz_dma.c +++ b/arch/mips/src/pic32mz/pic32mz_dma.c @@ -133,6 +133,7 @@ static void pic32mz_dma_config(struct pic32mz_dmach_s *dmach, static struct pic32mz_dmac_s g_dmac = { + .chlock = NXMUTEX_INITIALIZER, .dmachs = { { @@ -735,10 +736,6 @@ void weak_function up_dma_initialize(void) /* Enable the DMA module. */ pic32mz_dma_putglobal(PIC32MZ_DMA_CONSET_OFFSET, DMA_CON_ON); - - /* Initialize the mutex. */ - - nxmutex_init(&g_dmac.chlock); } /**************************************************************************** diff --git a/arch/mips/src/pic32mz/pic32mz_spi.c b/arch/mips/src/pic32mz/pic32mz_spi.c index cc0cda16b1..a9aad4ad1b 100644 --- a/arch/mips/src/pic32mz/pic32mz_spi.c +++ b/arch/mips/src/pic32mz/pic32mz_spi.c @@ -283,7 +283,11 @@ static struct pic32mz_dev_s g_spi1dev = { &g_spi1ops }, - .config = &g_spi1config + .config = &g_spi1config, + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_PIC32MZ_SPI_DMA + .dmawait = SEM_INITIALIZER(0), +#endif }; #endif @@ -333,6 +337,10 @@ static struct pic32mz_dev_s g_spi2dev = &g_spi2ops }, .config = &g_spi2config, + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_PIC32MZ_SPI_DMA + .dmawait = SEM_INITIALIZER(0), +#endif }; #endif @@ -382,6 +390,10 @@ static struct pic32mz_dev_s g_spi3dev = &g_spi3ops }, .config = &g_spi3config, + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_PIC32MZ_SPI_DMA + .dmawait = SEM_INITIALIZER(0), +#endif }; #endif @@ -431,6 +443,10 @@ static struct pic32mz_dev_s g_spi4dev = &g_spi4ops }, .config = &g_spi4config, + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_PIC32MZ_SPI_DMA + .dmawait = SEM_INITIALIZER(0), +#endif }; #endif @@ -480,6 +496,10 @@ static struct pic32mz_dev_s g_spi5dev = &g_spi5ops }, .config = &g_spi5config, + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_PIC32MZ_SPI_DMA + .dmawait = SEM_INITIALIZER(0), +#endif }; #endif @@ -529,6 +549,10 @@ static struct pic32mz_dev_s g_spi6dev = &g_spi6ops }, .config = &g_spi6config, + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_PIC32MZ_SPI_DMA + .dmawait = SEM_INITIALIZER(0), +#endif }; #endif @@ -2015,8 +2039,6 @@ struct spi_dev_s *pic32mz_spibus_initialize(int port) { spierr("ERROR: Failed to allocate the TX DMA channel\n"); } - - nxsem_init(&priv->dmawait, 0, 0); #endif #ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS @@ -2078,10 +2100,6 @@ struct spi_dev_s *pic32mz_spibus_initialize(int port) priv->nbits = 8; priv->mode = SPIDEV_MODE0; - /* Initialize the SPI mutex that enforces mutually exclusive access */ - - nxmutex_init(&priv->lock); - #ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS /* Enable interrupts at the SPI controller */ diff --git a/arch/renesas/src/rx65n/rx65n_rspi.c b/arch/renesas/src/rx65n/rx65n_rspi.c index d68570e2fc..8d5bc96bdd 100644 --- a/arch/renesas/src/rx65n/rx65n_rspi.c +++ b/arch/renesas/src/rx65n/rx65n_rspi.c @@ -308,13 +308,17 @@ static struct rx65n_rspidev_s g_rspi0dev = .rspigrpbase = RX65N_GRPAL0_ADDR, .rspierimask = RX65N_GRPAL0_SPEI0_MASK, .rspiidlimask = RX65N_GRPAL0_SPII0_MASK, + .waitsem = SEM_INITIALIZER(0), #endif #if defined(CONFIG_RX65N_RSPI_DTC_DT_MODE) .p_txdt = &g_tx0dt, .p_rxdt = &g_rx0dt, + .txsem = SEM_INITIALIZER(0), + .rxsem = SEM_INITIALIZER(0), .txvec = RX65N_RSPI0_TXVECT, .rxvec = RX65N_RSPI0_RXVECT, #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -370,13 +374,17 @@ static struct rx65n_rspidev_s g_rspi1dev = .rspigrpbase = RX65N_GRPAL0_ADDR, .rspierimask = RX65N_GRPAL0_SPEI1_MASK, .rspiidlimask = RX65N_GRPAL0_SPII1_MASK, + .waitsem = SEM_INITIALIZER(0), #endif #if defined(CONFIG_RX65N_RSPI_DTC_DT_MODE) .p_txdt = &g_tx1dt, .p_rxdt = &g_rx1dt, + .txsem = SEM_INITIALIZER(0), + .rxsem = SEM_INITIALIZER(0), .txvec = RX65N_RSPI1_TXVECT, .rxvec = RX65N_RSPI1_RXVECT, #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -432,13 +440,17 @@ static struct rx65n_rspidev_s g_rspi2dev = .rspigrpbase = RX65N_GRPAL0_ADDR, .rspierimask = RX65N_GRPAL0_SPEI2_MASK, .rspiidlimask = RX65N_GRPAL0_SPII2_MASK, + .waitsem = SEM_INITIALIZER(0), #endif #if defined(CONFIG_RX65N_RSPI_DTC_DT_MODE) .p_txdt = &g_tx2dt, .p_rxdt = &g_rx2dt, + .txsem = SEM_INITIALIZER(0), + .rxsem = SEM_INITIALIZER(0), .txvec = RX65N_RSPI2_TXVECT, .rxvec = RX65N_RSPI2_RXVECT, #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -2209,17 +2221,6 @@ static void rspi_bus_initialize(FAR struct rx65n_rspidev_s *priv) #if defined(CONFIG_RX65N_RSPI_DTC_DT_MODE) int ret; -#endif - -#ifdef CONFIG_RX65N_RSPI_SW_DT_MODE -#ifndef CONFIG_SPI_POLLWAIT - nxsem_init(&priv->waitsem, 0, 0); -#endif -#elif defined(CONFIG_RX65N_RSPI_DTC_DT_MODE) - /* Initialize the SPI semaphores that is used to wait for DTC completion */ - - nxsem_init(&priv->rxsem, 0, 0); - nxsem_init(&priv->txsem, 0, 0); /* Prepare Transmit and receive parameter */ @@ -2243,7 +2244,6 @@ static void rspi_bus_initialize(FAR struct rx65n_rspidev_s *priv) } #endif - nxmutex_init(&priv->lock); /* Initialize control register */ diff --git a/arch/renesas/src/rx65n/rx65n_rspi_sw.c b/arch/renesas/src/rx65n/rx65n_rspi_sw.c index c983464799..9a3a1d82d0 100644 --- a/arch/renesas/src/rx65n/rx65n_rspi_sw.c +++ b/arch/renesas/src/rx65n/rx65n_rspi_sw.c @@ -291,7 +291,9 @@ static struct rx65n_rspidev_s g_rspi0dev = .rspigrpbase = RX65N_GRPAL0_ADDR, .rspierimask = RX65N_GRPAL0_SPEI0_MASK, .rspiidlimask = RX65N_GRPAL0_SPII0_MASK, + .waitsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -343,7 +345,9 @@ static struct rx65n_rspidev_s g_rspi1dev = .rspigrpbase = RX65N_GRPAL0_ADDR, .rspierimask = RX65N_GRPAL0_SPEI1_MASK, .rspiidlimask = RX65N_GRPAL0_SPII1_MASK, + .waitsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -395,7 +399,9 @@ static struct rx65n_rspidev_s g_rspi2dev = .rspigrpbase = RX65N_GRPAL0_ADDR, .rspierimask = RX65N_GRPAL0_SPEI2_MASK, .rspiidlimask = RX65N_GRPAL0_SPII2_MASK, + .waitsem = SEM_INITIALIZER(0), #endif + .lock = NXMUTEX_INITIALIZER, }; #endif @@ -1843,11 +1849,6 @@ static void rspi_bus_initialize(FAR struct rx65n_rspidev_s *priv) uint8_t regval8; uint16_t regval16; -#ifndef CONFIG_SPI_POLLWAIT - nxsem_init(&priv->waitsem, 0, 0); -#endif - nxmutex_init(&priv->lock); - /* Initialize control register */ regval8 = rspi_getreg8(priv, RX65N_RSPI_SPCR_OFFSET); diff --git a/arch/renesas/src/rx65n/rx65n_rtc_lowerhalf.c b/arch/renesas/src/rx65n/rx65n_rtc_lowerhalf.c index 56a8f8e30c..17ddfc3372 100644 --- a/arch/renesas/src/rx65n/rx65n_rtc_lowerhalf.c +++ b/arch/renesas/src/rx65n/rx65n_rtc_lowerhalf.c @@ -160,6 +160,7 @@ static const struct rtc_ops_s g_rtc_ops = static struct rx65n_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, + .devlock = NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -729,7 +730,6 @@ static int rx65n_cancelperiodic(FAR struct rtc_lowerhalf_s *lower, int id) FAR struct rtc_lowerhalf_s *rx65n_rtc_lowerhalf(void) { - nxmutex_init(&g_rtc_lowerhalf.devlock); return (FAR struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/renesas/src/rx65n/rx65n_usbhost.c b/arch/renesas/src/rx65n/rx65n_usbhost.c index 152d398fd7..ad6149d8e2 100644 --- a/arch/renesas/src/rx65n/rx65n_usbhost.c +++ b/arch/renesas/src/rx65n/rx65n_usbhost.c @@ -459,7 +459,11 @@ static void *hw_usb_get_fifoctr_adr (uint16_t pipemode); * single globalinstance. */ -static struct rx65n_usbhost_s g_usbhost; +static struct rx65n_usbhost_s g_usbhost = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), +}; /* This is the connection/enumeration interface */ @@ -8360,11 +8364,6 @@ struct usbhost_connection_s *rx65n_usbhost_initialize(int controller) usbhost_devaddr_initialize(&priv->rhport); - /* Initialize semaphores & mutex */ - - nxsem_init(&priv->pscsem, 0, 0); - nxmutex_init(&priv->lock); - #ifndef CONFIG_USBHOST_INT_DISABLE priv->ininterval = MAX_PERINTERVAL; priv->outinterval = MAX_PERINTERVAL; diff --git a/arch/risc-v/src/bl602/bl602_dma.c b/arch/risc-v/src/bl602/bl602_dma.c index 5a1a7a2251..b153b9b5e5 100644 --- a/arch/risc-v/src/bl602/bl602_dma.c +++ b/arch/risc-v/src/bl602/bl602_dma.c @@ -67,7 +67,11 @@ struct dma_controller_s /* This is the overall state of the DMA controller */ -static struct dma_controller_s g_dmac; +static struct dma_controller_s g_dmac = +{ + .exclsem = NXSEM_INITIALIZER(1, PRIOINHERIT_FLAGS_ENABLE), + .chansem = SEM_INITIALIZER(BL602_DMA_NCHANNELS), +}; /* This is the array of all DMA channels */ @@ -357,9 +361,6 @@ void weak_function riscv_dma_initialize(void) /* Initialize the channel list */ - nxsem_init(&g_dmac.exclsem, 0, 1); - nxsem_init(&g_dmac.chansem, 0, BL602_DMA_NCHANNELS); - for (ch = 0; ch < BL602_DMA_NCHANNELS; ch++) { g_dmach[ch].chan = ch; diff --git a/arch/risc-v/src/bl602/bl602_netdev.c b/arch/risc-v/src/bl602/bl602_netdev.c index 09ea73aaf1..2bb2ff7232 100644 --- a/arch/risc-v/src/bl602/bl602_netdev.c +++ b/arch/risc-v/src/bl602/bl602_netdev.c @@ -202,8 +202,8 @@ static struct tx_buf_ind_s g_tx_buf_indicator = static uint8_t locate_data(".wifi_ram.txbuff") g_tx_buff[BL602_NET_TXBUFF_NUM][BL602_NET_TXBUFF_SIZE]; -static mutex_t g_wifi_scan_lock; /* wifi scan complete mutex */ -static sem_t g_wifi_connect_sem; +static mutex_t g_wifi_scan_lock = NXMUTEX_INITIALIZER; +static sem_t g_wifi_connect_sem = SEM_INITIALIZER(0); /* Rx Pending List */ @@ -2106,24 +2106,9 @@ void bl602_net_event(int evt, int val) int bl602_net_initialize(void) { struct bl602_net_driver_s *priv; - int tmp; int idx; uint8_t mac[6]; - /* Initialize scan mutex & semaphore */ - - tmp = nxmutex_init(&g_wifi_scan_lock); - if (tmp < 0) - { - return tmp; - } - - tmp = sem_init(&g_wifi_connect_sem, 0, 0); - if (tmp < 0) - { - return tmp; - } - list_initialize(&g_rx_pending); /* Start wifi process */ @@ -2202,12 +2187,7 @@ int bl602_net_initialize(void) * performed */ - tmp = netdev_register(&priv->net_dev, NET_LL_IEEE80211); - if (tmp < 0) - { - nxmutex_destroy(&g_wifi_scan_lock); - return tmp; - } + return netdev_register(&priv->net_dev, NET_LL_IEEE80211); } return OK; diff --git a/arch/risc-v/src/bl602/bl602_rtc_lowerhalf.c b/arch/risc-v/src/bl602/bl602_rtc_lowerhalf.c index 13169cc15b..839dd65704 100644 --- a/arch/risc-v/src/bl602/bl602_rtc_lowerhalf.c +++ b/arch/risc-v/src/bl602/bl602_rtc_lowerhalf.c @@ -155,6 +155,7 @@ static const struct rtc_ops_s g_rtc_ops = static struct bl602_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, + .devlock = NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -678,13 +679,6 @@ int up_rtc_initialize(void) struct rtc_lowerhalf_s *bl602_rtc_lowerhalf_initialize(void) { - nxmutex_init(&g_rtc_lowerhalf.devlock); - -#ifdef CONFIG_RTC_PERIODIC - g_rtc_lowerhalf.periodic_enable = 0; -#endif - memset(&g_rtc_lowerhalf.rtc_base, 0, sizeof(g_rtc_lowerhalf.rtc_base)); - g_rtc_lowerhalf.rtc_base.tm_year = 70; g_rtc_lowerhalf.rtc_base.tm_mday = 1; diff --git a/arch/risc-v/src/esp32c3/esp32c3_rng.c b/arch/risc-v/src/esp32c3/esp32c3_rng.c index e0c0d056e3..f100f413f2 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rng.c +++ b/arch/risc-v/src/esp32c3/esp32c3_rng.c @@ -56,7 +56,6 @@ * Private Function Prototypes ****************************************************************************/ -static int esp32c3_rng_initialize(void); static ssize_t esp32c3_rng_read(struct file *filep, char *buffer, size_t buflen); @@ -74,7 +73,10 @@ struct rng_dev_s * Private Data ****************************************************************************/ -static struct rng_dev_s g_rngdev; +static struct rng_dev_s g_rngdev = +{ + .rd_lock = NXMUTEX_INITIALIZER, +}; static const struct file_operations g_rngops = { @@ -122,20 +124,6 @@ uint32_t IRAM_ATTR esp_random(void) return result ^ getreg32(WDEV_RND_REG); } -/**************************************************************************** - * Name: esp32c3_rng_initialize - ****************************************************************************/ - -static int esp32c3_rng_initialize(void) -{ - _info("Initializing RNG\n"); - - memset(&g_rngdev, 0, sizeof(struct rng_dev_s)); - nxmutex_init(&g_rngdev.rd_lock); - - return OK; -} - /**************************************************************************** * Name: esp32c3_rng_read ****************************************************************************/ @@ -194,7 +182,6 @@ static ssize_t esp32c3_rng_read(struct file *filep, char *buffer, #ifdef CONFIG_DEV_RANDOM void devrandom_register(void) { - esp32c3_rng_initialize(); register_driver("/dev/random", &g_rngops, 0444, NULL); } #endif @@ -216,9 +203,6 @@ void devrandom_register(void) #ifdef CONFIG_DEV_URANDOM_ARCH void devurandom_register(void) { -#ifndef CONFIG_DEV_RANDOM - esp32c3_rng_initialize(); -#endif register_driver("/dev/urandom", &g_rngops, 0444, NULL); } #endif diff --git a/arch/risc-v/src/esp32c3/esp32c3_rt_timer.c b/arch/risc-v/src/esp32c3/esp32c3_rt_timer.c index 3ea81a3bc7..0c27f8e7e5 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rt_timer.c +++ b/arch/risc-v/src/esp32c3/esp32c3_rt_timer.c @@ -82,6 +82,7 @@ struct esp32c3_rt_priv_s static struct esp32c3_rt_priv_s g_rt_priv = { .pid = INVALID_PROCESS_ID, + .toutsem = SEM_INITIALIZER(0), }; /**************************************************************************** @@ -719,8 +720,6 @@ int esp32c3_rt_timer_init(void) return -EINVAL; } - nxsem_init(&priv->toutsem, 0, 0); - pid = kthread_create(RT_TIMER_TASK_NAME, RT_TIMER_TASK_PRIORITY, RT_TIMER_TASK_STACK_SIZE, @@ -794,6 +793,4 @@ void esp32c3_rt_timer_deinit(void) kthread_delete(priv->pid); priv->pid = INVALID_PROCESS_ID; } - - nxsem_destroy(&priv->toutsem); } diff --git a/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c b/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c index 187b385a6d..c75aad573e 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c +++ b/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c @@ -5091,13 +5091,6 @@ int esp_wifi_adapter_init(void) goto errout_init_txdone; } - ret = esp_wifi_scan_init(); - if (ret < 0) - { - nerr("ERROR: Initialize Wi-Fi scan parameter error: %d\n", ret); - return ret; - } - ret = esp_wifi_set_country(&country); if (ret < 0) { diff --git a/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c b/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c index 605fcaa0b5..0c640f8b12 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c +++ b/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c @@ -86,7 +86,10 @@ struct wifi_scan_result_s * Private Data ****************************************************************************/ -static struct wifi_scan_result_s g_scan_priv; +static struct wifi_scan_result_s g_scan_priv = +{ + .scan_signal = SEM_INITIALIZER(0), +}; static uint8_t g_channel_num = 0; static uint8_t g_channel_list[CHANNEL_MAX_NUM]; @@ -558,37 +561,3 @@ scan_result_full: priv->scan_status = ESP_SCAN_DONE; nxsem_post(&priv->scan_signal); } - -/**************************************************************************** - * Name: esp_wifi_scan_init - * - * Description: - * Initialize Wi-Fi scan parameter. - * - * Input Parameters: - * None - * - * Returned Value: - * OK is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp_wifi_scan_init(void) -{ - int ret; - struct wifi_scan_result_s *scan_priv = &g_scan_priv; - - /* Initialize the scan structure */ - - memset(scan_priv, 0, sizeof(struct wifi_scan_result_s)); - - /* Init scan signal */ - - if ((ret = nxsem_init(&scan_priv->scan_signal, 0, 0)) != OK) - { - wlerr("ERROR: Initialization scan signal failed: %d\n", ret); - return ret; - } - - return ret; -} diff --git a/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.h b/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.h index 8c4f2c0e5c..00b10d32aa 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.h +++ b/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.h @@ -95,22 +95,6 @@ int esp_wifi_get_scan_results(struct iwreq *iwr); void esp_wifi_scan_event_parse(void); -/**************************************************************************** - * Name: esp_wifi_scan_init - * - * Description: - * Initialize Wi-Fi scan parameter. - * - * Input Parameters: - * None - * - * Returned Value: - * OK is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp_wifi_scan_init(void); - #ifdef __cplusplus } #endif diff --git a/arch/risc-v/src/litex/litex_sdio.c b/arch/risc-v/src/litex/litex_sdio.c index 4fdd03c8b0..9be0b2e958 100644 --- a/arch/risc-v/src/litex/litex_sdio.c +++ b/arch/risc-v/src/litex/litex_sdio.c @@ -212,6 +212,7 @@ struct litex_dev_s g_sdiodev = .callbackenable = litex_callbackenable, .registercallback = litex_registercallback, }, + .waitsem = SEM_INITIALIZER(0), }; /**************************************************************************** @@ -1442,8 +1443,6 @@ struct sdio_dev_s *sdio_initialize(int slotno) mcinfo("slotno: %d\n", slotno); - nxsem_init(&priv->waitsem, 0, 0); - litex_reset(&priv->dev); return &g_sdiodev.dev; } diff --git a/arch/risc-v/src/mpfs/mpfs_emmcsd.c b/arch/risc-v/src/mpfs/mpfs_emmcsd.c index 972a02d195..372d87c952 100644 --- a/arch/risc-v/src/mpfs/mpfs_emmcsd.c +++ b/arch/risc-v/src/mpfs/mpfs_emmcsd.c @@ -464,6 +464,7 @@ struct mpfs_dev_s g_emmcsd_dev = .blocksize = 512, .onebit = false, .polltransfer = true, + .waitsem = SEM_INITIALIZER(0), }; /**************************************************************************** @@ -2956,10 +2957,6 @@ struct sdio_dev_s *sdio_initialize(int slotno) struct mpfs_dev_s *priv = NULL; priv = &g_emmcsd_dev; - /* Initialize semaphores */ - - nxsem_init(&priv->waitsem, 0, 0); - /* Reset the card and assure that it is in the initial, unconfigured * state. */ diff --git a/arch/x86_64/src/intel64/intel64_rng.c b/arch/x86_64/src/intel64/intel64_rng.c index 5440c0d5de..957be6a0bc 100644 --- a/arch/x86_64/src/intel64/intel64_rng.c +++ b/arch/x86_64/src/intel64/intel64_rng.c @@ -31,7 +31,6 @@ #include #include -#include #include #include @@ -48,21 +47,10 @@ static int x86_rng_initialize(void); static ssize_t x86_rngread(struct file *filep, char *buffer, size_t); -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct rng_dev_s -{ - sem_t rd_readsem; /* To block until the buffer is filled NOT used */ -}; - /**************************************************************************** * Private Data ****************************************************************************/ -static struct rng_dev_s g_rngdev; - static const struct file_operations g_rngops = { NULL, /* open */ @@ -88,8 +76,6 @@ static const struct file_operations g_rngops = static int x86_rng_initialize(void) { _info("Initializing RNG\n"); - - memset(&g_rngdev, 0, sizeof(struct rng_dev_s)); return OK; } diff --git a/arch/xtensa/src/esp32/esp32_i2s.c b/arch/xtensa/src/esp32/esp32_i2s.c index abb34f0439..876499f963 100644 --- a/arch/xtensa/src/esp32/esp32_i2s.c +++ b/arch/xtensa/src/esp32/esp32_i2s.c @@ -413,7 +413,9 @@ static struct esp32_i2s_s esp32_i2s0_priv = { .ops = &g_i2sops }, - .config = &esp32_i2s0_config + .lock = NXMUTEX_INITIALIZER, + .config = &esp32_i2s0_config, + .bufsem = SEM_INITIALIZER(0), }; #endif /* CONFIG_ESP32_I2S0 */ @@ -472,7 +474,9 @@ static struct esp32_i2s_s esp32_i2s1_priv = { .ops = &g_i2sops }, - .config = &esp32_i2s1_config + .lock = NXMUTEX_INITIALIZER, + .config = &esp32_i2s1_config, + .bufsem = SEM_INITIALIZER(0), }; #endif /* CONFIG_ESP32_I2S1 */ @@ -616,14 +620,6 @@ static int i2s_buf_initialize(struct esp32_i2s_s *priv) priv->tx.carry.value = 0; priv->bf_freelist = NULL; - ret = nxsem_init(&priv->bufsem, 0, 0); - - if (ret < 0) - { - i2serr("ERROR: nxsem_init failed: %d\n", ret); - return ret; - } - for (int i = 0; i < CONFIG_ESP32_I2S_MAXINFLIGHT; i++) { i2s_buf_free(priv, &priv->containers[i]); @@ -1902,8 +1898,6 @@ struct i2s_dev_s *esp32_i2sbus_initialize(int port) flags = spin_lock_irqsave(&priv->slock); - nxmutex_init(&priv->lock); - i2s_configure(priv); /* Allocate buffer containers */ @@ -1937,8 +1931,7 @@ struct i2s_dev_s *esp32_i2sbus_initialize(int port) /* Failure exit */ err: - spin_unlock_irqrestore(&priv->slock, flags); - nxmutex_destroy(&priv->lock); + spin_unlock_irqrestore(&priv->lock, flags); return NULL; } diff --git a/arch/xtensa/src/esp32/esp32_rng.c b/arch/xtensa/src/esp32/esp32_rng.c index 48cf1085fc..d1193381cb 100644 --- a/arch/xtensa/src/esp32/esp32_rng.c +++ b/arch/xtensa/src/esp32/esp32_rng.c @@ -58,7 +58,6 @@ * Private Function Prototypes ****************************************************************************/ -static int esp32_rng_initialize(void); static ssize_t esp32_rng_read(struct file *filep, char *buffer, size_t buflen); /**************************************************************************** @@ -75,7 +74,10 @@ struct rng_dev_s * Private Data ****************************************************************************/ -static struct rng_dev_s g_rngdev; +static struct rng_dev_s g_rngdev = +{ + .rd_lock = NXMUTEX_INITIALIZER, +}; static const struct file_operations g_rngops = { @@ -122,20 +124,6 @@ uint32_t IRAM_ATTR esp_random(void) return result ^ getreg32(WDEV_RND_REG); } -/**************************************************************************** - * Name: esp32_rng_initialize - ****************************************************************************/ - -static int esp32_rng_initialize(void) -{ - _info("Initializing RNG\n"); - - memset(&g_rngdev, 0, sizeof(struct rng_dev_s)); - nxmutex_init(&g_rngdev.rd_lock); - - return OK; -} - /**************************************************************************** * Name: esp32_rng_read ****************************************************************************/ @@ -194,7 +182,6 @@ static ssize_t esp32_rng_read(struct file *filep, char *buffer, #ifdef CONFIG_DEV_RANDOM void devrandom_register(void) { - esp32_rng_initialize(); register_driver("/dev/random", &g_rngops, 0444, NULL); } #endif @@ -216,9 +203,6 @@ void devrandom_register(void) #ifdef CONFIG_DEV_URANDOM_ARCH void devurandom_register(void) { -#ifndef CONFIG_DEV_RANDOM - esp32_rng_initialize(); -#endif register_driver("/dev/urandom", &g_rngops, 0444, NULL); } #endif diff --git a/arch/xtensa/src/esp32/esp32_rt_timer.c b/arch/xtensa/src/esp32/esp32_rt_timer.c index 34f3c21673..ce7212b933 100644 --- a/arch/xtensa/src/esp32/esp32_rt_timer.c +++ b/arch/xtensa/src/esp32/esp32_rt_timer.c @@ -83,7 +83,8 @@ struct esp32_rt_priv_s static struct esp32_rt_priv_s g_rt_priv = { - .pid = INVALID_PROCESS_ID + .pid = INVALID_PROCESS_ID, + .toutsem = SEM_INITIALIZER(0), }; /**************************************************************************** @@ -690,8 +691,6 @@ int esp32_rt_timer_init(void) return -EINVAL; } - nxsem_init(&priv->toutsem, 0, 0); - pid = kthread_create(RT_TIMER_TASK_NAME, RT_TIMER_TASK_PRIORITY, RT_TIMER_TASK_STACK_SIZE, @@ -765,7 +764,5 @@ void esp32_rt_timer_deinit(void) kthread_delete(priv->pid); priv->pid = INVALID_PROCESS_ID; } - - nxsem_destroy(&priv->toutsem); } diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 74ef017550..33067719ff 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -202,10 +202,10 @@ */ #ifdef USE_DMA0 -static sem_t g_dma0_sem; +static sem_t g_dma0_sem = SEM_INITIALIZER(1); #endif #ifdef USE_DMA1 -static sem_t g_dma1_sem; +static sem_t g_dma1_sem = SEM_INITIALIZER(1); #endif /* UART DMA RX/TX descriptors */ @@ -2079,12 +2079,10 @@ void xtensa_serialinit(void) #ifdef CONFIG_SERIAL_TXDMA #ifdef USE_DMA0 - nxsem_init(&g_dma0_sem, 0, 1); dma_config(0); dma_attach(0); #endif #ifdef USE_DMA1 - nxsem_init(&g_dma1_sem, 0, 1); dma_config(1); dma_attach(1); #endif diff --git a/arch/xtensa/src/esp32/esp32_wifi_utils.c b/arch/xtensa/src/esp32/esp32_wifi_utils.c index 01507ce254..392fae49bc 100644 --- a/arch/xtensa/src/esp32/esp32_wifi_utils.c +++ b/arch/xtensa/src/esp32/esp32_wifi_utils.c @@ -87,7 +87,10 @@ struct wifi_scan_result * Private Data ****************************************************************************/ -static struct wifi_scan_result g_scan_priv; +static struct wifi_scan_result g_scan_priv = +{ + .scan_signal = SEM_INITIALIZER(0), +}; static uint8_t g_channel_num = 0; static uint8_t g_channel_list[CHANNEL_MAX_NUM]; @@ -540,37 +543,3 @@ scan_result_full: priv->scan_status = ESP_SCAN_DONE; nxsem_post(&priv->scan_signal); } - -/**************************************************************************** - * Name: esp_wifi_scan_init - * - * Description: - * Initialize ESP32 Wi-Fi scan parameter. - * - * Input Parameters: - * None - * - * Returned Value: - * OK is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp_wifi_scan_init(void) -{ - int ret; - struct wifi_scan_result *scan_priv = &g_scan_priv; - - /* Initialize the scan structure */ - - memset(scan_priv, 0, sizeof(*scan_priv)); - - /* Init scan signal */ - - if ((ret = nxsem_init(&scan_priv->scan_signal, 0, 0)) != OK) - { - wlerr("ERROR: Initialization scan signal failed: %d\n", ret); - return ret; - } - - return ret; -} diff --git a/arch/xtensa/src/esp32/esp32_wifi_utils.h b/arch/xtensa/src/esp32/esp32_wifi_utils.h index 958d5a483e..0ef37848f9 100644 --- a/arch/xtensa/src/esp32/esp32_wifi_utils.h +++ b/arch/xtensa/src/esp32/esp32_wifi_utils.h @@ -95,22 +95,6 @@ int esp_wifi_get_scan_results(struct iwreq *iwr); void esp_wifi_scan_event_parse(void); -/**************************************************************************** - * Name: esp_wifi_scan_para - * - * Description: - * Initialize ESP32 Wi-Fi scan parameter. - * - * Input Parameters: - * None - * - * Returned Value: - * OK is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp_wifi_scan_init(void); - #ifdef __cplusplus } #endif diff --git a/arch/xtensa/src/esp32/esp32_wlan.c b/arch/xtensa/src/esp32/esp32_wlan.c index 6a84ba1933..9a5c71d93a 100644 --- a/arch/xtensa/src/esp32/esp32_wlan.c +++ b/arch/xtensa/src/esp32/esp32_wlan.c @@ -1776,13 +1776,6 @@ int esp32_wlan_sta_initialize(void) eth_mac[0], eth_mac[1], eth_mac[2], eth_mac[3], eth_mac[4], eth_mac[5]); - ret = esp_wifi_scan_init(); - if (ret < 0) - { - nerr("ERROR: Initialize Wi-Fi scan parameter error: %d\n", ret); - return ret; - } - ret = esp32_net_initialize(ESP32_WLAN_STA_DEVNO, eth_mac, &g_sta_ops); if (ret < 0) { @@ -1843,13 +1836,6 @@ int esp32_wlan_softap_initialize(void) eth_mac[0], eth_mac[1], eth_mac[2], eth_mac[3], eth_mac[4], eth_mac[5]); - ret = esp_wifi_scan_init(); - if (ret < 0) - { - nerr("ERROR: Initialize Wi-Fi scan parameter error: %d\n", ret); - return ret; - } - ret = esp32_net_initialize(ESP32_WLAN_SOFTAP_DEVNO, eth_mac, &g_softap_ops); if (ret < 0) diff --git a/arch/xtensa/src/esp32s2/esp32s2_i2s.c b/arch/xtensa/src/esp32s2/esp32s2_i2s.c index 6260e912e3..8bd48262c9 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_i2s.c +++ b/arch/xtensa/src/esp32s2/esp32s2_i2s.c @@ -396,7 +396,9 @@ static struct esp32s2_i2s_s esp32s2_i2s0_priv = { .ops = &g_i2sops }, - .config = &esp32s2_i2s0_config + .lock = NXMUTEX_INITIALIZER, + .config = &esp32s2_i2s0_config, + .bufsem = SEM_INITIALIZER(0) }; #endif /* CONFIG_ESP32S2_I2S */ @@ -534,19 +536,10 @@ static void i2s_buf_free(struct esp32s2_i2s_s *priv, static int i2s_buf_initialize(struct esp32s2_i2s_s *priv) { - int ret; - priv->tx.carry.bytes = 0; priv->tx.carry.value = 0; priv->bf_freelist = NULL; - ret = nxsem_init(&priv->bufsem, 0, 0); - - if (ret < 0) - { - i2serr("ERROR: nxsem_init failed: %d\n", ret); - return ret; - } for (int i = 0; i < CONFIG_ESP32S2_I2S_MAXINFLIGHT; i++) { @@ -1747,8 +1740,6 @@ struct i2s_dev_s *esp32s2_i2sbus_initialize(void) flags = enter_critical_section(); - nxmutex_init(&priv->lock); - i2s_configure(priv); /* Allocate buffer containers */ @@ -1783,7 +1774,6 @@ struct i2s_dev_s *esp32s2_i2sbus_initialize(void) err: leave_critical_section(flags); - nxmutex_destroy(&priv->lock); return NULL; } diff --git a/arch/xtensa/src/esp32s2/esp32s2_rng.c b/arch/xtensa/src/esp32s2/esp32s2_rng.c index c9ef15c77d..4417b35280 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_rng.c +++ b/arch/xtensa/src/esp32s2/esp32s2_rng.c @@ -59,7 +59,6 @@ * Private Function Prototypes ****************************************************************************/ -static int esp32s2_rng_initialize(void); static ssize_t esp32s2_rng_read(struct file *filep, char *buffer, size_t buflen); @@ -77,7 +76,10 @@ struct rng_dev_s * Private Data ****************************************************************************/ -static struct rng_dev_s g_rngdev; +static struct rng_dev_s g_rngdev = +{ + .rd_lock = NXMUTEX_INITIALIZER, +}; static const struct file_operations g_rngops = { @@ -124,16 +126,6 @@ uint32_t IRAM_ATTR esp_random(void) return result ^ getreg32(WDEV_RND_REG); } -static int esp32s2_rng_initialize(void) -{ - _info("Initializing RNG\n"); - - memset(&g_rngdev, 0, sizeof(struct rng_dev_s)); - nxmutex_init(&g_rngdev.rd_lock); - - return OK; -} - /**************************************************************************** * Name: esp32s2_rng_read ****************************************************************************/ @@ -192,7 +184,6 @@ static ssize_t esp32s2_rng_read(struct file *filep, char *buffer, #ifdef CONFIG_DEV_RANDOM void devrandom_register(void) { - esp32s2_rng_initialize(); register_driver("/dev/random", &g_rngops, 0444, NULL); } #endif @@ -214,9 +205,6 @@ void devrandom_register(void) #ifdef CONFIG_DEV_URANDOM_ARCH void devurandom_register(void) { -#ifndef CONFIG_DEV_RANDOM - esp32s2_rng_initialize(); -#endif register_driver("dev/urandom", &g_rngops, 0444, NULL); } #endif diff --git a/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c b/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c index 86e2161d37..a0e668913d 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c +++ b/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c @@ -88,6 +88,7 @@ struct esp32s2_rt_priv_s static struct esp32s2_rt_priv_s g_rt_priv = { .pid = INVALID_PROCESS_ID, + .toutsem = SEM_INITIALIZER(0), }; /**************************************************************************** @@ -735,8 +736,6 @@ int esp32s2_rt_timer_init(void) return -EINVAL; } - nxsem_init(&priv->toutsem, 0, 0); - pid = kthread_create(RT_TIMER_TASK_NAME, RT_TIMER_TASK_PRIORITY, RT_TIMER_TASK_STACK_SIZE, @@ -837,6 +836,4 @@ void esp32s2_rt_timer_deinit(void) kthread_delete(priv->pid); priv->pid = INVALID_PROCESS_ID; } - - nxsem_destroy(&priv->toutsem); } diff --git a/arch/xtensa/src/esp32s2/esp32s2_spi.c b/arch/xtensa/src/esp32s2/esp32s2_spi.c index 70aa470cfa..990d91bf4d 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_spi.c +++ b/arch/xtensa/src/esp32s2/esp32s2_spi.c @@ -1431,9 +1431,6 @@ static void esp32s2_spi_init(struct spi_dev_s *dev) SPI_USER1_REG(id)); #if defined(CONFIG_ESP32S2_SPI2_DMA) || defined(CONFIG_ESP32S2_SPI3_DMA) - nxsem_init(&priv->sem_isr, 0, 0); - nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE); - esp32s2_spi_dma_init(dev); #endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c b/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c index 52d9f669fa..305389c124 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c +++ b/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c @@ -91,9 +91,10 @@ struct esp32s3_rt_priv_s static struct esp32s3_rt_priv_s g_rt_priv = { - .pid = INVALID_PROCESS_ID, - .cpuint = -ENOMEM, - .core = -ENODEV + .pid = INVALID_PROCESS_ID, + .cpuint = -ENOMEM, + .core = -ENODEV, + .toutsem = SEM_INITIALIZER(0), }; /**************************************************************************** @@ -945,8 +946,6 @@ int esp32s3_rt_timer_init(void) irqstate_t flags; struct esp32s3_rt_priv_s *priv = &g_rt_priv; - nxsem_init(&priv->toutsem, 0, 0); - pid = kthread_create(RT_TIMER_TASK_NAME, RT_TIMER_TASK_PRIORITY, RT_TIMER_TASK_STACK_SIZE, @@ -1049,6 +1048,4 @@ void esp32s3_rt_timer_deinit(void) kthread_delete(priv->pid); priv->pid = INVALID_PROCESS_ID; } - - nxsem_destroy(&priv->toutsem); } diff --git a/arch/z16/src/z16f/z16f_espi.c b/arch/z16/src/z16f/z16f_espi.c index b12cb77e8b..531f6f1447 100644 --- a/arch/z16/src/z16f/z16f_espi.c +++ b/arch/z16/src/z16f/z16f_espi.c @@ -49,10 +49,10 @@ struct z16f_spi_s { struct spi_dev_s spi; /* Externally visible part of the SPI interface */ + mutex_t lock; /* Assures mutually exclusive access to SPI */ bool initialized; /* TRUE: Controller has been initialized */ uint8_t nbits; /* Width of word in bits (1-8) */ uint8_t mode; /* Mode 0,1,2,3 */ - mutex_t lock; /* Assures mutually exclusive access to SPI */ uint32_t frequency; /* Requested clock frequency */ uint32_t actual; /* Actual clock frequency */ @@ -144,7 +144,13 @@ static const struct spi_ops_s g_epsiops = /* ESPI driver state */ -static struct z16f_spi_s g_espi; +static struct z16f_spi_s g_espi = +{ + { + &g_epsiops + }, + NXMUTEX_INITIALIZER +}; /**************************************************************************** * Public Data @@ -792,8 +798,6 @@ FAR struct spi_dev_s *z16_spibus_initialize(int port) /* Initialize the ESPI state structure */ flags = enter_critical_section(); - priv->spi.ops = &g_epsiops; - nxmutex_init(&priv->lock); /* Set up the SPI pin configuration (board-specific logic is required * to configure and manage all chip selects). diff --git a/arch/z80/src/ez80/ez80_i2c.c b/arch/z80/src/ez80/ez80_i2c.c index 8b80c2d089..db633c169e 100644 --- a/arch/z80/src/ez80/ez80_i2c.c +++ b/arch/z80/src/ez80/ez80_i2c.c @@ -89,8 +89,8 @@ static int ez80_i2c_transfer(FAR struct i2c_master_s *dev, * Private Data ****************************************************************************/ -static bool g_initialized; /* true:I2C has been initialized */ -static mutex_t g_i2clock; /* Serialize I2C transfers */ +static bool g_initialized; /* true:I2C has been initialized */ +static mutex_t g_i2clock = NXMUTEX_INITIALIZER; /* Serialize I2C transfers */ const struct i2c_ops_s g_ops = { @@ -912,10 +912,6 @@ FAR struct i2c_master_s *ez80_i2cbus_initialize(int port) * SCL/SDA are not multiplexed */ - /* This mutex enforces serialized access for I2C transfers */ - - nxmutex_init(&g_i2clock); - /* Enable I2C -- but not interrupts */ regval = inp(EZ80_I2C_CTL); diff --git a/arch/z80/src/ez80/ez80_rtc_lowerhalf.c b/arch/z80/src/ez80/ez80_rtc_lowerhalf.c index 63f590e4d4..9519dc73af 100644 --- a/arch/z80/src/ez80/ez80_rtc_lowerhalf.c +++ b/arch/z80/src/ez80/ez80_rtc_lowerhalf.c @@ -135,7 +135,8 @@ static const struct rtc_ops_s g_rtc_ops = static struct ez80_lowerhalf_s g_rtc_lowerhalf = { - &g_rtc_ops /* ops */ + &g_rtc_ops, /* ops */ + NXMUTEX_INITIALIZER, }; /**************************************************************************** @@ -569,7 +570,6 @@ static int ez80_rdalarm(FAR struct rtc_lowerhalf_s *lower, FAR struct rtc_lowerhalf_s *ez80_rtc_lowerhalf(void) { - nxmutex_init(&g_rtc_lowerhalf.devlock); return (FAR struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/z80/src/z8/z8_i2c.c b/arch/z80/src/z8/z8_i2c.c index abaaafa3a1..099ccfc772 100644 --- a/arch/z80/src/z8/z8_i2c.c +++ b/arch/z80/src/z8/z8_i2c.c @@ -95,10 +95,10 @@ extern uint32_t get_freq(void); * Private Data ****************************************************************************/ -static bool g_initialized; /* true:I2C has been initialized */ -static mutex_t g_i2clock; /* Serialize I2C transfers */ +static bool g_initialized; /* true:I2C has been initialized */ +static mutex_t g_i2clock = NXMUTEX_INITIALIZER; /* Serialize I2C transfers */ -const struct i2c_ops_s g_ops = +static const struct i2c_ops_s g_ops = { z8_i2c_transfer, #ifdef CONFIG_I2C_RESET @@ -631,10 +631,6 @@ FAR struct i2c_master_s *z8_i2cbus_initialize(int port) PAADDR = 0x02; PACTL |= 0xc0; - /* This mutex enforces serialized access for I2C transfers */ - - nxmutex_init(&g_i2clock); - /* Enable I2C -- no interrupts */ I2CCTL = I2C_CTL_IEN; diff --git a/boards/arm/cxd56xx/common/src/cxd56_imageproc.c b/boards/arm/cxd56xx/common/src/cxd56_imageproc.c index 92f112a84b..9ef611093b 100644 --- a/boards/arm/cxd56xx/common/src/cxd56_imageproc.c +++ b/boards/arm/cxd56xx/common/src/cxd56_imageproc.c @@ -209,10 +209,10 @@ struct aligned_data(16) ge2d_abcmd_s ****************************************************************************/ static bool g_imageprocinitialized = false; -static sem_t g_rotwait; -static mutex_t g_rotlock; -static mutex_t g_gelock; -static mutex_t g_ablock; +static sem_t g_rotwait = SEM_INITIALIZER(0); +static mutex_t g_rotlock = NXMUTEX_INITIALIZER; +static mutex_t g_gelock = NXMUTEX_INITIALIZER; +static mutex_t g_ablock = NXMUTEX_INITIALIZER; static struct file g_gfile; static char g_gcmdbuf[256] aligned_data(16); @@ -551,14 +551,7 @@ void imageproc_initialize(void) } g_imageprocinitialized = true; - - nxmutex_init(&g_rotlock); - nxsem_init(&g_rotwait, 0, 0); - nxmutex_init(&g_gelock); - nxmutex_init(&g_ablock); - cxd56_ge2dinitialize(GEDEVNAME); - file_open(&g_gfile, GEDEVNAME, O_RDWR); putreg32(1, ROT_INTR_CLEAR); @@ -585,12 +578,6 @@ void imageproc_finalize(void) } cxd56_ge2duninitialize(GEDEVNAME); - - nxsem_destroy(&g_rotwait); - nxmutex_destroy(&g_rotlock); - nxmutex_destroy(&g_gelock); - nxmutex_destroy(&g_ablock); - g_imageprocinitialized = false; } diff --git a/boards/arm/samv7/samv71-xult/src/sam_ili9488.c b/boards/arm/samv7/samv71-xult/src/sam_ili9488.c index bc9f58d7ea..c66b60fce9 100644 --- a/boards/arm/samv7/samv71-xult/src/sam_ili9488.c +++ b/boards/arm/samv7/samv71-xult/src/sam_ili9488.c @@ -490,6 +490,7 @@ static struct sam_dev_s g_lcddev = .getcontrast = sam_getcontrast, .setcontrast = sam_setcontrast, }, + .waitsem = SEM_INITIALIZER(0), }; /**************************************************************************** @@ -1562,18 +1563,13 @@ int board_lcd_initialize(void) sam_smc_initialize(); - /* Initialize the LCD state structure */ - - nxsem_init(&priv->waitsem, 0, 0); - /* Allocate a DMA channel */ priv->dmach = sam_dmachannel(0, DMA_FLAGS); if (!priv->dmach) { lcderr("ERROR: Failed to allocate a DMA channel\n"); - ret = -EAGAIN; - goto errout_with_waitsem; + return -EAGAIN; } /* Identify and configure the LCD */ @@ -1604,9 +1600,6 @@ int board_lcd_initialize(void) errout_with_dmach: sam_dmafree(priv->dmach); priv->dmach = NULL; - -errout_with_waitsem: - nxsem_destroy(&priv->waitsem); return ret; } @@ -1648,7 +1641,6 @@ void board_lcd_uninitialize(void) /* Free other resources */ wd_cancel(&priv->dmadog); - nxsem_destroy(&priv->waitsem); /* Put the LCD in the lowest possible power state */ diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c b/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c index fbda2fec7b..1f8fb1f640 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c +++ b/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c @@ -68,7 +68,7 @@ static void *g_chmediaarg; /* Semafor to inform stm32_cd_thread that card was inserted or pulled out */ -static sem_t g_cdsem; +static sem_t g_cdsem = SEM_INITIALIZER(0); /**************************************************************************** * Private Functions @@ -185,9 +185,7 @@ int stm32_mmcsd_initialize(int minor) stm32_gpiosetevent(GPIO_SD_CD, true, true, true, stm32_cd, NULL); - nxsem_init(&g_cdsem, 0, 0); pthread_attr_init(&pattr); - #ifdef CONFIG_DEBUG_FS pthread_attr_setstacksize(&pattr, 1024); #else diff --git a/crypto/random_pool.c b/crypto/random_pool.c index e864d4130b..9348dbfe0b 100644 --- a/crypto/random_pool.c +++ b/crypto/random_pool.c @@ -89,7 +89,10 @@ enum * Private Data ****************************************************************************/ -static struct rng_s g_rng; +static struct rng_s g_rng = +{ + NXMUTEX_INITIALIZER, +}; #ifdef CONFIG_BOARD_ENTROPY_POOL /* Entropy pool structure can be provided by board source. Use for this is, @@ -357,21 +360,6 @@ static void rng_buf_internal(FAR uint8_t *bytes, size_t nbytes) } } -static void rng_init(void) -{ - cryptinfo("Initializing RNG\n"); - - memset(&g_rng, 0, sizeof(struct rng_s)); - nxmutex_init(&g_rng.rd_lock); - - /* We do not initialize output here because this is called - * quite early in boot and there may not be enough entropy. - * - * Board level may define CONFIG_BOARD_INITRNGSEED if it implements - * early random seeding. - */ -} - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -517,8 +505,6 @@ void up_rngreseed(void) void up_randompool_initialize(void) { - rng_init(); - #ifdef CONFIG_BOARD_INITRNGSEED board_init_rngseed(); #endif diff --git a/drivers/net/tun.c b/drivers/net/tun.c index df6450e542..359b7a4648 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -148,8 +148,8 @@ struct tun_device_s struct tun_driver_s { - uint8_t free_tuns; mutex_t lock; + uint8_t free_tuns; }; /**************************************************************************** @@ -205,7 +205,11 @@ static int tun_poll(FAR struct file *filep, FAR struct pollfd *fds, * Private Data ****************************************************************************/ -static struct tun_driver_s g_tun; +static struct tun_driver_s g_tun = +{ + NXMUTEX_INITIALIZER, +}; + static struct tun_device_s g_tun_devices[CONFIG_TUN_NINTERFACES]; static const struct file_operations g_tun_file_ops = @@ -1315,10 +1319,7 @@ static int tun_ioctl(FAR struct file *filep, int cmd, unsigned long arg) int tun_initialize(void) { - nxmutex_init(&g_tun.lock); - g_tun.free_tuns = (1 << CONFIG_TUN_NINTERFACES) - 1; - register_driver("/dev/tun", &g_tun_file_ops, 0644, &g_tun); return OK; } diff --git a/drivers/serial/ptmx.c b/drivers/serial/ptmx.c index e8a245168b..e54cd2a277 100644 --- a/drivers/serial/ptmx.c +++ b/drivers/serial/ptmx.c @@ -63,8 +63,8 @@ struct ptmx_dev_s { - uint8_t px_next; /* Next minor number to allocate */ mutex_t px_lock; /* Supports mutual exclusion */ + uint8_t px_next; /* Next minor number to allocate */ uint32_t px_alloctab[INDEX_MAX]; /* Set of allocated PTYs */ }; @@ -96,7 +96,10 @@ static const struct file_operations g_ptmx_fops = #endif }; -static struct ptmx_dev_s g_ptmx; +static struct ptmx_dev_s g_ptmx = +{ + NXMUTEX_INITIALIZER, +}; /**************************************************************************** * Private Functions @@ -275,10 +278,6 @@ static ssize_t ptmx_write(FAR struct file *filep, int ptmx_register(void) { - /* Initialize driver state */ - - nxmutex_init(&g_ptmx.px_lock); - /* Register the PTMX driver */ return register_driver("/dev/ptmx", &g_ptmx_fops, 0666, NULL); diff --git a/drivers/usbhost/usbhost_hidkbd.c b/drivers/usbhost/usbhost_hidkbd.c index 7279d3c367..6664ded5b5 100644 --- a/drivers/usbhost/usbhost_hidkbd.c +++ b/drivers/usbhost/usbhost_hidkbd.c @@ -353,8 +353,8 @@ static uint32_t g_devinuse; /* The following are used to managed the class creation operation */ -static mutex_t g_lock; /* For mutually exclusive thread creation */ -static sem_t g_syncsem; /* Thread data passing interlock */ +static mutex_t g_lock = NXMUTEX_INITIALIZER; +static sem_t g_syncsem = SEM_INITIALIZER(0); static struct usbhost_state_s *g_priv; /* Data passed to thread */ /* The following tables map keyboard scan codes to printable ASIC @@ -2443,11 +2443,6 @@ errout: int usbhost_kbdinit(void) { - /* Perform any one-time initialization of the class implementation */ - - nxmutex_init(&g_lock); - nxsem_init(&g_syncsem, 0, 0); - /* Advertise our availability to support (certain) devices */ return usbhost_registerclass(&g_hidkbd); diff --git a/drivers/usbhost/usbhost_hidmouse.c b/drivers/usbhost/usbhost_hidmouse.c index 3b1ad6d2da..91eb387056 100644 --- a/drivers/usbhost/usbhost_hidmouse.c +++ b/drivers/usbhost/usbhost_hidmouse.c @@ -403,8 +403,8 @@ static uint32_t g_devinuse; /* The following are used to managed the class creation operation */ -static mutex_t g_lock; /* For mutually exclusive thread creation */ -static sem_t g_syncsem; /* Thread data passing interlock */ +static mutex_t g_lock = NXMUTEX_INITIALIZER; +static sem_t g_syncsem = SEM_INITIALIZER(0); static struct usbhost_state_s *g_priv; /* Data passed to thread */ /**************************************************************************** @@ -2436,11 +2436,6 @@ errout: int usbhost_mouse_init(void) { - /* Perform any one-time initialization of the class implementation */ - - nxmutex_init(&g_lock); - nxsem_init(&g_syncsem, 0, 0); - /* Advertise our availability to support (certain) mouse devices */ return usbhost_registerclass(&g_hidmouse); diff --git a/drivers/usbhost/usbhost_xboxcontroller.c b/drivers/usbhost/usbhost_xboxcontroller.c index bfc91730df..143ce39405 100644 --- a/drivers/usbhost/usbhost_xboxcontroller.c +++ b/drivers/usbhost/usbhost_xboxcontroller.c @@ -308,8 +308,8 @@ static uint32_t g_devinuse; /* The following are used to managed the class creation operation */ -static mutex_t g_lock; /* For mutually exclusive thread creation */ -static sem_t g_syncsem; /* Thread data passing interlock */ +static mutex_t g_lock = NXMUTEX_INITIALIZER; +static sem_t g_syncsem = SEM_INITIALIZER(0); static struct usbhost_state_s *g_priv; /* Data passed to thread */ /**************************************************************************** @@ -2197,11 +2197,6 @@ errout: int usbhost_xboxcontroller_init(void) { - /* Perform any one-time initialization of the class implementation */ - - nxmutex_init(&g_lock); - nxsem_init(&g_syncsem, 0, 0); - /* Advertise our availability to support (certain) devices */ return usbhost_registerclass(&g_xboxcontroller); diff --git a/drivers/video/isx012.c b/drivers/video/isx012.c index 19e21b2984..242e41b015 100644 --- a/drivers/video/isx012.c +++ b/drivers/video/isx012.c @@ -262,7 +262,10 @@ static int isx012_set_value * Private Data ****************************************************************************/ -static isx012_dev_t g_isx012_private; +static isx012_dev_t g_isx012_private = +{ + NXMUTEX_INITIALIZER, +}; #ifndef ISX012_NOT_USE_NSTBY static const isx012_reg_t g_isx012_presleep[] = @@ -3156,8 +3159,6 @@ int isx012_initialize(void) /* Initialize other information */ priv->state = STATE_ISX012_POWEROFF; - - nxmutex_init(&priv->i2c_lock); return OK; } diff --git a/drivers/video/isx019.c b/drivers/video/isx019.c index da3bddcdba..3acd9803b0 100644 --- a/drivers/video/isx019.c +++ b/drivers/video/isx019.c @@ -292,7 +292,11 @@ static int send_read_cmd(FAR struct i2c_config_s *config, * Private Data ****************************************************************************/ -static isx019_dev_t g_isx019_private; +static isx019_dev_t g_isx019_private = +{ + NXMUTEX_INITIALIZER, + NXMUTEX_INITIALIZER, +}; static struct imgsensor_ops_s g_isx019_ops = { @@ -3362,15 +3366,11 @@ static int isx019_set_value(uint32_t id, int isx019_initialize(void) { imgsensor_register(&g_isx019_ops); - nxmutex_init(&g_isx019_private.i2c_lock); - nxmutex_init(&g_isx019_private.fpga_lock); return OK; } int isx019_uninitialize(void) { - nxmutex_destroy(&g_isx019_private.i2c_lock); - nxmutex_destroy(&g_isx019_private.fpga_lock); return OK; } diff --git a/libs/libc/wqueue/work_usrthread.c b/libs/libc/wqueue/work_usrthread.c index cdc3d4d6c4..d04be2fe94 100644 --- a/libs/libc/wqueue/work_usrthread.c +++ b/libs/libc/wqueue/work_usrthread.c @@ -59,7 +59,12 @@ /* The state of the user mode work queue. */ -struct usr_wqueue_s g_usrwork; +struct usr_wqueue_s g_usrwork = +{ + {NULL, NULL}, + NXMUTEX_INITIALIZER, + SEM_INITIALIZER(0), +}; /**************************************************************************** * Private Functions @@ -278,13 +283,6 @@ int work_usrstart(void) struct sched_param param; #endif - /* Set up the work queue lock */ - - nxmutex_init(&g_usrwork.lock); - - _SEM_INIT(&g_usrwork.wake, 0, 0); - _SEM_SETPROTOCOL(&g_usrwork.wake, SEM_PRIO_NONE); - /* Initialize the work queue */ dq_init(&g_usrwork.q); diff --git a/net/tcp/tcp_wrbuffer.c b/net/tcp/tcp_wrbuffer.c index 00a884b86c..b53df7373a 100644 --- a/net/tcp/tcp_wrbuffer.c +++ b/net/tcp/tcp_wrbuffer.c @@ -73,7 +73,10 @@ struct wrbuffer_s /* This is the state of the global write buffer resource */ -static struct wrbuffer_s g_wrbuffer; +static struct wrbuffer_s g_wrbuffer = +{ + SEM_INITIALIZER(CONFIG_NET_TCP_NWRBCHAINS), +}; /**************************************************************************** * Public Functions @@ -98,8 +101,6 @@ void tcp_wrbuffer_initialize(void) { sq_addfirst(&g_wrbuffer.buffers[i].wb_node, &g_wrbuffer.freebuffers); } - - nxsem_init(&g_wrbuffer.sem, 0, CONFIG_NET_TCP_NWRBCHAINS); } /**************************************************************************** diff --git a/net/udp/udp_wrbuffer.c b/net/udp/udp_wrbuffer.c index 29cb3d1549..b4b14899a7 100644 --- a/net/udp/udp_wrbuffer.c +++ b/net/udp/udp_wrbuffer.c @@ -72,7 +72,10 @@ struct wrbuffer_s /* This is the state of the global write buffer resource */ -static struct wrbuffer_s g_wrbuffer; +static struct wrbuffer_s g_wrbuffer = +{ + SEM_INITIALIZER(CONFIG_NET_UDP_NWRBCHAINS) +}; /**************************************************************************** * Public Functions @@ -99,8 +102,6 @@ void udp_wrbuffer_initialize(void) { sq_addfirst(&g_wrbuffer.buffers[i].wb_node, &g_wrbuffer.freebuffers); } - - nxsem_init(&g_wrbuffer.sem, 0, CONFIG_NET_UDP_NWRBCHAINS); } /**************************************************************************** diff --git a/wireless/bluetooth/bt_ioctl.c b/wireless/bluetooth/bt_ioctl.c index 8f61e51838..a94f41ccaf 100644 --- a/wireless/bluetooth/bt_ioctl.c +++ b/wireless/bluetooth/bt_ioctl.c @@ -114,7 +114,10 @@ struct btnet_wrstate_s * the unharvested results. */ -static struct btnet_scanstate_s g_scanstate; +static struct btnet_scanstate_s g_scanstate = +{ + NXMUTEX_INITIALIZER, +}; /**************************************************************************** * Private Functions @@ -618,7 +621,6 @@ int btnet_ioctl(FAR struct net_driver_s *netdev, int cmd, unsigned long arg) { /* Initialize scan state */ - nxmutex_init(&g_scanstate.bs_lock); g_scanstate.bs_scanning = true; g_scanstate.bs_head = 0; g_scanstate.bs_tail = 0; @@ -629,7 +631,6 @@ int btnet_ioctl(FAR struct net_driver_s *netdev, int cmd, unsigned long arg) if (ret < 0) { - nxmutex_destroy(&g_scanstate.bs_lock); g_scanstate.bs_scanning = false; } } @@ -664,7 +665,6 @@ int btnet_ioctl(FAR struct net_driver_s *netdev, int cmd, unsigned long arg) ret = bt_stop_scanning(); wlinfo("Stop scanning: %d\n", ret); - nxmutex_destroy(&g_scanstate.bs_lock); g_scanstate.bs_scanning = false; } break; diff --git a/wireless/pktradio/pktradio_metadata.c b/wireless/pktradio/pktradio_metadata.c index 72199c8630..e3aa4a442f 100644 --- a/wireless/pktradio/pktradio_metadata.c +++ b/wireless/pktradio/pktradio_metadata.c @@ -49,7 +49,7 @@ static FAR struct pktradio_metadata_s *g_free_metadata; /* Supports mutually exclusive access to the free list */ -static mutex_t g_metadata_lock; +static mutex_t g_metadata_lock = NXMUTEX_INITIALIZER; /* Idempotence support */ @@ -103,9 +103,6 @@ void pktradio_metadata_initialize(void) g_free_metadata = metadata; } - /* Initialize the mutual exclusion mutex */ - - nxmutex_init(&g_metadata_lock); g_metadata_initialized = true; } }