PIC32MZ: Add interrupt controller support
This commit is contained in:
Gregory Nutt
parent
acef552fac
commit
d0940671cf
@ -195,7 +195,7 @@ void up_disable_irq(int irq)
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/* Disable the interrupt by clearing the associated bit in the IEC register */
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DEBUGASSERT(irq >= PIC32MX_IRQSRC_FIRST && irq <= PIC32MX_IRQSRC_LAST)
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DEBUGASSERT(irq >= PIC32MX_IRQSRC_FIRST && irq <= PIC32MX_IRQSRC_LAST);
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if (irq >= PIC32MX_IRQSRC_FIRST)
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{
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if (irq <= PIC32MX_IRQSRC0_LAST)
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@ -249,7 +249,7 @@ void up_enable_irq(int irq)
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/* Enable the interrupt by setting the associated bit in the IEC register */
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DEBUGASSERT(irq >= PIC32MX_IRQSRC_FIRST && irq <= PIC32MX_IRQSRC_LAST)
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DEBUGASSERT(irq >= PIC32MX_IRQSRC_FIRST && irq <= PIC32MX_IRQSRC_LAST);
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if (irq >= PIC32MX_IRQSRC_FIRST)
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{
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if (irq <= PIC32MX_IRQSRC0_LAST)
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@ -303,13 +303,12 @@ bool up_pending_irq(int irq)
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uint32_t regval;
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int bitno;
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/* Disable the interrupt by clearing the associated bit in the IEC and then
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* acknowledge the interrupt by clearing the associated bit in the IFS
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* register. It is necessary to do this BEFORE lowering the interrupt
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* priority level otherwise recursive interrupts would occur.
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/* Test if the interrupt is pending by reading both the IEC and IFS
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* register. Return true if the bit associated with the irq is both pending
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* the IFs and enabled in the IEC.
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*/
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DEBUGASSERT(irq >= PIC32MX_IRQSRC_FIRST && irq <= PIC32MX_IRQSRC_LAST)
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DEBUGASSERT(irq >= PIC32MX_IRQSRC_FIRST && irq <= PIC32MX_IRQSRC_LAST);
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if (irq >= PIC32MX_IRQSRC_FIRST)
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{
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if (irq <= PIC32MX_IRQSRC0_LAST)
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@ -374,7 +373,7 @@ void up_clrpend_irq(int irq)
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* priority level otherwise recursive interrupts would occur.
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*/
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DEBUGASSERT(irq >= PIC32MX_IRQSRC_FIRST && irq <= PIC32MX_IRQSRC_LAST)
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DEBUGASSERT(irq >= PIC32MX_IRQSRC_FIRST && irq <= PIC32MX_IRQSRC_LAST);
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if (irq >= PIC32MX_IRQSRC_FIRST)
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{
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if (irq <= PIC32MX_IRQSRC0_LAST)
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@ -407,7 +406,7 @@ void up_clrpend_irq(int irq)
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return;
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}
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/* Disable then acknowledge interrupt */
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/* Acknowledge the interrupt */
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putreg32((1 << bitno), regaddr);
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}
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@ -64,6 +64,6 @@ endif
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# Required PIC32MZ files
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CHIP_ASRCS =
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CHIP_CSRCS = pic32mz-lowinit.c
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CHIP_CSRCS = pic32mz-lowinit.c pic32mz-irq.c
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# Configuration-dependent PIC32MZ files
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@ -42,7 +42,6 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#include "pic32mz-memorymap.h"
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/****************************************************************************
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@ -117,7 +117,7 @@
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#define PIC32MZ_CVREF_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000e00) /* CVREF */
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#define PIC32MZ_OSC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001200) /* Oscillator */
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#define PIC32MZ_PPS_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001400) /* PPS */
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#define PIC32MZ_INTC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00010000) /* Interrupt Controller */
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#define PIC32MZ_INT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00010000) /* Interrupt Controller */
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#define PIC32MZ_DMA_K1BASE (PIC32MZ_SFR_K1BASE + 0x00011000) /* DMA */
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#define PIC32MZ_I2C_K1BASE (PIC32MZ_SFR_K1BASE + 0x00020000) /* I2C1-I2C5 */
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#define PIC32MZ_SPI_K1BASE (PIC32MZ_SFR_K1BASE + 0x00021000) /* SPI1-SPI6 */
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448
arch/mips/src/pic32mz/pic32mz-irq.c
Normal file
448
arch/mips/src/pic32mz/pic32mz-irq.c
Normal file
@ -0,0 +1,448 @@
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/****************************************************************************
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* arch/mips/src/pic32mz/pic32mz-irq.c
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include <arch/pic32mz/cp0.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "chip/pic32mz-int.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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#ifdef CONFIG_PIC32MZ_MVEC
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# error "Multi-vectors not supported"
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#endif
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/* Interrupt controller definitions *****************************************/
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/* Number of interrupt enable/interrupt status registers */
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#define INT_NREGS ((NR_IRQS + 31) >> 5)
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/****************************************************************************
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* Public Data
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****************************************************************************/
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volatile uint32_t *current_regs;
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: pic32mz_prioritize_irq
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****************************************************************************/
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#ifndef CONFIG_ARCH_IRQPRIO
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static int pic32mz_prioritize_irq(int irq, int priority);
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#else
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# define pic32mz_prioritize_irq(i,p) up_prioritize_irq(i,p)
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#endif
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/****************************************************************************
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* Name: pic32mz_ifs
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****************************************************************************/
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static uintptr_t pic32mz_ifs(int irq)
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{
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if ((unsigned)irq < NR_IRQS)
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{
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return PIC32MZ_INT_IFS(irq);
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}
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return 0;
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}
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/****************************************************************************
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* Name: pic32mz_ifsclr
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****************************************************************************/
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static uintptr_t pic32mz_ifsclr(int irq)
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{
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if ((unsigned)irq < NR_IRQS)
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{
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return PIC32MZ_INT_IFSCLR(irq);
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}
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return 0;
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}
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/****************************************************************************
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* Name: pic32mz_iec
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****************************************************************************/
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static uintptr_t pic32mz_iec(int irq)
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{
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if ((unsigned)irq < NR_IRQS)
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{
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return PIC32MZ_INT_IEC_OFFSET(irq);
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}
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return 0;
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}
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/****************************************************************************
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* Name: pic32mz_iecset
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****************************************************************************/
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static uintptr_t pic32mz_iecset(int irq)
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{
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if ((unsigned)irq < NR_IRQS)
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{
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return PIC32MZ_INT_IECSET_OFFSET(irq);
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}
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return 0;
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}
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/****************************************************************************
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* Name: pic32mz_iecclr
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****************************************************************************/
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static uintptr_t pic32mz_iecclr(int irq)
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{
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if ((unsigned)irq < NR_IRQS)
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{
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return PIC32MZ_INT_IECCLR_OFFSET(irq);
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}
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return 0;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_irqinitialize
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****************************************************************************/
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void up_irqinitialize(void)
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{
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uint32_t regval;
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int irq;
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/* Disable all interrupts */
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putreg32(0xffff, PIC32MZ_INT_IEC0CLR); /* Interrupts 0-31 */
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putreg32(0xffff, PIC32MZ_INT_IEC1CLR); /* Interrupts 32-63 */
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putreg32(0xffff, PIC32MZ_INT_IEC2CLR); /* Interrupts 64-95 */
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putreg32(0xffff, PIC32MZ_INT_IEC3CLR); /* Interrupts 96-127 */
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putreg32(0xffff, PIC32MZ_INT_IEC4CLR); /* Interrupts 128-159 */
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putreg32(0xffff, PIC32MZ_INT_IEC5CLR); /* Interrupts 160-191 */
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/* Set all interrupts to the default (middle) priority */
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for (irq = 0; irq < NR_IRQS; irq++)
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{
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(void)pic32mz_prioritize_irq(irq, (INT_IPC_MID_PRIORITY << 2));
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}
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/* Set the BEV bit in the STATUS register */
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regval = cp0_getstatus();
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regval |= CP0_STATUS_BEV;
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cp0_putstatus(regval);
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/* Set the EBASE value to the beginning of boot FLASH. In single-vector
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* mode, interrupt vectors should go to EBASE + 0x0200 0r 0xbfc00200.
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*/
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cp0_putebase(0xbfc00000);
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/* Set the INTCTL vector spacing to non-zero */
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cp0_putintctl(0x00000020);
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/* Set the IV bit in the CAUSE register */
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regval = cp0_getcause();
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regval |= CP0_CAUSE_IV;
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cp0_putcause(regval);
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/* Clear the EXL and BEV bits in the STATUS register */
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regval = cp0_getstatus();
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regval &= ~(CP0_STATUS_EXL | CP0_STATUS_BEV);
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cp0_putstatus(regval);
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/* Configure multi- or single- vector interrupts */
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#ifdef CONFIG_PIC32MZ_MVEC
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putreg32(INT_INTCON_MVEC, PIC32MZ_INT_INTCONSET);
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#else
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putreg32(INT_INTCON_MVEC, PIC32MZ_INT_INTCONCLR);
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#endif
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/* Initialize GPIO change notification handling */
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#ifdef CONFIG_GPIO_IRQ
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pic32mz_gpioirqinitialize();
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#endif
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/* Attach and enable software interrupts */
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irq_attach(PIC32MZ_IRQ_CS0, up_swint0);
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up_enable_irq(PIC32MZ_IRQ_CS0);
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/* currents_regs is non-NULL only while processing an interrupt */
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current_regs = NULL;
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/* And finally, enable interrupts */
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/* Interrupts are enabled by setting the IE bit in the CP0 status register */
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regval = 0;
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asm volatile("ei %0" : "=r"(regval));
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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/* Then enable all interrupt levels */
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irqrestore(CP0_STATUS_IM_ALL);
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#else
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/* Enable only software interrupts */
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irqrestore(CP0_STATUS_IM_SWINTS);
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#endif
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}
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/****************************************************************************
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* Name: up_disable_irq
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*
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* Description:
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* Disable the IRQ specified by 'irq'
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*
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****************************************************************************/
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void up_disable_irq(int irq)
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{
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uint32_t regaddr;
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int bitno;
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/* Disable the interrupt by clearing the associated bit in the IEC register */
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DEBUGASSERT((unsigned)irq < NR_IRQS)
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regaddr = pic32mz_iecclr(irq);
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bitno = (unsigned)irq & 31;
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DEBUGASSERT(regaddr);
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if (regaddr)
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{
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/* Disable the interrupt */
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putreg32((1 << bitno), regaddr);
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}
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}
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/****************************************************************************
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* Name: up_enable_irq
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*
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* Description:
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* Enable the IRQ specified by 'irq'
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*
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****************************************************************************/
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void up_enable_irq(int irq)
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{
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uint32_t regaddr;
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int bitno;
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/* Enable the interrupt by setting the associated bit in the IEC register */
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DEBUGASSERT((unsigned)irq < NR_IRQS);
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regaddr = pic32mz_iecset(irq);
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bitno = (unsigned)irq & 31;
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DEBUGASSERT(regaddr);
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if (regaddr)
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{
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/* Disable the interrupt */
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putreg32((1 << bitno), regaddr);
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}
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}
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/****************************************************************************
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* Name: up_pending_irq
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*
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* Description:
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* Return true if the interrupt is pending and unmasked.
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*
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****************************************************************************/
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bool up_pending_irq(int irq)
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{
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uintptr_t ifsaddr;
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uintptr_t iecaddr;
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uint32_t regval;
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int bitno;
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/* Test if the interrupt is pending by reading both the IEC and IFS
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* register. Return true if the bit associated with the irq is both pending
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* the IFs and enabled in the IEC.
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*/
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DEBUGASSERT((unsigned)irq < NR_IRQS);
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ifsaddr = pic32mz_ifs(irq);
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iecaddr = pic32mz_iec(irq);
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bitno = (unsigned)irq & 31;
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DEBUGASSERT(ifsaddr && iecaddr);
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if (ifsaddr && iecaddr)
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{
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/* Get the set of unmasked, pending interrupts. Return true if the
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* interrupt is pending and unmask.
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*/
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regval = getreg32(ifsaddr) & getreg32(iecaddr);
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return (regval & (1 << bitno)) != 0;
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}
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return false;
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}
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/****************************************************************************
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* Name: up_clrpend_irq
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*
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* Description:
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* Clear any pending interrupt
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*
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****************************************************************************/
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void up_clrpend_irq(int irq)
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{
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uintptr_t regaddr;
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int bitno;
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/* Acknowledge the interrupt by clearing the associated bit in the IFS
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* register. It is necessary to do this BEFORE lowering the interrupt
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* priority level otherwise recursive interrupts would occur.
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*/
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DEBUGASSERT((unsigned)irq < NR_IRQS);
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regaddr = pic32mz_ifsclr(irq);
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bitno = (unsigned)irq & 31;
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DEBUGASSERT(regaddr);
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if (regaddr)
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{
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/* Acknowledge the interrupt */
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putreg32((1 << bitno), regaddr);
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}
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}
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/****************************************************************************
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* Name: up_prioritize_irq
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*
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* Description:
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* Set the priority of an IRQ by setting the priority and sub-priority
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* fields in the PIC32MZ IPC registers. There are 12 IPC registers, IPC0
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* through IPC11. Each has sub-priority fields for 8 interrupts for a
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* total of 96 interrupts max.
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*
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* Each interrupt priority is represent by a group of 5 bits: a 3-bit
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* priority and a 2-bit sub-priority. These have different meanings to
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* the hardware. The priority is the priority level that is enabled
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* or masked by the IPL field of the CAUSE register. The sub-priority
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* only mediates ties when two interrupts with the same priority pend
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* simultaneously.
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*
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* In this function, we just treat this as a single 5-bit priority.
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* (MS 3-bits=priority; LS 2-bits=sub-priority).
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*
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* The 5-bit priority/sub-priority fields are arranged at byte boundaries
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* within each IPC register:
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*
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* xxxP PPSS xxxP PPSS xxxP PPSS xxxP PPSS
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*
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****************************************************************************/
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#ifndef CONFIG_ARCH_IRQPRIO
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static int pic32mz_prioritize_irq(int irq, int priority)
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#else
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int up_prioritize_irq(int irq, int priority)
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||||
#endif
|
||||
{
|
||||
int regndx;
|
||||
int shift;
|
||||
|
||||
/* Don't allow this function to be used for disabling interrupts. There is
|
||||
* no good reason for this restriction other than I want to make sure that
|
||||
* the 5-bit priority values passed to this function are *not* confused with
|
||||
* the 3-bit hardware priority values.
|
||||
*/
|
||||
|
||||
DEBUGASSERT((unsigned)irq < NR_IRQS && (unsigned)(priority >> 2) > 0);
|
||||
if (irq < NR_IRQS)
|
||||
{
|
||||
/* Get the index to the IPC register and the shift to the 5-bit priority
|
||||
* field for this IRQ.
|
||||
*/
|
||||
|
||||
regndx = irq >> 2; /* Range: 0-11 */
|
||||
shift = (irq & 3) << 3; /* {0, 8, 16, 24 } */
|
||||
|
||||
/* Set the new interrupt priority (momentarily disabling interrupts) */
|
||||
|
||||
putreg32(0x1f << shift, PIC32MZ_INT_IPCCLR(regndx));
|
||||
putreg32(priority << shift, PIC32MZ_INT_IPCSET(regndx));
|
||||
return OK;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user