Add CMSIS ITM header file and library
This commit is contained in:
Gregory Nutt
parent
d930f2cdbc
commit
d094fd1c19
176
arch/arm/src/armv7-m/itm.h
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176
arch/arm/src/armv7-m/itm.h
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@ -0,0 +1,176 @@
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/***********************************************************************************************
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* arch/arm/src/armv7-m/itm.h
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*
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* Copyright (c) 2009 - 2013 ARM LIMITED
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*
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* All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
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* Author: Pierre-noel Bouteville <pnb990@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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***********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV7_M_ITM_H
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#define __ARCH_ARM_SRC_ARMV7_M_ITM_H
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/***********************************************************************************************
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* Included Files
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***********************************************************************************************/
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#include <stdint.h>
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/***********************************************************************************************
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* Pre-processor Definitions
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***********************************************************************************************/
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/* Instrumentation Trace Macrocell Register (ITM) ase address. */
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#define ITM_BASE (0xe0000000ul)
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/* ITM port used : 0-31 */
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#define ITM_PORT(i) (ITM_BASE+(i*4)) /* Stimulus Port 32-bit */
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#define ITM_TER (ITM_BASE+0x0e00) /* Trace Enable Register */
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#define ITM_TPR (ITM_BASE+0x0e40) /* Trace Privilege Register */
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#define ITM_TCR (ITM_BASE+0x0e80) /* Trace Control Register */
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#define ITM_IWR (ITM_BASE+0x0ef8) /* Integration Write Register */
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#define ITM_IRR (ITM_BASE+0x0efc) /* Integration Read Register */
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#define ITM_IMCR (ITM_BASE+0x0f00) /* Integration Mode Control Register */
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#define ITM_LAR (ITM_BASE+0x0fb0) /* Lock Access Register */
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#define ITM_LSR (ITM_BASE+0x0fb4) /* Lock Status Register */
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#define ITM_PID4 (ITM_BASE+0x0fd0) /* Peripheral Identification Register #4 */
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#define ITM_PID5 (ITM_BASE+0x0fd4) /* Peripheral Identification Register #5 */
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#define ITM_PID6 (ITM_BASE+0x0fd8) /* Peripheral Identification Register #6 */
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#define ITM_PID7 (ITM_BASE+0x0fdc) /* Peripheral Identification Register #7 */
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#define ITM_PID0 (ITM_BASE+0x0fe0) /* Peripheral Identification Register #0 */
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#define ITM_PID1 (ITM_BASE+0x0fe4) /* Peripheral Identification Register #1 */
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#define ITM_PID2 (ITM_BASE+0x0fe8) /* Peripheral Identification Register #2 */
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#define ITM_PID3 (ITM_BASE+0x0fec) /* Peripheral Identification Register #3 */
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#define ITM_CID0 (ITM_BASE+0x0ff0) /* Component Identification Register #0 */
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#define ITM_CID1 (ITM_BASE+0x0ff4) /* Component Identification Register #1 */
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#define ITM_CID2 (ITM_BASE+0x0ff8) /* Component Identification Register #2 */
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#define ITM_CID3 (ITM_BASE+0x0ffc) /* Component Identification Register #3 */
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#define ITM_TPR_PRIVMASK_Pos 0 /* ITM TPR: PRIVMASK Position */
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#define ITM_TPR_PRIVMASK_Msk (0xful << ITM_TPR_PRIVMASK_Pos) /* ITM TPR: PRIVMASK Mask */
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#define ITM_TCR_BUSY_Pos 23 /* ITM TCR: BUSY Position */
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#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /* ITM TCR: BUSY Mask */
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#define ITM_TCR_TraceBusID_Pos 16 /* ITM TCR: ATBID Position */
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#define ITM_TCR_TraceBusID_Msk (0x7ful << ITM_TCR_TraceBusID_Pos) /* ITM TCR: ATBID Mask */
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#define ITM_TCR_GTSFREQ_Pos 10 /* ITM TCR: Global timestamp frequency Position */
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#define ITM_TCR_GTSFREQ_Msk (3ul << ITM_TCR_GTSFREQ_Pos) /* ITM TCR: Global timestamp frequency Mask */
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#define ITM_TCR_TSPrescale_Pos 8 /* ITM TCR: TSPrescale Position */
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#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /* ITM TCR: TSPrescale Mask */
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#define ITM_TCR_SWOENA_Pos 4 /* ITM TCR: SWOENA Position */
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#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /* ITM TCR: SWOENA Mask */
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#define ITM_TCR_DWTENA_Pos 3 /* ITM TCR: DWTENA Position */
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#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /* ITM TCR: DWTENA Mask */
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#define ITM_TCR_SYNCENA_Pos 2 /* ITM TCR: SYNCENA Position */
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#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /* ITM TCR: SYNCENA Mask */
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#define ITM_TCR_TSENA_Pos 1 /* ITM TCR: TSENA Position */
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#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /* ITM TCR: TSENA Mask */
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#define ITM_TCR_ITMENA_Pos 0 /* ITM TCR: ITM Enable bit Position */
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#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /* ITM TCR: ITM Enable bit Mask */
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#define ITM_IWR_ATVALIDM_Pos 0 /* ITM IWR: ATVALIDM Position */
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#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /* ITM IWR: ATVALIDM Mask */
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#define ITM_IRR_ATREADYM_Pos 0 /* ITM IRR: ATREADYM Position */
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#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /* ITM IRR: ATREADYM Mask */
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#define ITM_IMCR_INTEGRATION_Pos 0 /* ITM IMCR: INTEGRATION Position */
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#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /* ITM IMCR: INTEGRATION Mask */
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#define ITM_LSR_ByteAcc_Pos 2 /* ITM LSR: ByteAcc Position */
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#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /* ITM LSR: ByteAcc Mask */
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#define ITM_LSR_Access_Pos 1 /* ITM LSR: Access Position */
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#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /* ITM LSR: Access Mask */
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#define ITM_LSR_Present_Pos 0 /* ITM LSR: Present Position */
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#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /* ITM LSR: Present Mask */
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#define ITM_RXBUFFER_EMPTY 0x5aa55aa5 /* Value identifying g_itm_rxbuffer is ready for next character. */
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/***********************************************************************************************
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* Public Data
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***********************************************************************************************/
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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extern volatile int32_t g_itm_rxbuffer; /* External variable to receive characters. */
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/***********************************************************************************************
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* Public Function Prototypes
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***********************************************************************************************/
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uint32_t itm_sendchar(uint32_t ch);
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int32_t itm_receivechar(void);
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int32_t itm_checkchar(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ARCH_ARM_SRC_ARMV7_M_ITM_H */
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@ -143,4 +143,3 @@
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_ARMV7_M_SVCALL_H */
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155
arch/arm/src/armv7-m/up_itm.c
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155
arch/arm/src/armv7-m/up_itm.c
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@ -0,0 +1,155 @@
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/*****************************************************************************
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* arch/arm/src/armv7-m/up_itm.c
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*
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* Copyright (c) 2009 - 2013 ARM LIMITED
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*
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* All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* - Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Authors: Pierre-noel Bouteville <pnb990@gmail.com>
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* Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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/*****************************************************************************
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* Included Files
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*****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include "up_arch.h"
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#include "itm.h"
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/*****************************************************************************
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* Public Data
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*****************************************************************************/
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/*****************************************************************************
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* Public Functions
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*****************************************************************************/
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/*****************************************************************************
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* Name: itm_sendchar
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*
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* Description:
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* The function transmits a character via the ITM channel 0, and
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* - Just returns when no debugger is connected that has booked the output.
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* - Is blocking when a debugger is connected, but the previous character
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* sent has not been transmitted.
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*
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* Input Parameters:
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* ch - Character to transmit.
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*
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* Returned Value:
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* Character to transmit.
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*
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*****************************************************************************/
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uint32_t itm_sendchar(uint32_t ch)
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{
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if ((getreg32(ITM_TCR) & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
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(getreg32(ITM_TER) & (1UL << 0))) /* ITM Port #0 enabled */
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{
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while (getreg32(ITM_PORT(0)) == 0);
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putreg8((uint8_t)ch, ITM_PORT(0));
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}
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return ch;
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}
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/*****************************************************************************
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* Name: itm_receivechar
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*
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* Description:
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*
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* Input Parameters:
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* The function inputs a character via the external variable g_itm_rxbuffer.
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*
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* Returned Value:
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* Received character or -1 No character pending.
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*
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*****************************************************************************/
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int32_t itm_receivechar(void)
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{
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int32_t ch = -1; /* Assume no character available */
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if (g_itm_rxbuffer != ITM_RXBUFFER_EMPTY)
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{
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ch = g_itm_rxbuffer;
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g_itm_rxbuffer = ITM_RXBUFFER_EMPTY; /* Ready for next character */
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}
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return ch;
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}
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/*****************************************************************************
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* Name: itm_checkchar
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*
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* Description:
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*
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* Input Parameters:
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* The function checks whether a character is pending for reading in the variable g_itm_rxbuffer.
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*
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* Returned Value:
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* 0 No character available.
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* 1 Character available.
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*
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*****************************************************************************/
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int32_t itm_checkchar (void)
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{
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return (g_itm_rxbuffer != ITM_RXBUFFER_EMPTY);
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}
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@ -41,16 +41,14 @@ CMN_UCSRCS =
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CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
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CMN_ASRCS += vfork.S
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CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c
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CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
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CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copyfullstate.c
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CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c up_hardfault.c
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CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
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CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
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CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
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CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_systemreset.c
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CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c
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CMN_CSRCS += up_svcall.c up_vfork.c
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CMN_CSRCS += up_allocateheap.c
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CMN_CSRCS += up_stackframe.c
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CMN_CSRCS += up_itm.c up_mdelay.c up_memfault.c up_modifyreg8.c
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CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasepending.c
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CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c
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CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_svcall.c up_systemreset.c
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CMN_CSRCS += up_udelay.c up_unblocktask.c up_usestack.c up_vfork.c
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ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
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CMN_ASRCS += up_exception.S
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