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Tiva Timer: Implements configuration of the 32-bit RTC timer

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This commit is contained in:
Gregory Nutt 2015-01-10 12:41:15 -06:00
parent 2c6cf27405
commit d09a9e2741
3 changed files with 66 additions and 21 deletions
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2
arch/arm/src/tiva/chip/tiva_timer.h
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@ -521,7 +521,7 @@
/* GPTM Control (CTL) */ /* GPTM Control (CTL) */
#define TIMER_CTL_TAEN (1 << 0) /* Bit 0: Timer A Enable */ #define TIMER_CTL_TAEN (1 << 0) /* Bit 0: Timer A Enable */
#define TIMER_CTL_TASTALL_SHIFT (1 << 1) /* Bit 1: Timer A Stall Enable */ #define TIMER_CTL_TASTALL (1 << 1) /* Bit 1: Timer A Stall Enable */
#define TIMER_CTL_TAEVENT_SHIFT (2) /* Bits 2-3: GPTM Timer A Event Mode */ #define TIMER_CTL_TAEVENT_SHIFT (2) /* Bits 2-3: GPTM Timer A Event Mode */
#define TIMER_CTL_TAEVENT_MASK (3 << TIMER_CTL_TAEVENT_SHIFT) #define TIMER_CTL_TAEVENT_MASK (3 << TIMER_CTL_TAEVENT_SHIFT)
# define TIMER_CTL_TAEVENT_POS (0 << TIMER_CTL_TAEVENT_SHIFT) /* Positive edge */ # define TIMER_CTL_TAEVENT_POS (0 << TIMER_CTL_TAEVENT_SHIFT) /* Positive edge */

56
arch/arm/src/tiva/tiva_timer.c
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@ -923,10 +923,10 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv,
* a 1 to the appropriate bit of the GPTM Interrupt Clear Register * a 1 to the appropriate bit of the GPTM Interrupt Clear Register
* (GPTMICR). * (GPTMICR).
* *
* NOTE: This timer is started until tiva_gptm_enable() is called. * NOTE: This timer is not started until tiva_gptm_enable() is called.
*/ */
return -ENOSYS; return OK;
} }
/**************************************************************************** /****************************************************************************
@ -1143,10 +1143,10 @@ static int tiva_oneshot_periodic_mode16(struct tiva_gptmstate_s *priv,
* a 1 to the appropriate bit of the GPTM Interrupt Clear Register * a 1 to the appropriate bit of the GPTM Interrupt Clear Register
* (GPTMICR). * (GPTMICR).
* *
* NOTE: This timer is started until tiva_gptm_enable() is called. * NOTE: This timer is not started until tiva_gptm_enable() is called.
*/ */
return -ENOSYS; return OK;
} }
/**************************************************************************** /****************************************************************************
@ -1164,6 +1164,8 @@ static int tiva_oneshot_periodic_mode16(struct tiva_gptmstate_s *priv,
static int tiva_rtc_mode32(struct tiva_gptmstate_s *priv, static int tiva_rtc_mode32(struct tiva_gptmstate_s *priv,
const struct tiva_timer32config_s *timer) const struct tiva_timer32config_s *timer)
{ {
uint32_t regval;
/* To use the RTC mode, the timer must have a 32.768-KHz input signal on /* To use the RTC mode, the timer must have a 32.768-KHz input signal on
* an even CCP input. To enable the RTC feature, follow these steps: * an even CCP input. To enable the RTC feature, follow these steps:
* *
@ -1188,17 +1190,34 @@ static int tiva_rtc_mode32(struct tiva_gptmstate_s *priv,
/* 4. Write the match value to the GPTM Timer n Match Register /* 4. Write the match value to the GPTM Timer n Match Register
* (GPTMTnMATCHR). * (GPTMTnMATCHR).
*
* NOTE: The match register is not set until tiva_rtc_setalarm() is
* called.
*
* 5. Set/clear the RTCEN and TnSTALL bit in the GPTM Control Register
* (GPTMCTL) as needed.
*
* RTCEN - 1: RTC counting continues while the processor is
* halted by the debugger
* TASTALL - 1: Timer A freezes counting while the processor is
* halted by the debugger.
*/ */
/* 5. Set/clear the RTCEN and TnSTALL bit in the GPTM Control Register regval = tiva_getreg(priv, TIVA_TIMER_CTL_OFFSET);
* (GPTMCTL) as needed. #ifdef CONFIG_DEBUG_SYMBOLS
*/ regval |= (TIMER_CTL_RTCEN | TIMER_CTL_TASTALL);
#else
regval &= ~(TIMER_CTL_RTCEN | TIMER_CTL_TASTALL);
#endif
tiva_putreg(priv, TIVA_TIMER_CTL_OFFSET, regval);
/* 6. If interrupts are required, set the RTCIM bit in the GPTM Interrupt /* 6. If interrupts are required, set the RTCIM bit in the GPTM Interrupt
* Mask Register (GPTMIMR). * Mask Register (GPTMIMR).
*/ *
* NOTE: RTC interrupts are not enabled until tiva_rtc_setalarm() is
/* 7. Set the TAEN bit in the GPTMCTL register to enable the timer and * called.
*
* 7. Set the TAEN bit in the GPTMCTL register to enable the timer and
* start counting. * start counting.
* *
* When the timer count equals the value in the GPTMTnMATCHR register, * When the timer count equals the value in the GPTMTnMATCHR register,
@ -1209,10 +1228,11 @@ static int tiva_rtc_mode32(struct tiva_gptmstate_s *priv,
* begins counting at this new value and continues until it reaches * begins counting at this new value and continues until it reaches
* 0xFFFF.FFFF, at which point it rolls over. * 0xFFFF.FFFF, at which point it rolls over.
* *
* NOTE: The timer will not be enabled until tiva_gptm_enable() is called. * NOTE: The RTC timer will not be enabled until tiva_gptm_enable() is
* called.
*/ */
#warning Missing Logic
return -ENOSYS; return OK;
} }
/**************************************************************************** /****************************************************************************
@ -1276,7 +1296,7 @@ static int tiva_input_edgecount_mode16(struct tiva_gptmstate_s *priv,
* programmed number of edge events has been detected. To re-enable the * programmed number of edge events has been detected. To re-enable the
* timer, ensure that the TnEN bit is cleared and repeat steps 4 through 8. * timer, ensure that the TnEN bit is cleared and repeat steps 4 through 8.
* *
* NOTE: This timer is started until tiva_gptm_enable() is called. * NOTE: This timer is not started until tiva_gptm_enable() is called.
*/ */
return -ENOSYS; return -ENOSYS;
@ -1344,7 +1364,7 @@ static int tiva_input_time_mode16(struct tiva_gptmstate_s *priv,
* the GPTMTnMR register. The change takes effect at the next cycle after * the GPTMTnMR register. The change takes effect at the next cycle after
* the write. * the write.
* *
* NOTE: This timer is started until tiva_gptm_enable() is called. * NOTE: This timer is not started until tiva_gptm_enable() is called.
*/ */
return -ENOSYS; return -ENOSYS;
@ -1412,7 +1432,7 @@ static int tiva_pwm_mode16(struct tiva_gptmstate_s *priv,
* the GPTMTnILR register, and the change takes effect at the next cycle * the GPTMTnILR register, and the change takes effect at the next cycle
* after the write. * after the write.
* *
* NOTE: This timer is started until tiva_gptm_enable() is called. * NOTE: This timer is not started until tiva_gptm_enable() is called.
*/ */
return -ENOSYS; return -ENOSYS;
@ -1939,7 +1959,7 @@ void tiva_timer16_stop(TIMER_HANDLE handle, int tmndx)
} }
/**************************************************************************** /****************************************************************************
* Name: tiva_rtc_alarm * Name: tiva_rtc_setalarm
* *
* Description: * Description:
* Setup to receive an interrupt when the RTC counter equals a match time * Setup to receive an interrupt when the RTC counter equals a match time
@ -1958,7 +1978,7 @@ void tiva_timer16_stop(TIMER_HANDLE handle, int tmndx)
* *
****************************************************************************/ ****************************************************************************/
void tiva_rtc_alarm(TIMER_HANDLE handle, uint32_t delay) void tiva_rtc_setalarm(TIMER_HANDLE handle, uint32_t delay)
{ {
struct tiva_gptmstate_s *priv = (struct tiva_gptmstate_s *)handle; struct tiva_gptmstate_s *priv = (struct tiva_gptmstate_s *)handle;
const struct tiva_timer32config_s *config; const struct tiva_timer32config_s *config;

29
arch/arm/src/tiva/tiva_timer.h
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@ -572,7 +572,32 @@ static inline void tiva_timer16b_absmatch(TIMER_HANDLE handle, uint16_t absmatch
} }
/**************************************************************************** /****************************************************************************
* Name: tiva_rtc_alarm * Name: tiva_rtc_settime
*
* Description:
* Set the 32-bit RTC timer counter. When RTC mode is selected for the
* first time after reset, the counter is loaded with a value of 1. All
* subsequent load values must be written to the concatenated GPTM Timer A
* Interval Load (GPTMTAILR) registers. If the GPTMTnILR register is
* loaded with a new value, the counter begins counting at that value
* and rolls over at the fixed value of 0xffffffff.
*
* Input Parameters:
* handle - The handle value returned by tiva_gptm_configure()
* newtime - The new RTC time (seconds)
*
* Returned Value:
* None.
*
****************************************************************************/
static inline void tiva_rtc_setalarm(TIMER_HANDLE handle, uint32_t newtime)
{
tiva_gptm_putreg(handle, TIVA_TIMER_TAILR_OFFSET, newtime);
}
/****************************************************************************
* Name: tiva_rtc_setalarm
* *
* Description: * Description:
* Setup to receive an interrupt when the RTC counter equals a match time * Setup to receive an interrupt when the RTC counter equals a match time
@ -596,7 +621,7 @@ static inline void tiva_timer16b_absmatch(TIMER_HANDLE handle, uint16_t absmatch
* *
****************************************************************************/ ****************************************************************************/
void tiva_rtc_alarm(TIMER_HANDLE handle, uint32_t delay); void tiva_rtc_setalarm(TIMER_HANDLE handle, uint32_t delay);
/**************************************************************************** /****************************************************************************
* Name: tiva_timer32_relmatch * Name: tiva_timer32_relmatch