From d0b2cf34f963e18bfc6d2011eec2ba23135dd9f9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 23 Jan 2019 13:29:29 -0600 Subject: [PATCH] arch/arm/src/tiva/hardware: Add CC13x0 DDI0 OSC header file. arch/arm/src/tiva/cc13xx: Fix miscellaneous compilation issues. --- arch/arm/src/tiva/cc13xx/cc13x0_rom.c | 57 +-- .../tiva/hardware/cc13x0/cc13x0_ddi0_osc.h | 402 ++++++++++++++++++ .../cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h | 22 +- configs/beaglebone-black/README.txt | 32 +- 4 files changed, 471 insertions(+), 42 deletions(-) create mode 100644 arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h diff --git a/arch/arm/src/tiva/cc13xx/cc13x0_rom.c b/arch/arm/src/tiva/cc13xx/cc13x0_rom.c index fd25d6bf21..7744a59247 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x0_rom.c +++ b/arch/arm/src/tiva/cc13xx/cc13x0_rom.c @@ -42,14 +42,23 @@ * Included Files ************************************************************************************/ +#include + +#include "up_arch.h" + #include "hardware/tiva_adi2_refsys.h" #include "hardware/tiva_adi3_refsys.h" #include "hardware/tiva_adi4_aux.h" #include "hardware/tiva_aon_batmon.h" +#include "hardware/tiva_aon_rtc.h" #include "hardware/tiva_aon_sysctl.h" +#include "hardware/tiva_aux_wuc.h" #include "hardware/tiva_ccfg.h" #include "hardware/tiva_ddi0_osc.h" #include "hardware/tiva_fcfg1.h" +#include "hardware/tiva_vims.h" + +#include "cc13xx/cc13x0_rom.h" /************************************************************************************ * Private Functions @@ -72,7 +81,7 @@ static void rom_set_vddr_level(uint32_t ccfg_modeconf) rawtrim = ((getreg32(TIVA_FCFG1_VOLT_TRIM) & FCFG1_VOLT_TRIM_VDDR_TRIM_HH_MASK) >> - CFG1_VOLT_TRIM_VDDR_TRIM_HH_SHIFT); + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_SHIFT); targettrim = rom_signextend_vddrtrim(rawtrim); currenttrim = @@ -167,7 +176,7 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) */ putreg16((ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_MASK << 8) | - (ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31) + (ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31), TIVA_ADI3_REFSYS_MASK8B + (TIVA_ADI3_REFSYS_REFSYSCTL1_OFFSET * 2)); putreg8(ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN, TIVA_ADI3_REFSYS_SET + TIVA_ADI3_REFSYS_REFSYSCTL3_OFFSET); @@ -228,8 +237,8 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) if (getreg32(TIVA_AON_SYSCTL_PWRCTL) & AON_SYSCTL_PWRCTL_EXT_REG_MODE) { - ccfg_modeconf |= - (CCFG_MODE_CONF_DCDC_RECHARGE_MASK | CCFG_MODE_CONF_DCDC_ACTIVE_MASK); + ccfg_modeconf |= (CCFG_MODE_CONF_DCDC_RECHARGE | + CCFG_MODE_CONF_DCDC_ACTIVE); } else { @@ -244,7 +253,7 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) setbits = 0; clrbits = 0; - if ((ccfg_modecong & CCFG_MODE_CONF_DCDC_RECHARGE) != 0) + if ((ccfg_modeconf & CCFG_MODE_CONF_DCDC_RECHARGE) != 0) { clrbits |= AON_SYSCTL_PWRCTL_DCDC_EN; } @@ -257,7 +266,7 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) * polarity */ - if ((ccfg_modecong & CCFG_MODE_CONF_DCDC_ACTIVE) != 0) + if ((ccfg_modeconf & CCFG_MODE_CONF_DCDC_ACTIVE) != 0) { clrbits |= AON_SYSCTL_PWRCTL_DCDC_ACTIVE; } @@ -326,7 +335,7 @@ void rom_setup_coldreset_from_shutdown_cfg2(uint32_t fcfg1_revision, trim = rom_setup_get_trim_adcshvbufen(fcfg1_revision); putreg8(0x10 | trim, - TIVA_AUX_DDI0_OSC_BASE + DTIVA_DI_MASK4B_OFFSET + + TIVA_AUX_DDI0_OSC_BASE + TIVA_DI_MASK4B_OFFSET + (TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL_OFFSET * 2) + 1); /* Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields @@ -356,9 +365,9 @@ void rom_setup_coldreset_from_shutdown_cfg2(uint32_t fcfg1_revision, */ trim = rom_setup_get_trim_rcosc_lfibiastrim(fcfg1_revision); - putreg8(0x80 | (trim << 3, + putreg8(0x80 | (trim << 3), TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK4B_OFFSET + - (0x00000020 * 2) + 1)); + (0x00000020 * 2) + 1); /* Update DDI0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and * DDI0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write This can be @@ -444,7 +453,7 @@ void rom_setup_coldreset_from_shutdown_cfg3(uint32_t ccfg_modeconf) * FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit) */ regval = ((getreg32(TIVA_ADI2_REFSYS_HPOSCCTL2) & - ~(ADI2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_MASK | + ~(ADI2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN | ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_MASK)) | (((fcfg1_oscconf & FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_MASK) >> @@ -485,7 +494,7 @@ void rom_setup_coldreset_from_shutdown_cfg3(uint32_t ccfg_modeconf) FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_MASK) >> FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_SHIFT) << ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS_SHIFT)); - putreg32(regval, TIVA_ADI2_REFSYS_HPOSCCTL0)' + putreg32(regval, TIVA_ADI2_REFSYS_HPOSCCTL0); break; } /* Not a HPOSC chip - fall through to default */ @@ -698,13 +707,13 @@ uint32_t rom_setup_get_trim_rcosc_lfrtunectuntrim(void) ((getreg32(TIVA_FCFG1_CONFIG_OSC_TOP) & FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_MASK) >> FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_SHIFT) << - DDI0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S; + DDI0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_SHIFT; trimValue |= ((getreg32(TIVA_FCFG1_CONFIG_OSC_TOP) & FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_MASK) >> FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_SHIFT) << - DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S; + DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_SHIFT; return (trimValue); } @@ -722,7 +731,7 @@ uint32_t rom_setup_get_trim_xosc_hfibiastherm(void) trimValue = (getreg32(TIVA_FCFG1_ANABYPASS_VALUE2) & FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_MASK) >> - FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S; + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_SHIFT; return (trimValue); } @@ -744,7 +753,7 @@ uint32_t rom_setup_get_trim_ampcompth2(void) trimValue = ((ui32Fcfg1Value & FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_MASK) >> FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_SHIFT) << - DDI0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S; + DDI0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_SHIFT; trimValue |= (((ui32Fcfg1Value & FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_MASK) >> FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_SHIFT) << @@ -913,7 +922,7 @@ uint32_t rom_setup_get_trim_dblrloopfilter_resetvoltage(uint32_t fcfg1_revision) dblrLoopFilterResetVoltageValue = (getreg32(TIVA_FCFG1_MISC_OTP_DATA_1) & FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_MASK) >> - FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S; + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_SHIFT; } return (dblrLoopFilterResetVoltageValue); @@ -931,7 +940,7 @@ uint32_t rom_setup_get_trim_adcshmodeen(uint32_t fcfg1_revision) { getTrimForAdcShModeEnValue = (getreg32(TIVA_FCFG1_OSC_CONF) & FCFG1_OSC_CONF_ADC_SH_MODE_EN_MASK) >> - FCFG1_OSC_CONF_ADC_SH_MODE_EN_S; + FCFG1_OSC_CONF_ADC_SH_MODE_EN_SHIFT; } return (getTrimForAdcShModeEnValue); @@ -949,7 +958,7 @@ uint32_t rom_setup_get_trim_adcshvbufen(uint32_t fcfg1_revision) { getTrimForAdcShVbufEnValue = (getreg32(TIVA_FCFG1_OSC_CONF) & FCFG1_OSC_CONF_ADC_SH_VBUF_EN_MASK) >> - FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S; + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_SHIFT; } return (getTrimForAdcShVbufEnValue); @@ -999,7 +1008,7 @@ uint32_t rom_setup_get_trim_xosc_hffaststart(void) ui32XoscHfFastStartValue = (getreg32(TIVA_FCFG1_OSC_CONF) & FCFG1_OSC_CONF_XOSC_HF_FAST_START_MASK) >> - FCFG1_OSC_CONF_XOSC_HF_FAST_START_S; + FCFG1_OSC_CONF_XOSC_HF_FAST_START_SHIFT; return (ui32XoscHfFastStartValue); } @@ -1049,7 +1058,7 @@ uint32_t rom_setup_get_trim_rcosc_lfibiastrim(uint32_t fcfg1_revision) { trimForRcOscLfIBiasTrimValue = (getreg32(TIVA_FCFG1_OSC_CONF) & FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_MASK) - >> FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S; + >> FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_SHIFT; } return (trimForRcOscLfIBiasTrimValue); @@ -1071,7 +1080,7 @@ uint32_t rom_setup_get_trim_lfregulator_cmirrwr_ratio(uint32_t fcfg1_revision) (getreg32(TIVA_FCFG1_OSC_CONF) & (FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_MASK | FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_MASK)) >> - FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S; + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_SHIFT; } return (trimForXoscLfRegulatorAndCmirrwrRatioValue); @@ -1095,7 +1104,7 @@ void rom_setup_cachemode(void) uint32_t vims_ctlmode0; - while ((getreg32(TIVA_VIMS_STAT) & VIMS_STAT_MODE_CHANGING_BITN) != 0) + while ((getreg32(TIVA_VIMS_STAT) & VIMS_STAT_MODE_CHANGING) != 0) { /* Do nothing - wait for an eventual ongoing mode change to complete. * (There should typically be no wait time here, but need to be sure) @@ -1105,8 +1114,8 @@ void rom_setup_cachemode(void) /* Note that Mode=0 is equal to MODE_GPRAM */ vims_ctlmode0 = - ((getreg32(TIVA_VIMS_CTL) & ~VIMS_CTL_MODE_MASK) | VIMS_CTL_DYN_CG_EN_MASK | - VIMS_CTL_PREF_EN_MASK); + ((getreg32(TIVA_VIMS_CTL) & ~VIMS_CTL_MODE_MASK) | VIMS_CTL_DYN_CG_EN | + VIMS_CTL_PREF_EN); if (getreg32(TIVA_CCFG_SIZE_AND_DIS_FLAGS) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM) diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h new file mode 100644 index 0000000000..b954dbc43e --- /dev/null +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h @@ -0,0 +1,402 @@ +/******************************************************************************************************************** + * arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Technical content derives from a TI header file that has a compatible BSD license: + * + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_DDI0_OSC_H +#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_DDI0_OSC_H + +/******************************************************************************************************************** + * Included Files + ********************************************************************************************************************/ + +#include +#include "hardware/tiva_memorymap.h" +#include "hardware/tiva_ddi.h" + +/******************************************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************************************/ + +/* DDI0 OSC Register Offsets ****************************************************************************************/ + +#define TIVA_DDI0_OSC_CTL0_OFFSET 0x0000 /* Control 0 */ +#define TIVA_DDI0_OSC_CTL1_OFFSET 0x0004 /* Control 1 */ +#define TIVA_DDI0_OSC_RADCEXTCFG_OFFSET 0x0008 /* RADC External Configuration */ +#define TIVA_DDI0_OSC_AMPCOMPCTL_OFFSET 0x000c /* Amplitude Compensation Control */ +#define TIVA_DDI0_OSC_AMPCOMPTH1_OFFSET 0x0010 /* Amplitude Compensation Threshold 1 */ +#define TIVA_DDI0_OSC_AMPCOMPTH2_OFFSET 0x0014 /* Amplitude Compensation Threshold 2 */ +#define TIVA_DDI0_OSC_ANABYPASSVAL1_OFFSET 0x0018 /* Analog Bypass Values 1 */ +#define TIVA_DDI0_OSC_ANABYPASSVAL2_OFFSET 0x001c +#define TIVA_DDI0_OSC_ATESTCTL_OFFSET 0x0020 /* Analog Test Control */ +#define TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL_OFFSET 0x0024 /* ADC Doubler Nanoamp Control */ +#define TIVA_DDI0_OSC_XOSCHFCTL_OFFSET 0x0028 /* XOSCHF Control */ +#define TIVA_DDI0_OSC_LFOSCCTL_OFFSET 0x002c /* Low Frequency Oscillator Control */ +#define TIVA_DDI0_OSC_RCOSCHFCTL_OFFSET 0x0030 /* RCOSCHF Control */ +#define TIVA_DDI0_OSC_STAT0_OFFSET 0x0034 /* Status 0 */ +#define TIVA_DDI0_OSC_STAT1_OFFSET 0x0038 /* Status 1 */ +#define TIVA_DDI0_OSC_STAT2_OFFSET 0x003c /* Status 2 */ + +/* DDI0 OSC Register Addresses **************************************************************************************/ +/* Direct access */ + +#define TIVA_DDI0_OSC_CTL0 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_CTL0_OFFSET) +#define TIVA_DDI0_OSC_CTL1 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_CTL1_OFFSET) +#define TIVA_DDI0_OSC_RADCEXTCFG (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_RADCEXTCFG_OFFSET) +#define TIVA_DDI0_OSC_AMPCOMPCTL (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_AMPCOMPCTL_OFFSET) +#define TIVA_DDI0_OSC_AMPCOMPTH1 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_AMPCOMPTH1_OFFSET) +#define TIVA_DDI0_OSC_AMPCOMPTH2 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_AMPCOMPTH2_OFFSET) +#define TIVA_DDI0_OSC_ANABYPASSVAL1 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_ANABYPASSVAL1_OFFSET) +#define TIVA_DDI0_OSC_ANABYPASSVAL2 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_ANABYPASSVAL2_OFFSET) +#define TIVA_DDI0_OSC_ATESTCTL (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_ATESTCTL_OFFSET) +#define TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL_OFFSET) +#define TIVA_DDI0_OSC_XOSCHFCTL (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_XOSCHFCTL_OFFSET) +#define TIVA_DDI0_OSC_LFOSCCTL (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_LFOSCCTL_OFFSET) +#define TIVA_DDI0_OSC_RCOSCHFCTL (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_RCOSCHFCTL_OFFSET) +#define TIVA_DDI0_OSC_STAT0 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_STAT0_OFFSET) +#define TIVA_DDI0_OSC_STAT1 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_STAT1_OFFSET) +#define TIVA_DDI0_OSC_STAT2 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_STAT2_OFFSET) + +/* Offsets may also be used in conjunction with access as described in cc13x0_ddi.h */ + +#define TIVA_DDI0_OSC_DIR (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_DIR_OFFSET) +#define TIVA_DDI0_OSC_SET (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET) +#define TIVA_DDI0_OSC_CLR (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_CLR_OFFSET) +#define TIVA_DDI0_OSC_MASK4B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK4B_OFFSET) +#define TIVA_DDI0_OSC_MASK8B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK8B_OFFSET) +#define TIVA_DDI0_OSC_MASK16B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK16B_OFFSET) + +/* DDI0 OSC Bitfield Definitions ************************************************************************************/ + +/* DDI0_OSC_CTL0 */ + +#define DDI0_OSC_CTL0_SCLK_HF_SRC_SEL (1 << 0) /* Bit 0: Source select for sclk_hf */ +# define DDI0_OSC_CTL0_SCLK_HF_SRC_RCOSC (0) /* High frequency RCOSC clock */ +# define DDI0_OSC_CTL0_SCLK_HF_SRC_XOSC DDI0_OSC_CTL0_SCLK_HF_SRC_SEL /* High frequency XOSC clock */ +#define DDI0_OSC_CTL0_SCLK_MF_SRC_SEL (1 << 1) /* Bit 1 */ +# define DDI0_OSC_CTL0_SCLK_MF_SRC_SEL_RCOSCHFDMF 0 +# define DDI0_OSC_CTL0_SCLK_MF_SRC_SEL_XCOSCHFDMF DDI0_OSC_CTL0_SCLK_MF_SRC_SEL /* Medium frequency clock derived + * from high frequency XOSC */ +#define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT (2) /* Bits 2-3: Source select for sclk_lf */ +#define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) +# define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF (1 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency clock derived + * from High Frequency XOSC */ +# define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF (0 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency clock derived + * from High Frequency RCOSC */ +# define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF (2 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency RCOSC */ +# define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF (3 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency XOSC */ +#define DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT (5) /* Bits 5-6: Source select for aclk_ref */ +#define DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) +# define DDI0_OSC_CTL0_ACLK_REF_SRC_RCOSCHF (0 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* RCOSC_HF derived (31.25kHz) */ +# define DDI0_OSC_CTL0_ACLK_REF_SRC_XOSCHF (1 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* XOSC_HF derived (31.25kHz) */ +# define DDI0_OSC_CTL0_ACLK_REF_SRC_RCOSCLF (2 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* RCOSC_LF (32kHz) */ +# define DDI0_OSC_CTL0_ACLK_REF_SRC_XOSCLF (3 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* XOSC_LF (32.768kHz) */ +#define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT (7) /* Bits 7-8: ource select for aclk_tdc */ +#define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) +# define DDI0_OSC_CTL0_ACLK_TDC_SRC_RCOSCHF48 (0 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* RCOSC_HF (48MHz) */ +# define DDI0_OSC_CTL0_ACLK_TDC_SRC_RCOSCHF24 (1 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* RCOSC_HF (24MHz) */ +# define DDI0_OSC_CTL0_ACLK_TDC_SRC_XOSCHF24 (2 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* XOSC_HF (24MHz) */ +#define DDI0_OSC_CTL0_CLK_LOSS_EN (1 << 9) /* Bit 9: Enable SCLK_HF, SCLK_MF and SCLK_LF clock + * loss detection and indicators to the system + * controller */ +#define DDI0_OSC_CTL0_XOSC_LF_DIG_BYPASS (1 << 10) /* Bit 10: Bypass XOSC_LF and use the digital + * input clock from AON for the xosc_lf */ +# define DDI0_OSC_CTL0_XOSC_LF_DIG_32KHZ (0) /* Use 32kHz XOSC as xosc_lf + * clock source */ +# define DDI0_OSC_CTL0_XOSC_LF_DIG_DIGINPUT DDI0_OSC_CTL0_XOSC_LF_DIG_BYPASS /* Use digital input (from AON) + * as xosc_lf clock source */ +#define DDI0_OSC_CTL0_XOSC_HF_POWER_MODE (1 << 11) /* Bit 11 */ +#define DDI0_OSC_CTL0_RCOSC_LF_TRIMMED (1 << 12) /* Bit 12 */ +#define DDI0_OSC_CTL0_HPOSC_MODE_EN (1 << 14) /* Bit 14 */ +#define DDI0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING (1 << 16) /* Bit 16 */ +#define DDI0_OSC_CTL0_FORCE_KICKSTART_EN (1 << 22) /* Bit 22 */ +#define DDI0_OSC_CTL0_DOUBLER_RESET_DURATION (1 << 25) /* Bit 25 */ +#define DDI0_OSC_CTL0_DOUBLER_START_DURATION_SHIFT (26) /* Bits 26-27: Allows switching of sclk_hf source */ +#define DDI0_OSC_CTL0_DOUBLER_START_DURATION_MASK (3 << DDI0_OSC_CTL0_DOUBLER_START_DURATION_SHIFT) +# define DDI0_OSC_CTL0_DOUBLER_START_DURATION(n) ((uint32_t)(n) << DDI0_OSC_CTL0_DOUBLER_START_DURATION_SHIFT) +#define DDI0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL (1 << 28) /* Bit 28 */ +#define DDI0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL (1 << 29) /* Bit 29 */ +#define DDI0_OSC_CTL0_XTAL_IS_24M (1 << 31) /* Bit 31: Set based high frequency XTAL */ +# define DDI0_OSC_CTL0_XTAL_IS_24M_48M (0) +# define DDI0_OSC_CTL0_XTAL_IS_24M_24M DDI0_OSC_CTL0_XTAL_IS_24M + +/* DDI0_OSC_CTL1 */ + +#define DDI0_OSC_CTL1_XOSC_HF_FAST_START_SHIFT (0) /* Bits 0-7 */ +#define DDI0_OSC_CTL1_XOSC_HF_FAST_START_MASK (3 << DDI0_OSC_CTL1_XOSC_HF_FAST_START_SHIFT) +# define DDI0_OSC_CTL1_XOSC_HF_FAST_START(n) ((uint32_t)(n) << DDI0_OSC_CTL1_XOSC_HF_FAST_START_SHIFT) +#define DDI0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN (1 << 17) /* Bit 17 */ +#define DDI0_OSC_CTL1_RCOSCHFCTRIMFRACT_SHIFT (18) /* Bits 18-22 */ +#define DDI0_OSC_CTL1_RCOSCHFCTRIMFRACT_MASK (31 << DDI0_OSC_CTL1_RCOSCHFCTRIMFRACT_SHIFT) +# define DDI0_OSC_CTL1_RCOSCHFCTRIMFRACT(n) ((uint32_t)(n) << DDI0_OSC_CTL1_RCOSCHFCTRIMFRACT_SHIFT) + +/* DDI0_OSC_RADCEXTCFG */ + +#define DDI0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR (1 << 5) /* Bit 5 */ +#define DDI0_OSC_RADCEXTCFG_RADC_DAC_TH_SHIFT (6) /* Bits 6-11 */ +#define DDI0_OSC_RADCEXTCFG_RADC_DAC_TH_MASK (0x3f << DDI0_OSC_RADCEXTCFG_RADC_DAC_TH_SHIFT) +# define DDI0_OSC_RADCEXTCFG_RADC_DAC_TH(n) ((uint32_t)(n) << DDI0_OSC_RADCEXTCFG_RADC_DAC_TH_SHIFT) +#define DDI0_OSC_RADCEXTCFG_IDAC_STEP_SHIFT (12) /* Bits 12-15 */ +#define DDI0_OSC_RADCEXTCFG_IDAC_STEP_MASK (15 << DDI0_OSC_RADCEXTCFG_IDAC_STEP_SHIFT) +# define DDI0_OSC_RADCEXTCFG_IDAC_STEP(n) ((uint32_t)(n) << DDI0_OSC_RADCEXTCFG_IDAC_STEP_SHIFT) +#define DDI0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_SHIFT (16) /* Bits 16-21 */ +#define DDI0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_MASK (0x3f << DDI0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_SHIFT) +# define DDI0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT(n) ((uint32_t)(n) << DDI0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_SHIFT) +#define DDI0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_SHIFT (22) /* Bits 22-31 */ +#define DDI0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_MASK (0x3ff << DDI0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_SHIFT) +# define DDI0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT(n) ((uint32_t)(n) << DDI0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_SHIFT) + +/* DDI0_OSC_AMPCOMPCTL */ + +#define DDI0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_SHIFT (0) /* Bits 0-3 */ +#define DDI0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_MASK (15 << DDI0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_SHIFT) +# define DDI0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT(n) ((uint32_t)(n) << DDI0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_SHIFT) +#define DDI0_OSC_AMPCOMPCTL_CAP_STEP_SHIFT (4) /* Bits 4-7 */ +#define DDI0_OSC_AMPCOMPCTL_CAP_STEP_MASK (15 << DDI0_OSC_AMPCOMPCTL_CAP_STEP_SHIFT) +# define DDI0_OSC_AMPCOMPCTL_CAP_STEP(n) ((uint32_t)(n) << DDI0_OSC_AMPCOMPCTL_CAP_STEP_SHIFT) +#define DDI0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_SHIFT (8) /* Bits 8-15 */ +#define DDI0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_MASK (0xff << DDI0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_SHIFT) +# define DDI0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL(n) ((uint32_t)(n) << DDI0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_SHIFT) +#define DDI0_OSC_AMPCOMPCTL_IBIAS_INIT_SHIFT (16) /* Bits 16-19 */ +#define DDI0_OSC_AMPCOMPCTL_IBIAS_INIT_MASK (15 << DDI0_OSC_AMPCOMPCTL_IBIAS_INIT_SHIFT) +# define DDI0_OSC_AMPCOMPCTL_IBIAS_INIT(n) ((uint32_t)(n) << DDI0_OSC_AMPCOMPCTL_IBIAS_INIT_SHIFT) +#define DDI0_OSC_AMPCOMPCTL_IBIAS_OFFSET_SHIFT (20) /* Bits 20-23 */ +#define DDI0_OSC_AMPCOMPCTL_IBIAS_OFFSET_MASK (15 << DDI0_OSC_AMPCOMPCTL_IBIAS_OFFSET_SHIFT) +# define DDI0_OSC_AMPCOMPCTL_IBIAS_OFFSET(n) ((uint32_t)(n) << DDI0_OSC_AMPCOMPCTL_IBIAS_OFFSET_SHIFT) +#define DDI0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN (1 << 26) /* Bit 26 */ +#define DDI0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL (1 << 27) /* Bit 27 */ +#define DDI0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_SHIFT (28) /* Bits 28-29 */ +#define DDI0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_MASK (3 << DDI0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_SHIFT) +# define DDI0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ (0 << DDI0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_SHIFT) +# define DDI0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ (1 << DDI0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_SHIFT) +# define DDI0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ (2 << DDI0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_SHIFT) +# define DDI0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ (3 << DDI0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_SHIFT) +#define DDI0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE (1 << 30) /* Bit 30 */ + +/* DDI0_OSC_AMPCOMPTH1 */ + +#define DDI0_OSC_AMPCOMPTH1_HPMRAMP1_TH_SHIFT (0) /* Bits 0-5 */ +#define DDI0_OSC_AMPCOMPTH1_HPMRAMP1_TH_MASK (0x3f << DDI0_OSC_AMPCOMPTH1_HPMRAMP1_TH_SHIFT) +# define DDI0_OSC_AMPCOMPTH1_HPMRAMP1_TH(n) ((uint32_t)(n) << DDI0_OSC_AMPCOMPTH1_HPMRAMP1_TH_SHIFT) +#define DDI0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_SHIFT (6) /* Bits 6-9 */ +#define DDI0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_MASK (15 << DDI0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_SHIFT) +# define DDI0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT(n) ((uint32_t)(n) << DDI0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_SHIFT) +#define DDI0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_SHIFT (10) /* Bits 10-15 */ +#define DDI0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_MASK (0x3f << DDI0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_SHIFT) +# define DDI0_OSC_AMPCOMPTH1_HPMRAMP3_HTH(n) ((uint32_t)(n) << DDI0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_SHIFT) +#define DDI0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_SHIFT (18) /* Bits 18-23 */ +#define DDI0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_MASK (0x3f << DDI0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_SHIFT) +# define DDI0_OSC_AMPCOMPTH1_HPMRAMP3_LTH(n) ((uint32_t)(n) << DDI0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_SHIFT) + +/* DDI0_OSC_AMPCOMPTH2 */ + +#define DDI0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_SHIFT (2) /* Bits 2-7 */ +#define DDI0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_MASK (0x3f << DDI0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_SHIFT) +# define DDI0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM(n) ((uint32_t)(n) << DDI0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_SHIFT) +#define DDI0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_SHIFT (10) /* Bits 10-15 */ +#define DDI0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_MASK (0x3f << DDI0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_SHIFT) +# define DDI0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM(n) ((uint32_t)(n) << DDI0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_SHIFT) +#define DDI0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_SHIFT (18) /* Bits 18-23 */ +#define DDI0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_MASK (0x3f << DDI0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_SHIFT) +# define DDI0_OSC_AMPCOMPTH2_LPMUPDATE_HTH(n) ((uint32_t)(n) << DDI0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_SHIFT) +#define DDI0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_SHIFT (26) /* Bits 26-31 */ +#define DDI0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_MASK (0x3f << DDI0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_SHIFT) +# define DDI0_OSC_AMPCOMPTH2_LPMUPDATE_LTH(n) ((uint32_t)(n) << DDI0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_SHIFT) + +/* DDI0_OSC_ANABYPASSVAL1 */ + +#define DDI0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_SHIFT (0) /* Bits 0-15 */ +#define DDI0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_MASK (0xffff << DDI0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_SHIFT) +# define DDI0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12(n) ((uint32_t)(n) << DDI0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_SHIFT) +#define DDI0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_SHIFT (16) /* Bits 16-19 */ +#define DDI0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_MASK (15 << DDI0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_SHIFT) +# define DDI0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12(n) ((uint32_t)(n) << DDI0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_SHIFT) + +/* DDI0_OSC_ANABYPASSVAL2 */ + +#define DDI0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_SHIFT (0) /* Bits 0-13 */ +#define DDI0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_MASK (0x3fff << DDI0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_SHIFT) +# define DDI0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM(n) ((uint32_t)(n) << DDI0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_SHIFT) + +/* DDI0_OSC_ATESTCTL */ + +#define DDI0_OSC_ATESTCTL_SCLK_LF_AUX_EN (1 << 29) /* Bit 29: Enable 32 kHz clock to AUX_COMPB */ + +/* DDI0_OSC_ADCDOUBLERNANOAMPCTL */ + +#define DDI0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_SHIFT (0) /* Bits 0-1 */ +#define DDI0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_MASK (3 << DDI0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_SHIFT) +# define DDI0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL(n) ((uint32_t)(n) << DDI0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_SHIFT) +#define DDI0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN (1 << 4) /* Bit 4 */ +#define DDI0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN (1 << 5) /* Bit 5 */ +#define DDI0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 (1 << 23) /* Bit 23 */ +#define DDI0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE (1 << 24) /* Bit 24 */ + +/* DDI0_OSC_XOSCHFCTL */ + +#define DDI0_OSC_XOSCHFCTL_LP_BUF_ITRIM_SHIFT (0) /* Bits 0-1 */ +#define DDI0_OSC_XOSCHFCTL_LP_BUF_ITRIM_MASK (3 << DDI0_OSC_XOSCHFCTL_LP_BUF_ITRIM_SHIFT) +# define DDI0_OSC_XOSCHFCTL_LP_BUF_ITRIM(n) ((uint32_t)(n) << DDI0_OSC_XOSCHFCTL_LP_BUF_ITRIM_SHIFT) +#define DDI0_OSC_XOSCHFCTL_HP_BUF_ITRIM_SHIFT (2) /* Bits 2-7 */ +#define DDI0_OSC_XOSCHFCTL_HP_BUF_ITRIM_MASK (7 << DDI0_OSC_XOSCHFCTL_HP_BUF_ITRIM_SHIFT) +# define DDI0_OSC_XOSCHFCTL_HP_BUF_ITRIM(n) ((uint32_t)(n) << DDI0_OSC_XOSCHFCTL_HP_BUF_ITRIM_SHIFT) +#define DDI0_OSC_XOSCHFCTL_BYPASS (1 << 6) /* Bit 6 */ +#define DDI0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_SHIFT (8) /* Bits 8-9 */ +#define DDI0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_MASK (3 << DDI0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_SHIFT) +# define DDI0_OSC_XOSCHFCTL_PEAK_DET_ITRIM(n) ((uint32_t)(n) << DDI0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_SHIFT) + +/* DDI0_OSC_LFOSCCTL */ + +#define DDI0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_SHIFT (0) /* Bits 0-7 */ +#define DDI0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_MASK (0xff << DDI0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_SHIFT) +# define DDI0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM(n) ((uint32_t)(n) << DDI0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_SHIFT) +#define DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_SHIFT (8) /* Bits 8-9 */ +#define DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_MASK (3 << DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_SHIFT) +# define DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG (0 << DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_SHIFT) +# define DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG (1 << DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_SHIFT) +# define DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG (2 << DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_SHIFT) +# define DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG (3 << DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_SHIFT) +#define DDI0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_SHIFT (18) /* Bits 18-21 */ +#define DDI0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_MASK (15 << DDI0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_SHIFT) +# define DDI0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO(n) ((uint32_t)(n) << DDI0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_SHIFT) +#define DDI0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_SHIFT (22) /* Bits 22-23 */ +#define DDI0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_MASK (3 << DDI0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_SHIFT) +# define DDI0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM(n) ((uint32_t)(n) << DDI0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_SHIFT) + +/* DDI0_OSC_RCOSCHFCTL */ + +#define DDI0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_SHIFT (8) /* Bits 8-15 */ +#define DDI0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_MASK (0xff << DDI0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_SHIFT) +# define DDI0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM(n) ((uint32_t)(n) << DDI0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_SHIFT) + +/* DDI0_OSC_STAT0 */ + +#define DDI0_OSC_STAT0_PENDINGSCLKHFSWITCHING (1 << 0) /* Bit 0: Indicates when SCLK_HF clock source + * is ready to be switched */ +#define DDI0_OSC_STAT0_ADC_DATA_SHIFT (1) /* Bits 1-6: adc_data */ +#define DDI0_OSC_STAT0_ADC_DATA_MASK (0x3f << DDI0_OSC_STAT0_ADC_DATA_SHIFT) +# define DDI0_OSC_STAT0_ADC_DATA(n) ((uint32_t)(n) << DDI0_OSC_STAT0_ADC_DATA_SHIFT) +#define DDI0_OSC_STAT0_ADC_DATA_READY (1 << 7) /* Bit 7: Indicates when adc_data is ready */ +#define DDI0_OSC_STAT0_ADC_THMET (1 << 8) /* Bit 8: ADC_THMET */ +#define DDI0_OSC_STAT0_XOSC_HF_HP_BUF_EN (1 << 10) /* Bit 10: XOSC_HF_HP_BUF_EN */ +#define DDI0_OSC_STAT0_XOSC_HF_LP_BUF_EN (1 << 11) /* Bit 11: XOSC_HF_LP_BUF_EN */ +#define DDI0_OSC_STAT0_XB_48M_CLK_EN (1 << 13) /* Bit 13: Indicates that the 48MHz clock from + * the DOUBLER is enabled */ +#define DDI0_OSC_STAT0_XOSC_HF_EN (1 << 15) /* Bit 15: Indicates that XOSC_HF is enabled */ +#define DDI0_OSC_STAT0_SCLK_LF_LOSS (1 << 16) /* Bit 16: Indicates sclk_lf is lost */ +#define DDI0_OSC_STAT0_SCLK_HF_LOSS (1 << 17) /* Bit 17: Indicates sclk_hf is lost */ +#define DDI0_OSC_STAT0_CLK_DCDC_RDY_ACK (1 << 18) /* Bit 18: CLK_DCDC ready acknowledge */ +#define DDI0_OSC_STAT0_CLK_DCDC_RDY (1 << 19) /* Bit 19: CLK_DCDC ready */ +#define DDI0_OSC_STAT0_XOSC_LF_EN (1 << 20) /* Bit 20: XOSC_LF enable */ +#define DDI0_OSC_STAT0_RCOSC_LF_EN (1 << 21) /* Bit 21: RCOSC_LF enable */ +#define DDI0_OSC_STAT0_RCOSC_HF_EN (1 << 22) /* Bit 22: RSOSC_HF enable */ +#define DDI0_OSC_STAT0_SCLK_HF_SRC (1 << 28) /* Bit 28: Indicates source for sclk_hf */ +# define DDI0_OSC_STAT0_SCLK_HF_SRC_RCOSC (0) /* High frequency RCOSC clock */ +# define DDI0_OSC_STAT0_SCLK_HF_SRC_XOSC DDI0_OSC_STAT0_SCLK_HF_SRC /* High frequency XOSC */ +#define DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT (29) /* Bits 29-30: Indicates source for the sclk_lf */ +#define DDI0_OSC_STAT0_SCLK_LF_SRC_MASK (3 << DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT) +# define DDI0_OSC_STAT0_SCLK_LF_SRC(n) ((uint32_t)(n) << DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT) +# define DDI0_OSC_STAT0_SCLK_LF_SRC_XOSCLF (3 << DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT) /* Low frequency XOSC */ +# define DDI0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF (2 << DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT) /* Low frequency RCOSC */ +# define DDI0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF (1 << DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT) /* Low frequency clock derived from + * High Frequency XOSC */ +# define DDI0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF (0 << DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT) /* Low frequency clock derived from + * High Frequency RCOSC */ + +/* DDI0_OSC_STAT1 */ + +#define DDI0_OSC_STAT1_CLK_DCDC_GOOD (1 << 0) /* Bit 0: CLK_DCDC_GOOD */ +#define DDI0_OSC_STAT1_CLK_CHP_GOOD (1 << 1) /* Bit 1: CLK_CHP_GOOD */ +#define DDI0_OSC_STAT1_ACLK_REF_GOOD (1 << 2) /* Bit 2: ACLK_REF_GOOD */ +#define DDI0_OSC_STAT1_ACLK_TDC_GOOD (1 << 3) /* Bit 3: ACLK_TDC_GOOD */ +#define DDI0_OSC_STAT1_ACLK_ADC_GOOD (1 << 4) /* Bit 4: ACLK_ADC_GOOD */ +#define DDI0_OSC_STAT1_SCLK_LF_GOOD (1 << 5) /* Bit 5: SCLK_LF_GOOD */ +#define DDI0_OSC_STAT1_SCLK_MF_GOOD (1 << 6) /* Bit 6: SCLK_MF_GOOD */ +#define DDI0_OSC_STAT1_SCLK_HF_GOOD (1 << 7) /* Bit 7: SCLK_HF_GOOD */ +#define DDI0_OSC_STAT1_CLK_DCDC_EN (1 << 8) /* Bit 8: CLK_DCDC_EN */ +#define DDI0_OSC_STAT1_CLK_CHP_EN (1 << 9) /* Bit 9: CLK_CHP_EN */ +#define DDI0_OSC_STAT1_ACLK_REF_EN (1 << 10) /* Bit 10: ACLK_REF_EN */ +#define DDI0_OSC_STAT1_ACLK_TDC_EN (1 << 11) /* Bit 11: ACLK_TDC_EN */ +#define DDI0_OSC_STAT1_ACLK_ADC_EN (1 << 12) /* Bit 12: ACLK_ADC_EN */ +#define DDI0_OSC_STAT1_SCLK_MF_EN (1 << 13) /* Bit 13: SCLK_MF_EN */ +#define DDI0_OSC_STAT1_SCLK_HF_EN (1 << 14) /* Bit 14: SCLK_HF_EN */ +#define DDI0_OSC_STAT1_FORCE_RCOSC_HF (1 << 15) /* Bit 15: force_rcosc_hf */ +#define DDI0_OSC_STAT1_LPM_UPDATE_AMP_SHIFT (16) /* Bits 16-21: OSC amplitude during LPM_UPDATE state */ +#define DDI0_OSC_STAT1_LPM_UPDATE_AMP_MASK (0x3f << DDI0_OSC_STAT1_LPM_UPDATE_AMP_SHIFT) +# define DDI0_OSC_STAT1_LPM_UPDATE_AMP(n) ((uint32_t)(n) << DDI0_OSC_STAT1_LPM_UPDATE_AMP_SHIFT) +#define DDI0_OSC_STAT1_HPM_UPDATE_AMP_SHIFT (22) /* Bits 22-27: OSC amplitude during HPM_UPDATE state */ +#define DDI0_OSC_STAT1_HPM_UPDATE_AMP_MASK (0x3f << DDI0_OSC_STAT1_HPM_UPDATE_AMP_SHIFT) +# define DDI0_OSC_STAT1_HPM_UPDATE_AMP(n) ((uint32_t)(n) << DDI0_OSC_STAT1_HPM_UPDATE_AMP_SHIFT) +#define DDI0_OSC_STAT1_RAMPSTATE_SHIFT (28) /* Bits 28-31: AMPCOMP FSM State */ +#define DDI0_OSC_STAT1_RAMPSTATE_MASK (15 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) +# define DDI0_OSC_STAT1_RAMPSTATE_RESET (0 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* RESET */ +# define DDI0_OSC_STAT1_RAMPSTATE_INITIALIZATION (1 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* INITIALIZATION */ +# define DDI0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 (2 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* HPM_RAMP1 */ +# define DDI0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 (3 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* HPM_RAMP2 */ +# define DDI0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 (4 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* HPM_RAMP3 */ +# define DDI0_OSC_STAT1_RAMPSTATE_HPM_UPDATE (5 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* HPM_UPDATE */ +# define DDI0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT (6 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* IDAC_INCREMENT */ +# define DDI0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE (7 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* IBIAS_CAP_UPDATE */ +# define DDI0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE (8 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* IBIAS_DECREMENT_WITH_MEASURE */ +# define DDI0_OSC_STAT1_RAMPSTATE_LPM_UPDATE (9 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* LPM_UPDATE */ +# define DDI0_OSC_STAT1_RAMPSTATE_IBIAS_INC (10 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* IBIAS_INCREMENT */ +# define DDI0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE (11 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* IDAC_DECREMENT_WITH_MEASURE */ +# define DDI0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 (12 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* DUMMY_TO_INIT_1 */ +# define DDI0_OSC_STAT1_RAMPSTATE_FAST_START (13 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* FAST_START */ +# define DDI0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE (14 << DDI0_OSC_STAT1_RAMPSTATE_SHIFT) /* FAST_START_SETTLE */ + +/* DDI0_OSC_STAT2 */ + +#define DDI0_OSC_STAT2_XOSC_HF_RF_FREQGOOD (1 << 0) /* Bit 0: Frequency of xosc_hf is within +/- 20 ppm + * and xosc_hf is good for radio operations. */ +#define DDI0_OSC_STAT2_XOSC_HF_FREQGOOD (1 << 1) /* Bit 1: Frequency of xosc_hf is good to use for + * the digital clocks */ +#define DDI0_OSC_STAT2_XOSC_HF_AMPGOOD (1 << 2) /* Bit 2: Amplitude of xosc_hf is within the + * required threshold (set by DDI) */ +#define DDI0_OSC_STAT2_AMPCOMP_REQ (1 << 3) /* Bit 3: AMPCOMP_REQ */ +#define DDI0_OSC_STAT2_RAMPSTATE_SHIFT (12) /* Bits 12-15: xosc_hf amplitude compensation FSM */ +#define DDI0_OSC_STAT2_RAMPSTATE_MASK (15 << DDI0_OSC_STAT2_RAMPSTATE_SHIFT) +# define DDI0_OSC_STAT2_RAMPSTATE(n) ((uint32_t)(n) << DDI0_OSC_STAT2_RAMPSTATE_SHIFT) +#define DDI0_OSC_STAT2_HPM_RAMP3_THMET (1 << 23) /* Bit 23: Indication of threshold is met for hpm_ramp3 */ +#define DDI0_OSC_STAT2_HPM_RAMP2_THMET (1 << 24) /* Bit 24: Indication of threshold is met for hpm_ramp2 */ +#define DDI0_OSC_STAT2_HPM_RAMP1_THMET (1 << 25) /* Bit 25: Indication of threshold is met for hpm_ramp1 */ +#define DDI0_OSC_STAT2_ADC_DCBIAS_SHIFT (26) /* Bits 26-31: DC Bias read by RADC during SAR mode */ +#define DDI0_OSC_STAT2_ADC_DCBIAS_MASK (0x3f << DDI0_OSC_STAT2_ADC_DCBIAS_SHIFT) +# define DDI0_OSC_STAT2_ADC_DCBIAS(n) ((uint32_t)(n) << DDI0_OSC_STAT2_ADC_DCBIAS_SHIFT) + +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_DDI0_OSC_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h index 98c2cf68e5..b4d78bfb08 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h @@ -146,7 +146,7 @@ * 0=CLK_DCDC is 48 MHz clock from RCOSC or XOSC/HPOSC * 1=CLK_DCDC is always 48 MHz clock from RCOSC */ #define DDI0_OSC_CTL0_DOUBLER_RESET_DURATION (1 << 25) /* Bit 25 */ -#define DDI0_OSC_CTL0_DOUBLER_START_DURATION_SHIFT (26) /* Bits 16-27 */ +#define DDI0_OSC_CTL0_DOUBLER_START_DURATION_SHIFT (26) /* Bits 26-27 */ #define DDI0_OSC_CTL0_DOUBLER_START_DURATION_MASK (3 << DDI0_OSC_CTL0_DOUBLER_START_DURATION_SHIFT) # define DDI0_OSC_CTL0_DOUBLER_START_DURATION(n) ((uint32_t)(n) << DDI0_OSC_CTL0_DOUBLER_START_DURATION_SHIFT) #define DDI0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL (1 << 28) /* Bit 28 */ @@ -264,16 +264,16 @@ # define DDI0_OSC_ATESTCTL_ATEST_RCOSCMF_BIAS (3 << DDI0_OSC_ATESTCTL_ATEST_RCOSCMF_SHIFT) /* ATEST enabled, bias current connected, * ATEST internal to RCOSC_MF enabled * to send out 2MHz clock. */ -#define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT (14) /* Bits 14-15: Test mode control for RCOSC_MF */ -#define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_MASK (3 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) -# define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_DISABLE (0 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) /* Test modes disabled */ -# define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_BOOST (1 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) /* Boosted bias current into self - * biased inverter */ -# define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_QUALDIS (2 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) /* Clock qualification disabled */ -# define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_BOOSTDIS (3 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) /* Boosted bias current into self - * biased inverter + clock qualification - * disabled */ -#define DDI0_OSC_ATESTCTL_SCLK_LF_AUX_EN (1 << 31) /* Bit 31: Enable 32 kHz clock to AUX_COMPB */ +#define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT (14) /* Bits 14-15: Test mode control for RCOSC_MF */ +#define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_MASK (3 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) +# define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_DISABLE (0 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) /* Test modes disabled */ +# define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_BOOST (1 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) /* Boosted bias current into self + * biased inverter */ +# define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_QUALDIS (2 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) /* Clock qualification disabled */ +# define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_BOOSTDIS (3 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) /* Boosted bias current into self + * biased inverter + clock qualification + * disabled */ +#define DDI0_OSC_ATESTCTL_SCLK_LF_AUX_EN (1 << 31) /* Bit 31: Enable 32 kHz clock to AUX_COMPB */ /* DDI0_OSC_ADCDOUBLERNANOAMPCTL */ diff --git a/configs/beaglebone-black/README.txt b/configs/beaglebone-black/README.txt index de38d9e47b..93596c3d4e 100644 --- a/configs/beaglebone-black/README.txt +++ b/configs/beaglebone-black/README.txt @@ -46,7 +46,6 @@ README - SD Card - UART - TODO: Contents @@ -131,17 +130,36 @@ Booting NuttX from an SD card These are the steps to get U-Boot booting from SD Card: - 1. Stop Beaglebone Black boot process in U-Boot. + 1. Configure and build the NuttX Beaglebone Black configuration. You + should have a file alled nuttx.bin when the build completes. - 2. Insert a FLASH stick into host pc and format FAT32 FS. + 2. Insert a FLASH stick into the host PC and format it for FAT32 FS. 3. Copy nuttx.bin into FLASH stick root. - 4. Remove the FLASH stick from the host pc. Insert into the Beaglecone Black - microSD slot. Load Nuttx into memory and run + 4. Remove the FLASH stick from the host PC. Insert into the Beaglebone + Black microSD slot. - U-Boot# load mmc 0 0x8a000000 nuttx.bin - U-Boot# go 0x8a000000 + 5. Connect a RS-232 Converted or USB serial adapter onto the Beaglebone + Black board and open a serial terminal on the host PC to communicate + with the target. + + 6. Reset the Stop Beaglebone Black boot. You should see output from + U-boot in the serial console. Stop the normal boot-up sequence + after the U-Boot prompt before Linux is started.: + + Hit any key to stop autoboot: 0 + U-Boot# + + 7. Load Nuttx into memory from the U-Boot prompt and run + + U-Boot# load mmc 0 0x8a000000 nuttx.bin + U-Boot# go 0x8a000000 + + If your are running the 'nsh' configuration you then should see: + + NuttShell (NSH) + nsh> Configurations ==============