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Kinetis:Refactor clocking in kinetis_usbdev

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1) Removed SIM_CLKDIV2[USBFRAC, USBDIV] setting as it is now
     done in kinetis_clockconfig
  2) Use BOARD_USB_CLKSRC to select the clock source to the
     USB block
  3) Removed warning
  4) Removed CONFIG_TEENSY_3X_OVERCLOCK from the driver as
     the board.h will now provide BOARD_SIM_CLKDIV2_USBDIV
     and BOARD_SIM_CLKDIV2_USBFRAC to the kinetis_clockconfig
This commit is contained in:
David Sidrane 2017-02-27 13:13:24 -10:00
parent 1c518b223d
commit d0c58fffb3
1 changed files with 8 additions and 21 deletions
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29
arch/arm/src/kinetis/kinetis_usbdev.c
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@ -4393,37 +4393,24 @@ void up_usbinitialize(void)
* it using a pointer to make any future ports to multiple USB controllers
* easier.
*/
#if 1
#warning "This code needs to be driven by BOARD_ settings and SIM_SOPT2[PLLFLLSE] needs to be set globally"
/* 1: Select clock source */
/* Select clock source:
* SIM_SOPT2[PLLFLLSEL] and SIM_CLKDIV2[USBFRAC, USBDIV] will have been
* configured in kinetis_pllconfig. So here we select between USB_CLKIN
* or the output of SIM_CLKDIV2[USBFRAC, USBDIV]
*/
regval = getreg32(KINETIS_SIM_SOPT2);
regval |= SIM_SOPT2_PLLFLLSEL_MCGPLLCLK | SIM_SOPT2_USBSRC;
regval &= ~(SIM_SOPT2_USBSRC);
regval |= BOARD_USB_CLKSRC;
putreg32(regval, KINETIS_SIM_SOPT2);
regval = getreg32(KINETIS_SIM_CLKDIV2);
#if defined(CONFIG_TEENSY_3X_OVERCLOCK)
/* USBFRAC/USBDIV = 1/2 of 96Mhz clock = 48MHz */
regval = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
#else
/* USBFRAC/USBDIV = 2/3 of 72Mhz clock = 48MHz */
/* 72Mhz */
regval = SIM_CLKDIV2_USBDIV(3) | SIM_CLKDIV2_USBFRAC(2);
#endif
putreg32(regval, KINETIS_SIM_CLKDIV2);
/* 2: Gate USB clock */
regval = getreg32(KINETIS_SIM_SCGC4);
regval |= SIM_SCGC4_USBOTG;
putreg32(regval, KINETIS_SIM_SCGC4);
#endif
usbtrace(TRACE_DEVINIT, 0);
/* Initialize the driver state structure */