From d1057403c696bea257f45ef06e262760ee658c3d Mon Sep 17 00:00:00 2001 From: "Daniel P. Carvalho" Date: Wed, 4 Nov 2020 17:41:00 -0300 Subject: [PATCH] Add helper functions to: enable/disable timer dump timer registers The timer is no longer enabled at the end of stm32l4_tim_setclock(). --- arch/arm/src/stm32l4/stm32l4_tim.c | 83 +++++++++++++++++++++++------- arch/arm/src/stm32l4/stm32l4_tim.h | 4 ++ 2 files changed, 69 insertions(+), 18 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c index bd570c19f1..40e10ca657 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ b/arch/arm/src/stm32l4/stm32l4_tim.c @@ -254,8 +254,7 @@ static inline void stm32l4_putreg32(FAR struct stm32l4_tim_dev_s *dev, /* Timer helpers */ static void stm32l4_tim_reload_counter(FAR struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_enable(FAR struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_disable(FAR struct stm32l4_tim_dev_s *dev); +static void stm32l4_tim_enable(FAR struct stm32l4_tim_dev_s *dev, bool state); static void stm32l4_tim_reset(FAR struct stm32l4_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ @@ -264,6 +263,7 @@ static void stm32l4_tim_reset(FAR struct stm32l4_tim_dev_s *dev); defined(HAVE_TIM17_GPIOCONFIG) static void stm32l4_tim_gpioconfig(uint32_t cfg, enum stm32l4_tim_channel_e mode); #endif +static void stm32l4_tim_dumpregs(FAR struct stm32l4_tim_dev_s *dev); /* Timer methods */ @@ -311,6 +311,8 @@ static const struct stm32l4_tim_ops_s stm32l4_tim_ops = .disableint = stm32l4_tim_disableint, .ackint = stm32l4_tim_ackint, .checkint = stm32l4_tim_checkint, + .enable = stm32l4_tim_enable, + .dump_regs = stm32l4_tim_dumpregs, }; #ifdef CONFIG_STM32L4_TIM1 @@ -504,22 +506,19 @@ static void stm32l4_tim_reload_counter(FAR struct stm32l4_tim_dev_s *dev) * Name: stm32l4_tim_enable ************************************************************************************/ -static void stm32l4_tim_enable(FAR struct stm32l4_tim_dev_s *dev) +static void stm32l4_tim_enable(FAR struct stm32l4_tim_dev_s *dev, bool state) { uint16_t val = stm32l4_getreg16(dev, STM32L4_BTIM_CR1_OFFSET); - val |= ATIM_CR1_CEN; - stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32L4_BTIM_CR1_OFFSET, val); -} -/************************************************************************************ - * Name: stm32l4_tim_disable - ************************************************************************************/ - -static void stm32l4_tim_disable(FAR struct stm32l4_tim_dev_s *dev) -{ - uint16_t val = stm32l4_getreg16(dev, STM32L4_BTIM_CR1_OFFSET); - val &= ~ATIM_CR1_CEN; + if(state) + { + val |= ATIM_CR1_CEN; + stm32l4_tim_reload_counter(dev); + } + else + { + val &= ~ATIM_CR1_CEN; + } stm32l4_putreg16(dev, STM32L4_BTIM_CR1_OFFSET, val); } @@ -534,7 +533,7 @@ static void stm32l4_tim_disable(FAR struct stm32l4_tim_dev_s *dev) static void stm32l4_tim_reset(FAR struct stm32l4_tim_dev_s *dev) { ((struct stm32l4_tim_priv_s *)dev)->mode = STM32L4_TIM_MODE_DISABLED; - stm32l4_tim_disable(dev); + stm32l4_tim_enable(dev, false); } /************************************************************************************ @@ -561,6 +560,53 @@ static void stm32l4_tim_gpioconfig(uint32_t cfg, enum stm32l4_tim_channel_e mode } #endif +/************************************************************************************ + * Name: stm32l4_tim_dumpregs + ************************************************************************************/ + +static void stm32l4_tim_dumpregs(FAR struct stm32l4_tim_dev_s *dev) +{ + struct stm32l4_tim_priv_s *priv = (struct stm32l4_tim_priv_s *)dev; + { + /* data */ + }; + + ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET), + stm32l4_getreg16(dev, STM32L4_GTIM_CR2_OFFSET), + stm32l4_getreg16(dev, STM32L4_GTIM_SMCR_OFFSET), + stm32l4_getreg16(dev, STM32L4_GTIM_DIER_OFFSET)); + ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", + stm32l4_getreg16(dev, STM32L4_GTIM_SR_OFFSET), + stm32l4_getreg16(dev, STM32L4_GTIM_CCMR1_OFFSET), + stm32l4_getreg16(dev, STM32L4_GTIM_CCMR2_OFFSET)); + ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", + stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET), + stm32l4_getreg16(dev, STM32L4_GTIM_CNT_OFFSET), + stm32l4_getreg16(dev, STM32L4_GTIM_PSC_OFFSET), + stm32l4_getreg16(dev, STM32L4_GTIM_ARR_OFFSET)); + ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", + stm32l4_getreg16(dev, STM32L4_GTIM_CCR1_OFFSET), + stm32l4_getreg16(dev, STM32L4_GTIM_CCR2_OFFSET), + stm32l4_getreg16(dev, STM32L4_GTIM_CCR3_OFFSET), + stm32l4_getreg16(dev, STM32L4_GTIM_CCR4_OFFSET)); + + if (priv->base == STM32L4_TIM1_BASE || priv->base == STM32L4_TIM8_BASE) + { + ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", + stm32l4_getreg16(dev, STM32L4_ATIM_RCR_OFFSET), + stm32l4_getreg16(dev, STM32L4_ATIM_BDTR_OFFSET), + stm32l4_getreg16(dev, STM32L4_ATIM_DCR_OFFSET), + stm32l4_getreg16(dev, STM32L4_ATIM_DMAR_OFFSET)); + } + else + { + ainfo(" DCR: %04x DMAR: %04x\n", + stm32l4_getreg16(dev, STM32L4_GTIM_DCR_OFFSET), + stm32l4_getreg16(dev, STM32L4_GTIM_DMAR_OFFSET)); + } +} + /************************************************************************************ * Name: stm32l4_tim_setmode ************************************************************************************/ @@ -599,8 +645,10 @@ static int stm32l4_tim_setmode(FAR struct stm32l4_tim_dev_s *dev, case STM32L4_TIM_MODE_DOWN: val |= ATIM_CR1_DIR; + break; case STM32L4_TIM_MODE_UP: + val &= ~ATIM_CR1_DIR; break; case STM32L4_TIM_MODE_UPDOWN: @@ -650,7 +698,7 @@ static int stm32l4_tim_setclock(FAR struct stm32l4_tim_dev_s *dev, if (freq == 0) { - stm32l4_tim_disable(dev); + stm32l4_tim_enable(dev, false); return 0; } @@ -754,7 +802,6 @@ static int stm32l4_tim_setclock(FAR struct stm32l4_tim_dev_s *dev, } stm32l4_putreg16(dev, STM32L4_BTIM_PSC_OFFSET, prescaler); - stm32l4_tim_enable(dev); return prescaler; } diff --git a/arch/arm/src/stm32l4/stm32l4_tim.h b/arch/arm/src/stm32l4/stm32l4_tim.h index b5b939051b..51f1a37503 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/stm32l4_tim.h @@ -71,6 +71,8 @@ #define STM32L4_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) #define STM32L4_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) #define STM32L4_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32L4_TIM_ENABLE(d,s) ((d)->ops->enable(d,s)) +#define STM32L4_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) /************************************************************************************ * Public Types @@ -192,6 +194,8 @@ struct stm32l4_tim_ops_s void (*disableint)(FAR struct stm32l4_tim_dev_s *dev, int source); void (*ackint)(FAR struct stm32l4_tim_dev_s *dev, int source); int (*checkint)(FAR struct stm32l4_tim_dev_s *dev, int source); + void (*enable)(FAR struct stm32l4_tim_dev_s *dev, bool state); + void (*dump_regs)(FAR struct stm32l4_tim_dev_s *dev); }; /************************************************************************************