Finish Kinetis SDHC header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3871 42af7a65-404d-4744-a932-0658087f49c3
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@ -105,57 +105,266 @@
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/* Register Bit Definitions *********************************************************/
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/* DMA System Address Register */
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#define SDHC_DSADDR_
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/* Block Attributes Register */
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#define SDHC_BLKATTR_
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/* Command Argument Register */
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#define SDHC_CMDARG_
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/* Transfer Type Register */
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#define SDHC_XFERTYP_
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/* Command Response 0 */
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#define SDHC_CMDRSP0_
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/* Command Response 1 */
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#define SDHC_CMDRSP1_
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/* Command Response 2 */
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#define SDHC_CMDRSP2_
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/* Command Response 3 */
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#define SDHC_CMDRSP3_
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/* Buffer Data Port Register */
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#define SDHC_DATPORT_
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/* Present State Register */
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#define SDHC_PRSSTAT_
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/* Protocol Control Register */
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#define SDHC_PROCTL_
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/* System Control Register */
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#define SDHC_SYSCTL_
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/* Interrupt Status Register */
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#define SDHC_IRQSTAT_
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/* Interrupt Status Enable Register */
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#define SDHC_IRQSTATEN_
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/* Interrupt Signal Enable Register */
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#define SDHC_IRQSIGEN_
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/* Auto CMD12 Error Status Register */
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#define SDHC_AC12ERR_
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/* Host Controller Capabilities */
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#define SDHC_HTCAPBLT_
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/* Watermark Level Register */
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#define SDHC_WML_
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/* Force Event Register */
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#define SDHC_FEVT_
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/* ADMA Error Status Register */
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#define SDHC_ADMAES_
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/* ADMA System Address Register */
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#define SDHC_ADSADDR_
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/* Vendor Specific Register */
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#define SDHC_VENDOR_
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/* MMC Boot Register */
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#define SDHC_MMCBOOT_
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/* Host Controller Version */
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#define SDHC_HOSTVER_
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(1 << nn) /* Bit nn:
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_SHIFT (nn) /* Bits nn-nn:
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_MASK (nn << nn)
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#define SDHC_DSADDR_SHIFT (1) /* Bits 1-31: DMA System Address */
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#define SDHC_DSADDR_MASK (0xfffffffe)
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/* Bits 0-1: Reserved */
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/* Block Attributes Register */
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#define SDHC_BLKATTR_SIZE_SHIFT (0) /* Bits 0-12: Transfer Block Size */
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#define SDHC_BLKATTR_SIZE_MASK (0x1fff << SDHC_BLKATTR_BLKSIZE_SHIFT)
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/* Bits 13-15: Reserved */
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#define SDHC_BLKATTR_CNT_SHIFT (16) /* Bits 16-31: Blocks Count For Current Transfer */
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#define SDHC_BLKATTR_CNT_MASK (0xffff << SDHC_BLKATTR_BLKCNT_SHIFT)
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/* Command Argument Register (32-bit cmd/arg data) */
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/* Transfer Type Register */
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#define SDHC_XFERTYP_DMAEN (1 << 0) /* Bit 0: DMA Enable */
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#define SDHC_XFERTYP_BCEN (1 << 1) /* Bit 1: Block Count Enable */
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#define SDHC_XFERTYP_AC12EN (1 << 2) /* Bit 2: Auto CMD12 Enable */
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/* Bit 3: Reserved */
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#define SDHC_XFERTYP_DTDSEL (1 << 4) /* Bit 4: Data Transfer Direction Select */
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#define SDHC_XFERTYP_MSBSEL (1 << 5) /* Bit 5: Multi/Single Block Select */
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/* Bits 6-15: Reserved */
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#define SDHC_XFERTYP_RSPTYP_SHIFT (16) /* Bits 16-17: Response Type Select */
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#define SDHC_XFERTYP_RSPTYP_MASK (3 << SDHC_XFERTYP_RSPTYP_SHIFT)
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# define SDHC_XFERTYP_RSPTYP_NONE (0 << SDHC_XFERTYP_RSPTYP_SHIFT) /* No response */
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# define SDHC_XFERTYP_RSPTYP_LEN136 (1 << SDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 136 */
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# define SDHC_XFERTYP_RSPTYP_LEN48 (2 << SDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 48 */
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# define SDHC_XFERTYP_RSPTYP_LEN48BSY (3 << SDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 48, check busy */
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/* Bit 18: Reserved */
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#define SDHC_XFERTYP_CCCEN (1 << 19) /* Bit 19: Command CRC Check Enable */
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#define SDHC_XFERTYP_CICEN (1 << 20) /* Bit 20: Command Index Check Enable */
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#define SDHC_XFERTYP_DPSEL (1 << 21) /* Bit 21: Data Present Select */
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#define SDHC_XFERTYP_CMDTYP_SHIFT (22) /* Bits 22-23: Command Type */
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#define SDHC_XFERTYP_CMDTYP_MASK (3 << SDHC_XFERTYP_CMDTYP_SHIFT)
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# define SDHC_XFERTYP_CMDTYP_NORMAL (0 << SDHC_XFERTYP_CMDTYP_SHIFT) /* Normal other commands */
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# define SDHC_XFERTYP_CMDTYP_SUSPEND (1 << SDHC_XFERTYP_CMDTYP_SHIFT) /* Suspend CMD52 for writing bus suspend in CCCR */
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# define SDHC_XFERTYP_CMDTYP_RESUME (2 << SDHC_XFERTYP_CMDTYP_SHIFT) /* Resume CMD52 for writing function select in CCCR */
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# define SDHC_XFERTYP_CMDTYP_ABORT (3 << SDHC_XFERTYP_CMDTYP_SHIFT) /* Abort CMD12, CMD52 for writing I/O abort in CCCR */
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#define SDHC_XFERTYP_CMDINX_SHIFT (24) /* Bits 24-29: Command Index */
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#define SDHC_XFERTYP_CMDINX_MASK (63 << SDHC_XFERTYP_CMDINX_SHIFT)
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/* Bits 30-31: Reserved */
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/* Command Response 0-3 (32-bit response data) */
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/* Buffer Data Port Register (32-bit data content) */
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/* Present State Register */
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#define SDHC_PRSSTAT_CIHB (1 << 0) /* Bit 0: Command Inhibit (CMD) */
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#define SDHC_PRSSTAT_CDIHB (1 << 1) /* Bit 1: Command Inhibit (DAT) */
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#define SDHC_PRSSTAT_DLA (1 << 2) /* Bit 2: Data Line Active */
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#define SDHC_PRSSTAT_SDSTB (1 << 3) /* Bit 3: SD Clock Stable */
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#define SDHC_PRSSTAT_IPGOFF (1 << 4) /* Bit 4: Bus Clock */
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#define SDHC_PRSSTAT_HCKOFF (1 << 5) /* Bit 5: System Clock */
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#define SDHC_PRSSTAT_PEROFF (1 << 6) /* Bit 6: SDHC clock */
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#define SDHC_PRSSTAT_SDOFF (1 << 7) /* Bit 7: SD Clock Gated Off Internally */
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#define SDHC_PRSSTAT_WTA (1 << 8) /* Bit 8: Write Transfer Active */
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#define SDHC_PRSSTAT_RTA (1 << 9) /* Bit 9: Read Transfer Active */
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#define SDHC_PRSSTAT_BWEN (1 << 10) /* Bit 10: Buffer Write Enable */
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#define SDHC_PRSSTAT_BREN (1 << 11) /* Bit 11: Buffer Read Enable */
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/* Bits 12-15: Reserved */
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#define SDHC_PRSSTAT_CINS (1 << 16) /* Bit 16: Card Inserted */
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/* Bits 17-22: Reserved */
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#define SDHC_PRSSTAT_CLSL (1 << 23) /* Bit 23: CMD Line Signal Level */
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#define SDHC_PRSSTAT_DLSL_SHIFT (24) /* Bits 24-31: DAT Line Signal Level */
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#define SDHC_PRSSTAT_DLSL_MASK (0xff << SDHC_PRSSTAT_DLSL_SHIFT)
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# define SDHC_PRSSTAT_DLSL_DAT0 (0x01 << SDHC_PRSSTAT_DLSL_SHIFT)
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# define SDHC_PRSSTAT_DLSL_DAT1 (0x02 << SDHC_PRSSTAT_DLSL_SHIFT)
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# define SDHC_PRSSTAT_DLSL_DAT2 (0x04 << SDHC_PRSSTAT_DLSL_SHIFT)
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# define SDHC_PRSSTAT_DLSL_DAT3 (0x08 << SDHC_PRSSTAT_DLSL_SHIFT)
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# define SDHC_PRSSTAT_DLSL_DAT4 (0x10 << SDHC_PRSSTAT_DLSL_SHIFT)
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# define SDHC_PRSSTAT_DLSL_DAT5 (0x20 << SDHC_PRSSTAT_DLSL_SHIFT)
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# define SDHC_PRSSTAT_DLSL_DAT6 (0x40 << SDHC_PRSSTAT_DLSL_SHIFT)
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# define SDHC_PRSSTAT_DLSL_DAT7 (0x80 << SDHC_PRSSTAT_DLSL_SHIFT)
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/* Protocol Control Register */
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#define SDHC_PROCTL_LCTL (1 << 0) /* Bit 0: LED Control */
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#define SDHC_PROCTL_DTW_SHIFT (1) /* Bits 1-2: Data Transfer Width */
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#define SDHC_PROCTL_DTW_MASK (3 << SDHC_PROCTL_DTW_SHIFT)
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# define SDHC_PROCTL_DTW_1BIT (0 << SDHC_PROCTL_DTW_SHIFT) /* 1-bit mode */
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# define SDHC_PROCTL_DTW_4BIT (1 << SDHC_PROCTL_DTW_SHIFT) /* 4-bit mode */
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# define SDHC_PROCTL_DTW_8BIT (2 << SDHC_PROCTL_DTW_SHIFT) /* 8-bit mode */
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#define SDHC_PROCTL_D3CD (1 << 3) /* Bit nn: DAT3 as Card Detection Pin */
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#define SDHC_PROCTL_EMODE_SHIFT (4) /* Bits 4-5: Endian mode */
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#define SDHC_PROCTL_EMODE_MASK (3 << SDHC_PROCTL_EMODE_SHIFT)
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# define SDHC_PROCTL_EMODE_BE (0 << SDHC_PROCTL_EMODE_SHIFT) /* Big endian mode */
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# define SDHC_PROCTL_EMODE_HWBE (1 << SDHC_PROCTL_EMODE_SHIFT) /* Half word big endian mode */
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# define SDHC_PROCTL_EMODE_LE (2 << SDHC_PROCTL_EMODE_SHIFT) /* Little endian mode */
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#define SDHC_PROCTL_CDTL (1 << 6) /* Bit 6: Card Detect Test Level */
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#define SDHC_PROCTL_CDSS (1 << 7) /* Bit 7: Card Detect Signal Selection */
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#define SDHC_PROCTL_DMAS_SHIFT (8) /* Bits 8-9: DMA Select */
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#define SDHC_PROCTL_DMAS_MASK (3 << SDHC_PROCTL_DMAS_SHIFT)
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# define SDHC_PROCTL_DMAS_NODMA (0 << SDHC_PROCTL_DMAS_SHIFT) /* No DMA or simple DMA is selected */
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# define SDHC_PROCTL_DMAS_ADMA1 (1 << SDHC_PROCTL_DMAS_SHIFT) /* ADMA1 is selected */
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# define SDHC_PROCTL_DMAS_ADMA2 (2 << SDHC_PROCTL_DMAS_SHIFT) /* ADMA2 is selected */
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/* Bits 10-15: Reserved */
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#define SDHC_PROCTL_SABGREQ (1 << 16) /* Bit 16: Stop At Block Gap Request */
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#define SDHC_PROCTL_CREQ (1 << 17) /* Bit 17: Continue Request */
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#define SDHC_PROCTL_RWCTL (1 << 18) /* Bit 18: Read Wait Control */
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#define SDHC_PROCTL_IABG (1 << 19) /* Bit 19: Interrupt At Block Gap */
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/* Bits 20-23: Reserved */
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#define SDHC_PROCTL_WECINT (1 << 24) /* Bit 24: Wakeup Event Enable On Card Interrupt */
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#define SDHC_PROCTL_WECINS (1 << 25) /* Bit 25: Wakeup Event Enable On SD Card Insertion */
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#define SDHC_PROCTL_WECRM (1 << 26) /* Bit 26: Wakeup Event Enable On SD Card Removal */
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/* Bits 27-31: Reserved */
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/* System Control Register */
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#define SDHC_SYSCTL_IPGEN (1 << 0) /* Bit 0: IPG Clock Enable */
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#define SDHC_SYSCTL_HCKEN (1 << 1) /* Bit 1: System Clock Enable */
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#define SDHC_SYSCTL_PEREN (1 << 2) /* Bit 2: Peripheral Clock Enable */
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#define SDHC_SYSCTL_SDCLKEN (1 << 3) /* Bit 3: SD Clock Enable */
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#define SDHC_SYSCTL_DVS_SHIFT (4) /* Bits 4-7: Divisor */
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#define SDHC_SYSCTL_DVS_MASK (15 << SDHC_SYSCTL_DVS_SHIFT)
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# define SDHC_SYSCTL_DVS_DIV(n) (((n)-1) << SDHC_SYSCTL_DVS_SHIFT) /* Divide by n, n=1..16 */
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#define SDHC_SYSCTL_SDCLKFS_SHIFT (8) /* Bits 8-15: SDCLK Frequency Select */
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#define SDHC_SYSCTL_SDCLKFS_MASK (0xff << SDHC_SYSCTL_SDCLKFS_SHIFT)
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# define SDHC_SYSCTL_SDCLKFS_DIV2 (0x01 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 2 */
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# define SDHC_SYSCTL_SDCLKFS_DIV4 (0x02 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 4 */
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# define SDHC_SYSCTL_SDCLKFS_DIV8 (0x04 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 8 */
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# define SDHC_SYSCTL_SDCLKFS_DIV16 (0x08 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 16 */
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# define SDHC_SYSCTL_SDCLKFS_DIV32 (0x10 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 32 */
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# define SDHC_SYSCTL_SDCLKFS_DIV64 (0x20 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 64 */
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# define SDHC_SYSCTL_SDCLKFS_DIV128 (0x40 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 128 */
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# define SDHC_SYSCTL_SDCLKFS_DIV256 (0x80 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 256 */
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#define SDHC_SYSCTL_DTOCV_SHIFT (16) /* Bits 16-19: Data Timeout Counter Value */
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#define SDHC_SYSCTL_DTOCV_MASK (15 << SDHC_SYSCTL_DTOCV_SHIFT)
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# define SDHC_SYSCTL_DTOCV_MUL(n) (((n)-213) << SDHC_SYSCTL_DTOCV_SHIFT) /* SDCLK x n, n=213..227 */
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/* Bits 20-23: Reserved */
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#define SDHC_SYSCTL_RSTA (1 << 24) /* Bit 24: Software Reset For ALL */
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#define SDHC_SYSCTL_RSTC (1 << 25) /* Bit 25: Software Reset For CMD Line */
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#define SDHC_SYSCTL_RSTD (1 << 26) /* Bit 26: Software Reset For DAT Line */
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#define SDHC_SYSCTL_INITA (1 << 27) /* Bit 27: Initialization Active */
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/* Bits 28-31: Reserved */
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/* Interrupt Status Register, Interrupt Status Enable Register, and Interrupt Signal Enable Register
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* Common interrupt bit definitions
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*/
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#define SDHC_INT_CC (1 << 0) /* Bit 0: Command Complete */
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#define SDHC_INT_TC (1 << 1) /* Bit 1: Transfer Complete */
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#define SDHC_INT_BGE (1 << 2) /* Bit 2: Block Gap Event */
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#define SDHC_INT_DINT (1 << 3) /* Bit 3: DMA Interrupt */
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#define SDHC_INT_BWR (1 << 4) /* Bit 4: Buffer Write Ready */
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#define SDHC_INT_BRR (1 << 5) /* Bit 5: Buffer Read Ready */
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#define SDHC_INT_CINS (1 << 6) /* Bit 6: Card Insertion */
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#define SDHC_INT_CRM (1 << 7) /* Bit 7: Card Removal */
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#define SDHC_INT_CINT (1 << 8) /* Bit 8: Card Interrupt */
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/* Bits 9-15: Reserved */
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#define SDHC_INT_CTOE (1 << 16) /* Bit 16: Command Timeout Error */
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#define SDHC_INT_CCE (1 << 17) /* Bit 17: Command CRC Error */
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#define SDHC_INT_CEBE (1 << 18) /* Bit 18: Command End Bit Error */
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#define SDHC_INT_CIE (1 << 19) /* Bit 19: Command Index Error */
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#define SDHC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error */
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#define SDHC_INT_DCE (1 << 21) /* Bit 21: Data CRC Error */
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#define SDHC_INT_DEBE (1 << 22) /* Bit 22: Data End Bit Error */
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/* Bit 23: Reserved */
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#define SDHC_INT_AC12E (1 << 24) /* Bit 24: Auto CMD12 Error */
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/* Bits 25-27: Reserved */
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#define SDHC_INT_DMAE (1 << 28) /* Bit 28: DMA Error */
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/* Bits 29-31: Reserved */
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/* Auto CMD12 Error Status Register */
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#define SDHC_AC12ERR_NE (1 << 0) /* Bit 0: Auto CMD12 Not Executed */
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#define SDHC_AC12ERR_TOE (1 << 1) /* Bit 1: Auto CMD12 Timeout Error */
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#define SDHC_AC12ERR_EBE (1 << 2) /* Bit 2: Auto CMD12 End Bit Error */
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#define SDHC_AC12ERR_CE (1 << 3) /* Bit 3: Auto CMD12 CRC Error */
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#define SDHC_AC12ERR_IE (1 << 4) /* Bit 4: Auto CMD12 Index Error */
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/* Bits 5-6: Reserved */
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#define SDHC_AC12ERR_CNI (1 << 7) /* Bit 7: Command Not Issued By Auto CMD12 Error */
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/* Bits 8-31: Reserved */
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/* Host Controller Capabilities */
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/* Bits 0-15: Reserved */
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#define SDHC_HTCAPBLT_MBL_SHIFT (16) /* Bits 16-18: Max Block Length */
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#define SDHC_HTCAPBLT_MBL_MASK (7 << SDHC_HTCAPBLT_MBL_SHIFT)
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# define SDHC_HTCAPBLT_MBL_512BYTES (0 << SDHC_HTCAPBLT_MBL_SHIFT)
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# define SDHC_HTCAPBLT_MBL_1KB (1 << SDHC_HTCAPBLT_MBL_SHIFT)
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# define SDHC_HTCAPBLT_MBL_2KB (2 << SDHC_HTCAPBLT_MBL_SHIFT)
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# define SDHC_HTCAPBLT_MBL_4KB (3 << SDHC_HTCAPBLT_MBL_SHIFT)
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/* Bit 19: Reserved */
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#define SDHC_HTCAPBLT_ADMAS (1 << 20) /* Bit 20: ADMA Support */
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#define SDHC_HTCAPBLT_HSS (1 << 21) /* Bit 21: High Speed Support */
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#define SDHC_HTCAPBLT_DMAS (1 << 22) /* Bit 22: DMA Support */
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#define SDHC_HTCAPBLT_SRS (1 << 23) /* Bit 23: Suspend/Resume Support */
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#define SDHC_HTCAPBLT_VS33 (1 << 24) /* Bit 24: Voltage Support 3.3 V */
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#define SDHC_HTCAPBLT_VS30 (1 << 25) /* Bit 25: Voltage Support 3.0 V */
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#define SDHC_HTCAPBLT_VS18 (1 << 26) /* Bit 26: Voltage Support 1.8 */
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/* Bits 27-31: Reserved */
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/* Watermark Level Register */
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#define SDHC_WML_RD_SHIFT (0) /* Bits 0-7: Read Watermark Level */
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#define SDHC_WML_RD_MASK (0xff << SDHC_WML_RDWML_SHIFT)
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/* Bits 8-15: Reserved */
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#define SDHC_WML_WR_SHIFT (16) /* Bits 16-23: Write Watermark Level */
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#define SDHC_WML_WR_MASK (0xff << SDHC_WML_WRWML_SHIFT)
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/* Bits 24-31: Reserved */
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/* Force Event Register */
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#define SDHC_FEVT_AC12NE (1 << 0) /* Bit 0: Force Event Auto Command 12 Not Executed */
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#define SDHC_FEVT_AC12TOE (1 << 1) /* Bit 1: Force Event Auto Command 12 Time Out Error */
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#define SDHC_FEVT_AC12CE (1 << 2) /* Bit 2: Force Event Auto Command 12 CRC Error */
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#define SDHC_FEVT_AC12EBE (1 << 3) /* Bit 3: Force Event Auto Command 12 End Bit Error */
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#define SDHC_FEVT_AC12IE (1 << 4) /* Bit 4: Force Event Auto Command 12 Index Error */
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/* Bits 5-6: Reserved */
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#define SDHC_FEVT_CNIBAC12E (1 << 7) /* Bit 7: Force Event Command Not Executed By Auto Command 12 Error */
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/* Bits 8-15: Reserved */
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#define SDHC_FEVT_CTOE (1 << 16) /* Bit 16: Force Event Command Time Out Error */
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#define SDHC_FEVT_CCE (1 << 17) /* Bit 17: Force Event Command CRC Error */
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#define SDHC_FEVT_CEBE (1 << 18) /* Bit 18: Force Event Command End Bit Error */
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#define SDHC_FEVT_CIE (1 << 19) /* Bit 19: Force Event Command Index Error */
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#define SDHC_FEVT_DTOE (1 << 20) /* Bit 20: Force Event Data Time Out Error */
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#define SDHC_FEVT_DCE (1 << 21) /* Bit 21: Force Event Data CRC Error */
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#define SDHC_FEVT_DEBE (1 << 22) /* Bit 22: Force Event Data End Bit Error */
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/* Bit 23: Reserved */
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#define SDHC_FEVT_AC12E (1 << 24) /* Bit 24: Force Event Auto Command 12 Error */
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/* Bits 25-27: Reserved */
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#define SDHC_FEVT_DMAE (1 << 28) /* Bit 28: Force Event DMA Error */
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/* Bits 29-30: Reserved */
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#define SDHC_FEVT_CINT (1 << 31) /* Bit 31: Force Event Card Interrupt */
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/* ADMA Error Status Register */
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#define SDHC_ADMAES_SHIFT (0) /* Bits 0-1: ADMA Error State (when ADMA Error is occurred) */
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#define SDHC_ADMAES_MASK (3 << SDHC_ADMAES_ADMAES_SHIFT)
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#define SDHC_ADMAES_LME (1 << 2) /* Bit 2: ADMA Length Mismatch Error */
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#define SDHC_ADMAES_DCE (1 << 3) /* Bit 3: ADMA Descriptor Error */
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/* Bits 4-31: Reserved */
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/* ADMA System Address Register */
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#define SDHC_ADSADDR_SHIFT (1) /* Bits 1-31: ADMA System Address */
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#define SDHC_ADSADDR_MASK (0xfffffffe)
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/* Bits 0-1: Reserved */
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/* Vendor Specific Register */
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#define SDHC_VENDOR_EXTDMAEN (1 << 0) /* Bit 0: External DMA Request Enable */
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#define SDHC_VENDOR_EXBLKNU (1 << 1) /* Bit 1: Exact block number block read enable for SDIO CMD53 */
|
||||
/* Bits 2-15: Reserved */
|
||||
#define SDHC_VENDOR_INTSTVAL_SHIFT (16) /* Bits 16-23: Internal State Value */
|
||||
#define SDHC_VENDOR_INTSTVAL_MASK (0xff << SDHC_VENDOR_INTSTVAL_SHIFT)
|
||||
/* Bits 24-31: Reserved */
|
||||
/* MMC Boot Register */
|
||||
|
||||
#define SDHC_MMCBOOT_DTOCVACK_SHIFT (0) /* Bits 0-3: Boot ACK time out counter value */
|
||||
#define SDHC_MMCBOOT_DTOCVACK_MASK (15 << SDHC_MMCBOOT_DTOCVACK_SHIFT)
|
||||
# define SDHC_MMCBOOT_DTOCVACK_MUL(n) ((n-8) << SDHC_MMCBOOT_DTOCVACK_SHIFT) /* SDCLK x 2^n, n=8..22 */
|
||||
#define SDHC_MMCBOOT_BOOTACK (1 << 4) /* Bit 4: Boot ack mode select */
|
||||
#define SDHC_MMCBOOT_BOOTMODE (1 << 5) /* Bit 5: Boot mode select */
|
||||
#define SDHC_MMCBOOT_BOOTEN (1 << 6) /* Bit 6: Boot mode enable */
|
||||
#define SDHC_MMCBOOT_AUTOSABGEN (1 << 7) /* Bit 7: Enable auto stop at block gap function */
|
||||
/* Bits 8-15: Reserved */
|
||||
#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16) /* Bits 16-31: Stop at block gap value of automatic mode */
|
||||
#define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xffff << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)
|
||||
|
||||
/* Host Controller Version */
|
||||
|
||||
#define SDHC_HOSTVER_SVN_SHIFT (0) /* Bits 0-7: Specification Version Number */
|
||||
#define SDHC_HOSTVER_SVN_MASK (0xff << SDHC_HOSTVER_SVN_SHIFT)
|
||||
#define SDHC_HOSTVER_VVN_SHIFT (8) /* Bits 8-15: Vendor Version Number */
|
||||
#define SDHC_HOSTVER_VVN_MASK (0xff << SDHC_HOSTVER_VVN_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
|
||||
Loading…
Reference in New Issue
Block a user