ARMv7M/i.MX6: Implement CPUn n=1,2,3 startup logic
This commit is contained in:
Gregory Nutt
parent
7c52b8ddae
commit
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487
arch/arm/src/armv7-a/arm_cpuhead.S
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487
arch/arm/src/armv7-a/arm_cpuhead.S
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/****************************************************************************
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* arch/arm/src/armv7-a/arm_cpuhead.S
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/board/board.h>
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#include "arm.h"
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#include "cp15.h"
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#include "sctlr.h"
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#include "mmu.h"
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#include "chip.h"
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#include "up_internal.h"
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.file "arm_cpuhead.S"
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/**********************************************************************************
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* Configuration
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**********************************************************************************/
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/* Hard-coded options */
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#undef CPU_ALIGNMENT_TRAP
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#undef CPU_CACHE_ROUND_ROBIN
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#undef CPU_DCACHE_DISABLE
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#undef CPU_ICACHE_DISABLE
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#undef CPU_AFE_ENABLE
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/* Check for the identity mapping: For this configuration, this would be
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* the case where the virtual beginning of RAM is the same as the physical
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* beginning of RAM.
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*/
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#if !defined(CONFIG_RAM_START) || !defined(CONFIG_RAM_VSTART)
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# error "CONFIG_RAM_START or CONFIG_RAM_VSTART is not defined"
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#endif
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#if CONFIG_RAM_START == CONFIG_RAM_VSTART
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# define CONFIG_IDENTITY_TEXTMAP 1
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#endif
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/****************************************************************************
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* .text
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****************************************************************************/
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.text
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/****************************************************************************
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* Name: __cpu[n]_start
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*
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* Description:
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* Boot functions for each CPU (other than CPU0). These functions set up
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* the ARM operating mode, the initial stack, and configure co-processor
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* registers. At the end of the boot, arm_cpu_boot() is called.
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*
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* These functions are provided by the common ARMv7-A logic.
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*
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* Input parameters:
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* None
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*
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* Returned Value:
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* Do not return.
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*
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****************************************************************************/
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#if CONFIG_SMP_NCPUS > 1
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.global __cpu1_start
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.type __cpu1_start, #function
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__cpu1_start:
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/* Set up the stack pointer and the CPU index */
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ldr sp, .Lcpu1_stackpointer
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mov r5, #1
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/* Then branch to the common startup logic (PC-relative) */
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b .Lcpu_start
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.Lcpu1_stackpointer:
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.long .Lcpu1_stackbottom
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.size __cpu1_start, .-__cpu1_start
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#if CONFIG_SMP_NCPUS > 2
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.global __cpu2_start
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.type __cpu2_start, #function
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__cpu2_start:
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/* Set up the stack pointer and the CPU index */
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ldr sp, .Lcpu2_stackpointer
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mov r5, #2
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/* Then branch to the common startup logic (PC-relative) */
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b .Lcpu_start
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.Lcpu2_stackpointer:
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.long .Lcpu2_stackbottom
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.size __cpu2_start, .-__cpu2_start
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#if CONFIG_SMP_NCPUS > 3
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.global __cpu3_start
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.type __cpu3_start, #function
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__cpu3_start:
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/* Set up the stack pointer and the CPU index */
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ldr sp, .Lcpu3_stackpointer
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mov r5, #3
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/* Then branch to the common startup logic (PC-relative) */
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b .Lcpu_start
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.Lcpu3_stackpointer:
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.long .Lcpu3_stackbottom
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.size __cpu3_start, .-__cpu3_start
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#if CONFIG_SMP_NCPUS > 4
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# error This logic needs to extended for CONFIG_SMP_NCPUS > 4
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#endif /* CONFIG_SMP_NCPUS > 4 */
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#endif /* CONFIG_SMP_NCPUS > 3 */
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#endif /* CONFIG_SMP_NCPUS > 2 */
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#endif /* CONFIG_SMP_NCPUS > 1 */
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/****************************************************************************
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* Name: .Lcpu_start
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*
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* Description:
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* Common CPUn startup logic (n > 0)
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*
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* On input:
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* SP = Set to bottom of CPU IDLE stack (virtual)
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* R5 = CPU number
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*
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****************************************************************************/
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.type .Lcpu_start, #function
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.Lcpu_start:
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/* Make sure that we are in SVC mode with IRQs and FIQs disabled */
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mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r0
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/* The MMU and caches should be disabled */
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mrc CP15_SCTLR(r0)
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bic r0, r0, #(SCTLR_M | SCTLR_C)
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bic r0, r0, #(SCTLR_I)
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mcr CP15_SCTLR(r0)
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/* Invalidate caches and TLBs.
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*
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* NOTE: "The ARMv7 Virtual Memory System Architecture (VMSA) does not
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* support a CP15 operation to invalidate the entire data cache. ...
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* In normal usage the only time the entire data cache has to be
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* invalidated is on reset."
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*
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* The instruction cache is virtually indexed and physically tagged but
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* the data cache is physically indexed and physically tagged. So it
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* should not be an issue if the system comes up with a dirty Dcache;
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* the ICache, however, must be invalidated.
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*/
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mov r0, #0
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mcr CP15_TLBIALL(r0,c7) /* Invalidate the entire unified TLB */
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mcr CP15_TLBIALL(r0,c6)
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mcr CP15_TLBIALL(r0,c5)
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mcr CP15_BPIALL(r0) /* Invalidate entire branch prediction array */
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mcr CP15_ICIALLU(r0) /* Invalidate I-cache */
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/* Load the page table address.
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*
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* NOTES:
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* - Here we assume that the page table address is aligned to at least
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* least a 16KB boundary (bits 0-13 are zero). No masking is provided
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* to protect against an unaligned page table address.
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* - The ARMv7-A has two page table address registers, TTBR0 and 1.
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* Only TTBR0 is used in this implementation but both are initialized.
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*/
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ldr r1, .LCppgtable /* r1=phys. page table */
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orr r1, r1, #(TTBR0_RGN_WBWA | TTBR0_IRGN0) /* Select cache properties */
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mcr CP15_TTBR0(r1)
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mcr CP15_TTBR1(r1)
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/* Set the TTB control register (TTBCR) to indicate that we are using
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* TTBR0. r0 still holds the value of zero.
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*
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* N : 0=Selects TTBR0 and 16KB page table size indexed by VA[31:20]
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* PD0 : 0=Perform translation table walks using TTBR0
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* PD1 : 0=Perform translation table walks using TTBR1 (but it is disabled)
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* EAE : 0=Use 32-bit translation system
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*/
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mcr CP15_TTBCR(r0)
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/* Enable the MMU and caches
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* lr = Resume at .Lcpu_vstart with the MMU enabled
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*/
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ldr lr, .LCcpu_vstart /* Abs. virtual address */
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/* Configure the domain access register (see mmu.h). Only domain 0 is
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* supported and it uses the permissions in the TLB.
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*/
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mov r0, #DACR_CLIENT(0)
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mcr CP15_DACR(r0) /* Set domain access register */
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/* Configure the system control register (see sctrl.h) */
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mrc CP15_SCTLR(r0) /* Get control register */
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/* Clear bits to reset values. This is only necessary in situations like, for
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* example, we get here via a bootloader and the control register is in some
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* unknown state.
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*
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* SCTLR_M Bit 0: Enable the MMU
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* SCTLR_A Bit 1: Strict alignment disabled (reset value)
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* SCTLR_C Bit 2: DCache disabled (reset value)
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*
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* SCTLR_SW Bit 10: SWP/SWPB not enabled (reset value)
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* SCTLR_I Bit 12: ICache disabled (reset value)
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* SCTLR_V Bit 13: Assume low vectors (reset value)
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* SCTLR_RR Bit 14: The Cortex-A5 processor only supports a fixed random
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* replacement strategy.
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* SCTLR_HA Bit 17: Not supported by A5
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*
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* SCTLR_EE Bit 25: 0=Little endian (reset value).
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* SCTLR_TRE Bit 28: No memory region remapping (reset value)
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* SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value).
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* SCTLR_TE Bit 30: All exceptions handled in ARM state (reset value).
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*/
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bic r0, r0, #(SCTLR_A | SCTLR_C)
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bic r0, r0, #(SCTLR_SW | SCTLR_I | SCTLR_V | SCTLR_RR | SCTLR_HA)
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bic r0, r0, #(SCTLR_EE | SCTLR_TRE | SCTLR_AFE | SCTLR_TE)
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/* Set bits to enable the MMU
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*
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* SCTLR_M Bit 0: Enable the MMU
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* SCTLR_Z Bit 11: Program flow prediction control always enabled on A5
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*/
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orr r0, r0, #(SCTLR_M)
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#ifndef CONFIG_ARCH_CORTEXA5
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orr r0, r0, #(SCTLR_Z)
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#endif
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#ifndef CONFIG_ARCH_LOWVECTORS
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/* Position vectors to 0xffff0000 if so configured.
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*
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* SCTLR_V Bit 13: High vectors
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*/
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orr r0, r0, #(SCTLR_V)
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#endif
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#if defined(CPU_CACHE_ROUND_ROBIN) && !defined(CONFIG_ARCH_CORTEXA5)
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/* Round Robin cache replacement
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*
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* SCTLR_RR Bit 14: The Cortex-A5 processor only supports a fixed random
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* replacement strategy.
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*/
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orr r0, r0, #(SCTLR_RR)
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#endif
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#ifndef CPU_DCACHE_DISABLE
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/* Dcache enable
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*
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* SCTLR_C Bit 2: DCache enable
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*/
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orr r0, r0, #(SCTLR_C)
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#endif
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#ifndef CPU_ICACHE_DISABLE
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/* Icache enable
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*
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* SCTLR_I Bit 12: ICache enable
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*/
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orr r0, r0, #(SCTLR_I)
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#endif
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#ifdef CPU_ALIGNMENT_TRAP
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/* Alignment abort enable
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*
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* SCTLR_A Bit 1: Strict alignment enabled
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*/
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orr r0, r0, #(SCTLR_A)
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#endif
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#ifdef CONFIG_ENDIAN_BIG
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/* Big endian mode
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*
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* SCTLR_EE Bit 25: 1=Big endian.
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*/
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orr r0, r0, #(SCTLR_EE)
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#endif
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#ifdef CPU_AFE_ENABLE
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/* AP[0:2] Permissions model
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*
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* SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value).
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*
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* When AFE=1, the page table AP[0] is used as an access flag and AP[2:1]
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* control. When AFE=0, AP[2:0] control access permissions.
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*/
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orr r0, r0, #(SCTLR_AFE)
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#endif
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/* Then write the configured control register */
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mcr CP15_SCTLR(r0) /* Write control reg */
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.rept 12 /* Cortex A8 wants lots of NOPs here */
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nop
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.endr
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/* And "jump" to .Lcpu_vstart in the newly mapped virtual address space */
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mov pc, lr
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/****************************************************************************
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* PC_Relative Data
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****************************************************************************/
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/* The physical base address of the page table */
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.type .LCppgtable, %object
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.LCppgtable:
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.long PGTABLE_BASE_PADDR /* Physical start of page table */
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.size .LCppgtable, . -.LCppgtable
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/* The virtual start address of the second phase boot logic */
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.type .LCcpu_vstart, %object
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.LCcpu_vstart:
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.long .Lcpu_vstart
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.size .LCcpu_vstart, . -.LCcpu_vstart
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.size .Lcpu_start, .-.Lcpu_start
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/****************************************************************************
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* Name: .Lcpu_vstart
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*
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* Description:
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* Continue initialization after the MMU has been enabled.
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*
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* The following is executed after the MMU has been enabled. This uses
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* absolute addresses; this is not position independent.
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*
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* On input:
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* SP = Set to bottom of CPU IDLE stack (virtual)
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* R5 = CPU number
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*
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****************************************************************************/
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.align 8
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.globl arm_cpu_boot
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.type .Lcpu_vstart, %function
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.Lcpu_vstart:
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#ifdef CONFIG_STACK_COLORATION
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/* Write a known value to the IDLE thread stack to support stack
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* monitoring logic
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*/
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adr r3, .Lstkinit
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ldmia r3, {r0, r1, r2} /* R0 = start of IDLE stack; R1 = Size of stack; R2 = coloration */
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1: /* Top of the loop */
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sub r1, r1, #1 /* R1 = Number of words remaining */
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cmp r1, #0 /* Check (nwords == 0) */
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str r2, [r0], #4 /* Save stack color word, increment stack address */
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bne 1b /* Bottom of the loop */
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#endif
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/* Branch to continue C level CPU initialization */
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mov fp, #0 /* Clear framepointer */
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mov lr, #0 /* LR = return address (none) */
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mov r0, r5 /* Input parameter = CPU index */
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b arm_cpu_boot /* Branch to C level CPU initialization */
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.size .Lcpu_vstart, .-.Lcpu_vstart
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/***************************************************************************
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* Text-section constants
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***************************************************************************/
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/* Text-section constants: */
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#ifdef CONFIG_STACK_COLORATION
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.type .Lstkinit, %object
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.Lstkinit:
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.long ((CONFIG_IDLETHREAD_STACKSIZE + 7) & ~7) >> 2)
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.long STACK_COLOR /* Stack coloration word */
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.size .Lstkinit, . -.Lstkinit
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#endif
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/***************************************************************************
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* .noinit section data
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***************************************************************************/
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.section .noinit, "aw"
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#if CONFIG_SMP_NCPUS > 1
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.align 8
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.type .Lcpu1_idlestack, object
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.Lcpu1_idlestack:
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.space ((CONFIG_SMP_IDLETHREAD_STACKSIZE + 7) & ~7)
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.Lcpu1_stackbottom:
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.size .Lcpu1_idlestack, .Lcpu1_stackbottom-.Lcpu1_idlestack
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#if CONFIG_SMP_NCPUS > 2
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.align 8
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.type .Lcpu2_idlestack, object
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.Lcpu2_idlestack:
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.space ((CONFIG_SMP_IDLETHREAD_STACKSIZE + 7) & ~7)
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.Lcpu2_stackbottom:
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.size .Lcpu2_idlestack, .Lcpu2_stackbottom-.Lcpu2_idlestack
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#if CONFIG_SMP_NCPUS > 3
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.align 8
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.type .Lcpu3_idlestack, object
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.Lcpu3_idlestack:
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.space ((CONFIG_SMP_IDLETHREAD_STACKSIZE + 7) & ~7)
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.Lcpu3_stackbottom:
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.size .Lcpu3_idlestack, .Lcpu3_stackbottom-.Lcpu3_idlestack
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#if CONFIG_SMP_NCPUS > 4
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# error This logic needs to extended for CONFIG_SMP_NCPUS > 4
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#endif /* CONFIG_SMP_NCPUS > 4 */
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#endif /* CONFIG_SMP_NCPUS > 3 */
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||||
#endif /* CONFIG_SMP_NCPUS > 2 */
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#endif /* CONFIG_SMP_NCPUS > 1 */
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.end
|
||||
@ -49,6 +49,9 @@ ifeq ($(CONFIG_PAGING),y)
|
||||
CMN_ASRCS = arm_pghead.S
|
||||
else
|
||||
CMN_ASRCS = arm_head.S
|
||||
ifeq ($(CONFIG_SMP),y)
|
||||
CMN_ASRCS += arm_cpuhead.S
|
||||
endif
|
||||
endif
|
||||
|
||||
# Common assembly language files
|
||||
|
||||
Loading…
Reference in New Issue
Block a user