sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

arch/risc-v: Remove dupped irq code from c906

Browse Source 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2022-01-20 22:37:52 +08:00 committed by Xiang Xiao
parent bd57229f3c
commit d1edd887d5
5 changed files with 17 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
arch/risc-v/include/c906/irq.h
View File

@ -33,34 +33,7 @@
/* Map RISC-V exception code to NuttX IRQ */
/* IRQ 0-15 : (exception:interrupt=0) */
#define C906_IRQ_IAMISALIGNED (0) /* Instruction Address Misaligned */
#define C906_IRQ_IAFAULT (1) /* Instruction Address Fault */
#define C906_IRQ_IINSTRUCTION (2) /* Illegal Instruction */
#define C906_IRQ_BPOINT (3) /* Break Point */
#define C906_IRQ_LAMISALIGNED (4) /* Load Address Misaligned */
#define C906_IRQ_LAFAULT (5) /* Load Access Fault */
#define C906_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */
#define C906_IRQ_SAFAULT (7) /* Store/AMO Access Fault */
#define C906_IRQ_ECALLU (8) /* Environment Call from U-mode */
#define C906_IRQ_ECALLM (11) /* Environment Call from M-mode */
/* IRQ 16- : (async event:interrupt=1) */
#define C906_IRQ_ASYNC (16)
#define C906_IRQ_SSOFT (C906_IRQ_ASYNC + 1) /* Supervisor Software Int */
#define C906_IRQ_MSOFT (C906_IRQ_ASYNC + 3) /* Machine Software Int */
#define C906_IRQ_STIMER (C906_IRQ_ASYNC + 5) /* Supervisor Timer Int */
#define C906_IRQ_MTIMER (C906_IRQ_ASYNC + 7) /* Machine Timer Int */
#define C906_IRQ_SEXT (C906_IRQ_ASYNC + 9) /* Supervisor External Int */
#define C906_IRQ_MEXT (C906_IRQ_ASYNC + 11) /* Machine External Int */
#define C906_IRQ_HPMOV (C906_IRQ_ASYNC + 17) /* HPM Overflow Int */
/* Machine Global External Interrupt */
#define C906_IRQ_PERI_START (C906_IRQ_ASYNC + 18)
#define C906_IRQ_PERI_START (RISCV_IRQ_ASYNC + 18)
#ifdef CONFIG_C906_WITH_QEMU
#define C906_IRQ_UART0 (C906_IRQ_PERI_START + 32)

5
arch/risc-v/include/irq.h
View File

@ -65,10 +65,13 @@
/* IRQ 16- : (async event:interrupt=1) */
#define RISCV_IRQ_ASYNC (16)
#define RISCV_IRQ_SSOFT (RISCV_IRQ_ASYNC + 1) /* Supervisor Software Int */
#define RISCV_IRQ_MSOFT (RISCV_IRQ_ASYNC + 3) /* Machine Software Int */
#define RISCV_IRQ_STIMER (RISCV_IRQ_ASYNC + 5) /* Supervisor Timer Int */
#define RISCV_IRQ_MTIMER (RISCV_IRQ_ASYNC + 7) /* Machine Timer Int */
#define RISCV_IRQ_SEXT (RISCV_IRQ_ASYNC + 9) /* Supervisor External Int */
#define RISCV_IRQ_MEXT (RISCV_IRQ_ASYNC + 11) /* Machine External Int */
#define RISCV_IRQ_HPMOV (RISCV_IRQ_ASYNC + 17) /* HPM Overflow Int */
/* Configuration ************************************************************/

12
arch/risc-v/src/c906/c906_irq.c
View File

@ -97,10 +97,10 @@ void up_irqinitialize(void)
/* Attach the ecall interrupt handler */
irq_attach(C906_IRQ_ECALLM, riscv_swint, NULL);
irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
#ifdef CONFIG_BUILD_PROTECTED
irq_attach(C906_IRQ_ECALLU, riscv_swint, NULL);
irq_attach(RISCV_IRQ_ECALLU, riscv_swint, NULL);
#endif
#ifndef CONFIG_SUPPRESS_INTERRUPTS
@ -124,13 +124,13 @@ void up_disable_irq(int irq)
int extirq = 0;
uint64_t oldstat = 0;
if (irq == C906_IRQ_MSOFT)
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & clear machine software interrupt enable in mie */
asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
}
else if (irq == C906_IRQ_MTIMER)
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & clear machine timer interrupt enable in mie */
@ -167,13 +167,13 @@ void up_enable_irq(int irq)
int extirq;
uint64_t oldstat;
if (irq == C906_IRQ_MSOFT)
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & set machine software interrupt enable in mie */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
}
else if (irq == C906_IRQ_MTIMER)
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & set machine timer interrupt enable in mie */

8
arch/risc-v/src/c906/c906_irq_dispatch.c
View File

@ -58,14 +58,14 @@ void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs)
/* Check if fault happened */
if (vector < C906_IRQ_ECALLU)
if (vector < RISCV_IRQ_ECALLU)
{
up_fault((int)irq, regs);
}
/* Firstly, check if the irq is machine external interrupt */
if (C906_IRQ_MEXT == irq)
if (RISCV_IRQ_MEXT == irq)
{
uint32_t val = getreg32(C906_PLIC_MCLAIM);
@ -76,7 +76,7 @@ void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs)
/* NOTE: In case of ecall, we need to adjust mepc in the context */
if (C906_IRQ_ECALLM == irq || C906_IRQ_ECALLU == irq)
if (RISCV_IRQ_ECALLM == irq || RISCV_IRQ_ECALLU == irq)
{
*mepc += 4;
}
@ -99,7 +99,7 @@ void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs)
/* MEXT means no interrupt */
if (C906_IRQ_MEXT != irq)
if (RISCV_IRQ_MEXT != irq)
{
/* Deliver the IRQ */

4
arch/risc-v/src/c906/c906_timerisr.c
View File

@ -120,7 +120,7 @@ void up_timer_initialize(void)
{
/* Attach timer interrupt handler */
irq_attach(C906_IRQ_MTIMER, c906_timerisr, NULL);
irq_attach(RISCV_IRQ_MTIMER, c906_timerisr, NULL);
/* Reload CLINT mtimecmp */
@ -128,5 +128,5 @@ void up_timer_initialize(void)
/* And enable the timer interrupt */
up_enable_irq(C906_IRQ_MTIMER);
up_enable_irq(RISCV_IRQ_MTIMER);
}