SAM4E: Update SAM3/4 EEFC, MATRIX, and PMC register definition header files
This commit is contained in:
Gregory Nutt
parent
36ead78f07
commit
d20d82b90e
@ -56,7 +56,7 @@
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#define SAM_PID_RTT (3) /* Real Time Timer */
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#define SAM_PID_WDT (4) /* Watchdog Timer */
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#define SAM_PID_PMC (5) /* Power Management Controller */
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#define SAM_PID_EEFC (6) /* Enhanced Embedded Flash Controller */
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#define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller */
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#define SAM_PID_UART0 (7) /* Universal Asynchronous Receiver Transmitter 0 */
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#define SAM_PID_SMC (8) /* Static Memory Controller */
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#define SAM_PID_PIOA (9) /* Parallel I/O Controller A */
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@ -104,7 +104,7 @@
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#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* Real Time Timer */
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#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* Watchdog Timer */
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#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */
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#define SAM_IRQ_EEFC (SAM_IRQ_EXTINT+SAM_PID_EEFC) /* Enhanced Embedded Flash Controller */
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#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* Enhanced Embedded Flash Controller */
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#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* Universal Asynchronous Receiver Transmitter 0 */
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#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* Parallel I/O Controller A */
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#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* Parallel I/O Controller B */
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@ -126,6 +126,7 @@
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#define SAM_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */
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/* 0x400e0800-0x400e09ff: Reserved */
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#define SAM_EEFC_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller */
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# define SAM_EEFC0_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: (For compatibility) */
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/* 0x400e0c00-0x400e0dff: Reserved */
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#define SAM_PIO_BASE 0x400e0e00 /* 0x400e0e00-0x400e13ff: Parallel I/O Controllers */
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# define SAM_PION_BASE(n) (0x400e0e00 + ((n) << 9))
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@ -1,9 +1,9 @@
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/****************************************************************************************
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* arch/arm/src/sam34/chip/sam3u_eefc.h
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* Enhanced Embedded Flash Controller (EEFC) defintions for the SAM3U, SAM3X, SAM3A and
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* SAM4S
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* arch/arm/src/sam34/chip/sam_eefc.h
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* Enhanced Embedded Flash Controller (EEFC) definitions for the SAM3U, SAM3X, SAM3A,
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* SAM4E, and SAM4S
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*
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* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -35,8 +35,8 @@
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_EEFC_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_EEFC_H
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H
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/****************************************************************************************
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* Included Files
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@ -70,10 +70,12 @@
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#define SAM_EEFC0_FSR (SAM_EEFC0_BASE+SAM_EEFC_FSR_OFFSET)
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#define SAM_EEFC0_FRR (SAM_EEFC0_BASE+SAM_EEFC_FRR_OFFSET)
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#define SAM_EEFC1_FMR (SAM_EEFC1_BASE+SAM_EEFC_FMR_OFFSET)
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#define SAM_EEFC1_FCR (SAM_EEFC1_BASE+SAM_EEFC_FCR_OFFSET)
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#define SAM_EEFC1_FSR (SAM_EEFC1_BASE+SAM_EEFC_FSR_OFFSET)
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#define SAM_EEFC1_FRR (SAM_EEFC1_BASE+SAM_EEFC_FRR_OFFSET)
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#if !defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_EEFC1_FMR (SAM_EEFC1_BASE+SAM_EEFC_FMR_OFFSET)
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# define SAM_EEFC1_FCR (SAM_EEFC1_BASE+SAM_EEFC_FCR_OFFSET)
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# define SAM_EEFC1_FSR (SAM_EEFC1_BASE+SAM_EEFC_FSR_OFFSET)
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# define SAM_EEFC1_FRR (SAM_EEFC1_BASE+SAM_EEFC_FRR_OFFSET)
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#endif
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/* EEFC register bit definitions ********************************************************/
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/* EEFC Flash Mode Register */
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@ -83,13 +85,13 @@
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#define EEFC_FMR_FWS_MASK (15 << EEFC_FMR_FWS_SHIFT)
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# define EEFC_FMR_FWS(n) ((n) << EEFC_FMR_FWS_SHIFT)
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define EEFC_FMR_SCOD (1 << 16) /* Bit 16: Sequential Code Optimization Disable */
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#endif
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#define EEFC_FMR_FAM (1 << 24) /* Bit 24: Flash Access Mode */
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define EEFC_FMR_CLOE (1 << 26) /* Bit 26: Code Loops Optimization Enable */
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#endif
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@ -105,7 +107,7 @@
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# define EEFC_FCR_FCMD_EWPL (4 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page then lock */
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# define EEFC_FCR_FCMD_EA (5 << EEFC_FCR_FCMD_SHIFT) /* Erase all */
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define EEFC_FCR_FCMD_EPA (7 << EEFC_FCR_FCMD_SHIFT) /* Erase Pages */
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#endif
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@ -118,11 +120,12 @@
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# define EEFC_FCR_FCMD_STUI (14 << EEFC_FCR_FCMD_SHIFT) /* Start Read Unique Identifier */
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# define EEFC_FCR_FCMD_SPUI (15 << EEFC_FCR_FCMD_SHIFT) /* Stop Read Unique Identifier */
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
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defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define EEFC_FCR_FCMD_GCALB (16 << EEFC_FCR_FCMD_SHIFT) /* Get CALIB Bit */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define EEFC_FCR_FCMD_ES (17 << EEFC_FCR_FCMD_SHIFT) /* Erase Sector */
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# define EEFC_FCR_FCMD_WUS (18 << EEFC_FCR_FCMD_SHIFT) /* Write User Signature */
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# define EEFC_FCR_FCMD_EUS (19 << EEFC_FCR_FCMD_SHIFT) /* Erase User Signature */
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@ -132,6 +135,7 @@
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#define EEFC_FCR_FARG_SHIFT (8) /* Bits 8-23: Flash Command Argument */
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#define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT)
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# define EEFC_FCR_FARG(n) ((uint32_t)(n) << EEFC_FCR_FARG_SHIFT)
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#define EEFC_FCR_FKEY_SHIFT (24) /* Bits 24-31: Flash Writing Protection Key */
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#define EEFC_FCR_FKEY_MASK (0xff << EEFC_FCR_FKEY_SHIFT)
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# define EEFC_FCR_FKEY_PASSWD (0x5a << EEFC_FCR_FKEY_SHIFT)
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@ -142,10 +146,12 @@
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#define EEFC_FSR_FCMDE (1 << 1) /* Bit 1: Flash Command Error Status */
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#define EEFC_FSR_FLOCKE (1 << 2) /* Bit 2: Flash Lock Error Status */
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define EEFC_FSR_FLERR (1 << 3) /* Bit 3: Flash Error Status */
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#endif
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/* EEFC Flash Result Register -- 32-bit value */
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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@ -158,4 +164,4 @@
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_EEFC_H */
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H */
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@ -1,8 +1,8 @@
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/****************************************************************************************
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* arch/arm/src/sam34/chip/sam_34matrix.h
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* Bux matrix definitions for the SAM3U, SAM3X, SAM3A, and SAM4S
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* arch/arm/src/sam34/chip/sam_matrix.h
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* Bux matrix definitions for the SAM3U, SAM3X, SAM3A, SAM4E, and SAM4S
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*
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* Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -34,8 +34,8 @@
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MATRIX_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MATRIX_H
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H
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/****************************************************************************************
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* Included Files
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@ -58,8 +58,14 @@
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#define SAM_MATRIX_MCFG2_OFFSET 0x0008 /* Master Configuration Register 2 */
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#define SAM_MATRIX_MCFG3_OFFSET 0x000c /* Master Configuration Register 3 */
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#define SAM_MATRIX_MCFG4_OFFSET 0x0010 /* Master Configuration Register 4 */
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
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defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_MCFG5_OFFSET 0x0014 /* Master Configuration Register 5 */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_MCFG6_OFFSET 0x0018 /* Master Configuration Register 6 */
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#endif
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/* 0x0018-0x003c: Reserved */
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#define SAM_MATRIX_SCFG_OFFSET(n) (0x0040+((n)<<2))
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@ -69,8 +75,11 @@
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#define SAM_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */
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#define SAM_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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# define SAM_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */
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# define SAM_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */
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# define SAM_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */
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@ -86,8 +95,11 @@
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#define SAM_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */
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#define SAM_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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# define SAM_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */
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# define SAM_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */
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# define SAM_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */
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@ -97,16 +109,16 @@
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
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defined(CONFIG_ARCH_CHIP_SAM4S)
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defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_CCFG_SYSIO_OFFSET 0x0114 /* System I/O Configuration Register */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_CCFG_SMCNFCS_OFFSET 0x011c /* SMC Chip Select NAND Flash Assignment Register */
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#endif
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@ -122,9 +134,13 @@
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#define SAM_MATRIX_MCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG2_OFFSET)
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#define SAM_MATRIX_MCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG3_OFFSET)
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#define SAM_MATRIX_MCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG4_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
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defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_MCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG5_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_MCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG6_OFFSET)
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#endif
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#define SAM_MATRIX_SCFG(n) (SAM_MATRIX_BASE+SAM_MATRIX_SCFG_OFFSET(n))
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#define SAM_MATRIX_SCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG0_OFFSET)
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@ -133,8 +149,11 @@
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#define SAM_MATRIX_SCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG3_OFFSET)
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#define SAM_MATRIX_SCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG4_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_SCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG5_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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# define SAM_MATRIX_SCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG6_OFFSET)
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# define SAM_MATRIX_SCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG7_OFFSET)
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# define SAM_MATRIX_SCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG8_OFFSET)
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@ -150,8 +169,11 @@
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#define SAM_MATRIX_PRAS3 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS3_OFFSET)
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#define SAM_MATRIX_PRAS4 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS4_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_PRAS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS5_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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# define SAM_MATRIX_PRAS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS6_OFFSET)
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# define SAM_MATRIX_PRAS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS7_OFFSET)
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# define SAM_MATRIX_PRAS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS8_OFFSET)
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@ -161,16 +183,16 @@
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_MRCR (SAM_MATRIX_BASE+SAM_MATRIX_MRCR_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
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defined(CONFIG_ARCH_CHIP_SAM4S)
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defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_CCFG_SYSIO (SAM_MATRIX_BASE+SAM_MATRIX_CCFG_SYSIO_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_CCFG_SMCNFCS (SAM_MATRIX_BASE+SAM_MATRIX_CCFG_SMCNFCS_OFFSET)
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#endif
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#define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT)
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# define MATRIX_MCFG_ULBT_INF (0 << MATRIX_MCFG_ULBT_SHIFT) /* Infinite Length Burst */
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# define MATRIX_MCFG_ULBT_SINGLE (1 << MATRIX_MCFG_ULBT_SHIFT) /* Single Access */
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# define MATRIX_MCFG_ULBT_4BEAT (2 << MATRIX_MCFG_ULBT_SHIFT) /* Four Beat Burst */
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# define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* Eight Beat Burst */
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# define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* Sixteen Beat Burst */
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# define MATRIX_MCFG_ULBT_4BEAT (2 << MATRIX_MCFG_ULBT_SHIFT) /* 4-beat Burst */
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# define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* 8-beat Burst */
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# define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* 16-beat Burst */
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# if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define MATRIX_MCFG_ULBT_32BEAT (5 << MATRIX_MCFG_ULBT_SHIFT) /* 32-beat Burst */
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# define MATRIX_MCFG_ULBT_64BEAT (6 << MATRIX_MCFG_ULBT_SHIFT) /* 64-beat Burst */
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||||
# define MATRIX_MCFG_ULBT_128BEAT (7 << MATRIX_MCFG_ULBT_SHIFT) /* 128-beat Burst */
|
||||
# endif
|
||||
|
||||
/* Bus Matrix Slave Configuration Registers */
|
||||
|
||||
#define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */
|
||||
#define MATRIX_SCFG_SLOTCYCLE_MASK (0xff << MATRIX_SCFG_SLOTCYCLE_SHIFT)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-8: Maximum Number of Allowed Cycles for a Burst */
|
||||
# define MATRIX_SCFG_SLOTCYCLE_MASK (0x1ff << MATRIX_SCFG_SLOTCYCLE_SHIFT)
|
||||
# define MATRIX_SCFG_SLOTCYCLE(n) ((uint32_t)(n) << MATRIX_SCFG_SLOTCYCLE_SHIFT)
|
||||
#else
|
||||
# define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */
|
||||
# define MATRIX_SCFG_SLOTCYCLE_MASK (0xff << MATRIX_SCFG_SLOTCYCLE_SHIFT)
|
||||
# define MATRIX_SCFG_SLOTCYCLE(n) ((uint32_t)(n) << MATRIX_SCFG_SLOTCYCLE_SHIFT)
|
||||
#endif
|
||||
|
||||
#define MATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */
|
||||
#define MATRIX_SCFG_DEFMSTRTYPE_MASK (3 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
|
||||
# define MATRIX_SCFG_DEFMSTRTYPE_NONE (0 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
|
||||
# define MATRIX_SCFG_DEFMSTRTYPE_LAST (1 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
|
||||
# define MATRIX_SCFG_DEFMSTRTYPE_FIXED (2 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
|
||||
|
||||
#define MATRIX_SCFG_FIXEDDEFMSTR_SHIFT (18) /* Bits 18-20: Fixed Default Master */
|
||||
#define MATRIX_SCFG_FIXEDDEFMSTR_MASK (7 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
|
||||
# define MATRIX_SCFG0_FIXEDDEFMSTR(n) ((uint32_t)(n) << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
|
||||
# define MATRIX_SCFG0_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
|
||||
# define MATRIX_SCFG1_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
|
||||
# define MATRIX_SCFG2_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
|
||||
@ -211,10 +248,13 @@
|
||||
# define MATRIX_SCFG8_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
|
||||
# define MATRIX_SCFG9_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
|
||||
# define MATRIX_SCFG9_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
|
||||
#define MATRIX_SCFG_ARBT_SHIFT (24) /* Bits 24-25: Arbitration Type */
|
||||
#define MATRIX_SCFG_ARBT_MASK (3 << MATRIX_SCFG_ARBT_SHIFT)
|
||||
# define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration */
|
||||
# define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration */
|
||||
|
||||
#if !defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define MATRIX_SCFG_ARBT_SHIFT (24) /* Bits 24-25: Arbitration Type */
|
||||
# define MATRIX_SCFG_ARBT_MASK (3 << MATRIX_SCFG_ARBT_SHIFT)
|
||||
# define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration */
|
||||
# define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration */
|
||||
#endif
|
||||
|
||||
/* Bus Matrix Priority Registers For Slaves */
|
||||
|
||||
@ -222,22 +262,37 @@
|
||||
#define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x))
|
||||
# define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */
|
||||
# define MATRIX_PRAS_M0PR_MASK (3 << MATRIX_PRAS_M0PR_SHIFT)
|
||||
# define MATRIX_PRAS_M0PR(n) ((uint32_t)(n) << MATRIX_PRAS_M0PR_SHIFT)
|
||||
# define MATRIX_PRAS_M1PR_SHIFT (4) /* Bits 4-5: Master 1 Priority */
|
||||
# define MATRIX_PRAS_M1PR_MASK (3 << MATRIX_PRAS_M1PR_SHIFT)
|
||||
# define MATRIX_PRAS_M1PR(n) ((uint32_t)(n) << MATRIX_PRAS_M1PR_SHIFT)
|
||||
# define MATRIX_PRAS_M2PR_SHIFT (8) /* Bits 8-9: Master 2 Priority */
|
||||
# define MATRIX_PRAS_M2PR_MASK (3 << MATRIX_PRAS_M2PR_SHIFT)
|
||||
# define MATRIX_PRAS_M2PR(n) ((uint32_t)(n) << MATRIX_PRAS_M2PR_SHIFT)
|
||||
# define MATRIX_PRAS_M3PR_SHIFT (12) /* Bits 12-13: Master 3 Priority */
|
||||
# define MATRIX_PRAS_M3PR_MASK (3 << MATRIX_PRAS_M3PR_SHIFT)
|
||||
# define MATRIX_PRAS_M3PR(n) ((uint32_t)(n) << MATRIX_PRAS_M3PR_SHIFT)
|
||||
# define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17: Master 4 Priority */
|
||||
# define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# define MATRIX_PRAS_M4PR(n) ((uint32_t)(n) << MATRIX_PRAS_M4PR_SHIFT)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define MATRIX_PRAS_M5PR_SHIFT (20) /* Bits 20-21: Master 5 Priority */
|
||||
# define MATRIX_PRAS_M5PR_MASK (3 << MATRIX_PRAS_M5PR_SHIFT)
|
||||
# define MATRIX_PRAS_M5PR(n) ((uint32_t)(n) << MATRIX_PRAS_M5PR_SHIFT)
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define MATRIX_PRAS_M6PR_SHIFT (24) /* Bits 24-25: Master 6 Priority */
|
||||
# define MATRIX_PRAS_M6PR_MASK (3 << MATRIX_PRAS_M6PR_SHIFT)
|
||||
# define MATRIX_PRAS_M6PR(n) ((uint32_t)(n) << MATRIX_PRAS_M6PR_SHIFT)
|
||||
# define MATRIX_PRAS_M7PR_SHIFT (28) /* Bits 28-29: Master 7 Priority */
|
||||
# define MATRIX_PRAS_M7PR_MASK (3 << MATRIX_PRAS_M7PR_SHIFT)
|
||||
# define MATRIX_PRAS_M7PR(n) ((uint32_t)(n) << MATRIX_PRAS_M7PR_SHIFT)
|
||||
#endif
|
||||
|
||||
/* System I/O Configuration Register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define MATRIX_CCFG_SYSIO_SYSIO4 (1 << 4) /* Bit 4: PB4 or TDI Assignment */
|
||||
# define MATRIX_CCFG_SYSIO_SYSIO5 (1 << 5) /* Bit 5: PB5 or TDO/TRACESWO Assignment */
|
||||
# define MATRIX_CCFG_SYSIO_SYSIO6 (1 << 6) /* Bit 6: PB6 or TMS/SWDIO Assignment */
|
||||
@ -253,7 +308,7 @@
|
||||
|
||||
/* SMC Chip Select NAND Flash Assignment Register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define MATRIX_CCFG_SMCNFCS_SMC_NFCS0 (1 << 0) /* Bit 0: SMC NAND Flash Chip Select 0 Assignment */
|
||||
# define MATRIX_CCFG_SMCNFCS_SMC_NFCS1 (1 << 1) /* Bit 1: SMC NAND Flash Chip Select 2 Assignment */
|
||||
# define MATRIX_CCFG_SMCNFCS_SMC_NFCS2 (1 << 2) /* Bit 2: SMC NAND Flash Chip Select 2 Assignment */
|
||||
@ -262,16 +317,30 @@
|
||||
|
||||
/* Master Remap Control Register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define MATRIX_MRCR_RCB(x) (1 << (x))
|
||||
# define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */
|
||||
# define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */
|
||||
# define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */
|
||||
# define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */
|
||||
# define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define MATRIX_MRCR_RCB5 (1 << 5) /* Bit 5: Remap Command Bit for AHB Master 5 */
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define MATRIX_MRCR_RCB6 (1 << 6) /* Bit 6: Remap Command Bit for AHB Master 6 */
|
||||
# define MATRIX_MRCR_RCB7 (1 << 7) /* Bit 7: Remap Command Bit for AHB Master 7 */
|
||||
# define MATRIX_MRCR_RCB8 (1 << 8) /* Bit 8: Remap Command Bit for AHB Master 8 */
|
||||
# define MATRIX_MRCR_RCB9 (1 << 9) /* Bit 9: Remap Command Bit for AHB Master 9 */
|
||||
# define MATRIX_MRCR_RCB10 (1 << 10) /* Bit 10: Remap Command Bit for AHB Master 10 */
|
||||
# define MATRIX_MRCR_RCB11 (1 << 11) /* Bit 11: Remap Command Bit for AHB Master 11 */
|
||||
# define MATRIX_MRCR_RCB12 (1 << 12) /* Bit 12: Remap Command Bit for AHB Master 12 */
|
||||
# define MATRIX_MRCR_RCB13 (1 << 13) /* Bit 13: Remap Command Bit for AHB Master 13 */
|
||||
# define MATRIX_MRCR_RCB14 (1 << 14) /* Bit 14: Remap Command Bit for AHB Master 14 */
|
||||
# define MATRIX_MRCR_RCB15 (1 << 15) /* Bit 15: Remap Command Bit for AHB Master 15 */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Write Protect Mode Register */
|
||||
@ -299,4 +368,4 @@
|
||||
* Public Functions
|
||||
****************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MATRIX_H */
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H */
|
||||
@ -1,8 +1,8 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/sam34/chip/sam_pmc.h
|
||||
* Power Management Controller (PMC) for the SAM3U, SAM3X, SAM3A, and SAM4S
|
||||
* Power Management Controller (PMC) for the SAM3U, SAM3X, SAM3A, SAM4E, and SAM4S
|
||||
*
|
||||
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -56,7 +56,8 @@
|
||||
#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */
|
||||
#define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */
|
||||
/* 0x000c: Reserved */
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_PMC_PCER0_OFFSET 0x0010 /* Peripheral Clock Enable Register 0 */
|
||||
# define SAM_PMC_PCDR0_OFFSET 0x0014 /* Peripheral Clock Disable Register 0 */
|
||||
# define SAM_PMC_PCSR0_OFFSET 0x0018 /* Peripheral Clock Status Register 0 */
|
||||
@ -66,7 +67,8 @@
|
||||
# define SAM_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# define SAM_PMC_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */
|
||||
#endif
|
||||
/* 0x001c: Reserved (SAM4S)*/
|
||||
@ -80,16 +82,17 @@
|
||||
/* 0x002c: Reserved (SAM3U)*/
|
||||
#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
/* 0x0034 Reserved */
|
||||
# define SAM_PMC_USB_OFFSET 0x0038 /* USB Clock Register PMC_USB */
|
||||
/* 0x003c Reserved */
|
||||
#endif
|
||||
/* 0x0034-0x003c Reserved (SAM3U) */
|
||||
#define SAM_PMC_PCK_OFFSET(n) (0x0040 + ((n) << 2))
|
||||
#define SAM_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */
|
||||
#define SAM_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */
|
||||
#define SAM_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */
|
||||
# define SAM_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */
|
||||
# define SAM_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */
|
||||
# define SAM_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */
|
||||
/* 0x004c-0x005c: Reserved */
|
||||
#define SAM_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */
|
||||
#define SAM_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */
|
||||
@ -102,7 +105,8 @@
|
||||
#define SAM_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
|
||||
#define SAM_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
/* 0x00ec-0x00fc Reserved */
|
||||
# define SAM_PMC_PCER1_OFFSET 0x0100 /* Peripheral Clock Enable Register 1 */
|
||||
# define SAM_PMC_PCDR1_OFFSET 0x0104 /* Peripheral Clock Disable Register 1 */
|
||||
@ -113,18 +117,22 @@
|
||||
# define SAM_PMC_PCR_OFFSET 0x010c /* Peripheral Control Register */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_PMC_OCR_OFFSET 0x0110 /* Oscillator Calibration Register */
|
||||
/* 0x003c Reserved */
|
||||
#endif
|
||||
|
||||
/* PMC register adresses ********************************************************************/
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_PMC_PMMR_OFFSET 0x0130 /* PLL Maximum Multiplier Value Register */
|
||||
#endif
|
||||
|
||||
/* PMC register addresses *******************************************************************/
|
||||
|
||||
#define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET)
|
||||
#define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET)
|
||||
#define SAM_PMC_SCSR (SAM_PMC_BASE+SAM_PMC_SCSR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_PMC_PCER0 (SAM_PMC_BASE+SAM_PMC_PCER0_OFFSET)
|
||||
# define SAM_PMC_PCDR0 (SAM_PMC_BASE+SAM_PMC_PCDR0_OFFSET)
|
||||
# define SAM_PMC_PCSR0 (SAM_PMC_BASE+SAM_PMC_PCSR0_OFFSET)
|
||||
@ -134,7 +142,8 @@
|
||||
# define SAM_PMC_PCSR (SAM_PMC_BASE+SAM_PMC_PCSR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# define SAM_PMC_CKGR_UCKR (SAM_PMC_BASE+SAM_PMC_CKGR_UCKR_OFFSET)
|
||||
#endif
|
||||
|
||||
@ -146,7 +155,8 @@
|
||||
# define SAM_PMC_CKGR_PLLBR (SAM_PMC_BASE+SAM_PMC_CKGR_PLLBR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_PMC_USB (SAM_PMC_BASE+SAM_PMC_USB_OFFSET)
|
||||
#endif
|
||||
|
||||
@ -165,7 +175,8 @@
|
||||
#define SAM_PMC_WPMR (SAM_PMC_BASE+SAM_PMC_WPMR_OFFSET)
|
||||
#define SAM_PMC_WPSR (SAM_PMC_BASE+SAM_PMC_WPSR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_PMC_PCER1 (SAM_PMC_BASE+SAM_PMC_PCER1_OFFSET)
|
||||
# define SAM_PMC_PCDR1 (SAM_PMC_BASE+SAM_PMC_PCDR1_OFFSET)
|
||||
# define SAM_PMC_PCSR1 (SAM_PMC_BASE+SAM_PMC_PCSR1_OFFSET)
|
||||
@ -175,10 +186,14 @@
|
||||
# define SAM_PMC_PCR (SAM_PMC_BASE+SAM_PMC_PCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_PMC_OCR (SAM_PMC_BASE+SAM_PMC_OCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_PMC_PMMR (SAM_PMC_BASE+SAM_PMC_PMMR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* PMC register bit definitions *************************************************************/
|
||||
|
||||
/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System
|
||||
@ -189,7 +204,7 @@
|
||||
# define PMC_UOTGCLK (1 << 5) /* Bit 5: Enable USB OTG Clock (48 MHz, USB_48M) for UTMI */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define PMC_UDP (1 << 7) /* Bit 7: USB Device Port Clock Enable */
|
||||
#endif
|
||||
|
||||
@ -247,7 +262,8 @@
|
||||
#define PMC_CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */
|
||||
#define PMC_CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define PMC_CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */
|
||||
#endif
|
||||
|
||||
@ -259,6 +275,7 @@
|
||||
# define PMC_CKGR_MOR_MOSCRCF_12MHz (2 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 12MHz */
|
||||
#define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */
|
||||
#define PMC_CKGR_MOR_MOSCXTST_MASK (0x1ff << PMC_CKGR_MOR_MOSCXTST_SHIFT)
|
||||
# define PMC_CKGR_MOR_MOSCXTST(n) ((uint32_t)(n) << PMC_CKGR_MOR_MOSCXTST_SHIFT)
|
||||
#define PMC_CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */
|
||||
#define PMC_CKGR_MOR_KEY_MASK (0xff << PMC_CKGR_MOR_KEY_SHIFT)
|
||||
# define PMC_CKGR_MOR_KEY (0x37 << PMC_CKGR_MOR_KEY_SHIFT)
|
||||
@ -269,9 +286,10 @@
|
||||
|
||||
#define PMC_CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */
|
||||
#define PMC_CKGR_MCFR_MAINF_MASK (0xffff << PMC_CKGR_MCFR_MAINF_SHIFT)
|
||||
# define PMC_CKGR_MCFR_MAINF(n) ((uint32_t)(n) << PMC_CKGR_MCFR_MAINF_SHIFT)
|
||||
#define PMC_CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define PMC_CKGR_MCFR_RCMEAS (1 << 20) /* Bit 20: RC Oscillator Frequency Measure (write-only) */
|
||||
#endif
|
||||
|
||||
@ -313,10 +331,13 @@
|
||||
|
||||
/* USB Clock Register PMC_USB */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define PMC_USB_USBS (1 << 0) /* Bit 0: USB Input Clock Selection */
|
||||
# define PMC_USB_USBS_PLLA (0)
|
||||
# define PMC_USB_USBS_PLLB PMC_USB_USBS
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define PMC_USB_USBS (1 << 0) /* Bit 0: USB Input Clock Selection */
|
||||
# define PMC_USB_USBS_PLLA (0)
|
||||
# define PMC_USB_USBS_PLLB PMC_USB_USBS
|
||||
# endif
|
||||
# define PMC_USB_USBDIV_SHIFT (8) /* Bits 8-11: Divider for USB Clock */
|
||||
# define PMC_USB_USBDIV_MASK (15 << PMC_USB_USBDIV_SHIFT)
|
||||
#endif
|
||||
@ -331,7 +352,8 @@
|
||||
|
||||
# if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define PMC_MCKR_CSS_PLLB (3 << PMC_MCKR_CSS_SHIFT) /* PLLB Clock */
|
||||
# elif defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# elif defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */
|
||||
# endif
|
||||
|
||||
@ -346,13 +368,15 @@
|
||||
# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */
|
||||
# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define PMC_MCKR_PLLADIV2 (1 << 12) /* Bit 12: PLLA Divider */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define PMC_MCKR_PLLBDIV2 (1 << 13) /* Bit 13: PLLB Divider */
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
# define PMC_MCKR_UPLLDIV2 (1 << 13) /* Bit 13: UPLL Divider */
|
||||
#endif
|
||||
|
||||
@ -366,7 +390,8 @@
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define PMC_PCK_CSS_PLLB (3 << PMC_PCK_CSS_MASK) /* PLLB Clock */
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */
|
||||
#endif
|
||||
|
||||
@ -395,15 +420,16 @@
|
||||
|
||||
#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
# define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */
|
||||
#endif
|
||||
|
||||
#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */
|
||||
#define PMC_INT_PCKRDY(n) (1 << ((n)+8)
|
||||
#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */
|
||||
#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */
|
||||
#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */
|
||||
# define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */
|
||||
# define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */
|
||||
# define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */
|
||||
#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */
|
||||
#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */
|
||||
#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */
|
||||
@ -415,39 +441,58 @@
|
||||
*/
|
||||
|
||||
#define PMC_FSTI(n) (1 << (n))
|
||||
#define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */
|
||||
#define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */
|
||||
#define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */
|
||||
#define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */
|
||||
#define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */
|
||||
#define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */
|
||||
#define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */
|
||||
#define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */
|
||||
#define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */
|
||||
#define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */
|
||||
#define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */
|
||||
#define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */
|
||||
#define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */
|
||||
#define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */
|
||||
#define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */
|
||||
#define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */
|
||||
# define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */
|
||||
# define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */
|
||||
# define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */
|
||||
# define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */
|
||||
# define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */
|
||||
# define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */
|
||||
# define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */
|
||||
# define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */
|
||||
# define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */
|
||||
# define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */
|
||||
# define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */
|
||||
# define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */
|
||||
# define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */
|
||||
# define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */
|
||||
# define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */
|
||||
# define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */
|
||||
#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */
|
||||
#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */
|
||||
#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define PMC_FSMR_FLPM_SHIFT (21) /* Bit 21-22: Low Power Mode (MR only) */
|
||||
# define PMC_FSMR_FLPM_MASK (3 << PMC_FSMR_FLPM_SHIFT)
|
||||
# define PMC_FSMR_FLPM_PWRDOWN (0 << PMC_FSMR_FLPM_SHIFT) /* Flash Standby Mode */
|
||||
# define PMC_FSMR_FLPM_STANDBY (1 << PMC_FSMR_FLPM_SHIFT) /* Flash deep power down mode */
|
||||
# define PMC_FSMR_FLPM_IDLE (2 << PMC_FSMR_FLPM_SHIFT) /* Idle mode */
|
||||
# define PMC_FSMR_FLPM_PWRDOWN (0 << PMC_FSMR_FLPM_SHIFT) /* Flash Standby Mode */
|
||||
# define PMC_FSMR_FLPM_STANDBY (1 << PMC_FSMR_FLPM_SHIFT) /* Flash deep power down mode */
|
||||
# define PMC_FSMR_FLPM_IDLE (2 << PMC_FSMR_FLPM_SHIFT) /* Idle mode */
|
||||
#endif
|
||||
|
||||
/* Fast Startup Polarity Register */
|
||||
|
||||
#define PMC_FSTP(n) (1 << (n)) /* Fast Startup Input Polarityn, n=0..15 */
|
||||
#define PMC_FSTP(n) (1 << (n)) /* Fast Startup Input Polarity n, n=0..15 */
|
||||
# define PMC_FSTP0 (1 << 0) /* Bit 0: Fast Startup Input Polarity 0 */
|
||||
# define PMC_FSTP1 (1 << 1) /* Bit 1: Fast Startup Input Polarity 1 */
|
||||
# define PMC_FSTP2 (1 << 2) /* Bit 2: Fast Startup Input Polarity 2 */
|
||||
# define PMC_FSTP3 (1 << 3) /* Bit 3: Fast Startup Input Polarity 3 */
|
||||
# define PMC_FSTP4 (1 << 4) /* Bit 4: Fast Startup Input Polarity 4 */
|
||||
# define PMC_FSTP5 (1 << 5) /* Bit 5: Fast Startup Input Polarity 5 */
|
||||
# define PMC_FSTP6 (1 << 6) /* Bit 6: Fast Startup Input Polarity 6 */
|
||||
# define PMC_FSTP7 (1 << 7) /* Bit 7: Fast Startup Input Polarity 7 */
|
||||
# define PMC_FSTP8 (1 << 8) /* Bit 8: Fast Startup Input Polarity 8 */
|
||||
# define PMC_FSTP9 (1 << 9) /* Bit 9: Fast Startup Input Polarity 9 */
|
||||
# define PMC_FSTP10 (1 << 10) /* Bit 10: Fast Startup Input Polarity 10 */
|
||||
# define PMC_FSTP11 (1 << 11) /* Bit 11: Fast Startup Input Polarity 11 */
|
||||
# define PMC_FSTP12 (1 << 12) /* Bit 12: Fast Startup Input Polarity 12 */
|
||||
# define PMC_FSTP13 (1 << 13) /* Bit 13: Fast Startup Input Polarity 13 */
|
||||
# define PMC_FSTP14 (1 << 14) /* Bit 14: Fast Startup Input Polarity 14 */
|
||||
# define PMC_FSTP15 (1 << 15) /* Bit 15: Fast Startup Input Polarity 15 */
|
||||
|
||||
/* PMC Fault Output Clear Register */
|
||||
|
||||
@ -470,12 +515,14 @@
|
||||
/* Peripheral Clock Disable Register 1 */
|
||||
/* Peripheral Clock Status Register 1 */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define PMC_PIDH(n) (1 << ((n) - 32))
|
||||
# define PMC_PID32 (1 << 0) /* Bit 0: PID32 */
|
||||
# define PMC_PID33 (1 << 1) /* Bit 1: PID33 */
|
||||
# define PMC_PID34 (1 << 2) /* Bit 2: PID34 */
|
||||
# if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3X)
|
||||
# if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define PMC_PID35 (1 << 3) /* Bit 3: PID35 */
|
||||
# define PMC_PID36 (1 << 4) /* Bit 4: PID36 */
|
||||
# define PMC_PID37 (1 << 5) /* Bit 5: PID37 */
|
||||
@ -487,6 +534,11 @@
|
||||
# define PMC_PID43 (1 << 11) /* Bit 11: PID43 */
|
||||
# define PMC_PID44 (1 << 12) /* Bit 12: PID44 */
|
||||
# endif
|
||||
# if defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define PMC_PID45 (1 << 13) /* Bit 13: PID45 */
|
||||
# define PMC_PID46 (1 << 14) /* Bit 14: PID46 */
|
||||
# define PMC_PID47 (1 << 15) /* Bit 15: PID47 */
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Peripheral Control Register */
|
||||
@ -505,18 +557,27 @@
|
||||
|
||||
/* Oscillator Calibration Register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define PMC_OCR_CAL4_SHIFT (0) /* Bits 0-6: 4MHzRC Oscillator Calibration */
|
||||
# define PMC_OCR_CAL4_MASK (0x7f << PMC_OCR_CAL4_SHIFT)
|
||||
# define PMC_OCR_CAL4(n) ((uint32_t)(n) << PMC_OCR_CAL4_SHIFT)
|
||||
# define PMC_OCR_SEL4 (1 << 7) /* Bit 7: Select 4MHz RC Oscillator Calibration */
|
||||
# define PMC_OCR_CAL8_SHIFT (8) /* Bits 8-14: 8MHzRC Oscillator Calibration */
|
||||
# define PMC_OCR_CAL8_MASK (0x7f << PMC_OCR_CAL8_SHIFT)
|
||||
# define PMC_OCR_CAL8(n) ((uint32_t)(n) << PMC_OCR_CAL8_SHIFT)
|
||||
# define PMC_OCR_SEL8 (1 << 15) /* Bit 15: Select 8MHz RC Oscillator Calibration */
|
||||
# define PMC_OCR_CAL12_SHIFT (16) /* Bits 16-22: 12MHzRC Oscillator Calibration */
|
||||
# define PMC_OCR_CAL12_MASK (0x7f << PMC_OCR_CAL12_SHIFT)
|
||||
# define PMC_OCR_CAL12(n) ((uint32_t)(n) << PMC_OCR_CAL12_SHIFT)
|
||||
# define PMC_OCR_SEL12 (1 << 23) /* Bit 23: Select 12MHz RC Oscillator Calibration */
|
||||
#endif
|
||||
|
||||
/* PLL Maximum Multiplier Value Register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define PMC_PMMR_MASK (0x7ff) /* Bits 0-10: PLLA Maximum Allowed Multiplier */
|
||||
#endif
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
@ -61,7 +61,7 @@
|
||||
#define sam_rtt_enableclk() sam_enableperiph0(SAM_PID_RTT)
|
||||
#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT)
|
||||
#define sam_pmc_enableclk() sam_enableperiph0(SAM_PID_PMC)
|
||||
#define sam_eefc_enableclk() sam_enableperiph0(SAM_PID_EEFC)
|
||||
#define sam_eefc0_enableclk() sam_enableperiph0(SAM_PID_EEFC0)
|
||||
#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
|
||||
#define sam_smc_enableclk() sam_enableperiph0(SAM_PID_SMC)
|
||||
#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
|
||||
@ -105,7 +105,7 @@
|
||||
#define sam_rtt_disableclk() sam_disableperiph0(SAM_PID_RTT)
|
||||
#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT)
|
||||
#define sam_pmc_disableclk() sam_disableperiph0(SAM_PID_PMC)
|
||||
#define sam_eefc_disableclk() sam_disableperiph0(SAM_PID_EEFC)
|
||||
#define sam_eefc0_disableclk() sam_disableperiph0(SAM_PID_EEFC0)
|
||||
#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
|
||||
#define sam_smc_disableclk() sam_disableperiph0(SAM_PID_SMC)
|
||||
#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/chip/sam_clockconfig.c
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2010, 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -50,10 +50,10 @@
|
||||
|
||||
#include "sam_clockconfig.h"
|
||||
#include "chip/sam_pmc.h"
|
||||
#include "chip/sam3u_eefc.h"
|
||||
#include "chip/sam_eefc.h"
|
||||
#include "chip/sam3u_wdt.h"
|
||||
#include "chip/sam3u_supc.h"
|
||||
#include "chip/sam3u_matrix.h"
|
||||
#include "chip/sam_matrix.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -73,7 +73,7 @@
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM3X)
|
||||
# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \
|
||||
BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV)
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \
|
||||
BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV)
|
||||
#endif
|
||||
@ -106,7 +106,9 @@
|
||||
static inline void sam_efcsetup(void)
|
||||
{
|
||||
putreg32((BOARD_FWS << EEFC_FMR_FWS_SHIFT), SAM_EEFC0_FMR);
|
||||
#if !defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
putreg32((BOARD_FWS << EEFC_FMR_FWS_SHIFT), SAM_EEFC1_FMR);
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -219,6 +221,16 @@ static inline void sam_pmcsetup(void)
|
||||
putreg32(regval, SAM_PMC_MCKR);
|
||||
sam_pmcwait(PMC_INT_MCKRDY);
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
/* Setup the maximum value for the PLLAR multiplier. The PMMR register
|
||||
* "defines the maximum value of multiplication factor that can be sent to
|
||||
* PLLA. Any value of the MULA bitfield ... above PLLA_MMAX is saturated
|
||||
* to PLLA_MMAX.
|
||||
*/
|
||||
|
||||
putreg32(PMC_PMMR_MASK, SAM_PMC_CKGR_PMMR);
|
||||
#endif
|
||||
|
||||
/* Setup PLLA and wait for LOCKA */
|
||||
|
||||
putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR);
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/sam34/sam_timerisr.c
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2010, 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -57,16 +57,17 @@
|
||||
****************************************************************************/
|
||||
/* Select MCU-specific settings
|
||||
*
|
||||
* For the SAM3U, SAM3A, and SAM3X, Systickis driven by the main clock
|
||||
* For the SAM3U, SAM3A, and SAM3X, Systick is driven by the main clock
|
||||
* (This could be the MCK/8 but that option has not yet been necessary).
|
||||
* For the SAM4L, Systick is driven by the CPU clock which is just the main
|
||||
* clock divided down.
|
||||
* For the SAM4L, SAM4S, and SAM4E, Systick is driven by the CPU clock which
|
||||
* is just the main clock divided down.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# define SAM_SYSTICK_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_SYSTICK_CLOCK BOARD_CPU_FREQUENCY /* CPU frequency */
|
||||
#else
|
||||
# error Unrecognized SAM architecture
|
||||
|
||||
Loading…
Reference in New Issue
Block a user