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arch/arm/src/stm32l4: Some updates to analog peripherals ADC, COMP and DFSDM for STM32L4XR

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This commit is contained in:
Juha Niskanen 2018-08-16 08:10:46 -06:00 committed by Gregory Nutt
parent c90ee015e4
commit d219182588
9 changed files with 133 additions and 85 deletions
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3
arch/arm/src/stm32l4/Kconfig
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@ -537,7 +537,6 @@ config STM32L4_STM32L4XR
select STM32L4_HAVE_USART3 select STM32L4_HAVE_USART3
select STM32L4_HAVE_UART4 select STM32L4_HAVE_UART4
select STM32L4_HAVE_UART5 select STM32L4_HAVE_UART5
select STM32L4_HAVE_ADC2
select STM32L4_HAVE_DAC2 select STM32L4_HAVE_DAC2
select STM32L4_HAVE_FSMC select STM32L4_HAVE_FSMC
select STM32L4_HAVE_TIM3 select STM32L4_HAVE_TIM3
@ -3508,7 +3507,7 @@ config STM32L4_ADC3_DMA
config STM32L4_ADC1_OUTPUT_DFSDM config STM32L4_ADC1_OUTPUT_DFSDM
bool "ADC1 output to DFSDM" bool "ADC1 output to DFSDM"
depends on STM32L4_ADC1 && STM32L4_DFSDM1 && STM32L4_STM32L496XX depends on STM32L4_ADC1 && STM32L4_DFSDM1 && (STM32L4_STM32L496XX || STM32L4_STM32L4XR)
default n default n
---help--- ---help---
Route ADC1 output directly to DFSDM parallel inputs. Route ADC1 output directly to DFSDM parallel inputs.

115
arch/arm/src/stm32l4/chip/stm32l4_dfsdm.h
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@ -1,7 +1,7 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4_dfsdm.h * arch/arm/src/stm32l4/chip/stm32l4_dfsdm.h
* *
* Copyright (C) 2017 Haltian Ltd. All rights reserved. * Copyright (C) 2017-2018 Haltian Ltd. All rights reserved.
* Author: Juha Niskanen <juha.niskanen@haltian.com> * Author: Juha Niskanen <juha.niskanen@haltian.com>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -107,64 +107,80 @@
#define STM32L4_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */ #define STM32L4_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */
#define STM32L4_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 channel data input register */ #define STM32L4_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 data input register */
#define STM32L4_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 channel data input register */ #define STM32L4_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 data input register */
#define STM32L4_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 channel data input register */ #define STM32L4_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 data input register */
#define STM32L4_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 channel data input register */ #define STM32L4_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 data input register */
#ifndef CONFIG_STM32L4_STM32L4X3 #ifndef CONFIG_STM32L4_STM32L4X3
# define STM32L4_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 channel data input register */ # define STM32L4_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 data input register */
# define STM32L4_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 channel data input register */ # define STM32L4_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 data input register */
# define STM32L4_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 channel data input register */ # define STM32L4_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 data input register */
# define STM32L4_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 channel data input register */ # define STM32L4_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 data input register */
#endif
#ifdef CONFIG_STM32L4_STM32L4XR
# define STM32L4_DFSDM_CHDLYR_OFFSET(ch) (0x14 + 0x20 * (ch)) /* DFSDM channel delay register */
# define STM32L4_DFSDM_CH0DLYR_OFFSET 0x0014 /* DFSDM channel 0 delay register */
# define STM32L4_DFSDM_CH1DLYR_OFFSET 0x0034 /* DFSDM channel 1 delay register */
# define STM32L4_DFSDM_CH2DLYR_OFFSET 0x0054 /* DFSDM channel 2 delay register */
# define STM32L4_DFSDM_CH3DLYR_OFFSET 0x0074 /* DFSDM channel 3 delay register */
# define STM32L4_DFSDM_CH4DLYR_OFFSET 0x0094 /* DFSDM channel 4 delay register */
# define STM32L4_DFSDM_CH5DLYR_OFFSET 0x00b4 /* DFSDM channel 5 delay register */
# define STM32L4_DFSDM_CH6DLYR_OFFSET 0x00d4 /* DFSDM channel 6 delay register */
# define STM32L4_DFSDM_CH7DLYR_OFFSET 0x00f4 /* DFSDM channel 7 delay register */
#endif #endif
/* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */ /* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */
#define STM32L4_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */ #define STM32L4_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */
#define STM32L4_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */ #define STM32L4_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */
#define STM32L4_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */ #define STM32L4_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */
#define STM32L4_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */ #define STM32L4_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */
#define STM32L4_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */ #define STM32L4_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */
#define STM32L4_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */ #define STM32L4_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */
#define STM32L4_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */ #define STM32L4_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */
#define STM32L4_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */ #define STM32L4_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */
#define STM32L4_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */ #define STM32L4_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */
#define STM32L4_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */ #define STM32L4_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */
#define STM32L4_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */ #define STM32L4_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */
#define STM32L4_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */ #define STM32L4_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */
#define STM32L4_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */ #define STM32L4_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */
#define STM32L4_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */ #define STM32L4_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */
#define STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */ #define STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */
/* Register Addresses ***************************************************************/ /* Register Addresses ***************************************************************/
/* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */ /* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */
#define STM32L4_DFSDM_CHCFGR1(y) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_CHCFGR1_OFFSET(y)) #define STM32L4_DFSDM_CHCFGR1(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHCFGR1_OFFSET(y))
#define STM32L4_DFSDM_CH0CFGR1 (STM32L4_DFSDM_BASE+STM32L4_DFSDM_CH0CFGR1_OFFSET) #define STM32L4_DFSDM_CH0CFGR1 (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CH0CFGR1_OFFSET)
#define STM32L4_DFSDM_CHCFGR2(y) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_CHCFGR2_OFFSET(y)) #define STM32L4_DFSDM_CHCFGR2(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHCFGR2_OFFSET(y))
#define STM32L4_DFSDM_CHAWSCDR(y) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_CHAWSCDR_OFFSET(y)) #define STM32L4_DFSDM_CHAWSCDR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHAWSCDR_OFFSET(y))
#define STM32L4_DFSDM_CHWDATR(y) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_CHWDATR_OFFSET(y) #define STM32L4_DFSDM_CHWDATR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHWDATR_OFFSET(y)
#define STM32L4_DFSDM_CHDATINR(y) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_CHDATINR_OFFSET(y)) #define STM32L4_DFSDM_CHDATINR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHDATINR_OFFSET(y))
#ifdef CONFIG_STM32L4_STM32L4XR
# define STM32L4_DFSDM_CHDLYR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHDLYR_OFFSET(y))
#endif
/* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */ /* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */
#define STM32L4_DFSDM_FLTCR1(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTCR1_OFFSET(x)) #define STM32L4_DFSDM_FLTCR1(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCR1_OFFSET(x))
#define STM32L4_DFSDM_FLTCR2(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTCR2_OFFSET(x)) #define STM32L4_DFSDM_FLTCR2(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCR2_OFFSET(x))
#define STM32L4_DFSDM_FLTISR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTISR_OFFSET(x)) #define STM32L4_DFSDM_FLTISR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTISR_OFFSET(x))
#define STM32L4_DFSDM_FLTICR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTICR_OFFSET(x)) #define STM32L4_DFSDM_FLTICR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTICR_OFFSET(x))
#define STM32L4_DFSDM_FLTJCHGR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTJCHGR_OFFSET(x)) #define STM32L4_DFSDM_FLTJCHGR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTJCHGR_OFFSET(x))
#define STM32L4_DFSDM_FLTFCR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTFCR_OFFSET(x)) #define STM32L4_DFSDM_FLTFCR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTFCR_OFFSET(x))
#define STM32L4_DFSDM_FLTJDATAR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTJDATAR_OFFSET(x)) #define STM32L4_DFSDM_FLTJDATAR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTJDATAR_OFFSET(x))
#define STM32L4_DFSDM_FLTRDATAR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTRDATAR_OFFSET(x)) #define STM32L4_DFSDM_FLTRDATAR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTRDATAR_OFFSET(x))
#define STM32L4_DFSDM_FLTAWHTR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTAWHTR_OFFSET(x)) #define STM32L4_DFSDM_FLTAWHTR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWHTR_OFFSET(x))
#define STM32L4_DFSDM_FLTAWLTR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTAWLTR_OFFSET(x)) #define STM32L4_DFSDM_FLTAWLTR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWLTR_OFFSET(x))
#define STM32L4_DFSDM_FLTAWSR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTAWSR_OFFSET(x)) #define STM32L4_DFSDM_FLTAWSR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWSR_OFFSET(x))
#define STM32L4_DFSDM_FLTAWCFR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTAWCFR_OFFSET(x)) #define STM32L4_DFSDM_FLTAWCFR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWCFR_OFFSET(x))
#define STM32L4_DFSDM_FLTEXMAX(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTEXMAX_OFFSET(x)) #define STM32L4_DFSDM_FLTEXMAX(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTEXMAX_OFFSET(x))
#define STM32L4_DFSDM_FLTEXMIN(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTEXMIN_OFFSET(x)) #define STM32L4_DFSDM_FLTEXMIN(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTEXMIN_OFFSET(x))
#define STM32L4_DFSDM_FLTCNVTIMR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x)) #define STM32L4_DFSDM_FLTCNVTIMR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x))
/* Register Bitfield Definitions ****************************************************/ /* Register Bitfield Definitions ****************************************************/
/* DFSDM channel configuration y register (DFSDM_CHyCFGR1) */ /* DFSDM channel configuration y register (DFSDM_CHyCFGR1) */
@ -251,6 +267,12 @@
#define DFSDM_CHDATINR_INDAT1_MASK (0xffff << DFSDM_CHDATINR_INDAT1_SHIFT) #define DFSDM_CHDATINR_INDAT1_MASK (0xffff << DFSDM_CHDATINR_INDAT1_SHIFT)
# define DFSDM_CHDATINR_INDAT1(n) ((n) << DFSDM_CHDATINR_INDAT1_SHIFT) # define DFSDM_CHDATINR_INDAT1(n) ((n) << DFSDM_CHDATINR_INDAT1_SHIFT)
/* DFSDM channel delay register (DFSDM_CHyDLYR) */
#define DFSDM_CHDLYR_PLSSKP_SHIFT (0) /* Bits 0-5: Pulses to skip for input data skipping function */
#define DFSDM_CHDLYR_PLSSKP_MASK (0x1f << DFSDM_CHDLYR_PLSSKP_SHIFT)
# define DFSDM_CHDLYR_PLSSKP(n) ((n) << DFSDM_CHDLYR_PLSSKP_SHIFT) /* n=0..63 */
/* DFSDM filter x module registers */ /* DFSDM filter x module registers */
/* DFSDM control register 1 (DFSDM_FLTxCR1) */ /* DFSDM control register 1 (DFSDM_FLTxCR1) */
@ -390,7 +412,8 @@
/* DFSDM data register for the regular channel (DFSDM_FLTxRDATAR) */ /* DFSDM data register for the regular channel (DFSDM_FLTxRDATAR) */
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX) #if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX) || \
defined(CONFIG_STM32L4_STM32L4XR)
# define DFSDM_FLTRDATAR_RDATACH_SHIFT (0) /* Bits 0-3: channel most recently converted */ # define DFSDM_FLTRDATAR_RDATACH_SHIFT (0) /* Bits 0-3: channel most recently converted */
# define DFSDM_FLTRDATAR_RDATACH_MASK (7 << DFSDM_FLTRDATAR_RDATACH_SHIFT) # define DFSDM_FLTRDATAR_RDATACH_MASK (7 << DFSDM_FLTRDATAR_RDATACH_SHIFT)
#endif #endif

4
arch/arm/src/stm32l4/chip/stm32l4_memorymap.h
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@ -52,9 +52,9 @@
# define STM32L4_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ # define STM32L4_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
# define STM32L4_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ # define STM32L4_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
#define STM32L4_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */ #define STM32L4_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */
#define STM32L4_QSPI_BASE 0xa0001000 /* 0xa0000000-0xbfffffff: QSPI register block */ #define STM32L4_QSPI_BASE 0xa0001000 /* 0xa0001000-0xbfffffff: QSPI register block */
#define STM32L4_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */ #define STM32L4_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */
#define STM32L4_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xbfffffff: OCTOSPI2 register block */ #define STM32L4_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xa00017ff: OCTOSPI2 register block */
/* 0xc0000000-0xdfffffff: 512Mb (not used) */ /* 0xc0000000-0xdfffffff: 512Mb (not used) */
#define STM32L4_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ #define STM32L4_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */

62
arch/arm/src/stm32l4/chip/stm32l4xrxx_pinmap.h
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@ -325,28 +325,36 @@
#define GPIO_OCTOSPIM_P1_DQS_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN1) #define GPIO_OCTOSPIM_P1_DQS_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN1)
#define GPIO_OCTOSPIM_P1_DQS_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN2) #define GPIO_OCTOSPIM_P1_DQS_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN2)
#define GPIO_OCTOSPIM_P1_DQS_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN3)
#define GPIO_OCTOSPIM_P1_NCS_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11) #define GPIO_OCTOSPIM_P1_NCS_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
#define GPIO_OCTOSPIM_P1_NCS_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11) #define GPIO_OCTOSPIM_P1_NCS_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11)
#define GPIO_OCTOSPIM_P1_NCS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN11)
#define GPIO_OCTOSPIM_P1_CLK_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10) #define GPIO_OCTOSPIM_P1_CLK_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10)
#define GPIO_OCTOSPIM_P1_CLK_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10) #define GPIO_OCTOSPIM_P1_CLK_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10)
#define GPIO_OCTOSPIM_1_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1) #define GPIO_OCTOSPIM_P1_CLK_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTF|GPIO_PIN10)
#define GPIO_OCTOSPIM_1_IO0_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12) #define GPIO_OCTOSPIM_P1_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
#define GPIO_OCTOSPIM_1_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0) #define GPIO_OCTOSPIM_P1_IO0_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12)
#define GPIO_OCTOSPIM_1_IO1_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13) #define GPIO_OCTOSPIM_P1_IO0_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN8)
#define GPIO_OCTOSPIM_1_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN7) #define GPIO_OCTOSPIM_P1_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
#define GPIO_OCTOSPIM_1_IO2_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14) #define GPIO_OCTOSPIM_P1_IO1_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13)
#define GPIO_OCTOSPIM_1_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN6) #define GPIO_OCTOSPIM_P1_IO1_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN9)
#define GPIO_OCTOSPIM_1_IO3_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN15) #define GPIO_OCTOSPIM_P1_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN7)
#define GPIO_OCTOSPIM_1_IO4_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN1) #define GPIO_OCTOSPIM_P1_IO2_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14)
#define GPIO_OCTOSPIM_1_IO4_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN4) #define GPIO_OCTOSPIM_P1_IO2_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN7)
#define GPIO_OCTOSPIM_1_IO4_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN2) #define GPIO_OCTOSPIM_P1_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN6)
#define GPIO_OCTOSPIM_1_IO5_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2) #define GPIO_OCTOSPIM_P1_IO3_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN15)
#define GPIO_OCTOSPIM_1_IO5_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN5) #define GPIO_OCTOSPIM_P1_IO3_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN6)
#define GPIO_OCTOSPIM_1_IO5_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTG|GPIO_PIN11) #define GPIO_OCTOSPIM_P1_IO4_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN1)
#define GPIO_OCTOSPIM_1_IO6_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3) #define GPIO_OCTOSPIM_P1_IO4_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN4)
#define GPIO_OCTOSPIM_1_IO6_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN6) #define GPIO_OCTOSPIM_P1_IO4_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN2)
#define GPIO_OCTOSPIM_1_IO7_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN4) #define GPIO_OCTOSPIM_P1_IO5_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2)
#define GPIO_OCTOSPIM_1_IO7_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN7) #define GPIO_OCTOSPIM_P1_IO5_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN5)
#define GPIO_OCTOSPIM_P1_IO5_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTG|GPIO_PIN11)
#define GPIO_OCTOSPIM_P1_IO5_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN0)
#define GPIO_OCTOSPIM_P1_IO6_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3)
#define GPIO_OCTOSPIM_P1_IO6_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN6)
#define GPIO_OCTOSPIM_P1_IO7_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN4)
#define GPIO_OCTOSPIM_P1_IO7_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN7)
#define GPIO_OCTOSPIM_P2_DQS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN12) #define GPIO_OCTOSPIM_P2_DQS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN12)
#define GPIO_OCTOSPIM_P2_DQS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN15) #define GPIO_OCTOSPIM_P2_DQS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN15)
@ -357,7 +365,23 @@
#define GPIO_OCTOSPIM_P2_CLK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN4) #define GPIO_OCTOSPIM_P2_CLK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN4)
#define GPIO_OCTOSPIM_P2_CLK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN6) #define GPIO_OCTOSPIM_P2_CLK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN6)
#define GPIO_OCTOSPIM_P2_CLK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN6) #define GPIO_OCTOSPIM_P2_CLK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN6)
/* TODO: IO lines */ #define GPIO_OCTOSPIM_P2_IO0_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN0)
#define GPIO_OCTOSPIM_P2_IO0_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN11)
#define GPIO_OCTOSPIM_P2_IO1_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN1)
#define GPIO_OCTOSPIM_P2_IO1_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN10)
#define GPIO_OCTOSPIM_P2_IO2_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN2)
#define GPIO_OCTOSPIM_P2_IO2_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN9)
#define GPIO_OCTOSPIM_P2_IO3_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN3)
#define GPIO_OCTOSPIM_P2_IO3_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN8)
#define GPIO_OCTOSPIM_P2_IO4_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN0)
#define GPIO_OCTOSPIM_P2_IO4_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN9)
#define GPIO_OCTOSPIM_P2_IO5_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN1)
#define GPIO_OCTOSPIM_P2_IO5_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN10)
#define GPIO_OCTOSPIM_P2_IO6_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN9)
#define GPIO_OCTOSPIM_P2_IO6_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN11)
#define GPIO_OCTOSPIM_P2_IO6_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN15)
#define GPIO_OCTOSPIM_P2_IO7_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN10)
#define GPIO_OCTOSPIM_P2_IO7_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN12)
/* RTC */ /* RTC */

9
arch/arm/src/stm32l4/stm32l4_comp.c
View File

@ -54,8 +54,8 @@
#include <errno.h> #include <errno.h>
#if !(defined(CONFIG_STM32L4_STM32L4X3) || \ #if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6)) defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR))
# error "Unrecognized STM32 chip" # error "Unrecognized STM32 chip"
#endif #endif
@ -105,7 +105,7 @@ static struct stm32l4_comp_config_s g_comp1priv =
.rising = true, .rising = true,
.falling = false .falling = false
}, },
.inp = STM32L4_COMP_INP_PIN_3, .inp = STM32L4_COMP_INP_PIN_2,
.inm = STM32L4_COMP_INM_VREF, .inm = STM32L4_COMP_INM_VREF,
.hyst = STM32L4_COMP_HYST_LOW, .hyst = STM32L4_COMP_HYST_LOW,
.speed = STM32L4_COMP_SPEED_MEDIUM, .speed = STM32L4_COMP_SPEED_MEDIUM,
@ -428,7 +428,8 @@ static int stm32l4_compconfig(FAR const struct comp_dev_s *dev)
case STM32L4_COMP_INM_PIN_2: case STM32L4_COMP_INM_PIN_2:
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_2 : GPIO_COMP2_INM_2); stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_2 : GPIO_COMP2_INM_2);
#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) #if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \
defined(CONFIG_STM32L4_STM32L4XR)
regval |= COMP_CSR_INMSEL_PIN2; regval |= COMP_CSR_INMSEL_PIN2;
#else #else
regval |= COMP_CSR_INMSEL_INMESEL; regval |= COMP_CSR_INMSEL_INMESEL;

3
arch/arm/src/stm32l4/stm32l4_comp.h
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@ -87,7 +87,8 @@ enum stm32l4_comp_inm_e
STM32L4_COMP_INM_PIN_5 /* COMP1: PA5, COMP2: PA5 */ STM32L4_COMP_INM_PIN_5 /* COMP1: PA5, COMP2: PA5 */
}; };
#elif defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) #else
/* Comparators */ /* Comparators */
enum stm32l4_comp_e enum stm32l4_comp_e

10
arch/arm/src/stm32l4/stm32l4_dfsdm.c
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@ -452,7 +452,7 @@ static void dfsdm_putreg(FAR struct stm32_dev_s *priv, int offset,
* Modify the value of an DFSDM register (not atomic). * Modify the value of an DFSDM register (not atomic).
* *
* Input Parameters: * Input Parameters:
* priv - A reference to the ADC block status * priv - A reference to the DFSDM block status
* offset - The offset to the register to modify * offset - The offset to the register to modify
* clrbits - The bits to clear * clrbits - The bits to clear
* setbits - The bits to set * setbits - The bits to set
@ -661,7 +661,7 @@ static int dfsdm_timinit(FAR struct stm32_dev_s *priv)
uint16_t ccer; uint16_t ccer;
uint16_t egr; uint16_t egr;
/* If the timer base address is zero, then this ADC was not configured to /* If the timer base address is zero, then this DFSDM was not configured to
* use a timer. * use a timer.
*/ */
@ -686,9 +686,9 @@ static int dfsdm_timinit(FAR struct stm32_dev_s *priv)
DFSDM_FLTCR1_JEXTEN_MASK | DFSDM_FLTCR1_JEXTSEL_MASK, DFSDM_FLTCR1_JEXTEN_MASK | DFSDM_FLTCR1_JEXTSEL_MASK,
DFSDM_FLTCR1_JEXTEN_RISING | priv->extsel); DFSDM_FLTCR1_JEXTEN_RISING | priv->extsel);
/* Configure the timer channel to drive the ADC */ /* Configure the timer channel. */
/* Caculate optimal values for the timer prescaler and for the timer /* Calculate optimal values for the timer prescaler and for the timer
* reload register. If freq is the desired frequency, then * reload register. If freq is the desired frequency, then
* *
* reload = timclk / freq * reload = timclk / freq
@ -1116,8 +1116,6 @@ static int dfsdm_bind(FAR struct adc_dev_s *dev,
* Reset the DFSDM device. Called early to initialize the hardware. This * Reset the DFSDM device. Called early to initialize the hardware. This
* is called, before dfsdm_setup() and on error conditions. * is called, before dfsdm_setup() and on error conditions.
* *
* Input Parameters:
*
****************************************************************************/ ****************************************************************************/
static void dfsdm_reset(FAR struct adc_dev_s *dev) static void dfsdm_reset(FAR struct adc_dev_s *dev)

4
arch/arm/src/stm32l4/stm32l4_exti_comp.c
View File

@ -69,8 +69,8 @@ static struct comp_callback_s g_comp_handlers[STM32L4_COMP_NUM];
static const uint32_t g_comp_lines[STM32L4_COMP_NUM] = static const uint32_t g_comp_lines[STM32L4_COMP_NUM] =
{ {
#if defined(CONFIG_STM32L4_STM32L4X3) || \ #if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
EXTI1_COMP1, EXTI1_COMP1,
EXTI1_COMP2 EXTI1_COMP2
#else #else

8
arch/arm/src/stm32l4/stm32l4x3xx_rcc.c
View File

@ -537,11 +537,13 @@ static inline void rcc_enableccip(void)
#ifdef CONFIG_STM32L4_DFSDM1 #ifdef CONFIG_STM32L4_DFSDM1
/* Select SYSCLK as DFSDM clock source */ /* Select SYSCLK as DFSDM clock source */
/* TODO: not sure if this can be done on these MCUs. /* RM0394 Rev 3, p. 525 is confused about DFSDM clock source.
* RM0394 Rev 3, p. 525 is confused. * ST has confirmed that at least in STM32L451, the bit DFSDMSEL
* in RCC_CCIPR is present and bit description was omitted from
* RM0394 by accident.
*/ */
//regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; regval |= RCC_CCIPR_DFSDMSEL_SYSCLK;
#endif #endif
putreg32(regval, STM32L4_RCC_CCIPR); putreg32(regval, STM32L4_RCC_CCIPR);