From d2b98cc15026a55a5f5fb66111f56463b28e6bab Mon Sep 17 00:00:00 2001 From: Mateusz Szafoni Date: Sun, 2 Dec 2018 11:49:25 +0000 Subject: [PATCH] Merged in raiden00/nuttx_pe (pull request #771) Use STM32 DMA IP core version instead of chip family names and some minor improvements arch/arm/src/stm32/chip/stm32_adc.h: raise error if two IP cores seleceted libs/libdsp/Kconfig: cosmetic change arch/arm/src/stm32/Kconfig: hide TIMER menu, HRTIM menu and USB Host debug menu if peripherals not enabled configs/stm32f429i-disco/highpri/defconfig: fix configuration warning Approved-by: GregoryN --- arch/arm/src/stm32/Kconfig | 97 +- arch/arm/src/stm32/chip/stm32_adc.h | 4 + arch/arm/src/stm32/chip/stm32_dma.h | 64 + .../{stm32f10xxx_dma.h => stm32_dma_v1.h} | 83 +- .../{stm32f40xxx_dma.h => stm32_dma_v2.h} | 13 +- arch/arm/src/stm32/chip/stm32f20xxx_dma.h | 520 --------- arch/arm/src/stm32/chip/stm32f33xxx_dma.h | 366 ------ arch/arm/src/stm32/stm32_dma.c | 28 +- arch/arm/src/stm32/stm32_dma.h | 48 +- .../{stm32f10xxx_dma.c => stm32_dma_v1.c} | 8 +- .../{stm32f40xxx_dma.c => stm32_dma_v2.c} | 11 +- arch/arm/src/stm32/stm32f20xxx_dma.c | 1032 ----------------- configs/stm32f429i-disco/highpri/defconfig | 2 - libs/libdsp/Kconfig | 5 +- 14 files changed, 249 insertions(+), 2032 deletions(-) create mode 100644 arch/arm/src/stm32/chip/stm32_dma.h rename arch/arm/src/stm32/chip/{stm32f10xxx_dma.h => stm32_dma_v1.h} (89%) rename arch/arm/src/stm32/chip/{stm32f40xxx_dma.h => stm32_dma_v2.h} (99%) delete mode 100644 arch/arm/src/stm32/chip/stm32f20xxx_dma.h delete mode 100644 arch/arm/src/stm32/chip/stm32f33xxx_dma.h rename arch/arm/src/stm32/{stm32f10xxx_dma.c => stm32_dma_v1.c} (98%) rename arch/arm/src/stm32/{stm32f40xxx_dma.c => stm32_dma_v2.c} (99%) delete mode 100644 arch/arm/src/stm32/stm32f20xxx_dma.c diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 2f719fd2d9..943156f819 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -1491,6 +1491,7 @@ config STM32_STM32L15XX select STM32_HAVE_RTC_SUBSECONDS if !STM32_LOWDENSITY select STM32_HAVE_IP_TIMERS_V1 select STM32_HAVE_IP_ADC_V1 + select STM32_HAVE_IP_DMA_V1 config STM32_ENERGYLITE bool @@ -1513,6 +1514,7 @@ config STM32_STM32F10XX select STM32_HAVE_TIM3 select STM32_HAVE_IP_TIMERS_V1 select STM32_HAVE_IP_ADC_V1_BASIC + select STM32_HAVE_IP_DMA_V1 config STM32_VALUELINE bool @@ -1625,6 +1627,7 @@ config STM32_STM32F20XX select STM32_HAVE_IOCOMPENSATION select STM32_HAVE_IP_TIMERS_V1 select STM32_HAVE_IP_ADC_V1 + select STM32_HAVE_IP_DMA_V2 config STM32_STM32F205 bool @@ -1709,6 +1712,7 @@ config STM32_STM32F30XX select STM32_HAVE_TIM17 select STM32_HAVE_IP_TIMERS_V2 select STM32_HAVE_IP_ADC_V2 + select STM32_HAVE_IP_DMA_V1 config STM32_STM32F302 bool @@ -1752,6 +1756,7 @@ config STM32_STM32F33XX select STM32_HAVE_USART3 select STM32_HAVE_IP_TIMERS_V2 select STM32_HAVE_IP_ADC_V2 + select STM32_HAVE_IP_DMA_V1 config STM32_STM32F37XX bool @@ -1777,6 +1782,7 @@ config STM32_STM32F37XX select STM32_HAVE_USART3 select STM32_HAVE_IP_TIMERS_V1 select STM32_HAVE_IP_ADC_V1_BASIC + select STM32_HAVE_IP_DMA_V1 config STM32_STM32F4XXX bool @@ -1786,6 +1792,7 @@ config STM32_STM32F4XXX select STM32_HAVE_IOCOMPENSATION select STM32_HAVE_IP_TIMERS_V1 select STM32_HAVE_IP_ADC_V1 + select STM32_HAVE_IP_DMA_V2 config STM32_STM32F401xBC bool @@ -2151,14 +2158,6 @@ config STM32_HAVE_UART8 bool default n -config STM32_HAVE_IP_TIMERS_V1 - bool - default n - -config STM32_HAVE_IP_TIMERS_V2 - bool - default n - config STM32_HAVE_TIM1 bool default n @@ -2227,24 +2226,6 @@ config STM32_HAVE_TIM17 bool default n -config STM32_HAVE_IP_ADC_V1 - bool - default n - -config STM32_HAVE_IP_ADC_V1_BASIC - bool - default n - select STM32_HAVE_IP_ADC_V1 - -config STM32_HAVE_IP_ADC_V2 - bool - default n - -config STM32_HAVE_IP_ADC_V2_BASIC - bool - default n - select STM32_HAVE_IP_ADC_V2 - config STM32_HAVE_ADC2 bool default n @@ -2405,6 +2386,42 @@ config STM32_HAVE_OPAMP4 bool default n +# These are STM32 peripherals IP blocks + +config STM32_HAVE_IP_DMA_V1 + bool + default n + +config STM32_HAVE_IP_DMA_V2 + bool + default n + +config STM32_HAVE_IP_TIMERS_V1 + bool + default n + +config STM32_HAVE_IP_TIMERS_V2 + bool + default n + +config STM32_HAVE_IP_ADC_V1 + bool + default n + +config STM32_HAVE_IP_ADC_V1_BASIC + bool + default n + select STM32_HAVE_IP_ADC_V1 + +config STM32_HAVE_IP_ADC_V2 + bool + default n + +config STM32_HAVE_IP_ADC_V2_BASIC + bool + default n + select STM32_HAVE_IP_ADC_V2 + # These are the peripheral selections proper config STM32_ADC1 @@ -2824,85 +2841,102 @@ config STM32_TIM1 bool "TIM1" default n depends on STM32_HAVE_TIM1 + select STM32_TIM config STM32_TIM2 bool "TIM2" default n + select STM32_TIM config STM32_TIM3 bool "TIM3" default n depends on STM32_HAVE_TIM3 + select STM32_TIM config STM32_TIM4 bool "TIM4" default n depends on STM32_HAVE_TIM4 + select STM32_TIM config STM32_TIM5 bool "TIM5" default n depends on STM32_HAVE_TIM5 + select STM32_TIM config STM32_TIM6 bool "TIM6" default n depends on STM32_HAVE_TIM6 + select STM32_TIM config STM32_TIM7 bool "TIM7" default n depends on STM32_HAVE_TIM7 + select STM32_TIM config STM32_TIM8 bool "TIM8" default n depends on STM32_HAVE_TIM8 + select STM32_TIM config STM32_TIM9 bool "TIM9" default n depends on STM32_HAVE_TIM9 + select STM32_TIM config STM32_TIM10 bool "TIM10" default n depends on STM32_HAVE_TIM10 + select STM32_TIM config STM32_TIM11 bool "TIM11" default n depends on STM32_HAVE_TIM11 + select STM32_TIM config STM32_TIM12 bool "TIM12" default n depends on STM32_HAVE_TIM12 + select STM32_TIM config STM32_TIM13 bool "TIM13" default n depends on STM32_HAVE_TIM13 + select STM32_TIM config STM32_TIM14 bool "TIM14" default n depends on STM32_HAVE_TIM14 + select STM32_TIM config STM32_TIM15 bool "TIM15" default n depends on STM32_HAVE_TIM15 + select STM32_TIM config STM32_TIM16 bool "TIM16" default n depends on STM32_HAVE_TIM16 + select STM32_TIM config STM32_TIM17 bool "TIM17" default n depends on STM32_HAVE_TIM17 + select STM32_TIM config STM32_TSC bool "TSC" @@ -2996,6 +3030,10 @@ config STM32_I2C config STM32_CAN bool +config STM32_TIM + bool + default n + config STM32_NOEXT_VECTORS bool "Disable the ARMv7-M EXT vectors" default n @@ -3316,6 +3354,7 @@ config STM32_FSMC_SRAM In addition to internal SRAM, SRAM may also be available through the FSMC. menu "Timer Configuration" + depends on STM32_TIM if SCHED_TICKLESS @@ -7051,8 +7090,7 @@ endmenu #STM32 TIMx Outputs Configuration endmenu # Timer Configuration menu "HRTIM Configuration" - -if STM32_HRTIM1 + depends on STM32_HRTIM config STM32_HRTIM_DISABLE_CHARDRV bool "HRTIM Disable Character Driver" @@ -7629,8 +7667,6 @@ config STM32_HRTIM_TIME_PSHPLL endmenu # "HRTIM Timer E Configuration" -endif # STM32_HRTIM1 - endmenu # "HRTIM Configuration" menu "ADC Configuration" @@ -9356,6 +9392,7 @@ config STM32_OTGHS_SOFINTR endmenu menu "USB Host Debug Configuration" + depends on STM32_USBHOST config STM32_USBHOST_REGDEBUG bool "Register-Level Debug" diff --git a/arch/arm/src/stm32/chip/stm32_adc.h b/arch/arm/src/stm32/chip/stm32_adc.h index 87a2d37aa2..1e57fe3e73 100644 --- a/arch/arm/src/stm32/chip/stm32_adc.h +++ b/arch/arm/src/stm32/chip/stm32_adc.h @@ -56,6 +56,10 @@ * which differs too much to keep it in the same file as ADC IPv1. */ +#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && defined(CONFIG_STM32_HAVE_IP_ADC_V2) +# error Only one STM32 ADC IP version must be selected +#endif + #if defined(CONFIG_STM32_HAVE_IP_ADC_V1) # if defined(CONFIG_STM32_STM32L15XX) # include "stm32_adc_v1l1.h" /* Special case for L1 */ diff --git a/arch/arm/src/stm32/chip/stm32_dma.h b/arch/arm/src/stm32/chip/stm32_dma.h new file mode 100644 index 0000000000..9b46b62f24 --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32_dma.h @@ -0,0 +1,64 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32_dma.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/* Include the correct DMA register definitions for selected STM32 DMA IP core: + * - STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4 + * - STM32 DMA IP version 2 - F2, F4, F7, H7 + */ + +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) && defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# error Only one STM32 DMA IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) +# include "stm32_dma_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# include "stm32_dma_v2.h" +#else +# error "STM32 DMA IP version not specified" +#endif + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H */ diff --git a/arch/arm/src/stm32/chip/stm32f10xxx_dma.h b/arch/arm/src/stm32/chip/stm32_dma_v1.h similarity index 89% rename from arch/arm/src/stm32/chip/stm32f10xxx_dma.h rename to arch/arm/src/stm32/chip/stm32_dma_v1.h index 6cbd365fc4..12654068a3 100644 --- a/arch/arm/src/stm32/chip/stm32f10xxx_dma.h +++ b/arch/arm/src/stm32/chip/stm32_dma_v1.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32/chip/stm32f10xxx_dma.h + * arch/arm/src/stm32/chip/stm32_dma_v1.h * * Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,12 +33,18 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_DMA_H -#define __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_DMA_H +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V1_DMA_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V1_DMA_H /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ + +/* This is implementation for STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4 */ + +#define HAVE_IP_DMA_V1 1 +#undef HAVE_IP_DMA_V2 + /* These definitions apply to both the STM32 F1 and F3 families */ /* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */ @@ -520,6 +526,75 @@ # define DMACHAN_UART4_TX STM32_DMA2_CHAN5 # define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5 +#elif defined(CONFIG_STM32_STM32F33XX) + +# define DMACHAN_ADC1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 +# define DMACHAN_TIM17_CH1_1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM17_UP_1 STM32_DMA1_CHAN1 + +# define DMACHAN_ADC2_1 STM32_DMA1_CHAN2 +# define DMACHAN_SPI1_RX_1 STM32_DMA1_CHAN2 +# define DMACHAN_USART3_TX STM32_DMA1_CHAN2 +# define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2 +# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 +# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 +# define DMACHAN_HRTIM1_M STM32_DMA1_CHAN2 + +# define DMACHAN_SPI1_TX_1 STM32_DMA1_CHAN3 +# define DMACHAN_USART3_RX STM32_DMA1_CHAN3 +# define DMACHAN_I2C1_RX_2 STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 +# define DMACHAN_TIM6_UP STM32_DMA1_CHAN3 +# define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3 +# define DMACHAN_TIM16_CH1_1 STM32_DMA1_CHAN3 +# define DMACHAN_TIM16_UP_1 STM32_DMA1_CHAN3 +# define DMACHAN_HRTIM1_A STM32_DMA1_CHAN3 + +# define DMACHAN_ADC2_2 STM32_DMA1_CHAN4 +# define DMACHAN_SPI1_RX_2 STM32_DMA1_CHAN4 +# define DMACHAN_USART1_TX STM32_DMA1_CHAN4 +# define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4 +# define DMACHAN_TIM7_UP STM32_DMA1_CHAN4 +# define DMACHAN_DAC1_CH2 STM32_DMA1_CHAN4 +# define DMACHAN_HRTIM1_B STM32_DMA1_CHAN4 + +# define DMACHAN_SPI1_TX_2 STM32_DMA1_CHAN5 +# define DMACHAN_USART1_RX STM32_DMA1_CHAN5 +# define DMACHAN_I2C1_RX_3 STM32_DMA1_CHAN5 +# define DMACHAN_TIM1_UP STM32_DMA1_CHAN5 +# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_UP STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_COM STM32_DMA1_CHAN5 +# define DMACHAN_HRTIM1_C STM32_DMA1_CHAN5 + +# define DMACHAN_SPI1_RX_3 STM32_DMA1_CHAN6 +# define DMACHAN_USART2_RX STM32_DMA1_CHAN6 +# define DMACHAN_I2C1_TX_1 STM32_DMA1_CHAN6 +# define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 +# define DMACHAN_TIM16_CH1_2 STM32_DMA1_CHAN6 +# define DMACHAN_TIM16_UP_2 STM32_DMA1_CHAN6 +# define DMACHAN_HRTIM1_D STM32_DMA1_CHAN6 + +# define DMACHAN_SPI1_TX_3 STM32_DMA1_CHAN7 +# define DMACHAN_USART2_TX STM32_DMA1_CHAN7 +# define DMACHAN_I2C1_RX_1 STM32_DMA1_CHAN7 +# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7 +# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7 +# define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN7 +# define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN7 +# define DMACHAN_HRTIM1_E STM32_DMA1_CHAN7 + #elif defined(CONFIG_STM32_STM32F37XX) # define DMACHAN_ADC1 STM32_DMA1_CHAN1 @@ -605,4 +680,4 @@ # error "Unknown DMA channel assignments" #endif -#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_DMA_H */ +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V1_DMA_H */ diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_dma.h b/arch/arm/src/stm32/chip/stm32_dma_v2.h similarity index 99% rename from arch/arm/src/stm32/chip/stm32f40xxx_dma.h rename to arch/arm/src/stm32/chip/stm32_dma_v2.h index 13dbc0e3e8..d3be1ed455 100644 --- a/arch/arm/src/stm32/chip/stm32f40xxx_dma.h +++ b/arch/arm/src/stm32/chip/stm32_dma_v2.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32/chip/stm32f40xxx_dma.h + * arch/arm/src/stm32/chip/stm32_dma_v2.h * * Copyright (C) 2011-2012, 2014-2015 Gregory Nutt. All rights reserved. * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. @@ -36,13 +36,18 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_DMA_H -#define __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_DMA_H +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V2_DMA_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V2_DMA_H /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ +/* This is implementation for STM32 DMA IP version 2 - F2, F4, F7, H7 */ + +#define HAVE_IP_DMA_V2 1 +#undef HAVE_IP_DMA_V1 + /* 2 DMA controllers */ #define DMA1 (0) @@ -558,4 +563,4 @@ #define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) #define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) -#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_DMA_H */ +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V2_DMA_H */ diff --git a/arch/arm/src/stm32/chip/stm32f20xxx_dma.h b/arch/arm/src/stm32/chip/stm32f20xxx_dma.h deleted file mode 100644 index f3660fb1db..0000000000 --- a/arch/arm/src/stm32/chip/stm32f20xxx_dma.h +++ /dev/null @@ -1,520 +0,0 @@ -/************************************************************************************ - * arch/arm/src/stm32/chip/stm32f20xxx_dma.h - * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_DMA_H -#define __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_DMA_H - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* 2 DMA controllers */ - -#define DMA1 (0) -#define DMA2 (1) - -/* 8 DMA streams */ - -#define DMA_STREAM0 (0) -#define DMA_STREAM1 (1) -#define DMA_STREAM2 (2) -#define DMA_STREAM3 (3) -#define DMA_STREAM4 (4) -#define DMA_STREAM5 (5) -#define DMA_STREAM6 (6) -#define DMA_STREAM7 (7) - -/* 8 DMA channels */ - -#define DMA_CHAN0 (0) -#define DMA_CHAN1 (1) -#define DMA_CHAN2 (2) -#define DMA_CHAN3 (3) -#define DMA_CHAN4 (4) -#define DMA_CHAN5 (5) -#define DMA_CHAN6 (6) -#define DMA_CHAN7 (7) - -/* Register Offsets *****************************************************************/ - -#define STM32_DMA_LISR_OFFSET 0x0000 /* DMA low interrupt status register */ -#define STM32_DMA_HISR_OFFSET 0x0004 /* DMA high interrupt status register */ -#define STM32_DMA_LIFCR_OFFSET 0x0008 /* DMA low interrupt flag clear register */ -#define STM32_DMA_HIFCR_OFFSET 0x000c /* DMA high interrupt flag clear register */ - -#define STM32_DMA_OFFSET(n) (0x0010+0x0018*(n)) -#define STM32_DMA_SCR_OFFSET 0x0000 /* DMA stream n configuration register */ -#define STM32_DMA_SNDTR_OFFSET 0x0004 /* DMA stream n number of data register */ -#define STM32_DMA_SPAR_OFFSET 0x0008 /* DMA stream n peripheral address register */ -#define STM32_DMA_SM0AR_OFFSET 0x000c /* DMA stream n memory 0 address register */ -#define STM32_DMA_SM1AR_OFFSET 0x0010 /* DMA stream n memory 1 address register */ -#define STM32_DMA_SFCR_OFFSET 0x0014 /* DMA stream n FIFO control register */ - -#define STM32_DMA_S0CR_OFFSET 0x0010 /* DMA stream 0 configuration register */ -#define STM32_DMA_S1CR_OFFSET 0x0028 /* DMA stream 1 configuration register */ -#define STM32_DMA_S2CR_OFFSET 0x0040 /* DMA stream 2 configuration register */ -#define STM32_DMA_S3CR_OFFSET 0x0058 /* DMA stream 3 configuration register */ -#define STM32_DMA_S4CR_OFFSET 0x0070 /* DMA stream 4 configuration register */ -#define STM32_DMA_S5CR_OFFSET 0x0088 /* DMA stream 5 configuration register */ -#define STM32_DMA_S6CR_OFFSET 0x00a0 /* DMA stream 6 configuration register */ -#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */ - -#define STM32_DMA_S0NDTR_OFFSET 0x0014 /* DMA stream 0 number of data register */ -#define STM32_DMA_S1NDTR_OFFSET 0x002c /* DMA stream 1 number of data register */ -#define STM32_DMA_S2NDTR_OFFSET 0x0044 /* DMA stream 2 number of data register */ -#define STM32_DMA_S3NDTR_OFFSET 0x005c /* DMA stream 3 number of data register */ -#define STM32_DMA_S4NDTR_OFFSET 0x0074 /* DMA stream 4 number of data register */ -#define STM32_DMA_S5NDTR_OFFSET 0x008c /* DMA stream 5 number of data register */ -#define STM32_DMA_S6NDTR_OFFSET 0x00a4 /* DMA stream 6 number of data register */ -#define STM32_DMA_S7NDTR_OFFSET 0x00bc /* DMA stream 7 number of data register */ - -#define STM32_DMA_S0PAR_OFFSET 0x0018 /* DMA stream 0 peripheral address register */ -#define STM32_DMA_S1PAR_OFFSET 0x0030 /* DMA stream 1 peripheral address register */ -#define STM32_DMA_S2PAR_OFFSET 0x0048 /* DMA stream 2 peripheral address register */ -#define STM32_DMA_S3PAR_OFFSET 0x0060 /* DMA stream 3 peripheral address register */ -#define STM32_DMA_S4PAR_OFFSET 0x0078 /* DMA stream 4 peripheral address register */ -#define STM32_DMA_S5PAR_OFFSET 0x0090 /* DMA stream 5 peripheral address register */ -#define STM32_DMA_S6PAR_OFFSET 0x00a8 /* DMA stream 6 peripheral address register */ -#define STM32_DMA_S7PAR_OFFSET 0x00c0 /* DMA stream 7 peripheral address register */ - -#define STM32_DMA_S0M0AR_OFFSET 0x001c /* DMA stream 0 memory 0 address register */ -#define STM32_DMA_S1M0AR_OFFSET 0x0034 /* DMA stream 1 memory 0 address register */ -#define STM32_DMA_S2M0AR_OFFSET 0x004c /* DMA stream 2 memory 0 address register */ -#define STM32_DMA_S3M0AR_OFFSET 0x0064 /* DMA stream 3 memory 0 address register */ -#define STM32_DMA_S4M0AR_OFFSET 0x007c /* DMA stream 4 memory 0 address register */ -#define STM32_DMA_S5M0AR_OFFSET 0x0094 /* DMA stream 5 memory 0 address register */ -#define STM32_DMA_S6M0AR_OFFSET 0x00ac /* DMA stream 6 memory 0 address register */ -#define STM32_DMA_S7M0AR_OFFSET 0x00c4 /* DMA stream 7 memory 0 address register */ - -#define STM32_DMA_S0M1AR_OFFSET 0x0020 /* DMA stream 0 memory 1 address register */ -#define STM32_DMA_S1M1AR_OFFSET 0x0038 /* DMA stream 1 memory 1 address register */ -#define STM32_DMA_S2M1AR_OFFSET 0x0050 /* DMA stream 2 memory 1 address register */ -#define STM32_DMA_S3M1AR_OFFSET 0x0068 /* DMA stream 3 memory 1 address register */ -#define STM32_DMA_S4M1AR_OFFSET 0x0080 /* DMA stream 4 memory 1 address register */ -#define STM32_DMA_S5M1AR_OFFSET 0x0098 /* DMA stream 5 memory 1 address register */ -#define STM32_DMA_S6M1AR_OFFSET 0x00b0 /* DMA stream 6 memory 1 address register */ -#define STM32_DMA_S7M1AR_OFFSET 0x00c8 /* DMA stream 7 memory 1 address register */ - -#define STM32_DMA_S0FCR_OFFSET 0x0024 /* DMA stream 0 FIFO control register */ -#define STM32_DMA_S1FCR_OFFSET 0x003c /* DMA stream 1 FIFO control register */ -#define STM32_DMA_S2FCR_OFFSET 0x0054 /* DMA stream 2 FIFO control register */ -#define STM32_DMA_S3FCR_OFFSET 0x006c /* DMA stream 3 FIFO control register */ -#define STM32_DMA_S4FCR_OFFSET 0x0084 /* DMA stream 4 FIFO control register */ -#define STM32_DMA_S5FCR_OFFSET 0x009c /* DMA stream 5 FIFO control register */ -#define STM32_DMA_S6FCR_OFFSET 0x00b4 /* DMA stream 6 FIFO control register */ -#define STM32_DMA_S7FCR_OFFSET 0x00cc /* DMA stream 7 FIFO control register */ - -/* Register Addresses ***************************************************************/ - -#define STM32_DMA1_LISRC (STM32_DMA1_BASE+STM32_DMA_LISR_OFFSET) -#define STM32_DMA1_HISRC (STM32_DMA1_BASE+STM32_DMA_HISR_OFFSET) -#define STM32_DMA1_LIFCR (STM32_DMA1_BASE+STM32_DMA_LIFCR_OFFSET) -#define STM32_DMA1_HIFCR (STM32_DMA1_BASE+STM32_DMA_HIFCR_OFFSET) - -#define STM32_DMA1_SCR(n) (STM32_DMA1_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA1_S0CR (STM32_DMA1_BASE+STM32_DMA_S0CR_OFFSET) -#define STM32_DMA1_S1CR (STM32_DMA1_BASE+STM32_DMA_S1CR_OFFSET) -#define STM32_DMA1_S2CR (STM32_DMA1_BASE+STM32_DMA_S2CR_OFFSET) -#define STM32_DMA1_S3CR (STM32_DMA1_BASE+STM32_DMA_S3CR_OFFSET) -#define STM32_DMA1_S4CR (STM32_DMA1_BASE+STM32_DMA_S4CR_OFFSET) -#define STM32_DMA1_S5CR (STM32_DMA1_BASE+STM32_DMA_S5CR_OFFSET) -#define STM32_DMA1_S6CR (STM32_DMA1_BASE+STM32_DMA_S6CR_OFFSET) -#define STM32_DMA1_S7CR (STM32_DMA1_BASE+STM32_DMA_S7CR_OFFSET) - -#define STM32_DMA1_SNDTR(n) (STM32_DMA1_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA1_S0NDTR (STM32_DMA1_BASE+STM32_DMA_S0NDTR_OFFSET) -#define STM32_DMA1_S1NDTR (STM32_DMA1_BASE+STM32_DMA_S1NDTR_OFFSET) -#define STM32_DMA1_S2NDTR (STM32_DMA1_BASE+STM32_DMA_S2NDTR_OFFSET) -#define STM32_DMA1_S3NDTR (STM32_DMA1_BASE+STM32_DMA_S3NDTR_OFFSET) -#define STM32_DMA1_S4NDTR (STM32_DMA1_BASE+STM32_DMA_S4NDTR_OFFSET) -#define STM32_DMA1_S5NDTR (STM32_DMA1_BASE+STM32_DMA_S5NDTR_OFFSET) -#define STM32_DMA1_S6NDTR (STM32_DMA1_BASE+STM32_DMA_S6NDTR_OFFSET) -#define STM32_DMA1_S7NDTR (STM32_DMA1_BASE+STM32_DMA_S7NDTR_OFFSET) - -#define STM32_DMA1_SPAR(n) (STM32_DMA1_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA1_S0PAR (STM32_DMA1_BASE+STM32_DMA_S0PAR_OFFSET) -#define STM32_DMA1_S1PAR (STM32_DMA1_BASE+STM32_DMA_S1PAR_OFFSET) -#define STM32_DMA1_S2PAR (STM32_DMA1_BASE+STM32_DMA_S2PAR_OFFSET) -#define STM32_DMA1_S3PAR (STM32_DMA1_BASE+STM32_DMA_S3PAR_OFFSET) -#define STM32_DMA1_S4PAR (STM32_DMA1_BASE+STM32_DMA_S4PAR_OFFSET) -#define STM32_DMA1_S5PAR (STM32_DMA1_BASE+STM32_DMA_S5PAR_OFFSET) -#define STM32_DMA1_S6PAR (STM32_DMA1_BASE+STM32_DMA_S6PAR_OFFSET) -#define STM32_DMA1_S7PAR (STM32_DMA1_BASE+STM32_DMA_S7PAR_OFFSET) - -#define STM32_DMA1_SM0AR(n) (STM32_DMA1_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA1_S0M0AR (STM32_DMA1_BASE+STM32_DMA_S0M0AR_OFFSET) -#define STM32_DMA1_S1M0AR (STM32_DMA1_BASE+STM32_DMA_S1M0AR_OFFSET) -#define STM32_DMA1_S2M0AR (STM32_DMA1_BASE+STM32_DMA_S2M0AR_OFFSET) -#define STM32_DMA1_S3M0AR (STM32_DMA1_BASE+STM32_DMA_S3M0AR_OFFSET) -#define STM32_DMA1_S4M0AR (STM32_DMA1_BASE+STM32_DMA_S4M0AR_OFFSET) -#define STM32_DMA1_S5M0AR (STM32_DMA1_BASE+STM32_DMA_S5M0AR_OFFSET) -#define STM32_DMA1_S6M0AR (STM32_DMA1_BASE+STM32_DMA_S6M0AR_OFFSET) -#define STM32_DMA1_S7M0AR (STM32_DMA1_BASE+STM32_DMA_S7M0AR_OFFSET) - -#define STM32_DMA1_SM1AR(n) (STM32_DMA1_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA1_S0M1AR (STM32_DMA1_BASE+STM32_DMA_S0M1AR_OFFSET) -#define STM32_DMA1_S1M1AR (STM32_DMA1_BASE+STM32_DMA_S1M1AR_OFFSET) -#define STM32_DMA1_S2M1AR (STM32_DMA1_BASE+STM32_DMA_S2M1AR_OFFSET) -#define STM32_DMA1_S3M1AR (STM32_DMA1_BASE+STM32_DMA_S3M1AR_OFFSET) -#define STM32_DMA1_S4M1AR (STM32_DMA1_BASE+STM32_DMA_S4M1AR_OFFSET) -#define STM32_DMA1_S5M1AR (STM32_DMA1_BASE+STM32_DMA_S5M1AR_OFFSET) -#define STM32_DMA1_S6M1AR (STM32_DMA1_BASE+STM32_DMA_S6M1AR_OFFSET) -#define STM32_DMA1_S7M1AR (STM32_DMA1_BASE+STM32_DMA_S7M1AR_OFFSET) - -#define STM32_DMA1_SFCR(n) (STM32_DMA1_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA1_S0FCR (STM32_DMA1_BASE+STM32_DMA_S0FCR_OFFSET) -#define STM32_DMA1_S1FCR (STM32_DMA1_BASE+STM32_DMA_S1FCR_OFFSET) -#define STM32_DMA1_S2FCR (STM32_DMA1_BASE+STM32_DMA_S2FCR_OFFSET) -#define STM32_DMA1_S3FCR (STM32_DMA1_BASE+STM32_DMA_S3FCR_OFFSET) -#define STM32_DMA1_S4FCR (STM32_DMA1_BASE+STM32_DMA_S4FCR_OFFSET) -#define STM32_DMA1_S5FCR (STM32_DMA1_BASE+STM32_DMA_S5FCR_OFFSET) -#define STM32_DMA1_S6FCR (STM32_DMA1_BASE+STM32_DMA_S6FCR_OFFSET) -#define STM32_DMA1_S7FCR (STM32_DMA1_BASE+STM32_DMA_S7FCR_OFFSET) - -#define STM32_DMA2_LISRC (STM32_DMA2_BASE+STM32_DMA_LISR_OFFSET) -#define STM32_DMA2_HISRC (STM32_DMA2_BASE+STM32_DMA_HISR_OFFSET) -#define STM32_DMA2_LIFCR (STM32_DMA2_BASE+STM32_DMA_LIFCR_OFFSET) -#define STM32_DMA2_HIFCR (STM32_DMA2_BASE+STM32_DMA_HIFCR_OFFSET) - -#define STM32_DMA2_SCR(n) (STM32_DMA2_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA2_S0CR (STM32_DMA2_BASE+STM32_DMA_S0CR_OFFSET) -#define STM32_DMA2_S1CR (STM32_DMA2_BASE+STM32_DMA_S1CR_OFFSET) -#define STM32_DMA2_S2CR (STM32_DMA2_BASE+STM32_DMA_S2CR_OFFSET) -#define STM32_DMA2_S3CR (STM32_DMA2_BASE+STM32_DMA_S3CR_OFFSET) -#define STM32_DMA2_S4CR (STM32_DMA2_BASE+STM32_DMA_S4CR_OFFSET) -#define STM32_DMA2_S5CR (STM32_DMA2_BASE+STM32_DMA_S5CR_OFFSET) -#define STM32_DMA2_S6CR (STM32_DMA2_BASE+STM32_DMA_S6CR_OFFSET) -#define STM32_DMA2_S7CR (STM32_DMA2_BASE+STM32_DMA_S7CR_OFFSET) - -#define STM32_DMA2_SNDTR(n) (STM32_DMA2_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA2_S0NDTR (STM32_DMA2_BASE+STM32_DMA_S0NDTR_OFFSET) -#define STM32_DMA2_S1NDTR (STM32_DMA2_BASE+STM32_DMA_S1NDTR_OFFSET) -#define STM32_DMA2_S2NDTR (STM32_DMA2_BASE+STM32_DMA_S2NDTR_OFFSET) -#define STM32_DMA2_S3NDTR (STM32_DMA2_BASE+STM32_DMA_S3NDTR_OFFSET) -#define STM32_DMA2_S4NDTR (STM32_DMA2_BASE+STM32_DMA_S4NDTR_OFFSET) -#define STM32_DMA2_S5NDTR (STM32_DMA2_BASE+STM32_DMA_S5NDTR_OFFSET) -#define STM32_DMA2_S6NDTR (STM32_DMA2_BASE+STM32_DMA_S6NDTR_OFFSET) -#define STM32_DMA2_S7NDTR (STM32_DMA2_BASE+STM32_DMA_S7NDTR_OFFSET) - -#define STM32_DMA2_SPAR(n) (STM32_DMA2_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA2_S0PAR (STM32_DMA2_BASE+STM32_DMA_S0PAR_OFFSET) -#define STM32_DMA2_S1PAR (STM32_DMA2_BASE+STM32_DMA_S1PAR_OFFSET) -#define STM32_DMA2_S2PAR (STM32_DMA2_BASE+STM32_DMA_S2PAR_OFFSET) -#define STM32_DMA2_S3PAR (STM32_DMA2_BASE+STM32_DMA_S3PAR_OFFSET) -#define STM32_DMA2_S4PAR (STM32_DMA2_BASE+STM32_DMA_S4PAR_OFFSET) -#define STM32_DMA2_S5PAR (STM32_DMA2_BASE+STM32_DMA_S5PAR_OFFSET) -#define STM32_DMA2_S6PAR (STM32_DMA2_BASE+STM32_DMA_S6PAR_OFFSET) -#define STM32_DMA2_S7PAR (STM32_DMA2_BASE+STM32_DMA_S7PAR_OFFSET) - -#define STM32_DMA2_SM0AR(n) (STM32_DMA2_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA2_S0M0AR (STM32_DMA2_BASE+STM32_DMA_S0M0AR_OFFSET) -#define STM32_DMA2_S1M0AR (STM32_DMA2_BASE+STM32_DMA_S1M0AR_OFFSET) -#define STM32_DMA2_S2M0AR (STM32_DMA2_BASE+STM32_DMA_S2M0AR_OFFSET) -#define STM32_DMA2_S3M0AR (STM32_DMA2_BASE+STM32_DMA_S3M0AR_OFFSET) -#define STM32_DMA2_S4M0AR (STM32_DMA2_BASE+STM32_DMA_S4M0AR_OFFSET) -#define STM32_DMA2_S5M0AR (STM32_DMA2_BASE+STM32_DMA_S5M0AR_OFFSET) -#define STM32_DMA2_S6M0AR (STM32_DMA2_BASE+STM32_DMA_S6M0AR_OFFSET) -#define STM32_DMA2_S7M0AR (STM32_DMA2_BASE+STM32_DMA_S7M0AR_OFFSET) - -#define STM32_DMA2_SM1AR(n) (STM32_DMA2_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA2_S0M1AR (STM32_DMA2_BASE+STM32_DMA_S0M1AR_OFFSET) -#define STM32_DMA2_S1M1AR (STM32_DMA2_BASE+STM32_DMA_S1M1AR_OFFSET) -#define STM32_DMA2_S2M1AR (STM32_DMA2_BASE+STM32_DMA_S2M1AR_OFFSET) -#define STM32_DMA2_S3M1AR (STM32_DMA2_BASE+STM32_DMA_S3M1AR_OFFSET) -#define STM32_DMA2_S4M1AR (STM32_DMA2_BASE+STM32_DMA_S4M1AR_OFFSET) -#define STM32_DMA2_S5M1AR (STM32_DMA2_BASE+STM32_DMA_S5M1AR_OFFSET) -#define STM32_DMA2_S6M1AR (STM32_DMA2_BASE+STM32_DMA_S6M1AR_OFFSET) -#define STM32_DMA2_S7M1AR (STM32_DMA2_BASE+STM32_DMA_S7M1AR_OFFSET) - -#define STM32_DMA2_SFCR(n) (STM32_DMA2_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA2_S0FCR (STM32_DMA2_BASE+STM32_DMA_S0FCR_OFFSET) -#define STM32_DMA2_S1FCR (STM32_DMA2_BASE+STM32_DMA_S1FCR_OFFSET) -#define STM32_DMA2_S2FCR (STM32_DMA2_BASE+STM32_DMA_S2FCR_OFFSET) -#define STM32_DMA2_S3FCR (STM32_DMA2_BASE+STM32_DMA_S3FCR_OFFSET) -#define STM32_DMA2_S4FCR (STM32_DMA2_BASE+STM32_DMA_S4FCR_OFFSET) -#define STM32_DMA2_S5FCR (STM32_DMA2_BASE+STM32_DMA_S5FCR_OFFSET) -#define STM32_DMA2_S6FCR (STM32_DMA2_BASE+STM32_DMA_S6FCR_OFFSET) -#define STM32_DMA2_S7FCR (STM32_DMA2_BASE+STM32_DMA_S7FCR_OFFSET) - -/* Register Bitfield Definitions ****************************************************/ - -#define DMA_STREAM_MASK 0x3f -#define DMA_STREAM_FEIF_BIT (1 << 0) /* Bit 0: Stream FIFO error interrupt flag */ -#define DMA_STREAM_DMEIF_BIT (1 << 2) /* Bit 2: Stream direct mode error interrupt flag */ -#define DMA_STREAM_TEIF_BIT (1 << 3) /* Bit 3: Stream Transfer Error flag */ -#define DMA_STREAM_HTIF_BIT (1 << 4) /* Bit 4: Stream Half Transfer flag */ -#define DMA_STREAM_TCIF_BIT (1 << 5) /* Bit 5: Stream Transfer Complete flag */ - -/* DMA interrupt status register and interrupt flag clear register field defintions */ - -#define DMA_INT_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt */ -#define DMA_INT_STREAM0_MASK (DMA_STREAM_MASK << DMA_INT_STREAM0_SHIFT) -#define DMA_INT_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt */ -#define DMA_INT_STREAM1_MASK (DMA_STREAM_MASK << DMA_INT_STREAM1_SHIFT) -#define DMA_INT_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt */ -#define DMA_INT_STREAM2_MASK (DMA_STREAM_MASK << DMA_INT_STREAM2_SHIFT) -#define DMA_INT_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt */ -#define DMA_INT_STREAM3_MASK (DMA_STREAM_MASK << DMA_INT_STREAM3_SHIFT) - -#define DMA_INT_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt */ -#define DMA_INT_STREAM4_MASK (DMA_STREAM_MASK << DMA_INT_STREAM4_SHIFT) -#define DMA_INT_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt */ -#define DMA_INT_STREAM5_MASK (DMA_STREAM_MASK << DMA_INT_STREAM5_SHIFT) -#define DMA_INT_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt */ -#define DMA_INT_STREAM6_MASK (DMA_STREAM_MASK << DMA_INT_STREAM6_SHIFT) -#define DMA_INT_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt */ -#define DMA_INT_STREAM7_MASK (DMA_STREAM_MASK << DMA_INT_STREAM7_SHIFT) - -/* DMA stream configuration register */ - -#define DMA_SCR_EN (1 << 0) /* Bit 0: Stream enable */ -#define DMA_SCR_DMEIE (1 << 1) /* Bit 1: Direct mode error interrupt enable */ -#define DMA_SCR_TEIE (1 << 2) /* Bit 2: Transfer error interrupt enable */ -#define DMA_SCR_HTIE (1 << 3) /* Bit 3: Half Transfer interrupt enable */ -#define DMA_SCR_TCIE (1 << 4) /* Bit 4: Transfer complete interrupt enable */ -#define DMA_SCR_PFCTRL (1 << 5) /* Bit 5: Peripheral flow controller */ -#define DMA_SCR_DIR_SHIFT (6) /* Bits 6-7: Data transfer direction */ -#define DMA_SCR_DIR_MASK (3 << DMA_SCR_DIR_SHIFT) -# define DMA_SCR_DIR_P2M (0 << DMA_SCR_DIR_SHIFT) /* 00: Peripheral-to-memory */ -# define DMA_SCR_DIR_M2P (1 << DMA_SCR_DIR_SHIFT) /* 01: Memory-to-peripheral */ -# define DMA_SCR_DIR_M2M (2 << DMA_SCR_DIR_SHIFT) /* 10: Memory-to-memory */ -#define DMA_SCR_CIRC (1 << 8) /* Bit 8: Circular mode */ -#define DMA_SCR_PINC (1 << 9) /* Bit 9: Peripheral increment mode */ -#define DMA_SCR_MINC (1 << 10) /* Bit 10: Memory increment mode */ -#define DMA_SCR_PSIZE_SHIFT (11) /* Bits 11-12: Peripheral size */ -#define DMA_SCR_PSIZE_MASK (3 << DMA_SCR_PSIZE_SHIFT) -# define DMA_SCR_PSIZE_8BITS (0 << DMA_SCR_PSIZE_SHIFT) /* 00: 8-bits */ -# define DMA_SCR_PSIZE_16BITS (1 << DMA_SCR_PSIZE_SHIFT) /* 01: 16-bits */ -# define DMA_SCR_PSIZE_32BITS (2 << DMA_SCR_PSIZE_SHIFT) /* 10: 32-bits */ -#define DMA_SCR_MSIZE_SHIFT (13) /* Bits 13-14: Memory size */ -#define DMA_SCR_MSIZE_MASK (3 << DMA_SCR_MSIZE_SHIFT) -# define DMA_SCR_MSIZE_8BITS (0 << DMA_SCR_MSIZE_SHIFT) /* 00: 8-bits */ -# define DMA_SCR_MSIZE_16BITS (1 << DMA_SCR_MSIZE_SHIFT) /* 01: 16-bits */ -# define DMA_SCR_MSIZE_32BITS (2 << DMA_SCR_MSIZE_SHIFT) /* 10: 32-bits */ -#define DMA_SCR_PINCOS (1 << 15) /* Bit 15: Peripheral increment offset size */ -#define DMA_SCR_PL_SHIFT (16) /* Bits 16-17: Stream Priority level */ -#define DMA_SCR_PL_MASK (3 << DMA_SCR_PL_SHIFT) -# define DMA_SCR_PRILO (0 << DMA_SCR_PL_SHIFT) /* 00: Low */ -# define DMA_SCR_PRIMED (1 << DMA_SCR_PL_SHIFT) /* 01: Medium */ -# define DMA_SCR_PRIHI (2 << DMA_SCR_PL_SHIFT) /* 10: High */ -# define DMA_SCR_PRIVERYHI (3 << DMA_SCR_PL_SHIFT) /* 11: Very high */ -#define DMA_SCR_DBM (1 << 18) /* Bit 15: Double buffer mode */ -#define DMA_SCR_CT (1 << 19) /* Bit 19: Current target */ -#define DMA_SCR_PBURST_SHIFT (21) /* Bits 21-22: Peripheral burst transfer configuration */ -#define DMA_SCR_PBURST_MASK (3 << DMA_SCR_PBURST_SHIFT) -# define DMA_SCR_PBURST_SINGLE (0 << DMA_SCR_PBURST_SHIFT) /* 00: Single transfer */ -# define DMA_SCR_PBURST_INCR4 (1 << DMA_SCR_PBURST_SHIFT) /* 01: Incremental burst of 4 beats */ -# define DMA_SCR_PBURST_INCR8 (2 << DMA_SCR_PBURST_SHIFT) /* 10: Incremental burst of 8 beats */ -# define DMA_SCR_PBURST_INCR16 (3 << DMA_SCR_PBURST_SHIFT) /* 11: Incremental burst of 16 beats */ -#define DMA_SCR_MBURST_SHIFT (23) /* Bits 23-24: Memory burst transfer configuration */ -#define DMA_SCR_MBURST_MASK (3 << DMA_SCR_MBURST_SHIFT) -# define DMA_SCR_MBURST_SINGLE (0 << DMA_SCR_MBURST_SHIFT) /* 00: Single transfer */ -# define DMA_SCR_MBURST_INCR4 (1 << DMA_SCR_MBURST_SHIFT) /* 01: Incremental burst of 4 beats */ -# define DMA_SCR_MBURST_INCR8 (2 << DMA_SCR_MBURST_SHIFT) /* 10: Incremental burst of 8 beats */ -# define DMA_SCR_MBURST_INCR16 (3 << DMA_SCR_MBURST_SHIFT) /* 11: Incremental burst of 16 beats */ -#define DMA_SCR_CHSEL_SHIFT (25) /* Bits 25-27: Channel selection */ -#define DMA_SCR_CHSEL_MASK (7 << DMA_SCR_CHSEL_SHIFT) -# define DMA_SCR_CHSEL(n) ((n) << DMA_SCR_CHSEL_SHIFT) - -#define DMA_SCR_ALLINTS (DMA_SCR_DMEIE|DMA_SCR_TEIE|DMA_SCR_HTIE|DMA_SCR_TCIE) - -/* DMA stream number of data register */ - -#define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ -#define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT) - -/* DMA stream n FIFO control register */ - -#define DMA_SFCR_FTH_SHIFT (0) /* Bits 0-1: FIFO threshold selection */ -#define DMA_SFCR_FTH_MASK (3 << DMA_SFCR_FTH_SHIFT) -# define DMA_SFCR_FTH_QUARTER (0 << DMA_SFCR_FTH_SHIFT) /* 1/4 full FIFO */ -# define DMA_SFCR_FTH_HALF (1 << DMA_SFCR_FTH_SHIFT) /* 1/2 full FIFO */ -# define DMA_SFCR_FTH_3QUARTER (2 << DMA_SFCR_FTH_SHIFT) /* 3/4 full FIFO */ -# define DMA_SFCR_FTH_FULL (3 << DMA_SFCR_FTH_SHIFT) /* full FIFO */ -#define DMA_SFCR_DMDIS (1 << 2) /* Bit 2: Direct mode disable */ -#define DMA_SFCR_FS_SHIFT (3) /* Bits 3-5: FIFO status */ -#define DMA_SFCR_FS_MASK (7 << DMA_SFCR_FS_SHIFT) -# define DMA_SFCR_FS_QUARTER (0 << DMA_SFCR_FS_SHIFT) /* 0 < fifo_level < 1/4 */ -# define DMA_SFCR_FS_HALF (1 << DMA_SFCR_FS_SHIFT) /* 1/4 = fifo_level < 1/2 */ -# define DMA_SFCR_FS_3QUARTER (2 << DMA_SFCR_FS_SHIFT) /* 1/2 = fifo_level < 3/4 */ -# define DMA_SFCR_FS_ALMOSTFULL (3 << DMA_SFCR_FS_SHIFT) /* 3/4 = fifo_level < full */ -# define DMA_SFCR_FS_EMPTY (4 << DMA_SFCR_FS_SHIFT) /* FIFO is empty */ -# define DMA_SFCR_FS_FULL (5 << DMA_SFCR_FS_SHIFT) /* FIFO is full */ - /* Bit 6: Reserved */ -#define DMA_SFCR_FEIE (1 << 7) /* Bit 7: FIFO error interrupt enable */ - /* Bits 8-31: Reserved */ - -/* DMA Stream mapping. Each DMA stream has a mapping to several possible - * sources/sinks of data. The requests from peripherals assigned to a stream - * are simply OR'ed together before entering the DMA block. This means that only - * one request on a given stream can be enabled at once. - * - * Alternative stream selections are provided with a numeric suffix like _1, _2, etc. - * The DMA driver, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if - * SPI3_RX connects via DMA STREAM0, then following should be application-specific - * mapping should be used: - * - * #define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1 - */ - -#define STM32_DMA_MAP(d,s,c) ((d) << 6 | (s) << 3 | (c)) -#define STM32_DMA_CONTROLLER(m) (((m) >> 6) & 1) -#define STM32_DMA_STREAM(m) (((m) >> 3) & 7) -#define STM32_DMA_CHANNEL(m) ((m) & 7) - -#define DMAMAP_SPI3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN0) -#define DMAMAP_SPI3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN0) -#define DMAMAP_SPI2_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN0) -#define DMAMAP_SPI2_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN0) -#define DMAMAP_SPI3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN0) -#define DMAMAP_SPI3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN0) - -#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1) -#define DMAMAP_TIM7_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN1) -#define DMAMAP_TIM7_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN1) -#define DMAMAP_I2C1_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1) -#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1) -#define DMAMAP_I2C1_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1) - -#define DMAMAP_TIM4_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN2) -#define DMAMAP_I2S2_EXT_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN2) -#define DMAMAP_TIM4_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN2) -#define DMAMAP_I2S2_EXT_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN2) -#define DMAMAP_I2S3_EXT_TX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN2) -#define DMAMAP_TIM4_UP STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN2) -#define DMAMAP_TIM4_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN2) - -#define DMAMAP_I2S3_EXT_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN3) -#define DMAMAP_TIM2_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3) -#define DMAMAP_TIM2_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) -#define DMAMAP_I2C3_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) -#define DMAMAP_I2S2_EXT_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN3) -#define DMAMAP_I2C3_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN3) -#define DMAMAP_TIM2_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN3) -#define DMAMAP_TIM2_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) -#define DMAMAP_TIM2_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) -#define DMAMAP_TIM2_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3) -#define DMAMAP_TIM2_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3) - -#define DMAMAP_UART5_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN4) -#define DMAMAP_USART3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN4) -#define DMAMAP_UART4_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN4) -#define DMAMAP_USART3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN4) -#define DMAMAP_UART4_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN4) -#define DMAMAP_USART2_RX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN4) -#define DMAMAP_USART2_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN4) -#define DMAMAP_UART5_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN4) - -#define DMAMAP_TIM3_CH4 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5) -#define DMAMAP_TIM3_UP STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5) -#define DMAMAP_TIM3_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5) -#define DMAMAP_TIM3_TRIG STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5) -#define DMAMAP_TIM3_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN5) -#define DMAMAP_TIM3_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN5) - -#define DMAMAP_TIM5_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6) -#define DMAMAP_TIM5_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6) -#define DMAMAP_TIM5_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6) -#define DMAMAP_TIM5_TRIG_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6) -#define DMAMAP_TIM5_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN6) -#define DMAMAP_TIM5_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6) -#define DMAMAP_TIM5_TRIG_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6) -#define DMAMAP_TIM5_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN6) -#define DMAMAP_TIM5_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN6) - -#define DMAMAP_TIM6_UP STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN7) -#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7) -#define DMAMAP_I2C2_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7) -#define DMAMAP_USART3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN7) -#define DMAMAP_DAC1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN7) -#define DMAMAP_DAC2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN7) -#define DMAMAP_I2C2_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN7) - -#define DMAMAP_ADC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN0) -#define DMAMAP_TIM8_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) -#define DMAMAP_TIM8_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) -#define DMAMAP_TIM8_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) -#define DMAMAP_ADC1_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN0) -#define DMAMAP_TIM1_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) -#define DMAMAP_TIM1_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) -#define DMAMAP_TIM1_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) - -#define DMAMAP_DCMI_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN1) -#define DMAMAP_ADC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN1) -#define DMAMAP_ADC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN1) -#define DMAMAP_DCMI_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN1) - -#define DMAMAP_ADC3_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN2) -#define DMAMAP_ADC3_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN2) -#define DMAMAP_CRYP_OUT STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN2) -#define DMAMAP_CRYP_IN STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN2) -#define DMAMAP_HASH_IN STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN2) - -#define DMAMAP_SPI1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN3) -#define DMAMAP_SPI1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN3) -#define DMAMAP_SPI1_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN3) -#define DMAMAP_SPI1_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN3) - -#define DMAMAP_USART1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN4) -#define DMAMAP_SDIO_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN4) -#define DMAMAP_USART1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN4) -#define DMAMAP_SDIO_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN4) -#define DMAMAP_USART1_TX STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN4) - -#define DMAMAP_USART6_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN5) -#define DMAMAP_USART6_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN5) -#define DMAMAP_USART6_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN5) -#define DMAMAP_USART6_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN5) - -#define DMAMAP_TIM1_TRIG_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN6) -#define DMAMAP_TIM1_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN6) -#define DMAMAP_TIM1_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN6) -#define DMAMAP_TIM1_CH1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN6) -#define DMAMAP_TIM1_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) -#define DMAMAP_TIM1_TRIG_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) -#define DMAMAP_TIM1_COM STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) -#define DMAMAP_TIM1_UP STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN6) -#define DMAMAP_TIM1_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN6) - -#define DMAMAP_TIM8_UP STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN7) -#define DMAMAP_TIM8_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN7) -#define DMAMAP_TIM8_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN7) -#define DMAMAP_TIM8_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN7) -#define DMAMAP_TIM8_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) -#define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) -#define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) - -#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_DMA_H */ diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_dma.h b/arch/arm/src/stm32/chip/stm32f33xxx_dma.h deleted file mode 100644 index 2642cf6772..0000000000 --- a/arch/arm/src/stm32/chip/stm32f33xxx_dma.h +++ /dev/null @@ -1,366 +0,0 @@ -/************************************************************************************ - * arch/arm/src/stm32/chip/stm32f33xxx_dma.h - * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Mateusz Szafoni - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H -#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */ - -#define DMA1 0 -#define DMA2 1 -#define DMA3 2 -#define DMA4 3 -#define DMA5 4 -#define DMA6 5 -#define DMA7 6 - -/* Register Offsets *****************************************************************/ - -#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32_DMACHAN1_OFFSET 0x0000 -#define STM32_DMACHAN2_OFFSET 0x0014 -#define STM32_DMACHAN3_OFFSET 0x0028 -#define STM32_DMACHAN4_OFFSET 0x003c -#define STM32_DMACHAN5_OFFSET 0x0050 -#define STM32_DMACHAN6_OFFSET 0x0064 -#define STM32_DMACHAN7_OFFSET 0x0078 - -#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel 1 memory address register */ - -#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) -#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) -#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) -#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) - -#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ - -/* Register Addresses ***************************************************************/ - -#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) -#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) - -#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) -#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) -#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) -#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) -#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) -#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) -#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) -#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) - -#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) -#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) -#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) -#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) -#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) -#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) -#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) -#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) - -#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) -#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) -#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) -#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) -#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) -#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) -#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) -#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) - -#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) -#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) -#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) -#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) -#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) -#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) -#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) -#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) - -#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) -#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) - -#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) -#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) -#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) -#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) -#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) -#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) - -#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) -#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) -#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) -#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) -#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) -#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) - -#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) -#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) -#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) -#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) -#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) -#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) - -#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) -#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) -#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) -#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) -#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) -#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) - -/* Register Bitfield Definitions ****************************************************/ - -#define DMA_CHAN_SHIFT(n) ((n) << 2) -#define DMA_CHAN_MASK 0x0f -#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */ -#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */ -#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */ -#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */ - -/* DMA interrupt status register */ - -#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) -#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */ -#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT) -#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */ -#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT) -#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */ -#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT) -#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */ -#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT) -#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */ -#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT) -#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */ -#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT) -#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */ -#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT) - -#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n)) - -/* DMA interrupt flag clear register */ - -#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) -#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */ -#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT) -#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */ -#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT) -#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */ -#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT) -#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */ -#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT) -#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */ -#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT) -#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */ -#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT) -#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */ -#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT) -#define DMA_IFCR_ALLCHANNELS (0x0fffffff) - -#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) - -/* DMA channel configuration register */ - -#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */ -#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */ -#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */ -#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */ -#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */ -#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */ -#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */ -#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */ -#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */ -#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT) -# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */ -# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */ -# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */ -#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */ -#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT) -# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */ -# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */ -# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */ -#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */ -#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT) -# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */ -# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */ -# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */ -# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */ -#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */ - -#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE) - -/* DMA channel number of data register */ - -#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ -#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT) - -/* DMA Channel mapping. Each DMA channel has a mapping to several possible - * sources/sinks of data. The requests from peripherals assigned to a channel - * are simply OR'ed together before entering the DMA block. This means that only - * one request on a given channel can be enabled at once. - * - * Alternative DMA channel selections are provided with a numeric suffix like _1, - * _2, etc. Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. - */ - -#define STM32_DMA1_CHAN1 (0) -#define STM32_DMA1_CHAN2 (1) -#define STM32_DMA1_CHAN3 (2) -#define STM32_DMA1_CHAN4 (3) -#define STM32_DMA1_CHAN5 (4) -#define STM32_DMA1_CHAN6 (5) -#define STM32_DMA1_CHAN7 (6) - -#define STM32_DMA2_CHAN1 (7) -#define STM32_DMA2_CHAN2 (8) -#define STM32_DMA2_CHAN3 (9) -#define STM32_DMA2_CHAN4 (10) -#define STM32_DMA2_CHAN5 (11) - -#define DMACHAN_ADC1 STM32_DMA1_CHAN1 -#define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 -#define DMACHAN_TIM17_CH1_1 STM32_DMA1_CHAN1 -#define DMACHAN_TIM17_UP_1 STM32_DMA1_CHAN1 - -#define DMACHAN_ADC2_1 STM32_DMA1_CHAN2 -#define DMACHAN_SPI1_RX_1 STM32_DMA1_CHAN2 -#define DMACHAN_USART3_TX STM32_DMA1_CHAN2 -#define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4 -#define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2 -#define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 -#define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 -#define DMACHAN_HRTIM1_M STM32_DMA1_CHAN2 - -#define DMACHAN_SPI1_TX_1 STM32_DMA1_CHAN3 -#define DMACHAN_USART3_RX STM32_DMA1_CHAN3 -#define DMACHAN_I2C1_RX_2 STM32_DMA1_CHAN3 -#define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 -#define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 -#define DMACHAN_TIM6_UP STM32_DMA1_CHAN3 -#define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3 -#define DMACHAN_TIM16_CH1_1 STM32_DMA1_CHAN3 -#define DMACHAN_TIM16_UP_1 STM32_DMA1_CHAN3 -#define DMACHAN_HRTIM1_A STM32_DMA1_CHAN3 - -#define DMACHAN_ADC2_2 STM32_DMA1_CHAN4 -#define DMACHAN_SPI1_RX_2 STM32_DMA1_CHAN4 -#define DMACHAN_USART1_TX STM32_DMA1_CHAN4 -#define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4 -#define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4 -#define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4 -#define DMACHAN_TIM1_COM STM32_DMA1_CHAN4 -#define DMACHAN_TIM7_UP STM32_DMA1_CHAN4 -#define DMACHAN_DAC1_CH2 STM32_DMA1_CHAN4 -#define DMACHAN_HRTIM1_B STM32_DMA1_CHAN4 - -#define DMACHAN_SPI1_TX_2 STM32_DMA1_CHAN5 -#define DMACHAN_USART1_RX STM32_DMA1_CHAN5 -#define DMACHAN_I2C1_RX_3 STM32_DMA1_CHAN5 -#define DMACHAN_TIM1_UP STM32_DMA1_CHAN5 -#define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 -#define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5 -#define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5 -#define DMACHAN_TIM15_UP STM32_DMA1_CHAN5 -#define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5 -#define DMACHAN_TIM15_COM STM32_DMA1_CHAN5 -#define DMACHAN_HRTIM1_C STM32_DMA1_CHAN5 - -#define DMACHAN_SPI1_RX_3 STM32_DMA1_CHAN6 -#define DMACHAN_USART2_RX STM32_DMA1_CHAN6 -#define DMACHAN_I2C1_TX_1 STM32_DMA1_CHAN6 -#define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6 -#define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 -#define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 -#define DMACHAN_TIM16_CH1_2 STM32_DMA1_CHAN6 -#define DMACHAN_TIM16_UP_2 STM32_DMA1_CHAN6 -#define DMACHAN_HRTIM1_D STM32_DMA1_CHAN6 - -#define DMACHAN_SPI1_TX_3 STM32_DMA1_CHAN7 -#define DMACHAN_USART2_TX STM32_DMA1_CHAN7 -#define DMACHAN_I2C1_RX_1 STM32_DMA1_CHAN7 -#define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7 -#define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7 -#define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN7 -#define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN7 -#define DMACHAN_HRTIM1_E STM32_DMA1_CHAN7 - -#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H */ diff --git a/arch/arm/src/stm32/stm32_dma.c b/arch/arm/src/stm32/stm32_dma.c index 6c0028aed7..a267c650aa 100644 --- a/arch/arm/src/stm32/stm32_dma.c +++ b/arch/arm/src/stm32/stm32_dma.c @@ -46,25 +46,17 @@ ****************************************************************************/ /* This file is only a thin shell that includes the correct DMA implementation - * for the selected STM32 family. The correct file cannot be selected by - * the make system because it needs the intelligence that only exists in - * chip.h that can associate an STM32 part number with an STM32 family. + * for the selected STM32 IP core: + * - STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4 + * - STM32 DMA IP version 2 - F2, F4, F7, H7 * - * The STM32 F4 DMA differs from the F1 DMA primarily in that it adds the - * concept of "streams" that are used to associate DMA sources with DMA - * channels. - * - * TODO: use STM32 DMA IP version instead of chip faimily: - * - STM32 DMA IP core version 1 - F0, F1, F3, L1 - * - STM32 DMA IP core version 2 - F2, F4, F7, H7 + * The STM32 DMA IPv2 differs from the STM32 DMA IPv1 primarily in that it + * adds the concept of "streams" that are used to associate DMA sources with + * DMA channels. */ -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# include "stm32f10xxx_dma.c" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "stm32f20xxx_dma.c" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "stm32f40xxx_dma.c" +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) +# include "stm32_dma_v1.c" +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# include "stm32_dma_v2.c" #endif diff --git a/arch/arm/src/stm32/stm32_dma.h b/arch/arm/src/stm32/stm32_dma.h index 3dcf762089..5d0aae27e2 100644 --- a/arch/arm/src/stm32/stm32_dma.h +++ b/arch/arm/src/stm32/stm32_dma.h @@ -45,54 +45,19 @@ #include "chip.h" -/* Include the correct DMA register definitions for this STM32 family */ - -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) -# include "chip/stm32f10xxx_dma.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "chip/stm32f33xxx_dma.h" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "chip/stm32f20xxx_dma.h" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "chip/stm32f40xxx_dma.h" -#else -# error "Unknown STM32 DMA" -#endif - -/* Support for STM32 DMA IP version 1 - F0, F1, F3, L0, L1 - * REVISIT: move this to Kconfig - */ - -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# define HAVE_IP_DMA_V1 -#endif - -/* Support for STM32 DMA IP version 2 - F2, F4, F7, H7 */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define HAVE_IP_DMA_V2 -#endif - -#if !defined(HAVE_IP_DMA_V1) && !defined(HAVE_IP_DMA_V2) -# error Unknown STM32 DMA IP version -#endif +#include "chip/stm32_dma.h" /* These definitions provide the bit encoding of the 'status' parameter passed to the * DMA callback function (see dma_callback_t). */ -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) +#if defined(HAVE_IP_DMA_V1) # define DMA_STATUS_FEIF 0 /* (Not available in F1) */ # define DMA_STATUS_DMEIF 0 /* (Not available in F1) */ # define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */ # define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */ # define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(HAVE_IP_DMA_V2) # define DMA_STATUS_FEIF 0 /* Stream FIFO error (ignored) */ # define DMA_STATUS_DMEIF DMA_STREAM_DMEIF_BIT /* Stream direct mode error */ # define DMA_STATUS_TEIF DMA_STREAM_TEIF_BIT /* Stream Transfer Error */ @@ -128,9 +93,8 @@ typedef FAR void *DMA_HANDLE; typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); #ifdef CONFIG_DEBUG_DMA_INFO -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) + +#if defined(HAVE_IP_DMA_V1) struct stm32_dmaregs_s { uint32_t isr; @@ -139,7 +103,7 @@ struct stm32_dmaregs_s uint32_t cpar; uint32_t cmar; }; -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(HAVE_IP_DMA_V2) struct stm32_dmaregs_s { uint32_t lisr; diff --git a/arch/arm/src/stm32/stm32f10xxx_dma.c b/arch/arm/src/stm32/stm32_dma_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32f10xxx_dma.c rename to arch/arm/src/stm32/stm32_dma_v1.c index f3972b3dc5..9010523406 100644 --- a/arch/arm/src/stm32/stm32f10xxx_dma.c +++ b/arch/arm/src/stm32/stm32_dma_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f10xxx_dma.c + * arch/arm/src/stm32/stm32_dma_v1.c * * Copyright (C) 2009, 2011-2013, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -55,9 +55,7 @@ #include "stm32_dma.h" #include "stm32.h" -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32L15XX) +/* This file supports the STM32 DMA IP core version 1 - F0, F1, F3, L1, L4 */ /**************************************************************************** * Pre-processor Definitions @@ -787,5 +785,3 @@ uint32_t stm32_dma_intget(unsigned int chndx) return dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan); } #endif /* CONFIG_ARCH_HIPRI_INTERRUPT */ - -#endif /* CONFIG_STM32_STM32F10XX */ diff --git a/arch/arm/src/stm32/stm32f40xxx_dma.c b/arch/arm/src/stm32/stm32_dma_v2.c similarity index 99% rename from arch/arm/src/stm32/stm32f40xxx_dma.c rename to arch/arm/src/stm32/stm32_dma_v2.c index 41fc843589..0a68b474f7 100644 --- a/arch/arm/src/stm32/stm32f40xxx_dma.c +++ b/arch/arm/src/stm32/stm32_dma_v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_dma.c + * arch/arm/src/stm32/stm32_dma_v2.c * * Copyright (C) 2011-2013, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -55,12 +55,11 @@ #include "stm32_dma.h" #include "stm32.h" -/* This file supports only the STM32 F4 family (an probably the F2 family - * as well?) +/* This file supports the STM32 DMA IP core version 2 - F2, F4, F7, H7 + * NOTE: F7 and H7 need support for DCACHE which is not implemented here + * but otherwise DMA IP cores look the same. */ -#if defined(CONFIG_STM32_STM32F4XXX) - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -1131,5 +1130,3 @@ uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream) return (uint8_t)regval; } #endif /* CONFIG_ARCH_HIPRI_INTERRUPT */ - -#endif /* CONFIG_STM32_STM32F4XXX */ diff --git a/arch/arm/src/stm32/stm32f20xxx_dma.c b/arch/arm/src/stm32/stm32f20xxx_dma.c deleted file mode 100644 index 38dc97858e..0000000000 --- a/arch/arm/src/stm32/stm32f20xxx_dma.c +++ /dev/null @@ -1,1032 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32f20xxx_dma.c - * - * Copyright (C) 2012-2013, 2016-2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "up_arch.h" -#include "up_internal.h" -#include "sched/sched.h" -#include "chip.h" -#include "stm32_dma.h" -#include "stm32.h" - -/* This file supports only the STM32 F2 family (although it is identical to - * the corresponding F4 file). - * - * TODO: merge this with stm32f40xxx_dma.c (STM32 DMA IP core version 2) - */ - -#if defined(CONFIG_STM32_STM32F20XX) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define DMA1_NSTREAMS 8 -#if STM32_NDMA > 1 -# define DMA2_NSTREAMS 8 -# define DMA_NSTREAMS (DMA1_NSTREAMS+DMA2_NSTREAMS) -#else -# define DMA_NSTREAMS DMA1_NSTREAMS -#endif - -#ifndef CONFIG_DMA_PRI -# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT -#endif - -/* Convert the DMA stream base address to the DMA register block address */ - -#define DMA_BASE(ch) (ch & 0xfffffc00) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure descibes one DMA channel */ - -struct stm32_dma_s -{ - uint8_t stream; /* DMA stream number (0-7) */ - uint8_t irq; /* DMA stream IRQ number */ - uint8_t shift; /* ISR/IFCR bit shift value */ - uint8_t channel; /* DMA channel number (0-7) */ - bool nonstop; /* Stream is configured in a non-stopping mode. */ - sem_t sem; /* Used to wait for DMA channel to become available */ - uint32_t base; /* DMA register channel base address */ - dma_callback_t callback; /* Callback invoked when the DMA completes */ - void *arg; /* Argument passed to callback function */ -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array describes the state of each DMA */ - -static struct stm32_dma_s g_dma[DMA_NSTREAMS] = -{ - { - .stream = 0, - .irq = STM32_IRQ_DMA1S0, - .shift = DMA_INT_STREAM0_SHIFT, - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(0), - }, - { - .stream = 1, - .irq = STM32_IRQ_DMA1S1, - .shift = DMA_INT_STREAM1_SHIFT, - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(1), - }, - { - .stream = 2, - .irq = STM32_IRQ_DMA1S2, - .shift = DMA_INT_STREAM2_SHIFT, - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(2), - }, - { - .stream = 3, - .irq = STM32_IRQ_DMA1S3, - .shift = DMA_INT_STREAM3_SHIFT, - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(3), - }, - { - .stream = 4, - .irq = STM32_IRQ_DMA1S4, - .shift = DMA_INT_STREAM4_SHIFT, - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(4), - }, - { - .stream = 5, - .irq = STM32_IRQ_DMA1S5, - .shift = DMA_INT_STREAM5_SHIFT, - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(5), - }, - { - .stream = 6, - .irq = STM32_IRQ_DMA1S6, - .shift = DMA_INT_STREAM6_SHIFT, - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(6), - }, - { - .stream = 7, - .irq = STM32_IRQ_DMA1S7, - .shift = DMA_INT_STREAM7_SHIFT, - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(7), - }, -#if STM32_NDMA > 1 - { - .stream = 0, - .irq = STM32_IRQ_DMA2S0, - .shift = DMA_INT_STREAM0_SHIFT, - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(0), - }, - { - .stream = 1, - .irq = STM32_IRQ_DMA2S1, - .shift = DMA_INT_STREAM1_SHIFT, - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(1), - }, - { - .stream = 2, - .irq = STM32_IRQ_DMA2S2, - .shift = DMA_INT_STREAM2_SHIFT, - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(2), - }, - { - .stream = 3, - .irq = STM32_IRQ_DMA2S3, - .shift = DMA_INT_STREAM3_SHIFT, - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(3), - }, - { - .stream = 4, - .irq = STM32_IRQ_DMA2S4, - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(4), - }, - { - .stream = 5, - .irq = STM32_IRQ_DMA2S5, - .shift = DMA_INT_STREAM5_SHIFT, - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(5), - }, - { - .stream = 6, - .irq = STM32_IRQ_DMA2S6, - .shift = DMA_INT_STREAM6_SHIFT, - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(6), - }, - { - .stream = 7, - .irq = STM32_IRQ_DMA2S7, - .shift = DMA_INT_STREAM7_SHIFT, - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(7), - }, -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * DMA register access functions - ****************************************************************************/ - -/* Get non-channel register from DMA1 or DMA2 */ - -static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmast, uint32_t offset) -{ - return getreg32(DMA_BASE(dmast->base) + offset); -} - -/* Write to non-channel register in DMA1 or DMA2 */ - -static inline void dmabase_putreg(struct stm32_dma_s *dmast, uint32_t offset, uint32_t value) -{ - putreg32(value, DMA_BASE(dmast->base) + offset); -} - -/* Get channel register from DMA1 or DMA2 */ - -static inline uint32_t dmast_getreg(struct stm32_dma_s *dmast, uint32_t offset) -{ - return getreg32(dmast->base + offset); -} - -/* Write to channel register in DMA1 or DMA2 */ - -static inline void dmast_putreg(struct stm32_dma_s *dmast, uint32_t offset, uint32_t value) -{ - putreg32(value, dmast->base + offset); -} - -/************************************************************************************ - * Name: stm32_dmatake() and stm32_dmagive() - * - * Description: - * Used to get exclusive access to a DMA channel. - * - ************************************************************************************/ - -static void stm32_dmatake(FAR struct stm32_dma_s *dmast) -{ - int ret; - - do - { - /* Take the semaphore (perhaps waiting) */ - - ret = nxsem_wait(&dmast->sem); - - /* The only case that an error should occur here is if the wait was - * awakened by a signal. - */ - - DEBUGASSERT(ret == OK || ret == -EINTR); - } - while (ret == -EINTR); -} - -static inline void stm32_dmagive(FAR struct stm32_dma_s *dmast) -{ - (void)nxsem_post(&dmast->sem); -} - -/************************************************************************************ - * Name: stm32_dmastream - * - * Description: - * Get the g_dma table entry associated with a DMA controller and a stream number - * - ************************************************************************************/ - -static inline FAR struct stm32_dma_s *stm32_dmastream(unsigned int stream, - unsigned int controller) -{ - int index; - - DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32_NDMA); - - /* Convert the controller + stream based on the fact that there are 8 streams - * per controller. - */ - -#if STM32_NDMA > 1 - index = controller << 3 | stream; -#else - index = stream; -#endif - - /* Then return the stream structure associated with the stream index */ - - return &g_dma[index]; -} - -/************************************************************************************ - * Name: stm32_dmamap - * - * Description: - * Get the g_dma table entry associated with a bit-encoded DMA selection - * - ************************************************************************************/ - -static inline FAR struct stm32_dma_s *stm32_dmamap(unsigned long dmamap) -{ - /* Extract the DMA controller number from the bit encoded value */ - - unsigned int controller = STM32_DMA_CONTROLLER(dmamap); - - /* Extact the stream number from the bit encoded value */ - - unsigned int stream = STM32_DMA_STREAM(dmamap); - - /* Return the table entry associated with the controller + stream */ - - return stm32_dmastream(stream, controller); -} - -/************************************************************************************ - * Name: stm32_dmastreamdisable - * - * Description: - * Disable the DMA stream - * - ************************************************************************************/ - -static void stm32_dmastreamdisable(struct stm32_dma_s *dmast) -{ - uint32_t regoffset; - uint32_t regval; - - /* Disable all interrupts at the DMA controller */ - - regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); - regval &= ~DMA_SCR_ALLINTS; - - /* Disable the DMA stream */ - - regval &= ~DMA_SCR_EN; - dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval); - - /* Clear pending stream interrupts by setting bits in the upper or lower IFCR - * register - */ - - if (dmast->stream < 4) - { - regoffset = STM32_DMA_LIFCR_OFFSET; - } - else - { - regoffset = STM32_DMA_HIFCR_OFFSET; - } - - dmabase_putreg(dmast, regoffset, (DMA_STREAM_MASK << dmast->shift)); -} - -/************************************************************************************ - * Name: stm32_dmainterrupt - * - * Description: - * DMA interrupt handler - * - ************************************************************************************/ - -static int stm32_dmainterrupt(int irq, void *context, FAR void *arg) -{ - struct stm32_dma_s *dmast; - uint32_t status; - uint32_t regoffset = 0; - unsigned int stream = 0; - unsigned int controller = 0; - - /* Get the stream and the controller that generated the interrupt */ - - if (irq >= STM32_IRQ_DMA1S0 && irq <= STM32_IRQ_DMA1S6) - { - stream = irq - STM32_IRQ_DMA1S0; - controller = DMA1; - } - else if (irq == STM32_IRQ_DMA1S7) - { - stream = 7; - controller = DMA1; - } - else -#if STM32_NDMA > 1 - if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4) - { - stream = irq - STM32_IRQ_DMA2S0; - controller = DMA2; - } - else if (irq >= STM32_IRQ_DMA2S5 && irq <= STM32_IRQ_DMA2S7) - { - stream = irq - STM32_IRQ_DMA2S5 + 5; - controller = DMA2; - } - else -#endif - { - DEBUGPANIC(); - } - - /* Get the stream structure from the stream and controller numbers */ - - dmast = stm32_dmastream(stream, controller); - - /* Select the interrupt status register (either the LISR or HISR) - * based on the stream number that caused the interrupt. - */ - - if (stream < 4) - { - regoffset = STM32_DMA_LISR_OFFSET; - } - else - { - regoffset = STM32_DMA_HISR_OFFSET; - } - - /* Get the interrupt status for this stream */ - - status = (dmabase_getreg(dmast, regoffset) >> dmast->shift) & DMA_STREAM_MASK; - - /* Clear fetched stream interrupts by setting bits in the upper or lower IFCR - * register - */ - - if (stream < 4) - { - regoffset = STM32_DMA_LIFCR_OFFSET; - } - else - { - regoffset = STM32_DMA_HIFCR_OFFSET; - } - - dmabase_putreg(dmast, regoffset, (status << dmast->shift)); - - /* Invoke the callback */ - - if (dmast->callback) - { - dmast->callback(dmast, status, dmast->arg); - } - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dmainitialize - * - * Description: - * Initialize the DMA subsystem - * - * Returned Value: - * None - * - ****************************************************************************/ - -void weak_function up_dma_initialize(void) -{ - struct stm32_dma_s *dmast; - int stream; - - /* Initialize each DMA stream */ - - for (stream = 0; stream < DMA_NSTREAMS; stream++) - { - dmast = &g_dma[stream]; - nxsem_init(&dmast->sem, 0, 1); - - /* Attach DMA interrupt vectors */ - - (void)irq_attach(dmast->irq, stm32_dmainterrupt, dmast); - - /* Disable the DMA stream */ - - stm32_dmastreamdisable(dmast); - - /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ - - up_enable_irq(dmast->irq); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(dmast->irq, CONFIG_DMA_PRI); -#endif - } -} - -/**************************************************************************** - * Name: stm32_dmachannel - * - * Description: - * Allocate a DMA channel. This function gives the caller mutually - * exclusive access to the DMA channel specified by the 'dmamap' argument. - * DMA channels are shared on the STM32: Devices sharing the same DMA - * channel cannot do DMA concurrently! See the DMACHAN_* definitions in - * stm32_dma.h. - * - * If the DMA channel is not available, then stm32_dmachannel() will wait - * until the holder of the channel relinquishes the channel by calling - * stm32_dmafree(). WARNING: If you have two devices sharing a DMA - * channel and the code never releases the channel, the stm32_dmachannel - * call for the other will hang forever in this function! Don't let your - * design do that! - * - * Hmm.. I suppose this interface could be extended to make a non-blocking - * version. Feel free to do that if that is what you need. - * - * Input Parameters: - * dmamap - Identifies the stream/channel resource. For the STM32 F2, this - * is a bit-encoded value as provided by the DMAMAP_* definitions - * in chip/stm32f20xxx_dma.h - * - * Returned Value: - * Provided that 'dmamap' is valid, this function ALWAYS returns a non-NULL, - * void* DMA channel handle. (If 'dmamap' is invalid, the function will - * assert if debug is enabled or do something ignorant otherwise). - * - * Assumptions: - * - The caller does not hold he DMA channel. - * - The caller can wait for the DMA channel to be freed if it is no - * available. - * - ****************************************************************************/ - -DMA_HANDLE stm32_dmachannel(unsigned int dmamap) -{ - FAR struct stm32_dma_s *dmast; - - /* Get the stream index from the bit-encoded channel value */ - - dmast = stm32_dmamap(dmamap); - DEBUGASSERT(dmast != NULL); - - /* Get exclusive access to the DMA channel -- OR wait until the channel - * is available if it is currently being used by another driver - */ - - stm32_dmatake(dmast); - - /* The caller now has exclusive use of the DMA channel. Assign the - * channel to the stream and return an opaque reference to the stream - * structure. - */ - - dmast->channel = STM32_DMA_CHANNEL(dmamap); - return (DMA_HANDLE)dmast; -} - -/**************************************************************************** - * Name: stm32_dmafree - * - * Description: - * Release a DMA channel. If another thread is waiting for this DMA channel - * in a call to stm32_dmachannel, then this function will re-assign the - * DMA channel to that thread and wake it up. NOTE: The 'handle' used - * in this argument must NEVER be used again until stm32_dmachannel() is - * called again to re-gain access to the channel. - * - * Returned Value: - * None - * - * Assumptions: - * - The caller holds the DMA channel. - * - There is no DMA in progress - * - ****************************************************************************/ - -void stm32_dmafree(DMA_HANDLE handle) -{ - struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; - - DEBUGASSERT(handle != NULL); - - /* Release the channel */ - - stm32_dmagive(dmast); -} - -/**************************************************************************** - * Name: stm32_dmasetup - * - * Description: - * Configure DMA before using - * - ****************************************************************************/ - -void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t scr) -{ - struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; - uint32_t regoffset; - uint32_t regval; - - dmainfo("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n", - paddr, maddr, ntransfers, scr); - - /* "If the stream is enabled, disable it by resetting the EN bit in the - * DMA_SxCR register, then read this bit in order to confirm that there is no - * ongoing stream operation. Writing this bit to 0 is not immediately - * effective since it is actually written to 0 once all the current transfers - * have finished. When the EN bit is read as 0, this means that the stream is - * ready to be configured. It is therefore necessary to wait for the EN bit - * to be cleared before starting any stream configuration. ..." - */ - - while ((dmast_getreg(dmast, STM32_DMA_SCR_OFFSET) & DMA_SCR_EN) != 0); - - /* "... All the stream dedicated bits set in the status register (DMA_LISR - * and DMA_HISR) from the previous data block DMA transfer should be cleared - * before the stream can be re-enabled." - * - * Clear pending stream interrupts by setting bits in the upper or lower IFCR - * register - */ - - if (dmast->stream < 4) - { - regoffset = STM32_DMA_LIFCR_OFFSET; - } - else - { - regoffset = STM32_DMA_HIFCR_OFFSET; - } - - dmabase_putreg(dmast, regoffset, (DMA_STREAM_MASK << dmast->shift)); - - /* "Set the peripheral register address in the DMA_SPARx register. The data - * will be moved from/to this address to/from the memory after the - * peripheral event. - */ - - dmast_putreg(dmast, STM32_DMA_SPAR_OFFSET, paddr); - - /* "Set the memory address in the DMA_SM0ARx ... register. The data will be - * written to or read from this memory after the peripheral event." - * - * Note that in double-buffered mode it is explicitly assumed that the second - * buffer immediately follows the first. - */ - - dmast_putreg(dmast, STM32_DMA_SM0AR_OFFSET, maddr); - if (scr & DMA_SCR_DBM) - { - dmast_putreg(dmast, STM32_DMA_SM1AR_OFFSET, maddr + ntransfers); - } - - /* "Configure the total number of data items to be transferred in the - * DMA_SNDTRx register. After each peripheral event, this value will be - * decremented." - * - * "When the peripheral flow controller is used for a given stream, the value - * written into the DMA_SxNDTR has no effect on the DMA transfer. Actually, - * whatever the value written, it will be forced by hardware to 0xFFFF as soon - * as the stream is enabled..." - */ - - dmast_putreg(dmast, STM32_DMA_SNDTR_OFFSET, ntransfers); - - /* "Select the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR register." - * - * "Configure the stream priority using the PL[1:0] bits in the DMA_SCRx" - * register." - */ - - regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); - regval &= ~(DMA_SCR_PL_MASK | DMA_SCR_CHSEL_MASK); - regval |= scr & DMA_SCR_PL_MASK; - regval |= (uint32_t)dmast->channel << DMA_SCR_CHSEL_SHIFT; - dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval); - - /* "Configure the FIFO usage (enable or disable, threshold in transmission and - * reception)" - * - * "Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the - * DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] of the - * DMA_SxCR register): The content pointed by the FIFO threshold must exactly - * match to an integer number of memory burst transfers. If this is not in the - * case, a FIFO error (flag FEIFx of the DMA_HISR or DMA_LISR register) will be - * generated when the stream is enabled, then the stream will be automatically - * disabled." - * - * The FIFO is disabled in circular mode when transferring data from a - * peripheral to memory, as in this case it is usually desirable to know that - * every byte from the peripheral is transferred immediately to memory. It is - * not practical to flush the DMA FIFO, as this requires disabling the channel - * which triggers the transfer-complete interrupt. - * - * NOTE: The FEIFx error interrupt is not enabled because the FEIFx seems to - * be reported spuriously causing good transfers to be marked as failures. - */ - - regval = dmast_getreg(dmast, STM32_DMA_SFCR_OFFSET); - regval &= ~(DMA_SFCR_FTH_MASK | DMA_SFCR_FS_MASK | DMA_SFCR_FEIE); - if (!((scr & (DMA_SCR_CIRC | DMA_SCR_DIR_MASK)) == (DMA_SCR_CIRC | DMA_SCR_DIR_P2M))) - { - regval |= (DMA_SFCR_FTH_FULL | DMA_SFCR_DMDIS); - } - dmast_putreg(dmast, STM32_DMA_SFCR_OFFSET, regval); - - /* "Configure data transfer direction, circular mode, peripheral & memory - * incremented mode, peripheral & memory data size, and interrupt after - * half and/or full transfer in the DMA_CCRx register." - * - * Note: The CT bit is always reset. - */ - - regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); - regval &= ~(DMA_SCR_PFCTRL | DMA_SCR_DIR_MASK | DMA_SCR_PINC | DMA_SCR_MINC | - DMA_SCR_PSIZE_MASK | DMA_SCR_MSIZE_MASK | DMA_SCR_PINCOS | - DMA_SCR_CIRC | DMA_SCR_DBM | DMA_SCR_CT | - DMA_SCR_PBURST_MASK | DMA_SCR_MBURST_MASK); - scr &= (DMA_SCR_PFCTRL | DMA_SCR_DIR_MASK | DMA_SCR_PINC | DMA_SCR_MINC | - DMA_SCR_PSIZE_MASK | DMA_SCR_MSIZE_MASK | DMA_SCR_PINCOS | - DMA_SCR_DBM | DMA_SCR_CIRC | - DMA_SCR_PBURST_MASK | DMA_SCR_MBURST_MASK); - regval |= scr; - dmast->nonstop = (scr & (DMA_SCR_DBM | DMA_SCR_CIRC)) != 0; - dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval); -} - -/**************************************************************************** - * Name: stm32_dmastart - * - * Description: - * Start the DMA transfer - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - No DMA in progress - * - ****************************************************************************/ - -void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) -{ - struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; - uint32_t scr; - - DEBUGASSERT(handle != NULL); - - /* Save the callback info. This will be invoked whent the DMA commpletes */ - - dmast->callback = callback; - dmast->arg = arg; - - /* Activate the stream by setting the ENABLE bit in the DMA_SCRx register. - * As soon as the stream is enabled, it can serve any DMA request from the - * peripheral connected on the stream. - */ - - scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); - scr |= DMA_SCR_EN; - - if (!dmast->nonstop) - { - /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is - * set and an interrupt is generated if the Half-Transfer Interrupt Enable - * bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag - * (TCIF) is set and an interrupt is generated if the Transfer Complete - * Interrupt Enable bit (TCIE) is set. - */ - - scr |= (half ? (DMA_SCR_HTIE | DMA_SCR_TEIE) : (DMA_SCR_TCIE | DMA_SCR_TEIE)); - } - else - { - /* In nonstop mode, when the transfer completes it immediately resets - * and starts again. The transfer-complete interrupt is thus always - * enabled, and the half-complete interrupt can be used in circular - * mode to determine when the buffer is half-full, or in double-buffered - * mode to determine when one of the two buffers is full. - */ - - scr |= (half ? DMA_SCR_HTIE : 0) | DMA_SCR_TCIE | DMA_SCR_TEIE; - } - - dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, scr); -} - -/**************************************************************************** - * Name: stm32_dmastop - * - * Description: - * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is - * reset and stm32_dmasetup() must be called before stm32_dmastart() can be - * called again - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -void stm32_dmastop(DMA_HANDLE handle) -{ - struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; - stm32_dmastreamdisable(dmast); -} - -/**************************************************************************** - * Name: stm32_dmaresidual - * - * Description: - * Read the DMA bytes-remaining register. - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -size_t stm32_dmaresidual(DMA_HANDLE handle) -{ - struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; - uint32_t residual; - - /* Fetch the count of bytes remaining to be transferred. - * - * If the FIFO is enabled, this count may be inaccurate. ST don't - * appear to document whether this counts the peripheral or the memory - * side of the channel, and they don't make the memory pointer - * available either. - * - * For reception in circular mode the FIFO is disabled in order that - * this value can be useful. - */ - - residual = dmast_getreg(dmast, STM32_DMA_SNDTR_OFFSET); - - return (size_t)residual; -} - -/**************************************************************************** - * Name: stm32_dmacapable - * - * Description: - * Check if the DMA controller can transfer data to/from given memory - * address. This depends on the internal connections in the ARM bus matrix - * of the processor. Note that this only applies to memory addresses, it - * will return false for any peripheral address. - * - * Returned Value: - * True, if transfer is possible. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_DMACAPABLE -bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) -{ - uint32_t transfer_size, burst_length; - uint32_t mend; - - /* Verify that the address conforms to the memory transfer size. - * Transfers to/from memory performed by the DMA controller are - * required to be aligned to their size. - * - * See ST RM0090 rev4, section 9.3.11 - * - * Compute mend inline to avoid a possible non-constant integer - * multiply. - */ - - switch (ccr & DMA_SCR_MSIZE_MASK) - { - case DMA_SCR_MSIZE_8BITS: - transfer_size = 1; - mend = maddr + count - 1; - break; - - case DMA_SCR_MSIZE_16BITS: - transfer_size = 2; - mend = maddr + (count << 1) - 1; - break; - - case DMA_SCR_MSIZE_32BITS: - transfer_size = 4; - mend = maddr + (count << 2) - 1; - break; - - default: - return false; - } - - if ((maddr & (transfer_size - 1)) != 0) - { - return false; - } - - /* Verify that burst transfers do not cross a 1KiB boundary. */ - - if ((maddr / 1024) != (mend / 1024)) - { - /* The transfer as a whole crosses a 1KiB boundary. - * Verify that no burst does by asserting that the address - * is aligned to the burst length. - */ - - switch (ccr & DMA_SCR_MBURST_MASK) - { - case DMA_SCR_MBURST_SINGLE: - burst_length = transfer_size; - break; - - case DMA_SCR_MBURST_INCR4: - burst_length = transfer_size << 2; - break; - - case DMA_SCR_MBURST_INCR8: - burst_length = transfer_size << 3; - break; - - case DMA_SCR_MBURST_INCR16: - burst_length = transfer_size << 4; - break; - - default: - return false; - } - - if ((maddr & (burst_length - 1)) != 0) - { - return false; - } - } - - /* Verify that the transfer is to a memory region that supports DMA. */ - - if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) - { - return false; - } - - switch (maddr & STM32_REGION_MASK) - { - case STM32_FSMC_BANK1: - case STM32_FSMC_BANK2: - case STM32_FSMC_BANK3: - case STM32_FSMC_BANK4: - case STM32_SRAM_BASE: - case STM32_CODE_BASE: - /* All RAM and flash is supported */ - - return true; - - default: - /* Everything else is unsupported by DMA */ - - return false; - } -} -#endif - -/**************************************************************************** - * Name: stm32_dmasample - * - * Description: - * Sample DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) -{ - struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; - irqstate_t flags; - - flags = enter_critical_section(); - regs->lisr = dmabase_getreg(dmast, STM32_DMA_LISR_OFFSET); - regs->hisr = dmabase_getreg(dmast, STM32_DMA_HISR_OFFSET); - regs->scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); - regs->sndtr = dmast_getreg(dmast, STM32_DMA_SNDTR_OFFSET); - regs->spar = dmast_getreg(dmast, STM32_DMA_SPAR_OFFSET); - regs->sm0ar = dmast_getreg(dmast, STM32_DMA_SM0AR_OFFSET); - regs->sm1ar = dmast_getreg(dmast, STM32_DMA_SM1AR_OFFSET); - regs->sfcr = dmast_getreg(dmast, STM32_DMA_SFCR_OFFSET); - leave_critical_section(flags); -} -#endif - -/**************************************************************************** - * Name: stm32_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, - const char *msg) -{ - struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; - uint32_t dmabase = DMA_BASE(dmast->base); - - dmainfo("DMA Registers: %s\n", msg); - dmainfo(" LISR[%08x]: %08x\n", dmabase + STM32_DMA_LISR_OFFSET, regs->lisr); - dmainfo(" HISR[%08x]: %08x\n", dmabase + STM32_DMA_HISR_OFFSET, regs->hisr); - dmainfo(" SCR[%08x]: %08x\n", dmast->base + STM32_DMA_SCR_OFFSET, regs->scr); - dmainfo(" SNDTR[%08x]: %08x\n", dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr); - dmainfo(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar); - dmainfo(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar); - dmainfo(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar); - dmainfo(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr); -} -#endif - -#endif /* CONFIG_STM32_STM32F20XX */ diff --git a/configs/stm32f429i-disco/highpri/defconfig b/configs/stm32f429i-disco/highpri/defconfig index 210552bdcb..77dbf48159 100644 --- a/configs/stm32f429i-disco/highpri/defconfig +++ b/configs/stm32f429i-disco/highpri/defconfig @@ -1,5 +1,3 @@ -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_CCMEXCLUDE is not set # CONFIG_STM32_FLASH_PREFETCH is not set CONFIG_ADC=y CONFIG_ANALOG=y diff --git a/libs/libdsp/Kconfig b/libs/libdsp/Kconfig index 9cc9117729..5ff4a86b89 100644 --- a/libs/libdsp/Kconfig +++ b/libs/libdsp/Kconfig @@ -9,9 +9,10 @@ config LIBDSP ---help--- Enable build for various DSP functions +if LIBDSP + config LIBDSP_DEBUG bool "Libdsp debugging" - depends on LIBDSP default n ---help--- Enable debugging for libdsp. This option enables additional parameters @@ -28,3 +29,5 @@ config LIBDSP_PRECISION 0 - the fastest calculation but the lowest precision 1 - a little better precision than above, but slowest 2 - the most accuracte but the slowest one, use standard math functions. + +endif # LIBDSP