Update OpenOCD notes and scripts
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3088 42af7a65-404d-4744-a932-0658087f49c3
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@ -12,6 +12,7 @@ Contents
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IDEs
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NuttX buildroot Toolchain
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LEDs
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Using OpenOCD and GDB with an FT2232 JTAG emulator
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Olimex LPC1766-STK Configuration Options
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Configurations
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@ -287,6 +288,155 @@ LEDs
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of a signal or interrupt handler.
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ON Flashing Ooops! We crashed sometime after initialization.
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Using OpenOCD and GDB with an FT2232 JTAG emulator
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Downloading OpenOCD
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You can get information about OpenOCD here: http://openocd.berlios.de/web/
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and you can download it from here. http://sourceforge.net/projects/openocd/files/.
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To get the latest OpenOCD with more mature lpc17xx, you have to download
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from the GIT archive.
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git clone git://openocd.git.sourceforge.net/gitroot/openocd/openocd
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At present, there is only the older, frozen 0.4.0 version. These, of course,
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may have changed since I wrote this.
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Building OpenOCD under Cygwin:
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You can build OpenOCD for Windows using the Cygwin tools. Below are a
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few notes that worked as of November 7, 2010. Things may have changed
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by the time you read this, but perhaps the following will be helpful to
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you:
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1. Install Cygwin (http://www.cygwin.com/). My recommendation is to install
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everything. There are many tools you will need and it is best just to
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waste a little disk space and have everthing you need. Everything will
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require a couple of gigbytes of disk space.
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2. Create a directory /home/OpenOCD.
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3. Get the FT2232 drivr from http://www.ftdichip.com/Drivers/D2XX.htm and
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extract it into /home/OpenOCD/ftd2xx
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$ pwd
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/home/OpenOCD
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$ ls
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CDM20802 WHQL Certified.zip
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$ mkdir ftd2xx
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$ cd ftd2xx
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$ unzip ..CDM20802\ WHQL\ Certified.zip
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Archive: CDM20802 WHQL Certified.zip
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...
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3. Get the latest OpenOCD source
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$ pwd
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/home/OpenOCD
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$ git clone git://openocd.git.sourceforge.net/gitroot/openocd/openocd
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You will then have the source code in /home/OpenOCD/openocd
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4. Build OpenOCD for the FT22322 interface
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$ pwd
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/home/OpenOCD/openocd
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$ ./bootstrap
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Jim is a tiny version of the Tcl scripting language. It is needed
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by more recent versions of OpenOCD. Build libjim.a using the following
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instructions:
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$ git submodule init
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$ git submodule update
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$ cd jimtcl
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$./configure --with-jim-ext=nvp
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$ make
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$ make install
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Configure OpenOCD:
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.$ /configure --enable-maintainer-mode --disable-werror --disable-shared \
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--enable-ft2232_ftd2xx --with-ftd2xx-win32-zipdir=/home/OpenOCD/ftd2xx \
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LDFLAGS="-L/home/OpenOCD/openocd/jimtcl"
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Then build OpenOCD and its HTML documentation:
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$ make
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$ make html
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The result of the first make will be the "openocd.exe" will be
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created in the folder /home/openocd/src. The following command
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will install OpenOCD to a standard location (/usr/local/bin)
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using using this command:
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$ make install
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Helper Scripts.
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I have been using the Olimex ARM-USB-OCD JTAG debugger with the
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LPC1766-STK (http://www.olimex.com). OpenOCD requires a configuration
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file. I keep the one I used last here:
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configs/olimex-lpc1766stk/tools/olimex.cfg
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However, the "correct" configuration script to use with OpenOCD may
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change as the features of OpenOCD evolve. So you should at least
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compare that olimex.cfg file with configuration files in
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/usr/local/share/openocd/scripts/target (or /home/OpenOCD/openocd/tcl/target).
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As of this writing, there is no script for the lpc1766, but the
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lpc1768 configurtion can be used after changing the flash size to
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256Kb. That is, change:
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flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME ...
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To:
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flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME ...
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There is also a script on the tools/ directory that I use to start
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the OpenOCD daemon on my system called oocd.sh. That script will
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probably require some modifications to work in another environment:
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- Possibly the value of OPENOCD_PATH and TARGET_PATH
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- It assumes that the correct script to use is the one at
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configs/olimex-lpc1766stk/tools/olimex.cfg
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Starting OpenOCD
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Then you should be able to start the OpenOCD daemon like:
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configs/olimex-lpc1766stk/tools/oocd.sh $PWD
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If you use the setenv.sh file, that the path to oocd.sh will be added
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to your PATH environment variabl. So, in that case, the command simplifies
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to just:
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oocd.sh $PWD
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Where it is assumed that you are executing oocd.sh from the top-level
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directory where NuttX is installed. $PWD will be the path to the
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top-level NuttX directory.
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Connecting GDB
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Once the OpenOCD daemon has been started, you can connect to it via
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GDB using the following GDB command:
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arm-elf-gdb
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(gdb) target remote localhost:3333
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And you can load the NuttX ELF file:
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(gdb) symbol-file nuttx
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(gdb) load nuttx
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OpenOCD will support several special 'monitor' commands:
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(gdb) monitor reset
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(gdb) monitor halt
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Olimex LPC1766-STK Configuration Options
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -1,3 +1,5 @@
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# NXP LPC1766 Cortex-M3 with 256kB Flash and 32kB+32kB Local On-Chip SRAM,
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#daemon configuration
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telnet_port 4444
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gdb_port 3333
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@ -8,7 +10,9 @@ ft2232_device_desc "Olimex OpenOCD JTAG A"
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ft2232_layout "olimex-jtag"
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ft2232_vid_pid 0x15BA 0x0003
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# NXP LPC1766 Cortex-M3 with 256kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator
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# LPC17xx chips support both JTAG and SWD transports.
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# Adapt based on what transport is active.
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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@ -16,12 +20,18 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME lpc1766
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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# After reset the chip is clocked by the ~4MHz internal RC oscillator.
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# When board-specific code (reset-init handler or device firmware)
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# configures another oscillator and/or PLL0, set CCLK to match; if
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# you don't, then flash erase and write operations may misbehave.
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# (The ROM code doing those updates cares about core clock speed...)
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#
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# CCLK is the core clock frequency in KHz
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if { [info exists CCLK ] } {
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set _CCLK $CCLK
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} else {
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set _ENDIAN little
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set _CCLK 4000
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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@ -29,33 +39,45 @@ if { [info exists CPUTAPID ] } {
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}
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#delays on reset lines
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jtag_nsrst_delay 200
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adapter_nsrst_delay 200
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jtag_ntrst_delay 200
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# LPC2000 & LPC1700 -> SRST causes TRST
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reset_config trst_and_srst srst_pulls_trst
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
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target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
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# LPC1766 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
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$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
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# REVISIT is there any good reason to have this reset-init event handler??
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# Normally they should set up (board-specific) clocking then probe the flash...
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$_TARGETNAME configure -event reset-init {
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# Force NVIC.VTOR to point to flash at 0 ...
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# WHY? This is it's reset value; we run right after reset!!
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mwb 0xE000ED08 0x00
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}
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# LPC1766 has 256kB of user-available FLASH (bootloader is located in separate dedicated region).
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# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
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# LPC1766 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
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# and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
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$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
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# LPC1766 has 256kB of flash memory, managed by ROM code (including a
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# boot loader which verifies the flash exception table's checksum).
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# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc1700 80000 calc_checksum
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flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME \
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lpc1700 $_CCLK calc_checksum
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# 4MHz / 6 = 666kHz, so use 500
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jtag_khz 100
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# Run with *real slow* clock by default since the
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# boot rom could have been playing with the PLL, so
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# we have no idea what clock the target is running at.
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jtag_khz 10
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$_TARGETNAME configure -event reset-init {
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# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
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# "User Flash Mode" where interrupt vectors are _not_ remapped,
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# and reside in flash instead).
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#
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# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
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# Bit Symbol Value Description Reset
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# value
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# 0 MAP Memory map control. 0
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# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
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# 1 User mode. The on-chip Flash memory is mapped to address 0.
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# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
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#
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# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1766&type=user
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mww 0x400FC040 0x01
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}
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@ -1,4 +1,7 @@
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#!/bin/sh
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#
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# See configs/olimex-lpc1766stk/README.txt for information about
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# this file.
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TOPDIR=$1
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USAGE="$0 <TOPDIR> [-d]"
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@ -8,10 +11,16 @@ if [ -z "${TOPDIR}" ]; then
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exit 1
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fi
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OPENOCD_PATH="/cygdrive/c/OpenOCD/openocd-0.4.0/src"
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# Assume that OpenOCD was installed and at /usr/local/bin. Uncomment
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# the following to run directly from the build directory
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#OPENOCD_PATH="/home/OpenOCD/openocd/src"
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#TARGET_PATH="/home/OpenOCD/openocd/tcl"
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OPENOCD_PATH="/usr/local/bin"
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TARGET_PATH="/usr/local/share/openocd/scripts"
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OPENOCD_EXE=openocd.exe
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OPENOCD_CFG="${TOPDIR}/configs/olimex-lpc1766stk/tools/olimex.cfg"
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OPENOCD_ARGS="-f `cygpath -w ${OPENOCD_CFG}`"
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OPENOCD_ARGS="-f ${OPENOCD_CFG} -s ${TARGET_PATH}"
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if [ "X$2" = "X-d" ]; then
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OPENOCD_ARGS=$OPENOCD_ARGS" -d3"
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@ -32,7 +41,8 @@ if [ ! -f ${OPENOCD_CFG} ]; then
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fi
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echo "Starting OpenOCD"
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${OPENOCD_PATH}/${OPENOCD_EXE} ${OPENOCD_ARGS} &
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cd ${OPENOCD_PATH} || { echo "Failed to CD to ${OPENOCD_PATH}"; exit 1; }
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${OPENOCD_EXE} ${OPENOCD_ARGS} &
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echo "OpenOCD daemon started"
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ps -ef | grep openocd
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echo "In GDB: target remote localhost:3333"
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