From d321d62a80e87eff5f5dcefce903e4dabf430a82 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 15 Aug 2011 22:11:24 +0000 Subject: [PATCH] Add board support for the FreeScale Kinetis TWR-K60N512 git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3884 42af7a65-404d-4744-a932-0658087f49c3 --- arch/arm/src/kinetis/kinetis_flexbus.h | 40 ++++++++++++------------ arch/arm/src/kinetis/kinetis_internal.h | 12 ++++--- arch/arm/src/kinetis/kinetis_k60pinmux.h | 20 ++++++------ arch/arm/src/kinetis/kinetis_memorymap.h | 4 +-- arch/arm/src/kinetis/kinetis_pinirq.c | 12 ++++--- arch/arm/src/kinetis/kinetis_sim.h | 2 +- 6 files changed, 49 insertions(+), 41 deletions(-) diff --git a/arch/arm/src/kinetis/kinetis_flexbus.h b/arch/arm/src/kinetis/kinetis_flexbus.h index 8fddfeff92..e4936949ad 100644 --- a/arch/arm/src/kinetis/kinetis_flexbus.h +++ b/arch/arm/src/kinetis/kinetis_flexbus.h @@ -84,36 +84,36 @@ /* Register Addresses ***************************************************************/ # define 0x4000c000 /* FlexBus */ -#define KINETIS_FB_CS_BASE(n) (KINETIS_FLEXBUS_BASE+KINETIS_FB_CS_OFFSET(n)) +#define KINETIS_FB_CS_BASE(n) (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CS_OFFSET(n)) #define KINETIS_FB_CSAR(n) (KINETIS_FB_CS_BASE(n)+KINETIS_FB_CSAR_OFFSET) #define KINETIS_FB_CSMR(n) (KINETIS_FB_CS_BASE(n)+KINETIS_FB_CSMR_OFFSET) #define KINETIS_FB_CSCR(n) (KINETIS_FB_CS_BASE(n)+KINETIS_FB_CSCR_OFFSET) -#define KINETIS_FB_CSAR0 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSAR0_OFFSET) -#define KINETIS_FB_CSMR0 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSMR0_OFFSET) -#define KINETIS_FB_CSCR0 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSCR0_OFFSET) +#define KINETIS_FB_CSAR0 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSAR0_OFFSET) +#define KINETIS_FB_CSMR0 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSMR0_OFFSET) +#define KINETIS_FB_CSCR0 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSCR0_OFFSET) -#define KINETIS_FB_CSAR1 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSAR1_OFFSET) -#define KINETIS_FB_CSMR1 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSMR1_OFFSET) -#define KINETIS_FB_CSCR1 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSCR1_OFFSET) +#define KINETIS_FB_CSAR1 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSAR1_OFFSET) +#define KINETIS_FB_CSMR1 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSMR1_OFFSET) +#define KINETIS_FB_CSCR1 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSCR1_OFFSET) -#define KINETIS_FB_CSAR2 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSAR2_OFFSET) -#define KINETIS_FB_CSMR2 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSMR2_OFFSET) -#define KINETIS_FB_CSCR2 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSCR2_OFFSET) +#define KINETIS_FB_CSAR2 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSAR2_OFFSET) +#define KINETIS_FB_CSMR2 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSMR2_OFFSET) +#define KINETIS_FB_CSCR2 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSCR2_OFFSET) -#define KINETIS_FB_CSAR3 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSAR3_OFFSET) -#define KINETIS_FB_CSMR3 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSMR3_OFFSET) -#define KINETIS_FB_CSCR3 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSCR3_OFFSET) +#define KINETIS_FB_CSAR3 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSAR3_OFFSET) +#define KINETIS_FB_CSMR3 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSMR3_OFFSET) +#define KINETIS_FB_CSCR3 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSCR3_OFFSET) -#define KINETIS_FB_CSAR4 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSAR4_OFFSET) -#define KINETIS_FB_CSMR4 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSMR4_OFFSET) -#define KINETIS_FB_CSCR4 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSCR4_OFFSET) +#define KINETIS_FB_CSAR4 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSAR4_OFFSET) +#define KINETIS_FB_CSMR4 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSMR4_OFFSET) +#define KINETIS_FB_CSCR4 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSCR4_OFFSET) -#define KINETIS_FB_CSAR5 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSAR5_OFFSET) -#define KINETIS_FB_CSMR5 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSMR5_OFFSET) -#define KINETIS_FB_CSCR5 (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSCR5_OFFSET) +#define KINETIS_FB_CSAR5 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSAR5_OFFSET) +#define KINETIS_FB_CSMR5 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSMR5_OFFSET) +#define KINETIS_FB_CSCR5 (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSCR5_OFFSET) -#define KINETIS_FB_CSPMCR (KINETIS_FLEXBUS_BASE+KINETIS_FB_CSPMCR_OFFSET) +#define KINETIS_FB_CSPMCR (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSPMCR_OFFSET) /* Register Bit Definitions *********************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_internal.h b/arch/arm/src/kinetis/kinetis_internal.h index b743dac7ee..e9dfb29d75 100644 --- a/arch/arm/src/kinetis/kinetis_internal.h +++ b/arch/arm/src/kinetis/kinetis_internal.h @@ -470,11 +470,15 @@ EXTERN void kinetis_pinirqinitialize(void); #endif /************************************************************************************ - * Name: kinetis_pinirqconfig + * Name: kinetis_pinirqattach * * Description: - * Sets/clears PIN and interrupt triggers. On return PIN interrupts are always - * disabled. + * Attach a pin interrupt handler. The normal initalization sequence is: + * + * 1. Call kinetis_pinconfig() to configure the interrupting pin (pin interrupts + * will be disabled. + * 2. Call kinetis_pinirqattach() to attach the pin interrupt handling function. + * 3. Call kinetis_pinirqenable() to enable interrupts on the pin. * * Parameters: * - pinset: Pin configuration @@ -487,7 +491,7 @@ EXTERN void kinetis_pinirqinitialize(void); * ************************************************************************************/ -EXTERN xcpt_t kinetis_pinirqconfig(uint32_t pinset, xcpt_t pinisr); +EXTERN xcpt_t kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr); /************************************************************************************ * Name: kinetis_pinirqenable diff --git a/arch/arm/src/kinetis/kinetis_k60pinmux.h b/arch/arm/src/kinetis/kinetis_k60pinmux.h index 55a5df47d7..f65c8dff14 100644 --- a/arch/arm/src/kinetis/kinetis_k60pinmux.h +++ b/arch/arm/src/kinetis/kinetis_k60pinmux.h @@ -183,19 +183,19 @@ #define PIN_TSI0_CH7 (PIN_ANALOG | PIN_PORTB | PIN2) #define PIN_I2C0_SCL_2 (PIN_ALT2 | PIN_PORTB | PIN2) #define PIN_UART0_RTS_3 (PIN_ALT3 | PIN_PORTB | PIN2) -#define PIN_ENET0_1588_TMR0 (PIN_ALT4 | PIN_PORTB | PIN2) +#define PIN_ENET0_1588_TMR0_1 (PIN_ALT4 | PIN_PORTB | PIN2) #define PIN_FTM0_FLT3 (PIN_ALT6 | PIN_PORTB | PIN2) #define PIN_ADC0_SE13 (PIN_ANALOG | PIN_PORTB | PIN3) #define PIN_TSI0_CH8 (PIN_ANALOG | PIN_PORTB | PIN3) #define PIN_I2C0_SDA_2 (PIN_ALT2 | PIN_PORTB | PIN3) #define PIN_UART0_CTS_3 (PIN_ALT3 | PIN_PORTB | PIN3) -#define PIN_ENET0_1588_TMR1 (PIN_ALT4 | PIN_PORTB | PIN3) +#define PIN_ENET0_1588_TMR1_1 (PIN_ALT4 | PIN_PORTB | PIN3) #define PIN_FTM0_FLT0_2 (PIN_ALT6 | PIN_PORTB | PIN3) #define PIN_ADC1_SE10 (PIN_ANALOG | PIN_PORTB | PIN4) -#define PIN_ENET0_1588_TMR2 (PIN_ALT4 | PIN_PORTB | PIN4) +#define PIN_ENET0_1588_TMR2_1 (PIN_ALT4 | PIN_PORTB | PIN4) #define PIN_FTM1_FLT0_2 (PIN_ALT6 | PIN_PORTB | PIN4) #define PIN_ADC1_SE11 (PIN_ANALOG | PIN_PORTB | PIN5) -#define PIN_ENET0_1588_TMR3 (PIN_ALT4 | PIN_PORTB | PIN5) +#define PIN_ENET0_1588_TMR3_1 (PIN_ALT4 | PIN_PORTB | PIN5) #define PIN_FTM2_FLT0_1 (PIN_ALT6 | PIN_PORTB | PIN5) #define PIN_ADC1_SE12 (PIN_ANALOG | PIN_PORTB | PIN6) #define PIN_FB_AD23 (PIN_ALT5 | PIN_PORTB | PIN6) @@ -320,23 +320,23 @@ #define PIN_FB_AD24 (PIN_ALT5 | PIN_PORTC | PIN15) #define PIN_CAN1_RX_1 (PIN_ALT2 | PIN_PORTC | PIN16) #define PIN_UART3_RX_2 (PIN_ALT3 | PIN_PORTC | PIN16) -#define PIN_ENET0_1588_TMR0 (PIN_ALT4 | PIN_PORTC | PIN16) +#define PIN_ENET0_1588_TMR0_2 (PIN_ALT4 | PIN_PORTC | PIN16) #define PIN_FB_CS5 (PIN_ALT5 | PIN_PORTC | PIN16) #define PIN_FB_TSIZ1 (PIN_ALT5 | PIN_PORTC | PIN16) #define PIN_FB_BE23_16_BLS15_8 (PIN_ALT5 | PIN_PORTC | PIN16) #define PIN_CAN1_TX_1 (PIN_ALT2 | PIN_PORTC | PIN17) #define PIN_UART3_TX_2 (PIN_ALT3 | PIN_PORTC | PIN17) -#define PIN_ENET0_1588_TMR1 (PIN_ALT4 | PIN_PORTC | PIN17) +#define PIN_ENET0_1588_TMR1_2 (PIN_ALT4 | PIN_PORTC | PIN17) #define PIN_FB_CS4 (PIN_ALT5 | PIN_PORTC | PIN17) #define PIN_FB_TSIZ0 (PIN_ALT5 | PIN_PORTC | PIN17) #define PIN_FB_BE31_24_BLS7_0 (PIN_ALT5 | PIN_PORTC | PIN17) #define PIN_UART3_RTS_2 (PIN_ALT3 | PIN_PORTC | PIN18) -#define PIN_ENET0_1588_TMR2 (PIN_ALT4 | PIN_PORTC | PIN18) +#define PIN_ENET0_1588_TMR2_2 (PIN_ALT4 | PIN_PORTC | PIN18) #define PIN_FB_TBST (PIN_ALT5 | PIN_PORTC | PIN18) #define PIN_FB_CS2 (PIN_ALT5 | PIN_PORTC | PIN18) #define PIN_FB_BE15_8_BLS23_16 (PIN_ALT5 | PIN_PORTC | PIN18) #define PIN_UART3_CTS_2 (PIN_ALT3 | PIN_PORTC | PIN19) -#define PIN_ENET0_1588_TMR3 (PIN_ALT4 | PIN_PORTC | PIN19) +#define PIN_ENET0_1588_TMR3_2 (PIN_ALT4 | PIN_PORTC | PIN19) #define PIN_FB_CS3 (PIN_ALT5 | PIN_PORTC | PIN19) #define PIN_FB_BE7_0_BLS31_24 (PIN_ALT5 | PIN_PORTC | PIN19) #define PIN_FB_TA (PIN_ALT6 | PIN_PORTC | PIN19) @@ -380,7 +380,7 @@ #define PIN_I2C0_SCL_3 (PIN_ALT2 | PIN_PORTD | PIN8) #define PIN_UART5_RX_1 (PIN_ALT3 | PIN_PORTD | PIN8) #define PIN_FB_A16 (PIN_ALT6 | PIN_PORTD | PIN8) -#define PIN_I2C0_SDA (PIN_ALT2 | PIN_PORTD | PIN9) +#define PIN_I2C0_SDA_3 (PIN_ALT2 | PIN_PORTD | PIN9) #define PIN_UART5_TX_1 (PIN_ALT3 | PIN_PORTD | PIN9) #define PIN_FB_A17 (PIN_ALT6 | PIN_PORTD | PIN9) #define PIN_UART5_RTS_1 (PIN_ALT3 | PIN_PORTD | PIN10) @@ -436,7 +436,7 @@ #define PIN_I2S0_RX_FS_3 (PIN_ALT4 | PIN_PORTE | PIN8) #define PIN_UART5_RX_2 (PIN_ALT3 | PIN_PORTE | PIN9) #define PIN_I2S0_RX_BCLK_3 (PIN_ALT4 | PIN_PORTE | PIN9) -#define PIN_UART5_CTS_1 (PIN_ALT3 | PIN_PORTE | PIN10) +#define PIN_UART5_CTS_2 (PIN_ALT3 | PIN_PORTE | PIN10) #define PIN_I2S0_TXD_3 (PIN_ALT4 | PIN_PORTE | PIN10) #define PIN_UART5_RTS_2 (PIN_ALT3 | PIN_PORTE | PIN11) #define PIN_I2S0_TX_FS_3 (PIN_ALT4 | PIN_PORTE | PIN11) diff --git a/arch/arm/src/kinetis/kinetis_memorymap.h b/arch/arm/src/kinetis/kinetis_memorymap.h index 8f62eb210e..be0b229543 100644 --- a/arch/arm/src/kinetis/kinetis_memorymap.h +++ b/arch/arm/src/kinetis/kinetis_memorymap.h @@ -99,7 +99,7 @@ # define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ # define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ # define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ -# define KINETIS_FLEXBUS_BASE 0x4000c000 /* FlexBus */ +# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */ # define KINETIS_MPU_BASE 0x4000d000 /* MPU */ # define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ # define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */ @@ -230,7 +230,7 @@ # define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ # define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ # define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ -# define KINETIS_FLEXBUS_BASE 0x4000c000 /* FlexBus */ +# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */ # define KINETIS_MPU_BASE 0x4000d000 /* MPU */ # define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ # define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */ diff --git a/arch/arm/src/kinetis/kinetis_pinirq.c b/arch/arm/src/kinetis/kinetis_pinirq.c index 9829d22660..1ed9092e28 100644 --- a/arch/arm/src/kinetis/kinetis_pinirq.c +++ b/arch/arm/src/kinetis/kinetis_pinirq.c @@ -241,11 +241,15 @@ void kinetis_pinirqinitialize(void) } /**************************************************************************** - * Name: kinetis_pinirqconfig + * Name: kinetis_pinirqattach * * Description: - * Sets/clears PIN and interrupt triggers. On return PIN interrupts are - * always disabled. + * Attach a pin interrupt handler. The normal initalization sequence is: + * + * 1. Call kinetis_pinconfig() to configure the interrupting pin (pin interrupts + * will be disabled. + * 2. Call kinetis_pinirqattach() to attach the pin interrupt handling function. + * 3. Call kinetis_pinirqenable() to enable interrupts on the pin. * * Parameters: * - pinset: Pin configuration @@ -258,7 +262,7 @@ void kinetis_pinirqinitialize(void) * ****************************************************************************/ -xcpt_t kinetis_pinirqconfig(uint32_t pinset, xcpt_t pinisr) +xcpt_t kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr) { #ifdef HAVE_PORTINTS xcpt_t *isrtab; diff --git a/arch/arm/src/kinetis/kinetis_sim.h b/arch/arm/src/kinetis/kinetis_sim.h index 67e7df2457..2086f24cd5 100644 --- a/arch/arm/src/kinetis/kinetis_sim.h +++ b/arch/arm/src/kinetis/kinetis_sim.h @@ -511,7 +511,7 @@ # define SIM_FCFG1_FSIZE_64KB (4 << SIM_FCFG1_FSIZE_SHIFT) /* 64KB program flash, 2KB protection region */ # define SIM_FCFG1_FSIZE_128KB (6 << SIM_FCFG1_FSIZE_SHIFT) /* 128KB program flash, 4KB protection region */ # define SIM_FCFG1_FSIZE_256KB (8 << SIM_FCFG1_FSIZE_SHIFT) /* 256KB program flash, 8KB protection region */ -# define SIM_FCFG1_FSIZE_256KB (12 << SIM_FCFG1_FSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ +# define SIM_FCFG1_FSIZE_512KB (12 << SIM_FCFG1_FSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ #endif /* Flash Configuration Register 2 */