diff --git a/arch/arm/src/s32k3xx/Kconfig b/arch/arm/src/s32k3xx/Kconfig index 95ddde0ed4..94f446583c 100644 --- a/arch/arm/src/s32k3xx/Kconfig +++ b/arch/arm/src/s32k3xx/Kconfig @@ -1318,6 +1318,21 @@ config S32K3XX_LPUART_SINGLEWIRE bool "Signal Wire Support" default n +config S32K3XX_SERIAL_RXDMA_BUFFER_SIZE + int "RX DMA buffer size" + default 64 + depends on LPUART0_RXDMA || LPUART1_RXDMA || LPUART2_RXDMA || LPUART3_RXDMA || \ + LPUART4_RXDMA || LPUART5_RXDMA || LPUART6_RXDMA || LPUART7_RXDMA || \ + LPUART8_RXDMA || LPUART9_RXDMA || LPUART10_RXDMA || LPUART11_RXDMA || \ + LPUART12_RXDMA || LPUART13_RXDMA ||LPUART14_RXDMA || LPUART15_RXDMA + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half this number of bytes. + + Value given here will be rounded up to next multiple of 32 bytes. + endmenu menu "Ethernet Configuration" diff --git a/arch/arm/src/s32k3xx/s32k3xx_lowputc.c b/arch/arm/src/s32k3xx/s32k3xx_lowputc.c index 112b005c64..8d75856244 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_lowputc.c +++ b/arch/arm/src/s32k3xx/s32k3xx_lowputc.c @@ -215,7 +215,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART1_RX); s32k3xx_pinconfig(PIN_LPUART1_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART1_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART1_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || \ @@ -232,7 +232,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART2_RX); s32k3xx_pinconfig(PIN_LPUART2_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART2_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART2_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || \ @@ -249,7 +249,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART3_RX); s32k3xx_pinconfig(PIN_LPUART3_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART3_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART3_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || \ @@ -266,7 +266,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART4_RX); s32k3xx_pinconfig(PIN_LPUART4_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART4_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART4_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || \ @@ -283,7 +283,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART5_RX); s32k3xx_pinconfig(PIN_LPUART5_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART5_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART5_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || \ @@ -300,7 +300,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART6_RX); s32k3xx_pinconfig(PIN_LPUART6_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART6_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART6_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || \ @@ -317,7 +317,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART7_RX); s32k3xx_pinconfig(PIN_LPUART7_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART7_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART7_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || \ @@ -334,7 +334,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART8_RX); s32k3xx_pinconfig(PIN_LPUART8_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART8_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART8_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || \ @@ -351,7 +351,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART9_RX); s32k3xx_pinconfig(PIN_LPUART9_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART9_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART9_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART9_RS485RTSCONTROL)) || \ @@ -368,7 +368,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART10_RX); s32k3xx_pinconfig(PIN_LPUART10_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART10_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART10_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART10_RS485RTSCONTROL)) || \ @@ -385,7 +385,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART11_RX); s32k3xx_pinconfig(PIN_LPUART11_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART11_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART11_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART11_RS485RTSCONTROL)) || \ @@ -402,7 +402,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART12_RX); s32k3xx_pinconfig(PIN_LPUART12_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART12_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART12_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART12_RS485RTSCONTROL)) || \ @@ -419,7 +419,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART13_RX); s32k3xx_pinconfig(PIN_LPUART13_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART13_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART13_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART13_RS485RTSCONTROL)) || \ @@ -436,7 +436,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART14_RX); s32k3xx_pinconfig(PIN_LPUART14_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART14_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART14_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART14_RS485RTSCONTROL)) || \ @@ -453,7 +453,7 @@ void s32k3xx_lowsetup(void) s32k3xx_pinconfig(PIN_LPUART15_RX); s32k3xx_pinconfig(PIN_LPUART15_TX); -#ifdef CONFIG_LPUART0_OFLOWCONTROL +#ifdef CONFIG_LPUART15_OFLOWCONTROL s32k3xx_pinconfig(PIN_LPUART15_CTS); #endif #if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART15_RS485RTSCONTROL)) || \ @@ -641,14 +641,14 @@ int s32k3xx_lpuart_configure(uint32_t base, regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_EVEN; } - if (config->bits == 8) - { - regval &= ~LPUART_CTRL_M; - } - else if (config->bits == 9) + if (config->bits == 9 || (config->bits == 8 && config->parity != 0)) { regval |= LPUART_CTRL_M; } + else if ((config->bits == 8)) + { + regval &= ~LPUART_CTRL_M; + } else { /* REVISIT: Here should be added support of other bit modes. */ diff --git a/arch/arm/src/s32k3xx/s32k3xx_serial.c b/arch/arm/src/s32k3xx/s32k3xx_serial.c index 9150738c9c..c34be77771 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_serial.c +++ b/arch/arm/src/s32k3xx/s32k3xx_serial.c @@ -53,10 +53,14 @@ #include "arm_internal.h" #include "hardware/s32k3xx_lpuart.h" +#include "s32k3xx_edma.h" +#include "hardware/s32k3xx_dmamux.h" +#include "hardware/s32k3xx_pinmux.h" #include "hardware/s32k3xx_pinmux.h" #include "s32k3xx_config.h" #include "s32k3xx_pin.h" #include "s32k3xx_lowputc.h" +#include "s32k3xx_serial.h" #ifdef USE_SERIALDRIVER @@ -64,6 +68,187 @@ * Pre-processor Definitions ****************************************************************************/ +/* The DMA buffer size when using RX DMA to emulate a FIFO. + * + * When streaming data, the generic serial layer will be called every time + * the FIFO receives half this number of bytes. + * + * This buffer size should be an even multiple of the Cortex-M7 D-Cache line + * size, ARMV7M_DCACHE_LINESIZE, so that it can be individually invalidated. + * + * Should there be a Cortex-M7 without a D-Cache, ARMV7M_DCACHE_LINESIZE + * would be zero! + */ + +# if !defined(ARMV7M_DCACHE_LINESIZE) || ARMV7M_DCACHE_LINESIZE == 0 +# undef ARMV7M_DCACHE_LINESIZE +# define ARMV7M_DCACHE_LINESIZE 32 +# endif + +# if !defined(CONFIG_S32K3XX_SERIAL_RXDMA_BUFFER_SIZE) || \ + (CONFIG_S32K3XX_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) +# undef CONFIG_S32K3XX_SERIAL_RXDMA_BUFFER_SIZE +# define CONFIG_S32K3XX_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE +# endif + +# define RXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) +# define RXDMA_BUFFER_SIZE ((CONFIG_S32K3XX_SERIAL_RXDMA_BUFFER_SIZE \ + + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) + +/* The DMA buffer size when using TX DMA. + * + * This TX buffer size should be an even multiple of the Cortex-M7 D-Cache + * line size, ARMV7M_DCACHE_LINESIZE, so that it can be individually + * invalidated. + * + * Should there be a Cortex-M7 without a D-Cache, ARMV7M_DCACHE_LINESIZE + * would be zero! + */ + +#define TXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) +#define TXDMA_BUFFER_SIZE ((CONFIG_S32K3XX_SERIAL_RXDMA_BUFFER_SIZE \ + + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) + +/* If built with CONFIG_ARMV7M_DCACHE Buffers need to be aligned and + * multiples of ARMV7M_DCACHE_LINESIZE + */ + +#if defined(CONFIG_ARMV7M_DCACHE) +# define TXDMA_BUF_SIZE(b) (((b) + TXDMA_BUFFER_MASK) & ~TXDMA_BUFFER_MASK) +# define TXDMA_BUF_ALIGN aligned_data(ARMV7M_DCACHE_LINESIZE); +#else +# define TXDMA_BUF_SIZE(b) (b) +# define TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART0_TXDMA) +# define LPUART0_TXBUFSIZE_ADJUSTED CONFIG_LPUART0_TXBUFSIZE +# define LPUART0_TXBUFSIZE_ALGN +#else +# define LPUART0_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART0_TXBUFSIZE) +# define LPUART0_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART1_TXDMA) +# define LPUART1_TXBUFSIZE_ADJUSTED CONFIG_LPUART1_TXBUFSIZE +# define LPUART1_TXBUFSIZE_ALGN +#else +# define LPUART1_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART1_TXBUFSIZE) +# define LPUART1_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART2_TXDMA) +# define LPUART2_TXBUFSIZE_ADJUSTED CONFIG_LPUART2_TXBUFSIZE +# define LPUART2_TXBUFSIZE_ALGN +#else +# define LPUART2_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART2_TXBUFSIZE) +# define LPUART2_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART3_TXDMA) +# define LPUART3_TXBUFSIZE_ADJUSTED CONFIG_LPUART3_TXBUFSIZE +# define LPUART3_TXBUFSIZE_ALGN +#else +# define LPUART3_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART3_TXBUFSIZE) +# define LPUART3_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART4_TXDMA) +# define LPUART4_TXBUFSIZE_ADJUSTED CONFIG_LPUART4_TXBUFSIZE +# define LPUART4_TXBUFSIZE_ALGN +#else +# define LPUART4_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART4_TXBUFSIZE) +# define LPUART4_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART5_TXDMA) +# define LPUART5_TXBUFSIZE_ADJUSTED CONFIG_LPUART5_TXBUFSIZE +# define LPUART5_TXBUFSIZE_ALGN +#else +# define LPUART5_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART5_TXBUFSIZE) +# define LPUART5_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART6_TXDMA) +# define LPUART6_TXBUFSIZE_ADJUSTED CONFIG_LPUART6_TXBUFSIZE +# define LPUART6_TXBUFSIZE_ALGN +#else +# define LPUART6_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART6_TXBUFSIZE) +# define LPUART6_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART7_TXDMA) +# define LPUART7_TXBUFSIZE_ADJUSTED CONFIG_LPUART7_TXBUFSIZE +# define LPUART7_TXBUFSIZE_ALGN +#else +# define LPUART7_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART7_TXBUFSIZE) +# define LPUART7_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART8_TXDMA) +# define LPUART8_TXBUFSIZE_ADJUSTED CONFIG_LPUART8_TXBUFSIZE +# define LPUART8_TXBUFSIZE_ALGN +#else +# define LPUART8_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART8_TXBUFSIZE) +# define LPUART8_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART9_TXDMA) +# define LPUART9_TXBUFSIZE_ADJUSTED CONFIG_LPUART9_TXBUFSIZE +# define LPUART9_TXBUFSIZE_ALGN +#else +# define LPUART9_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART9_TXBUFSIZE) +# define LPUART9_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART10_TXDMA) +# define LPUART10_TXBUFSIZE_ADJUSTED CONFIG_LPUART10_TXBUFSIZE +# define LPUART10_TXBUFSIZE_ALGN +#else +# define LPUART10_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART10_TXBUFSIZE) +# define LPUART10_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART11_TXDMA) +# define LPUART11_TXBUFSIZE_ADJUSTED CONFIG_LPUART11_TXBUFSIZE +# define LPUART11_TXBUFSIZE_ALGN +#else +# define LPUART11_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART11_TXBUFSIZE) +# define LPUART11_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART12_TXDMA) +# define LPUART12_TXBUFSIZE_ADJUSTED CONFIG_LPUART12_TXBUFSIZE +# define LPUART12_TXBUFSIZE_ALGN +#else +# define LPUART12_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART12_TXBUFSIZE) +# define LPUART12_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART13_TXDMA) +# define LPUART13_TXBUFSIZE_ADJUSTED CONFIG_LPUART13_TXBUFSIZE +# define LPUART13_TXBUFSIZE_ALGN +#else +# define LPUART13_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART13_TXBUFSIZE) +# define LPUART13_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART14_TXDMA) +# define LPUART14_TXBUFSIZE_ADJUSTED CONFIG_LPUART14_TXBUFSIZE +# define LPUART14_TXBUFSIZE_ALGN +#else +# define LPUART14_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART14_TXBUFSIZE) +# define LPUART14_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART15_TXDMA) +# define LPUART15_TXBUFSIZE_ADJUSTED CONFIG_LPUART15_TXBUFSIZE +# define LPUART15_TXBUFSIZE_ALGN +#else +# define LPUART15_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART15_TXBUFSIZE) +# define LPUART15_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + /* Which LPUART with be tty0/console and which tty0-15? The console will * always be ttyS0. If there is no console then will use the lowest * numbered LPUART. @@ -72,930 +257,1030 @@ /* First pick the console and ttys0. This could be any of LPUART0-2 */ #if defined(CONFIG_LPUART0_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart0port /* LPUART0 is console */ -# define TTYS0_DEV g_uart0port /* LPUART0 is ttyS0 */ -# define UART1_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart0priv /* LPUART0 is console */ +# define TTYS0_DEV g_lpuart0priv /* LPUART0 is ttyS0 */ +# define LPUART0_ASSIGNED 1 +# if defined(CONFIG_LPUART0_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART0_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart1port /* LPUART1 is console */ -# define TTYS0_DEV g_uart1port /* LPUART1 is ttyS0 */ -# define UART2_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart1priv /* LPUART1 is console */ +# define TTYS0_DEV g_lpuart1priv /* LPUART1 is ttyS0 */ +# define LPUART1_ASSIGNED 1 +# if defined(CONFIG_LPUART1_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART1_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART2_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart2port /* LPUART2 is console */ -# define TTYS0_DEV g_uart2port /* LPUART2 is ttyS0 */ -# define UART3_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart2priv /* LPUART2 is console */ +# define TTYS0_DEV g_lpuart2priv /* LPUART2 is ttyS0 */ +# define LPUART2_ASSIGNED 1 +# if defined(CONFIG_LPUART2_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART2_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART3_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart3port /* LPUART3 is console */ -# define TTYS0_DEV g_uart3port /* LPUART3 is ttyS0 */ -# define UART4_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart3priv /* LPUART3 is console */ +# define TTYS0_DEV g_lpuart3priv /* LPUART3 is ttyS0 */ +# define LPUART3_ASSIGNED 1 +# if defined(CONFIG_LPUART3_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART3_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART4_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart4port /* LPUART4 is console */ -# define TTYS0_DEV g_uart4port /* LPUART4 is ttyS0 */ -# define UART5_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart4priv /* LPUART4 is console */ +# define TTYS0_DEV g_lpuart4priv /* LPUART4 is ttyS0 */ +# define LPUART4_ASSIGNED 1 +# if defined(CONFIG_LPUART4_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART4_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART5_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart5port /* LPUART5 is console */ -# define TTYS0_DEV g_uart5port /* LPUART5 is ttyS0 */ -# define UART6_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart5priv /* LPUART5 is console */ +# define TTYS0_DEV g_lpuart5priv /* LPUART5 is ttyS0 */ +# define LPUART5_ASSIGNED 1 +# if defined(CONFIG_LPUART5_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART5_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART6_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart6port /* LPUART6 is console */ -# define TTYS0_DEV g_uart6port /* LPUART6 is ttyS0 */ -# define UART7_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart6priv /* LPUART6 is console */ +# define TTYS0_DEV g_lpuart6priv /* LPUART6 is ttyS0 */ +# define LPUART6_ASSIGNED 1 +# if defined(CONFIG_LPUART6_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART6_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART7_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart7port /* LPUART7 is console */ -# define TTYS0_DEV g_uart7port /* LPUART7 is ttyS0 */ -# define UART8_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart7priv /* LPUART7 is console */ +# define TTYS0_DEV g_lpuart7priv /* LPUART7 is ttyS0 */ +# define LPUART7_ASSIGNED 1 +# if defined(CONFIG_LPUART7_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART7_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART8_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart8port /* LPUART8 is console */ -# define TTYS0_DEV g_uart8port /* LPUART8 is ttyS0 */ -# define UART9_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart8priv /* LPUART8 is console */ +# define TTYS0_DEV g_lpuart8priv /* LPUART8 is ttyS0 */ +# define LPUART8_ASSIGNED 1 +# if defined(CONFIG_LPUART8_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART8_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART9_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart9port /* LPUART9 is console */ -# define TTYS0_DEV g_uart9port /* LPUART9 is ttyS0 */ -# define UART10_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart9priv /* LPUART9 is console */ +# define TTYS0_DEV g_lpuart9priv /* LPUART9 is ttyS0 */ +# define LPUART9_ASSIGNED 1 +# if defined(CONFIG_LPUART9_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART9_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART10_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart10port /* LPUART10 is console */ -# define TTYS0_DEV g_uart10port /* LPUART10 is ttyS0 */ -# define UART11_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart10priv /* LPUART10 is console */ +# define TTYS0_DEV g_lpuart10priv /* LPUART10 is ttyS0 */ +# define LPUART10_ASSIGNED 1 +# if defined(CONFIG_LPUART10_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART10_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART11_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart11port /* LPUART11 is console */ -# define TTYS0_DEV g_uart11port /* LPUART11 is ttyS0 */ -# define UART12_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart11priv /* LPUART11 is console */ +# define TTYS0_DEV g_lpuart11priv /* LPUART11 is ttyS0 */ +# define LPUART11_ASSIGNED 1 +# if defined(CONFIG_LPUART11_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART11_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART12_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart12port /* LPUART12 is console */ -# define TTYS0_DEV g_uart12port /* LPUART12 is ttyS0 */ -# define UART13_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart12priv /* LPUART12 is console */ +# define TTYS0_DEV g_lpuart12priv /* LPUART12 is ttyS0 */ +# define LPUART12_ASSIGNED 1 +# if defined(CONFIG_LPUART12_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART12_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART13_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart13port /* LPUART13 is console */ -# define TTYS0_DEV g_uart13port /* LPUART13 is ttyS0 */ -# define UART14_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart13priv /* LPUART13 is console */ +# define TTYS0_DEV g_lpuart13priv /* LPUART13 is ttyS0 */ +# define LPUART13_ASSIGNED 1 +# if defined(CONFIG_LPUART13_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART13_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART14_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart14port /* LPUART14 is console */ -# define TTYS0_DEV g_uart14port /* LPUART14 is ttyS0 */ -# define UART15_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart14priv /* LPUART14 is console */ +# define TTYS0_DEV g_lpuart14priv /* LPUART14 is ttyS0 */ +# define LPUART14_ASSIGNED 1 +# if defined(CONFIG_LPUART14_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART14_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #elif defined(CONFIG_LPUART15_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart15port /* LPUART15 is console */ -# define TTYS0_DEV g_uart15port /* LPUART15 is ttyS0 */ -# define UART16_ASSIGNED 1 +# define CONSOLE_DEV g_lpuart15priv /* LPUART15 is console */ +# define TTYS0_DEV g_lpuart15priv /* LPUART15 is ttyS0 */ +# define LPUART15_ASSIGNED 1 +# if defined(CONFIG_LPUART15_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART15_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif #else # undef CONSOLE_DEV /* No console */ # if defined(CONFIG_S32K3XX_LPUART0) -# define TTYS0_DEV g_uart0port /* LPUART0 is ttyS0 */ -# define UART1_ASSIGNED 1 +# define TTYS0_DEV g_lpuart0priv /* LPUART0 is ttyS0 */ +# define LPUART0_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART1) -# define TTYS0_DEV g_uart1port /* LPUART1 is ttyS0 */ -# define UART2_ASSIGNED 1 +# define TTYS0_DEV g_lpuart1priv /* LPUART1 is ttyS0 */ +# define LPUART1_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART2) -# define TTYS0_DEV g_uart2port /* LPUART2 is ttyS0 */ -# define UART3_ASSIGNED 1 +# define TTYS0_DEV g_lpuart2priv /* LPUART2 is ttyS0 */ +# define LPUART2_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART3) -# define TTYS0_DEV g_uart3port /* LPUART3 is ttyS0 */ -# define UART4_ASSIGNED 1 +# define TTYS0_DEV g_lpuart3priv /* LPUART3 is ttyS0 */ +# define LPUART3_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART4) -# define TTYS0_DEV g_uart4port /* LPUART4 is ttyS0 */ -# define UART5_ASSIGNED 1 +# define TTYS0_DEV g_lpuart4priv /* LPUART4 is ttyS0 */ +# define LPUART4_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART5) -# define TTYS0_DEV g_uart5port /* LPUART5 is ttyS0 */ -# define UART6_ASSIGNED 1 +# define TTYS0_DEV g_lpuart5priv /* LPUART5 is ttyS0 */ +# define LPUART5_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART6) -# define TTYS0_DEV g_uart6port /* LPUART6 is ttyS0 */ -# define UART7_ASSIGNED 1 +# define TTYS0_DEV g_lpuart6priv /* LPUART6 is ttyS0 */ +# define LPUART6_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART7) -# define TTYS0_DEV g_uart7port /* LPUART7 is ttyS0 */ -# define UART8_ASSIGNED 1 +# define TTYS0_DEV g_lpuart7priv /* LPUART7 is ttyS0 */ +# define LPUART7_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART8) -# define TTYS0_DEV g_uart8port /* LPUART8 is ttyS0 */ -# define UART9_ASSIGNED 1 +# define TTYS0_DEV g_lpuart8priv /* LPUART8 is ttyS0 */ +# define LPUART8_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART9) -# define TTYS0_DEV g_uart9port /* LPUART9 is ttyS0 */ -# define UART10_ASSIGNED 1 +# define TTYS0_DEV g_lpuart9priv /* LPUART9 is ttyS0 */ +# define LPUART9_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART10) -# define TTYS0_DEV g_uart10port /* LPUART10 is ttyS0 */ -# define UART11_ASSIGNED 1 +# define TTYS0_DEV g_lpuart10priv /* LPUART10 is ttyS0 */ +# define LPUART10_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART11) -# define TTYS0_DEV g_uart11port /* LPUART11 is ttyS0 */ -# define UART12_ASSIGNED 1 +# define TTYS0_DEV g_lpuart11priv /* LPUART11 is ttyS0 */ +# define LPUART11_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART12) -# define TTYS0_DEV g_uart12port /* LPUART12 is ttyS0 */ -# define UART13_ASSIGNED 1 +# define TTYS0_DEV g_lpuart12priv /* LPUART12 is ttyS0 */ +# define LPUART12_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART13) -# define TTYS0_DEV g_uart13port /* LPUART13 is ttyS0 */ -# define UART14_ASSIGNED 1 +# define TTYS0_DEV g_lpuart13priv /* LPUART13 is ttyS0 */ +# define LPUART13_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART14) -# define TTYS0_DEV g_uart14port /* LPUART14 is ttyS0 */ -# define UART15_ASSIGNED 1 +# define TTYS0_DEV g_lpuart14priv /* LPUART14 is ttyS0 */ +# define LPUART14_ASSIGNED 1 # elif defined(CONFIG_S32K3XX_LPUART15) -# define TTYS0_DEV g_uart15port /* LPUART15 is ttyS0 */ -# define UART16_ASSIGNED 1 +# define TTYS0_DEV g_lpuart15priv /* LPUART15 is ttyS0 */ +# define LPUART15_ASSIGNED 1 # endif #endif +#if defined(SERIAL_HAVE_CONSOLE_RXDMA) || defined(SERIAL_HAVE_CONSOLE_TXDMA) +# define SERIAL_HAVE_CONSOLE_DMA +#endif + /* Pick ttys1. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS1_DEV g_uart0port /* LPUART0 is ttyS1 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS1_DEV g_uart1port /* LPUART1 is ttyS1 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS1_DEV g_uart2port /* LPUART2 is ttyS1 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS1_DEV g_uart3port /* LPUART3 is ttyS1 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS1_DEV g_uart4port /* LPUART4 is ttyS1 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS1_DEV g_uart5port /* LPUART5 is ttyS1 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS1_DEV g_uart6port /* LPUART6 is ttyS1 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS1_DEV g_uart7port /* LPUART7 is ttyS1 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS1_DEV g_uart8port /* LPUART8 is ttyS1 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS1_DEV g_uart9port /* LPUART9 is ttyS1 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS1_DEV g_uart10port /* LPUART10 is ttyS1 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS1_DEV g_uart11port /* LPUART11 is ttyS1 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS1_DEV g_uart12port /* LPUART12 is ttyS1 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS1_DEV g_uart13port /* LPUART13 is ttyS1 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS1_DEV g_uart14port /* LPUART14 is ttyS1 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS1_DEV g_uart15port /* LPUART15 is ttyS1 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS1_DEV g_lpuart0priv /* LPUART0 is ttyS1 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS1_DEV g_lpuart1priv /* LPUART1 is ttyS1 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS1_DEV g_lpuart2priv /* LPUART2 is ttyS1 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS1_DEV g_lpuart3priv /* LPUART3 is ttyS1 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS1_DEV g_lpuart4priv /* LPUART4 is ttyS1 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS1_DEV g_lpuart5priv /* LPUART5 is ttyS1 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS1_DEV g_lpuart6priv /* LPUART6 is ttyS1 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS1_DEV g_lpuart7priv /* LPUART7 is ttyS1 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS1_DEV g_lpuart8priv /* LPUART8 is ttyS1 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS1_DEV g_lpuart9priv /* LPUART9 is ttyS1 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS1_DEV g_lpuart10priv /* LPUART10 is ttyS1 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS1_DEV g_lpuart11priv /* LPUART11 is ttyS1 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS1_DEV g_lpuart12priv /* LPUART12 is ttyS1 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS1_DEV g_lpuart13priv /* LPUART13 is ttyS1 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS1_DEV g_lpuart14priv /* LPUART14 is ttyS1 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS1_DEV g_lpuart15priv /* LPUART15 is ttyS1 */ +# define LPUART15_ASSIGNED 1 #endif /* Pick ttys2. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS2_DEV g_uart0port /* LPUART0 is ttyS2 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS2_DEV g_uart1port /* LPUART1 is ttyS2 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS2_DEV g_uart2port /* LPUART2 is ttyS2 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS2_DEV g_uart3port /* LPUART3 is ttyS2 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS2_DEV g_uart4port /* LPUART4 is ttyS2 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS2_DEV g_uart5port /* LPUART5 is ttyS2 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS2_DEV g_uart6port /* LPUART6 is ttyS2 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS2_DEV g_uart7port /* LPUART7 is ttyS2 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS2_DEV g_uart8port /* LPUART8 is ttyS2 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS2_DEV g_uart9port /* LPUART9 is ttyS2 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS2_DEV g_uart10port /* LPUART10 is ttyS2 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS2_DEV g_uart11port /* LPUART11 is ttyS2 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS2_DEV g_uart12port /* LPUART12 is ttyS2 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS2_DEV g_uart13port /* LPUART13 is ttyS2 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS2_DEV g_uart14port /* LPUART14 is ttyS2 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS2_DEV g_uart15port /* LPUART15 is ttyS2 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS2_DEV g_lpuart0priv /* LPUART0 is ttyS2 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS2_DEV g_lpuart1priv /* LPUART1 is ttyS2 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS2_DEV g_lpuart2priv /* LPUART2 is ttyS2 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS2_DEV g_lpuart3priv /* LPUART3 is ttyS2 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS2_DEV g_lpuart4priv /* LPUART4 is ttyS2 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS2_DEV g_lpuart5priv /* LPUART5 is ttyS2 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS2_DEV g_lpuart6priv /* LPUART6 is ttyS2 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS2_DEV g_lpuart7priv /* LPUART7 is ttyS2 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS2_DEV g_lpuart8priv /* LPUART8 is ttyS2 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS2_DEV g_lpuart9priv /* LPUART9 is ttyS2 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS2_DEV g_lpuart10priv /* LPUART10 is ttyS2 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS2_DEV g_lpuart11priv /* LPUART11 is ttyS2 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS2_DEV g_lpuart12priv /* LPUART12 is ttyS2 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS2_DEV g_lpuart13priv /* LPUART13 is ttyS2 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS2_DEV g_lpuart14priv /* LPUART14 is ttyS2 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS2_DEV g_lpuart15priv /* LPUART15 is ttyS2 */ +# define LPUART15_ASSIGNED 1 #endif /* Pick ttys3. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS3_DEV g_uart0port /* LPUART0 is ttyS3 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS3_DEV g_uart1port /* LPUART1 is ttyS3 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS3_DEV g_uart2port /* LPUART2 is ttyS3 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS3_DEV g_uart3port /* LPUART3 is ttyS3 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS3_DEV g_uart4port /* LPUART4 is ttyS3 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS3_DEV g_uart5port /* LPUART5 is ttyS3 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS3_DEV g_uart6port /* LPUART6 is ttyS3 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS3_DEV g_uart7port /* LPUART7 is ttyS3 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS3_DEV g_uart8port /* LPUART8 is ttyS3 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS3_DEV g_uart9port /* LPUART9 is ttyS3 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS3_DEV g_uart10port /* LPUART10 is ttyS3 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS3_DEV g_uart11port /* LPUART11 is ttyS3 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS3_DEV g_uart12port /* LPUART12 is ttyS3 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS3_DEV g_uart13port /* LPUART13 is ttyS3 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS3_DEV g_uart14port /* LPUART14 is ttyS3 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS3_DEV g_uart15port /* LPUART15 is ttyS3 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS3_DEV g_lpuart0priv /* LPUART0 is ttyS3 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS3_DEV g_lpuart1priv /* LPUART1 is ttyS3 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS3_DEV g_lpuart2priv /* LPUART2 is ttyS3 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS3_DEV g_lpuart3priv /* LPUART3 is ttyS3 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS3_DEV g_lpuart4priv /* LPUART4 is ttyS3 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS3_DEV g_lpuart5priv /* LPUART5 is ttyS3 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS3_DEV g_lpuart6priv /* LPUART6 is ttyS3 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS3_DEV g_lpuart7priv /* LPUART7 is ttyS3 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS3_DEV g_lpuart8priv /* LPUART8 is ttyS3 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS3_DEV g_lpuart9priv /* LPUART9 is ttyS3 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS3_DEV g_lpuart10priv /* LPUART10 is ttyS3 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS3_DEV g_lpuart11priv /* LPUART11 is ttyS3 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS3_DEV g_lpuart12priv /* LPUART12 is ttyS3 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS3_DEV g_lpuart13priv /* LPUART13 is ttyS3 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS3_DEV g_lpuart14priv /* LPUART14 is ttyS3 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS3_DEV g_lpuart15priv /* LPUART15 is ttyS3 */ +# define LPUART15_ASSIGNED 1 #endif /* Pick ttys4. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS4_DEV g_uart0port /* LPUART0 is ttyS4 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS4_DEV g_uart1port /* LPUART1 is ttyS4 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS4_DEV g_uart2port /* LPUART2 is ttyS4 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS4_DEV g_uart3port /* LPUART3 is ttyS4 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS4_DEV g_uart4port /* LPUART4 is ttyS4 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS4_DEV g_uart5port /* LPUART5 is ttyS4 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS4_DEV g_uart6port /* LPUART6 is ttyS4 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS4_DEV g_uart7port /* LPUART7 is ttyS4 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS4_DEV g_uart8port /* LPUART8 is ttyS4 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS4_DEV g_uart9port /* LPUART9 is ttyS4 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS4_DEV g_uart10port /* LPUART10 is ttyS4 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS4_DEV g_uart11port /* LPUART11 is ttyS4 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS4_DEV g_uart12port /* LPUART12 is ttyS4 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS4_DEV g_uart13port /* LPUART13 is ttyS4 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS4_DEV g_uart14port /* LPUART14 is ttyS4 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS4_DEV g_uart15port /* LPUART15 is ttyS4 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS4_DEV g_lpuart0priv /* LPUART0 is ttyS4 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS4_DEV g_lpuart1priv /* LPUART1 is ttyS4 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS4_DEV g_lpuart2priv /* LPUART2 is ttyS4 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS4_DEV g_lpuart3priv /* LPUART3 is ttyS4 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS4_DEV g_lpuart4priv /* LPUART4 is ttyS4 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS4_DEV g_lpuart5priv /* LPUART5 is ttyS4 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS4_DEV g_lpuart6priv /* LPUART6 is ttyS4 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS4_DEV g_lpuart7priv /* LPUART7 is ttyS4 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS4_DEV g_lpuart8priv /* LPUART8 is ttyS4 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS4_DEV g_lpuart9priv /* LPUART9 is ttyS4 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS4_DEV g_lpuart10priv /* LPUART10 is ttyS4 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS4_DEV g_lpuart11priv /* LPUART11 is ttyS4 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS4_DEV g_lpuart12priv /* LPUART12 is ttyS4 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS4_DEV g_lpuart13priv /* LPUART13 is ttyS4 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS4_DEV g_lpuart14priv /* LPUART14 is ttyS4 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS4_DEV g_lpuart15priv /* LPUART15 is ttyS4 */ +# define LPUART15_ASSIGNED 1 #endif /* Pick ttys5. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS5_DEV g_uart0port /* LPUART0 is ttyS5 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS5_DEV g_uart1port /* LPUART1 is ttyS5 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS5_DEV g_uart2port /* LPUART2 is ttyS5 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS5_DEV g_uart3port /* LPUART3 is ttyS5 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS5_DEV g_uart4port /* LPUART4 is ttyS5 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS5_DEV g_uart5port /* LPUART5 is ttyS5 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS5_DEV g_uart6port /* LPUART6 is ttyS5 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS5_DEV g_uart7port /* LPUART7 is ttyS5 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS5_DEV g_uart8port /* LPUART8 is ttyS5 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS5_DEV g_uart9port /* LPUART9 is ttyS5 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS5_DEV g_uart10port /* LPUART10 is ttyS5 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS5_DEV g_uart11port /* LPUART11 is ttyS5 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS5_DEV g_uart12port /* LPUART12 is ttyS5 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS5_DEV g_uart13port /* LPUART13 is ttyS5 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS5_DEV g_uart14port /* LPUART14 is ttyS5 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS5_DEV g_uart15port /* LPUART15 is ttyS5 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS5_DEV g_lpuart0priv /* LPUART0 is ttyS5 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS5_DEV g_lpuart1priv /* LPUART1 is ttyS5 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS5_DEV g_lpuart2priv /* LPUART2 is ttyS5 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS5_DEV g_lpuart3priv /* LPUART3 is ttyS5 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS5_DEV g_lpuart4priv /* LPUART4 is ttyS5 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS5_DEV g_lpuart5priv /* LPUART5 is ttyS5 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS5_DEV g_lpuart6priv /* LPUART6 is ttyS5 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS5_DEV g_lpuart7priv /* LPUART7 is ttyS5 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS5_DEV g_lpuart8priv /* LPUART8 is ttyS5 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS5_DEV g_lpuart9priv /* LPUART9 is ttyS5 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS5_DEV g_lpuart10priv /* LPUART10 is ttyS5 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS5_DEV g_lpuart11priv /* LPUART11 is ttyS5 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS5_DEV g_lpuart12priv /* LPUART12 is ttyS5 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS5_DEV g_lpuart13priv /* LPUART13 is ttyS5 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS5_DEV g_lpuart14priv /* LPUART14 is ttyS5 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS5_DEV g_lpuart15priv /* LPUART15 is ttyS5 */ +# define LPUART15_ASSIGNED 1 #endif /* Pick ttys6. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS6_DEV g_uart0port /* LPUART0 is ttyS6 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS6_DEV g_uart1port /* LPUART1 is ttyS6 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS6_DEV g_uart2port /* LPUART2 is ttyS6 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS6_DEV g_uart3port /* LPUART3 is ttyS6 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS6_DEV g_uart4port /* LPUART4 is ttyS6 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS6_DEV g_uart5port /* LPUART5 is ttyS6 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS6_DEV g_uart6port /* LPUART6 is ttyS6 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS6_DEV g_uart7port /* LPUART7 is ttyS6 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS6_DEV g_uart8port /* LPUART8 is ttyS6 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS6_DEV g_uart9port /* LPUART9 is ttyS6 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS6_DEV g_uart10port /* LPUART10 is ttyS6 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS6_DEV g_uart11port /* LPUART11 is ttyS6 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS6_DEV g_uart12port /* LPUART12 is ttyS6 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS6_DEV g_uart13port /* LPUART13 is ttyS6 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS6_DEV g_uart14port /* LPUART14 is ttyS6 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS6_DEV g_uart15port /* LPUART15 is ttyS6 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS6_DEV g_lpuart0priv /* LPUART0 is ttyS6 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS6_DEV g_lpuart1priv /* LPUART1 is ttyS6 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS6_DEV g_lpuart2priv /* LPUART2 is ttyS6 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS6_DEV g_lpuart3priv /* LPUART3 is ttyS6 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS6_DEV g_lpuart4priv /* LPUART4 is ttyS6 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS6_DEV g_lpuart5priv /* LPUART5 is ttyS6 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS6_DEV g_lpuart6priv /* LPUART6 is ttyS6 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS6_DEV g_lpuart7priv /* LPUART7 is ttyS6 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS6_DEV g_lpuart8priv /* LPUART8 is ttyS6 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS6_DEV g_lpuart9priv /* LPUART9 is ttyS6 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS6_DEV g_lpuart10priv /* LPUART10 is ttyS6 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS6_DEV g_lpuart11priv /* LPUART11 is ttyS6 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS6_DEV g_lpuart12priv /* LPUART12 is ttyS6 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS6_DEV g_lpuart13priv /* LPUART13 is ttyS6 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS6_DEV g_lpuart14priv /* LPUART14 is ttyS6 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS6_DEV g_lpuart15priv /* LPUART15 is ttyS6 */ +# define LPUART15_ASSIGNED 1 #endif /* Pick ttys7. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS7_DEV g_uart0port /* LPUART0 is ttyS7 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS7_DEV g_uart1port /* LPUART1 is ttyS7 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS7_DEV g_uart2port /* LPUART2 is ttyS7 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS7_DEV g_uart3port /* LPUART3 is ttyS7 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS7_DEV g_uart4port /* LPUART4 is ttyS7 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS7_DEV g_uart5port /* LPUART5 is ttyS7 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS7_DEV g_uart6port /* LPUART6 is ttyS7 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS7_DEV g_uart7port /* LPUART7 is ttyS7 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS7_DEV g_uart8port /* LPUART8 is ttyS7 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS7_DEV g_uart9port /* LPUART9 is ttyS7 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS7_DEV g_uart10port /* LPUART10 is ttyS7 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS7_DEV g_uart11port /* LPUART11 is ttyS7 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS7_DEV g_uart12port /* LPUART12 is ttyS7 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS7_DEV g_uart13port /* LPUART13 is ttyS7 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS7_DEV g_uart14port /* LPUART14 is ttyS7 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS7_DEV g_uart15port /* LPUART15 is ttyS7 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS7_DEV g_lpuart0priv /* LPUART0 is ttyS7 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS7_DEV g_lpuart1priv /* LPUART1 is ttyS7 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS7_DEV g_lpuart2priv /* LPUART2 is ttyS7 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS7_DEV g_lpuart3priv /* LPUART3 is ttyS7 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS7_DEV g_lpuart4priv /* LPUART4 is ttyS7 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS7_DEV g_lpuart5priv /* LPUART5 is ttyS7 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS7_DEV g_lpuart6priv /* LPUART6 is ttyS7 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS7_DEV g_lpuart7priv /* LPUART7 is ttyS7 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS7_DEV g_lpuart8priv /* LPUART8 is ttyS7 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS7_DEV g_lpuart9priv /* LPUART9 is ttyS7 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS7_DEV g_lpuart10priv /* LPUART10 is ttyS7 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS7_DEV g_lpuart11priv /* LPUART11 is ttyS7 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS7_DEV g_lpuart12priv /* LPUART12 is ttyS7 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS7_DEV g_lpuart13priv /* LPUART13 is ttyS7 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS7_DEV g_lpuart14priv /* LPUART14 is ttyS7 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS7_DEV g_lpuart15priv /* LPUART15 is ttyS7 */ +# define LPUART15_ASSIGNED 1 #endif /* Pick ttys8. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS8_DEV g_uart0port /* LPUART0 is ttyS8 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS8_DEV g_uart1port /* LPUART1 is ttyS8 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS8_DEV g_uart2port /* LPUART2 is ttyS8 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS8_DEV g_uart3port /* LPUART3 is ttyS8 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS8_DEV g_uart4port /* LPUART4 is ttyS8 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS8_DEV g_uart5port /* LPUART5 is ttyS8 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS8_DEV g_uart6port /* LPUART6 is ttyS8 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS8_DEV g_uart7port /* LPUART7 is ttyS8 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS8_DEV g_uart8port /* LPUART8 is ttyS8 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS8_DEV g_uart9port /* LPUART9 is ttyS8 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS8_DEV g_uart10port /* LPUART10 is ttyS8 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS8_DEV g_uart11port /* LPUART11 is ttyS8 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS8_DEV g_uart12port /* LPUART12 is ttyS8 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS8_DEV g_uart13port /* LPUART13 is ttyS8 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS8_DEV g_uart14port /* LPUART14 is ttyS8 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS8_DEV g_uart15port /* LPUART15 is ttyS8 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS8_DEV g_lpuart0priv /* LPUART0 is ttyS8 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS8_DEV g_lpuart1priv /* LPUART1 is ttyS8 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS8_DEV g_lpuart2priv /* LPUART2 is ttyS8 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS8_DEV g_lpuart3priv /* LPUART3 is ttyS8 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS8_DEV g_lpuart4priv /* LPUART4 is ttyS8 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS8_DEV g_lpuart5priv /* LPUART5 is ttyS8 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS8_DEV g_lpuart6priv /* LPUART6 is ttyS8 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS8_DEV g_lpuart7priv /* LPUART7 is ttyS8 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS8_DEV g_lpuart8priv /* LPUART8 is ttyS8 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS8_DEV g_lpuart9priv /* LPUART9 is ttyS8 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS8_DEV g_lpuart10priv /* LPUART10 is ttyS8 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS8_DEV g_lpuart11priv /* LPUART11 is ttyS8 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS8_DEV g_lpuart12priv /* LPUART12 is ttyS8 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS8_DEV g_lpuart13priv /* LPUART13 is ttyS8 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS8_DEV g_lpuart14priv /* LPUART14 is ttyS8 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS8_DEV g_lpuart15priv /* LPUART15 is ttyS8 */ +# define LPUART15_ASSIGNED 1 #endif /* Pick ttys9. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS9_DEV g_uart0port /* LPUART0 is ttyS9 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS9_DEV g_uart1port /* LPUART1 is ttyS9 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS9_DEV g_uart2port /* LPUART2 is ttyS9 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS9_DEV g_uart3port /* LPUART3 is ttyS9 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS9_DEV g_uart4port /* LPUART4 is ttyS9 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS9_DEV g_uart5port /* LPUART5 is ttyS9 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS9_DEV g_uart6port /* LPUART6 is ttyS9 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS9_DEV g_uart7port /* LPUART7 is ttyS9 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS9_DEV g_uart8port /* LPUART8 is ttyS9 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS9_DEV g_uart9port /* LPUART9 is ttyS9 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS9_DEV g_uart10port /* LPUART10 is ttyS9 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS9_DEV g_uart11port /* LPUART11 is ttyS9 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS9_DEV g_uart12port /* LPUART12 is ttyS9 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS9_DEV g_uart13port /* LPUART13 is ttyS9 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS9_DEV g_uart14port /* LPUART14 is ttyS9 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS9_DEV g_uart15port /* LPUART15 is ttyS9 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS9_DEV g_lpuart0priv /* LPUART0 is ttyS9 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS9_DEV g_lpuart1priv /* LPUART1 is ttyS9 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS9_DEV g_lpuart2priv /* LPUART2 is ttyS9 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS9_DEV g_lpuart3priv /* LPUART3 is ttyS9 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS9_DEV g_lpuart4priv /* LPUART4 is ttyS9 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS9_DEV g_lpuart5priv /* LPUART5 is ttyS9 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS9_DEV g_lpuart6priv /* LPUART6 is ttyS9 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS9_DEV g_lpuart7priv /* LPUART7 is ttyS9 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS9_DEV g_lpuart8priv /* LPUART8 is ttyS9 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS9_DEV g_lpuart9priv /* LPUART9 is ttyS9 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS9_DEV g_lpuart10priv /* LPUART10 is ttyS9 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS9_DEV g_lpuart11priv /* LPUART11 is ttyS9 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS9_DEV g_lpuart12priv /* LPUART12 is ttyS9 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS9_DEV g_lpuart13priv /* LPUART13 is ttyS9 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS9_DEV g_lpuart14priv /* LPUART14 is ttyS9 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS9_DEV g_lpuart15priv /* LPUART15 is ttyS9 */ +# define LPUART15_ASSIGNED 1 #endif /* Pick ttys10. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS10_DEV g_uart0port /* LPUART0 is ttyS10 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS10_DEV g_uart1port /* LPUART1 is ttyS10 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS10_DEV g_uart2port /* LPUART2 is ttyS10 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS10_DEV g_uart3port /* LPUART3 is ttyS10 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS10_DEV g_uart4port /* LPUART4 is ttyS10 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS10_DEV g_uart5port /* LPUART5 is ttyS10 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS10_DEV g_uart6port /* LPUART6 is ttyS10 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS10_DEV g_uart7port /* LPUART7 is ttyS10 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS10_DEV g_uart8port /* LPUART8 is ttyS10 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS10_DEV g_uart9port /* LPUART9 is ttyS10 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS10_DEV g_uart10port /* LPUART10 is ttyS10 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS10_DEV g_uart11port /* LPUART11 is ttyS10 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS10_DEV g_uart12port /* LPUART12 is ttyS10 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS10_DEV g_uart13port /* LPUART13 is ttyS10 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS10_DEV g_uart14port /* LPUART14 is ttyS10 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS10_DEV g_uart15port /* LPUART15 is ttyS10 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS10_DEV g_lpuart0priv /* LPUART0 is ttyS10 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS10_DEV g_lpuart1priv /* LPUART1 is ttyS10 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS10_DEV g_lpuart2priv /* LPUART2 is ttyS10 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS10_DEV g_lpuart3priv /* LPUART3 is ttyS10 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS10_DEV g_lpuart4priv /* LPUART4 is ttyS10 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS10_DEV g_lpuart5priv /* LPUART5 is ttyS10 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS10_DEV g_lpuart6priv /* LPUART6 is ttyS10 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS10_DEV g_lpuart7priv /* LPUART7 is ttyS10 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS10_DEV g_lpuart8priv /* LPUART8 is ttyS10 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS10_DEV g_lpuart9priv /* LPUART9 is ttyS10 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS10_DEV g_lpuart10priv /* LPUART10 is ttyS10 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS10_DEV g_lpuart11priv /* LPUART11 is ttyS10 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS10_DEV g_lpuart12priv /* LPUART12 is ttyS10 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS10_DEV g_lpuart13priv /* LPUART13 is ttyS10 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS10_DEV g_lpuart14priv /* LPUART14 is ttyS10 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS10_DEV g_lpuart15priv /* LPUART15 is ttyS10 */ +# define LPUART15_ASSIGNED 1 #endif /* Pick ttys11. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS11_DEV g_uart0port /* LPUART0 is ttyS11 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS11_DEV g_uart1port /* LPUART1 is ttyS11 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS11_DEV g_uart2port /* LPUART2 is ttyS11 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS11_DEV g_uart3port /* LPUART3 is ttyS11 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS11_DEV g_uart4port /* LPUART4 is ttyS11 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS11_DEV g_uart5port /* LPUART5 is ttyS11 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS11_DEV g_uart6port /* LPUART6 is ttyS11 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS11_DEV g_uart7port /* LPUART7 is ttyS11 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS11_DEV g_uart8port /* LPUART8 is ttyS11 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS11_DEV g_uart9port /* LPUART9 is ttyS11 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS11_DEV g_uart10port /* LPUART10 is ttyS11 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS11_DEV g_uart11port /* LPUART11 is ttyS11 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS11_DEV g_uart12port /* LPUART12 is ttyS11 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS11_DEV g_uart13port /* LPUART13 is ttyS11 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS11_DEV g_uart14port /* LPUART14 is ttyS11 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS11_DEV g_uart15port /* LPUART15 is ttyS11 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS11_DEV g_lpuart0priv /* LPUART0 is ttyS11 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS11_DEV g_lpuart1priv /* LPUART1 is ttyS11 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS11_DEV g_lpuart2priv /* LPUART2 is ttyS11 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS11_DEV g_lpuart3priv /* LPUART3 is ttyS11 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS11_DEV g_lpuart4priv /* LPUART4 is ttyS11 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS11_DEV g_lpuart5priv /* LPUART5 is ttyS11 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS11_DEV g_lpuart6priv /* LPUART6 is ttyS11 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS11_DEV g_lpuart7priv /* LPUART7 is ttyS11 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS11_DEV g_lpuart8priv /* LPUART8 is ttyS11 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS11_DEV g_lpuart9priv /* LPUART9 is ttyS11 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS11_DEV g_lpuart10priv /* LPUART10 is ttyS11 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS11_DEV g_lpuart11priv /* LPUART11 is ttyS11 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS11_DEV g_lpuart12priv /* LPUART12 is ttyS11 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS11_DEV g_lpuart13priv /* LPUART13 is ttyS11 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS11_DEV g_lpuart14priv /* LPUART14 is ttyS11 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS11_DEV g_lpuart15priv /* LPUART15 is ttyS11 */ +# define LPUART15_ASSIGNED 1 #endif /* Pick ttys12. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS12_DEV g_uart0port /* LPUART0 is ttyS12 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS12_DEV g_uart1port /* LPUART1 is ttyS12 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS12_DEV g_uart2port /* LPUART2 is ttyS12 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS12_DEV g_uart3port /* LPUART3 is ttyS12 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS12_DEV g_uart4port /* LPUART4 is ttyS12 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS12_DEV g_uart5port /* LPUART5 is ttyS12 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS12_DEV g_uart6port /* LPUART6 is ttyS12 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS12_DEV g_uart7port /* LPUART7 is ttyS12 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS12_DEV g_uart8port /* LPUART8 is ttyS12 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS12_DEV g_uart9port /* LPUART9 is ttyS12 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS12_DEV g_uart10port /* LPUART10 is ttyS12 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS12_DEV g_uart11port /* LPUART11 is ttyS12 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS12_DEV g_uart12port /* LPUART12 is ttyS12 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS12_DEV g_uart13port /* LPUART13 is ttyS12 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS12_DEV g_uart14port /* LPUART14 is ttyS12 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS12_DEV g_uart15port /* LPUART15 is ttyS12 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS12_DEV g_lpuart0priv /* LPUART0 is ttyS12 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS12_DEV g_lpuart1priv /* LPUART1 is ttyS12 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS12_DEV g_lpuart2priv /* LPUART2 is ttyS12 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS12_DEV g_lpuart3priv /* LPUART3 is ttyS12 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS12_DEV g_lpuart4priv /* LPUART4 is ttyS12 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS12_DEV g_lpuart5priv /* LPUART5 is ttyS12 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS12_DEV g_lpuart6priv /* LPUART6 is ttyS12 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS12_DEV g_lpuart7priv /* LPUART7 is ttyS12 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS12_DEV g_lpuart8priv /* LPUART8 is ttyS12 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS12_DEV g_lpuart9priv /* LPUART9 is ttyS12 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS12_DEV g_lpuart10priv /* LPUART10 is ttyS12 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS12_DEV g_lpuart11priv /* LPUART11 is ttyS12 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS12_DEV g_lpuart12priv /* LPUART12 is ttyS12 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS12_DEV g_lpuart13priv /* LPUART13 is ttyS12 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS12_DEV g_lpuart14priv /* LPUART14 is ttyS12 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS12_DEV g_lpuart15priv /* LPUART15 is ttyS12 */ +# define LPUART15_ASSIGNED 1 #endif /* Pick ttys13. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS13_DEV g_uart0port /* LPUART0 is ttyS13 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS13_DEV g_uart1port /* LPUART1 is ttyS13 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS13_DEV g_uart2port /* LPUART2 is ttyS13 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS13_DEV g_uart3port /* LPUART3 is ttyS13 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS13_DEV g_uart4port /* LPUART4 is ttyS13 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS13_DEV g_uart5port /* LPUART5 is ttyS13 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS13_DEV g_uart6port /* LPUART6 is ttyS13 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS13_DEV g_uart7port /* LPUART7 is ttyS13 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS13_DEV g_uart8port /* LPUART8 is ttyS13 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS13_DEV g_uart9port /* LPUART9 is ttyS13 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS13_DEV g_uart10port /* LPUART10 is ttyS13 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS13_DEV g_uart11port /* LPUART11 is ttyS13 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS13_DEV g_uart12port /* LPUART12 is ttyS13 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS13_DEV g_uart13port /* LPUART13 is ttyS13 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS13_DEV g_uart14port /* LPUART14 is ttyS13 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS13_DEV g_uart15port /* LPUART15 is ttyS13 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS13_DEV g_lpuart0priv /* LPUART0 is ttyS13 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS13_DEV g_lpuart1priv /* LPUART1 is ttyS13 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS13_DEV g_lpuart2priv /* LPUART2 is ttyS13 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS13_DEV g_lpuart3priv /* LPUART3 is ttyS13 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS13_DEV g_lpuart4priv /* LPUART4 is ttyS13 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS13_DEV g_lpuart5priv /* LPUART5 is ttyS13 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS13_DEV g_lpuart6priv /* LPUART6 is ttyS13 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS13_DEV g_lpuart7priv /* LPUART7 is ttyS13 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS13_DEV g_lpuart8priv /* LPUART8 is ttyS13 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS13_DEV g_lpuart9priv /* LPUART9 is ttyS13 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS13_DEV g_lpuart10priv /* LPUART10 is ttyS13 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS13_DEV g_lpuart11priv /* LPUART11 is ttyS13 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS13_DEV g_lpuart12priv /* LPUART12 is ttyS13 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS13_DEV g_lpuart13priv /* LPUART13 is ttyS13 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS13_DEV g_lpuart14priv /* LPUART14 is ttyS13 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS13_DEV g_lpuart15priv /* LPUART15 is ttyS13 */ +# define LPUART15_ASSIGNED 1 #endif /* Pick ttys14. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS14_DEV g_uart0port /* LPUART0 is ttyS14 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS14_DEV g_uart1port /* LPUART1 is ttyS14 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS14_DEV g_uart2port /* LPUART2 is ttyS14 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS14_DEV g_uart3port /* LPUART3 is ttyS14 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS14_DEV g_uart4port /* LPUART4 is ttyS14 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS14_DEV g_uart5port /* LPUART5 is ttyS14 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS14_DEV g_uart6port /* LPUART6 is ttyS14 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS14_DEV g_uart7port /* LPUART7 is ttyS14 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS14_DEV g_uart8port /* LPUART8 is ttyS14 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS14_DEV g_uart9port /* LPUART9 is ttyS14 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS14_DEV g_uart10port /* LPUART10 is ttyS14 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS14_DEV g_uart11port /* LPUART11 is ttyS14 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS14_DEV g_uart12port /* LPUART12 is ttyS14 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS14_DEV g_uart13port /* LPUART13 is ttyS14 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS14_DEV g_uart14port /* LPUART14 is ttyS14 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS14_DEV g_uart15port /* LPUART15 is ttyS14 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS14_DEV g_lpuart0priv /* LPUART0 is ttyS14 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS14_DEV g_lpuart1priv /* LPUART1 is ttyS14 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS14_DEV g_lpuart2priv /* LPUART2 is ttyS14 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS14_DEV g_lpuart3priv /* LPUART3 is ttyS14 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS14_DEV g_lpuart4priv /* LPUART4 is ttyS14 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS14_DEV g_lpuart5priv /* LPUART5 is ttyS14 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS14_DEV g_lpuart6priv /* LPUART6 is ttyS14 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS14_DEV g_lpuart7priv /* LPUART7 is ttyS14 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS14_DEV g_lpuart8priv /* LPUART8 is ttyS14 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS14_DEV g_lpuart9priv /* LPUART9 is ttyS14 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS14_DEV g_lpuart10priv /* LPUART10 is ttyS14 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS14_DEV g_lpuart11priv /* LPUART11 is ttyS14 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS14_DEV g_lpuart12priv /* LPUART12 is ttyS14 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS14_DEV g_lpuart13priv /* LPUART13 is ttyS14 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS14_DEV g_lpuart14priv /* LPUART14 is ttyS14 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS14_DEV g_lpuart15priv /* LPUART15 is ttyS14 */ +# define LPUART15_ASSIGNED 1 #endif /* Pick ttys15. * One of LPUART0-15 could be the console; */ -#if defined(CONFIG_S32K3XX_LPUART0) && !defined(UART1_ASSIGNED) -# define TTYS15_DEV g_uart0port /* LPUART0 is ttyS15 */ -# define UART1_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(UART2_ASSIGNED) -# define TTYS15_DEV g_uart1port /* LPUART1 is ttyS15 */ -# define UART2_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(UART3_ASSIGNED) -# define TTYS15_DEV g_uart2port /* LPUART2 is ttyS15 */ -# define UART3_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(UART4_ASSIGNED) -# define TTYS15_DEV g_uart3port /* LPUART3 is ttyS15 */ -# define UART4_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(UART5_ASSIGNED) -# define TTYS15_DEV g_uart4port /* LPUART4 is ttyS15 */ -# define UART5_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(UART6_ASSIGNED) -# define TTYS15_DEV g_uart5port /* LPUART5 is ttyS15 */ -# define UART6_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(UART7_ASSIGNED) -# define TTYS15_DEV g_uart6port /* LPUART6 is ttyS15 */ -# define UART7_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(UART8_ASSIGNED) -# define TTYS15_DEV g_uart7port /* LPUART7 is ttyS15 */ -# define UART8_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(UART9_ASSIGNED) -# define TTYS15_DEV g_uart8port /* LPUART8 is ttyS15 */ -# define UART9_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(UART10_ASSIGNED) -# define TTYS15_DEV g_uart9port /* LPUART9 is ttyS15 */ -# define UART10_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(UART11_ASSIGNED) -# define TTYS15_DEV g_uart10port /* LPUART10 is ttyS15 */ -# define UART11_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(UART12_ASSIGNED) -# define TTYS15_DEV g_uart11port /* LPUART11 is ttyS15 */ -# define UART12_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(UART13_ASSIGNED) -# define TTYS15_DEV g_uart12port /* LPUART12 is ttyS15 */ -# define UART13_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(UART14_ASSIGNED) -# define TTYS15_DEV g_uart13port /* LPUART13 is ttyS15 */ -# define UART14_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(UART15_ASSIGNED) -# define TTYS15_DEV g_uart14port /* LPUART14 is ttyS15 */ -# define UART15_ASSIGNED 1 -#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(UART16_ASSIGNED) -# define TTYS15_DEV g_uart15port /* LPUART15 is ttyS15 */ -# define UART16_ASSIGNED 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS15_DEV g_lpuart0priv /* LPUART0 is ttyS15 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS15_DEV g_lpuart1priv /* LPUART1 is ttyS15 */ +# define LPUART1_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(LPUART2_ASSIGNED) +# define TTYS15_DEV g_lpuart2priv /* LPUART2 is ttyS15 */ +# define LPUART2_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(LPUART3_ASSIGNED) +# define TTYS15_DEV g_lpuart3priv /* LPUART3 is ttyS15 */ +# define LPUART3_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(LPUART4_ASSIGNED) +# define TTYS15_DEV g_lpuart4priv /* LPUART4 is ttyS15 */ +# define LPUART4_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(LPUART5_ASSIGNED) +# define TTYS15_DEV g_lpuart5priv /* LPUART5 is ttyS15 */ +# define LPUART5_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(LPUART6_ASSIGNED) +# define TTYS15_DEV g_lpuart6priv /* LPUART6 is ttyS15 */ +# define LPUART6_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(LPUART7_ASSIGNED) +# define TTYS15_DEV g_lpuart7priv /* LPUART7 is ttyS15 */ +# define LPUART7_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(LPUART8_ASSIGNED) +# define TTYS15_DEV g_lpuart8priv /* LPUART8 is ttyS15 */ +# define LPUART8_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(LPUART9_ASSIGNED) +# define TTYS15_DEV g_lpuart9priv /* LPUART9 is ttyS15 */ +# define LPUART9_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(LPUART10_ASSIGNED) +# define TTYS15_DEV g_lpuart10priv /* LPUART10 is ttyS15 */ +# define LPUART10_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(LPUART11_ASSIGNED) +# define TTYS15_DEV g_lpuart11priv /* LPUART11 is ttyS15 */ +# define LPUART11_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(LPUART12_ASSIGNED) +# define TTYS15_DEV g_lpuart12priv /* LPUART12 is ttyS15 */ +# define LPUART12_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(LPUART13_ASSIGNED) +# define TTYS15_DEV g_lpuart13priv /* LPUART13 is ttyS15 */ +# define LPUART13_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(LPUART14_ASSIGNED) +# define TTYS15_DEV g_lpuart14priv /* LPUART14 is ttyS15 */ +# define LPUART14_ASSIGNED 1 +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(LPUART15_ASSIGNED) +# define TTYS15_DEV g_lpuart15priv /* LPUART15 is ttyS15 */ +# define LPUART15_ASSIGNED 1 #endif /* Power management definitions */ @@ -1014,6 +1299,7 @@ struct s32k3xx_uart_s { + struct uart_dev_s dev; /* Generic UART device */ uint32_t uartbase; /* Base address of UART registers */ uint32_t baud; /* Configured baud */ uint32_t ie; /* Saved enabled interrupts */ @@ -1022,10 +1308,13 @@ struct s32k3xx_uart_s uint8_t bits; /* Number of bits (7 or 8) */ #if defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL) uint8_t inviflow:1; /* Invert RTS sense */ - const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ + const uint32_t rts_gpio; /* LPUART RTS GPIO pin configuration */ #endif #ifdef CONFIG_SERIAL_OFLOWCONTROL - const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */ + const uint32_t cts_gpio; /* LPUART CTS GPIO pin configuration */ +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + const uint32_t tx_gpio; /* TX GPIO pin configuration */ #endif uint8_t stopbits2:1; /* 1: Configure with 2 stop bits vs 1 */ @@ -1037,6 +1326,23 @@ struct s32k3xx_uart_s #endif #ifdef CONFIG_SERIAL_RS485CONTROL uint8_t rs485mode:1; /* We are in RS485 (RTS on TX) mode */ +#endif + /* TX DMA state */ + +#ifdef SERIAL_HAVE_TXDMA + const unsigned int dma_txreqsrc; /* DMAMUX source of TX DMA request */ + DMACH_HANDLE txdma; /* currently-open transmit DMA stream */ + sem_t txdmasem; /* Indicate TX DMA completion */ +#endif + + /* RX DMA state */ + +#ifdef SERIAL_HAVE_RXDMA + const unsigned int dma_rxreqsrc; /* DMAMUX source of RX DMA request */ + DMACH_HANDLE rxdma; /* currently-open receive DMA stream */ + bool rxenable; /* DMA-based reception en/disable */ + uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */ + char *const rxfifo; /* Receive DMA buffer */ #endif }; @@ -1059,12 +1365,49 @@ static int s32k3xx_attach(struct uart_dev_s *dev); static void s32k3xx_detach(struct uart_dev_s *dev); static int s32k3xx_interrupt(int irq, void *context, void *arg); static int s32k3xx_ioctl(struct file *filep, int cmd, unsigned long arg); +#if !defined(SERIAL_HAVE_ONLY_RXDMA) static int s32k3xx_receive(struct uart_dev_s *dev, unsigned int *status); static void s32k3xx_rxint(struct uart_dev_s *dev, bool enable); static bool s32k3xx_rxavailable(struct uart_dev_s *dev); -static void s32k3xx_send(struct uart_dev_s *dev, int ch); +#endif +#if !defined(SERIAL_HAVE_ONLY_TXDMA) static void s32k3xx_txint(struct uart_dev_s *dev, bool enable); +#endif + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool s32k3xx_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper); +#endif +static void s32k3xx_send(struct uart_dev_s *dev, int ch); + static bool s32k3xx_txready(struct uart_dev_s *dev); + +#ifdef SERIAL_HAVE_TXDMA +static void s32k3xx_dma_send(struct uart_dev_s *dev); +static void s32k3xx_dma_txint(struct uart_dev_s *dev, bool enable); +static void s32k3xx_dma_txavailable(struct uart_dev_s *dev); +static void s32k3xx_dma_txcallback(DMACH_HANDLE handle, void *arg, bool done, + int result); +#endif + +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) +static int s32k3xx_dma_setup(struct uart_dev_s *dev); +static void s32k3xx_dma_shutdown(struct uart_dev_s *dev); +#endif + +#ifdef SERIAL_HAVE_RXDMA +static int s32k3xx_dma_receive(struct uart_dev_s *dev, + unsigned int *status); +#ifdef CONFIG_PM +static void s32k3xx_dma_reenable(struct s32k3xx_uart_s *priv); +#endif +static void s32k3xx_dma_rxint(struct uart_dev_s *dev, bool enable); +static bool s32k3xx_dma_rxavailable(struct uart_dev_s *dev); + +static void s32k3xx_dma_rxcallback(DMACH_HANDLE handle, void *arg, bool done, + int result); +#endif + static bool s32k3xx_txempty(struct uart_dev_s *dev); #ifdef CONFIG_PM @@ -1080,7 +1423,8 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, /* Serial driver UART operations */ -static const struct uart_ops_s g_uart_ops = +#if !defined(SERIAL_HAVE_ONLY_TXDMA) && !defined(SERIAL_HAVE_ONLY_RXDMA) +static const struct uart_ops_s g_lpuart_ops = { .setup = s32k3xx_setup, .shutdown = s32k3xx_shutdown, @@ -1091,99 +1435,295 @@ static const struct uart_ops_s g_uart_ops = .rxint = s32k3xx_rxint, .rxavailable = s32k3xx_rxavailable, #ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = NULL, + .rxflowcontrol = s32k3xx_rxflowcontrol, #endif .send = s32k3xx_send, .txint = s32k3xx_txint, .txready = s32k3xx_txready, .txempty = s32k3xx_txempty, }; +#endif + +#if defined(SERIAL_HAVE_RXDMA) && defined(SERIAL_HAVE_TXDMA) +static const struct uart_ops_s g_lpuart_rxtxdma_ops = +{ + .setup = s32k3xx_dma_setup, + .shutdown = s32k3xx_dma_shutdown, + .attach = s32k3xx_attach, + .detach = s32k3xx_detach, + .ioctl = s32k3xx_ioctl, + .receive = s32k3xx_dma_receive, + .rxint = s32k3xx_dma_rxint, + .rxavailable = s32k3xx_dma_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = s32k3xx_rxflowcontrol, +#endif + .send = s32k3xx_send, + .txint = s32k3xx_dma_txint, + .txready = s32k3xx_txready, + .txempty = s32k3xx_txempty, + .dmatxavail = s32k3xx_dma_txavailable, + .dmasend = s32k3xx_dma_send, +}; +#endif + +#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_RXDMA) +static const struct uart_ops_s g_lpuart_rxdma_ops = +{ + .setup = s32k3xx_dma_setup, + .shutdown = s32k3xx_dma_shutdown, + .attach = s32k3xx_attach, + .detach = s32k3xx_detach, + .ioctl = s32k3xx_ioctl, + .receive = s32k3xx_dma_receive, + .rxint = s32k3xx_dma_rxint, + .rxavailable = s32k3xx_dma_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = s32k3xx_rxflowcontrol, +#endif + .send = s32k3xx_send, + .txint = s32k3xx_txint, + .txready = s32k3xx_txready, + .txempty = s32k3xx_txempty, +}; +#endif + +#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_TXDMA) +static const struct uart_ops_s g_lpuart_txdma_ops = +{ + .setup = s32k3xx_dma_setup, + .shutdown = s32k3xx_dma_shutdown, + .attach = s32k3xx_attach, + .detach = s32k3xx_detach, + .ioctl = s32k3xx_ioctl, + .receive = s32k3xx_receive, + .rxint = s32k3xx_rxint, + .rxavailable = s32k3xx_rxavailable, + #ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = s32k3xx_rxflowcontrol, + #endif + .send = s32k3xx_send, + .txint = s32k3xx_dma_txint, + .txready = s32k3xx_txready, + .txempty = s32k3xx_txempty, + .dmatxavail = s32k3xx_dma_txavailable, + .dmasend = s32k3xx_dma_send, +}; +#endif + +/* Avoid unused warning */ +#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_RXDMA) +const struct uart_ops_s *g_o0 = &g_lpuart_rxdma_ops; +#endif +#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_TXDMA) +const struct uart_ops_s *g_o1 = &g_lpuart_txdma_ops; +#endif /* I/O buffers */ +#ifdef CONFIG_LPUART0_RXDMA +static char g_lpuart0rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART1_RXDMA +static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +# ifdef CONFIG_LPUART2_RXDMA +static char g_lpuart2rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART3_RXDMA +static char g_lpuart3rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART4_RXDMA +static char g_lpuart4rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART5_RXDMA +static char g_lpuart5rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART6_RXDMA +static char g_lpuart6rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART7_RXDMA +static char g_lpuart7rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART8_RXDMA +static char g_lpuart8rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART9_RXDMA +static char g_lpuart9rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART10_RXDMA +static char g_lpuart10rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART11_RXDMA +static char g_lpuart11rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART12_RXDMA +static char g_lpuart12rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART13_RXDMA +static char g_lpuart13rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART14_RXDMA +static char g_lpuart14rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART15_RXDMA +static char g_lpuart15rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV7M_DCACHE_LINESIZE); +#endif + #ifdef CONFIG_S32K3XX_LPUART0 -static char g_uart0rxbuffer[CONFIG_LPUART0_RXBUFSIZE]; -static char g_uart0txbuffer[CONFIG_LPUART0_TXBUFSIZE]; +static char g_lpuart0rxbuffer[CONFIG_LPUART0_RXBUFSIZE]; +static char g_lpuart0txbuffer[LPUART0_TXBUFSIZE_ADJUSTED] \ + LPUART0_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART1 -static char g_uart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; -static char g_uart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; +static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; +static char g_lpuart1txbuffer[LPUART1_TXBUFSIZE_ADJUSTED] + LPUART1_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART2 -static char g_uart2rxbuffer[CONFIG_LPUART2_RXBUFSIZE]; -static char g_uart2txbuffer[CONFIG_LPUART2_TXBUFSIZE]; +static char g_lpuart2rxbuffer[CONFIG_LPUART2_RXBUFSIZE]; +static char g_lpuart2txbuffer[LPUART2_TXBUFSIZE_ADJUSTED] + LPUART2_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART3 -static char g_uart3rxbuffer[CONFIG_LPUART3_RXBUFSIZE]; -static char g_uart3txbuffer[CONFIG_LPUART3_TXBUFSIZE]; +static char g_lpuart3rxbuffer[CONFIG_LPUART3_RXBUFSIZE]; +static char g_lpuart3txbuffer[LPUART3_TXBUFSIZE_ADJUSTED] + LPUART3_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART4 -static char g_uart4rxbuffer[CONFIG_LPUART4_RXBUFSIZE]; -static char g_uart4txbuffer[CONFIG_LPUART4_TXBUFSIZE]; +static char g_lpuart4rxbuffer[CONFIG_LPUART4_RXBUFSIZE]; +static char g_lpuart4txbuffer[LPUART4_TXBUFSIZE_ADJUSTED] + LPUART4_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART5 -static char g_uart5rxbuffer[CONFIG_LPUART5_RXBUFSIZE]; -static char g_uart5txbuffer[CONFIG_LPUART5_TXBUFSIZE]; +static char g_lpuart5rxbuffer[CONFIG_LPUART5_RXBUFSIZE]; +static char g_lpuart5txbuffer[LPUART5_TXBUFSIZE_ADJUSTED] + LPUART5_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART6 -static char g_uart6rxbuffer[CONFIG_LPUART6_RXBUFSIZE]; -static char g_uart6txbuffer[CONFIG_LPUART6_TXBUFSIZE]; +static char g_lpuart6rxbuffer[CONFIG_LPUART6_RXBUFSIZE]; +static char g_lpuart6txbuffer[LPUART6_TXBUFSIZE_ADJUSTED] + LPUART6_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART7 -static char g_uart7rxbuffer[CONFIG_LPUART7_RXBUFSIZE]; -static char g_uart7txbuffer[CONFIG_LPUART7_TXBUFSIZE]; +static char g_lpuart7rxbuffer[CONFIG_LPUART7_RXBUFSIZE]; +static char g_lpuart7txbuffer[LPUART7_TXBUFSIZE_ADJUSTED] + LPUART7_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART8 -static char g_uart8rxbuffer[CONFIG_LPUART8_RXBUFSIZE]; -static char g_uart8txbuffer[CONFIG_LPUART8_TXBUFSIZE]; +static char g_lpuart8rxbuffer[CONFIG_LPUART8_RXBUFSIZE]; +static char g_lpuart8txbuffer[LPUART8_TXBUFSIZE_ADJUSTED] + LPUART8_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART9 -static char g_uart9rxbuffer[CONFIG_LPUART9_RXBUFSIZE]; -static char g_uart9txbuffer[CONFIG_LPUART9_TXBUFSIZE]; +static char g_lpuart9rxbuffer[CONFIG_LPUART9_RXBUFSIZE]; +static char g_lpuart9txbuffer[LPUART9_TXBUFSIZE_ADJUSTED] + LPUART9_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART10 -static char g_uart10rxbuffer[CONFIG_LPUART10_RXBUFSIZE]; -static char g_uart10txbuffer[CONFIG_LPUART10_TXBUFSIZE]; +static char g_lpuart10rxbuffer[CONFIG_LPUART10_RXBUFSIZE]; +static char g_lpuart10txbuffer[LPUART10_TXBUFSIZE_ADJUSTED] + LPUART10_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART11 -static char g_uart11rxbuffer[CONFIG_LPUART11_RXBUFSIZE]; -static char g_uart11txbuffer[CONFIG_LPUART11_TXBUFSIZE]; +static char g_lpuart11rxbuffer[CONFIG_LPUART11_RXBUFSIZE]; +static char g_lpuart11txbuffer[LPUART11_TXBUFSIZE_ADJUSTED] + LPUART11_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART12 -static char g_uart12rxbuffer[CONFIG_LPUART12_RXBUFSIZE]; -static char g_uart12txbuffer[CONFIG_LPUART12_TXBUFSIZE]; +static char g_lpuart12rxbuffer[CONFIG_LPUART12_RXBUFSIZE]; +static char g_lpuart12txbuffer[LPUART12_TXBUFSIZE_ADJUSTED] + LPUART12_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART13 -static char g_uart13rxbuffer[CONFIG_LPUART13_RXBUFSIZE]; -static char g_uart13txbuffer[CONFIG_LPUART13_TXBUFSIZE]; +static char g_lpuart13rxbuffer[CONFIG_LPUART13_RXBUFSIZE]; +static char g_lpuart13txbuffer[LPUART13_TXBUFSIZE_ADJUSTED] + LPUART13_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART14 -static char g_uart14rxbuffer[CONFIG_LPUART14_RXBUFSIZE]; -static char g_uart14txbuffer[CONFIG_LPUART14_TXBUFSIZE]; +static char g_lpuart14rxbuffer[CONFIG_LPUART14_RXBUFSIZE]; +static char g_lpuart14txbuffer[LPUART14_TXBUFSIZE_ADJUSTED] + LPUART14_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART15 -static char g_uart15rxbuffer[CONFIG_LPUART15_RXBUFSIZE]; -static char g_uart15txbuffer[CONFIG_LPUART15_TXBUFSIZE]; +static char g_lpuart15rxbuffer[CONFIG_LPUART15_RXBUFSIZE]; +static char g_lpuart15txbuffer[LPUART15_TXBUFSIZE_ADJUSTED] + LPUART15_TXBUFSIZE_ALGN; #endif #ifdef CONFIG_S32K3XX_LPUART0 -static struct s32k3xx_uart_s g_uart0priv = +static struct s32k3xx_uart_s g_lpuart0priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART0_RXBUFSIZE, + .buffer = g_lpuart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART0_TXBUFSIZE, + .buffer = g_lpuart0txbuffer, + }, + #if defined(CONFIG_LPUART0_RXDMA) && defined(CONFIG_LPUART0_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART0_RXDMA) && !defined(CONFIG_LPUART0_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART0_RXDMA) && defined(CONFIG_LPUART0_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart0priv, + }, + .uartbase = S32K3XX_LPUART0_BASE, .baud = CONFIG_LPUART0_BAUD, .irq = S32K3XX_IRQ_LPUART0, @@ -1192,44 +1732,65 @@ static struct s32k3xx_uart_s g_uart0priv = .stopbits2 = CONFIG_LPUART0_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART0_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART0_CTS, + .cts_gpio = PIN_LPUART0_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART0_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART0_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART0_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART0_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART0_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART0_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART0_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART0_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART0_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART0_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART0_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart0port = -{ - .recv = - { - .size = CONFIG_LPUART0_RXBUFSIZE, - .buffer = g_uart0rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART0_TXBUFSIZE, - .buffer = g_uart0txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart0priv, +#ifdef CONFIG_LPUART0_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART08_TX, +#endif +#ifdef CONFIG_LPUART0_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART08_RX, + .rxfifo = g_lpuart0rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART1 -static struct s32k3xx_uart_s g_uart1priv = +static struct s32k3xx_uart_s g_lpuart1priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART1_RXBUFSIZE, + .buffer = g_lpuart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART1_TXBUFSIZE, + .buffer = g_lpuart1txbuffer, + }, + #if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart1priv, + }, + .uartbase = S32K3XX_LPUART1_BASE, .baud = CONFIG_LPUART1_BAUD, .irq = S32K3XX_IRQ_LPUART1, @@ -1238,44 +1799,65 @@ static struct s32k3xx_uart_s g_uart1priv = .stopbits2 = CONFIG_LPUART1_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART1_CTS, + .cts_gpio = PIN_LPUART1_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART1_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART1_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART1_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART1_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART1_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart1port = -{ - .recv = - { - .size = CONFIG_LPUART1_RXBUFSIZE, - .buffer = g_uart1rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART1_TXBUFSIZE, - .buffer = g_uart1txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart1priv, +#ifdef CONFIG_LPUART1_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART19_TX, +#endif +#ifdef CONFIG_LPUART1_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART19_RX, + .rxfifo = g_lpuart1rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART2 -static struct s32k3xx_uart_s g_uart2priv = +static struct s32k3xx_uart_s g_lpuart2priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART2_RXBUFSIZE, + .buffer = g_lpuart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART2_TXBUFSIZE, + .buffer = g_lpuart2txbuffer, + }, + #if defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART2_RXDMA) && !defined(CONFIG_LPUART2_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart2priv, + }, + .uartbase = S32K3XX_LPUART2_BASE, .baud = CONFIG_LPUART2_BAUD, .irq = S32K3XX_IRQ_LPUART2, @@ -1284,44 +1866,65 @@ static struct s32k3xx_uart_s g_uart2priv = .stopbits2 = CONFIG_LPUART2_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART2_CTS, + .cts_gpio = PIN_LPUART2_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART2_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART2_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART2_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART2_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART2_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart2port = -{ - .recv = - { - .size = CONFIG_LPUART2_RXBUFSIZE, - .buffer = g_uart2rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART2_TXBUFSIZE, - .buffer = g_uart2txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart2priv, +#ifdef CONFIG_LPUART2_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART210_TX, +#endif +#ifdef CONFIG_LPUART2_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART210_RX, + .rxfifo = g_lpuart2rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART3 -static struct s32k3xx_uart_s g_uart3priv = +static struct s32k3xx_uart_s g_lpuart3priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART3_RXBUFSIZE, + .buffer = g_lpuart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART3_TXBUFSIZE, + .buffer = g_lpuart3txbuffer, + }, + #if defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART3_RXDMA) && !defined(CONFIG_LPUART3_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart3priv, + }, + .uartbase = S32K3XX_LPUART3_BASE, .baud = CONFIG_LPUART3_BAUD, .irq = S32K3XX_IRQ_LPUART3, @@ -1330,44 +1933,65 @@ static struct s32k3xx_uart_s g_uart3priv = .stopbits2 = CONFIG_LPUART3_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART3_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART3_CTS, + .cts_gpio = PIN_LPUART3_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART3_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART3_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART3_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART3_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART3_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart3port = -{ - .recv = - { - .size = CONFIG_LPUART3_RXBUFSIZE, - .buffer = g_uart3rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART3_TXBUFSIZE, - .buffer = g_uart3txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart3priv, +#ifdef CONFIG_LPUART3_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART311_TX, +#endif +#ifdef CONFIG_LPUART3_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART311_RX, + .rxfifo = g_lpuart3rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART4 -static struct s32k3xx_uart_s g_uart4priv = +static struct s32k3xx_uart_s g_lpuart4priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART4_RXBUFSIZE, + .buffer = g_lpuart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART4_TXBUFSIZE, + .buffer = g_lpuart4txbuffer, + }, + #if defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART4_RXDMA) && !defined(CONFIG_LPUART4_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart4priv, + }, + .uartbase = S32K3XX_LPUART4_BASE, .baud = CONFIG_LPUART4_BAUD, .irq = S32K3XX_IRQ_LPUART4, @@ -1376,44 +2000,65 @@ static struct s32k3xx_uart_s g_uart4priv = .stopbits2 = CONFIG_LPUART4_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART4_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART4_CTS, + .cts_gpio = PIN_LPUART4_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART4_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART4_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART4_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART4_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART4_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart4port = -{ - .recv = - { - .size = CONFIG_LPUART4_RXBUFSIZE, - .buffer = g_uart4rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART4_TXBUFSIZE, - .buffer = g_uart4txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart4priv, +#ifdef CONFIG_LPUART4_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART412_TX, +#endif +#ifdef CONFIG_LPUART4_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART412_RX, + .rxfifo = g_lpuart4rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART5 -static struct s32k3xx_uart_s g_uart5priv = +static struct s32k3xx_uart_s g_lpuart5priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART5_RXBUFSIZE, + .buffer = g_lpuart5rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART5_TXBUFSIZE, + .buffer = g_lpuart5txbuffer, + }, + #if defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART5_RXDMA) && !defined(CONFIG_LPUART5_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart5priv, + }, + .uartbase = S32K3XX_LPUART5_BASE, .baud = CONFIG_LPUART5_BAUD, .irq = S32K3XX_IRQ_LPUART5, @@ -1422,44 +2067,65 @@ static struct s32k3xx_uart_s g_uart5priv = .stopbits2 = CONFIG_LPUART5_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART5_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART5_CTS, + .cts_gpio = PIN_LPUART5_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART5_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART5_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART5_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART5_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART5_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart5port = -{ - .recv = - { - .size = CONFIG_LPUART5_RXBUFSIZE, - .buffer = g_uart5rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART5_TXBUFSIZE, - .buffer = g_uart5txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart5priv, +#ifdef CONFIG_LPUART5_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART513_TX, +#endif +#ifdef CONFIG_LPUART5_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART513_RX, + .rxfifo = g_lpuart5rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART6 -static struct s32k3xx_uart_s g_uart6priv = +static struct s32k3xx_uart_s g_lpuart6priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART6_RXBUFSIZE, + .buffer = g_lpuart6rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART6_TXBUFSIZE, + .buffer = g_lpuart6txbuffer, + }, + #if defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART6_RXDMA) && !defined(CONFIG_LPUART6_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart6priv, + }, + .uartbase = S32K3XX_LPUART6_BASE, .baud = CONFIG_LPUART6_BAUD, .irq = S32K3XX_IRQ_LPUART6, @@ -1468,44 +2134,65 @@ static struct s32k3xx_uart_s g_uart6priv = .stopbits2 = CONFIG_LPUART6_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART6_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART6_CTS, + .cts_gpio = PIN_LPUART6_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART6_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART6_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART6_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART6_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART6_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart6port = -{ - .recv = - { - .size = CONFIG_LPUART6_RXBUFSIZE, - .buffer = g_uart6rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART6_TXBUFSIZE, - .buffer = g_uart6txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart6priv, +#ifdef CONFIG_LPUART6_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART614_TX, +#endif +#ifdef CONFIG_LPUART6_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART614_RX, + .rxfifo = g_lpuart6rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART7 -static struct s32k3xx_uart_s g_uart7priv = +static struct s32k3xx_uart_s g_lpuart7priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART7_RXBUFSIZE, + .buffer = g_lpuart7rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART7_TXBUFSIZE, + .buffer = g_lpuart7txbuffer, + }, + #if defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART7_RXDMA) && !defined(CONFIG_LPUART7_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart7priv, + }, + .uartbase = S32K3XX_LPUART7_BASE, .baud = CONFIG_LPUART7_BAUD, .irq = S32K3XX_IRQ_LPUART7, @@ -1514,44 +2201,65 @@ static struct s32k3xx_uart_s g_uart7priv = .stopbits2 = CONFIG_LPUART7_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART7_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART7_CTS, + .cts_gpio = PIN_LPUART7_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART7_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART7_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART7_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART7_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART7_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart7port = -{ - .recv = - { - .size = CONFIG_LPUART7_RXBUFSIZE, - .buffer = g_uart7rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART7_TXBUFSIZE, - .buffer = g_uart7txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart7priv, +#ifdef CONFIG_LPUART7_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART715_TX, +#endif +#ifdef CONFIG_LPUART7_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART715_RX, + .rxfifo = g_lpuart7rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART8 -static struct s32k3xx_uart_s g_uart8priv = +static struct s32k3xx_uart_s g_lpuart8priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART8_RXBUFSIZE, + .buffer = g_lpuart8rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART8_TXBUFSIZE, + .buffer = g_lpuart8txbuffer, + }, + #if defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART8_RXDMA) && !defined(CONFIG_LPUART8_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart8priv, + }, + .uartbase = S32K3XX_LPUART8_BASE, .baud = CONFIG_LPUART8_BAUD, .irq = S32K3XX_IRQ_LPUART8, @@ -1560,44 +2268,65 @@ static struct s32k3xx_uart_s g_uart8priv = .stopbits2 = CONFIG_LPUART8_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART8_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART8_CTS, + .cts_gpio = PIN_LPUART8_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART8_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART8_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART8_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART8_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART8_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart8port = -{ - .recv = - { - .size = CONFIG_LPUART8_RXBUFSIZE, - .buffer = g_uart8rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART8_TXBUFSIZE, - .buffer = g_uart8txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart8priv, +#ifdef CONFIG_LPUART8_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART08_TX, +#endif +#ifdef CONFIG_LPUART8_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART08_RX, + .rxfifo = g_lpuart8rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART9 -static struct s32k3xx_uart_s g_uart9priv = +static struct s32k3xx_uart_s g_lpuart9priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART9_RXBUFSIZE, + .buffer = g_lpuart9rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART9_TXBUFSIZE, + .buffer = g_lpuart9txbuffer, + }, + #if defined(CONFIG_LPUART9_RXDMA) && defined(CONFIG_LPUART9_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART9_RXDMA) && !defined(CONFIG_LPUART9_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART9_RXDMA) && defined(CONFIG_LPUART9_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart9priv, + }, + .uartbase = S32K3XX_LPUART9_BASE, .baud = CONFIG_LPUART9_BAUD, .irq = S32K3XX_IRQ_LPUART9, @@ -1606,44 +2335,65 @@ static struct s32k3xx_uart_s g_uart9priv = .stopbits2 = CONFIG_LPUART9_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART9_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART9_CTS, + .cts_gpio = PIN_LPUART9_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART9_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART9_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART9_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART9_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART9_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART9_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART9_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART9_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART9_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART9_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART9_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart9port = -{ - .recv = - { - .size = CONFIG_LPUART9_RXBUFSIZE, - .buffer = g_uart9rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART9_TXBUFSIZE, - .buffer = g_uart9txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart9priv, +#ifdef CONFIG_LPUART9_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART19_TX, +#endif +#ifdef CONFIG_LPUART9_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART19_RX, + .rxfifo = g_lpuart9rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART10 -static struct s32k3xx_uart_s g_uart10priv = +static struct s32k3xx_uart_s g_lpuart10priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART10_RXBUFSIZE, + .buffer = g_lpuart10rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART10_TXBUFSIZE, + .buffer = g_lpuart10txbuffer, + }, + #if defined(CONFIG_LPUART10_RXDMA) && defined(CONFIG_LPUART10_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART10_RXDMA) && !defined(CONFIG_LPUART10_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART10_RXDMA) && defined(CONFIG_LPUART10_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart10priv, + }, + .uartbase = S32K3XX_LPUART10_BASE, .baud = CONFIG_LPUART10_BAUD, .irq = S32K3XX_IRQ_LPUART10, @@ -1652,44 +2402,65 @@ static struct s32k3xx_uart_s g_uart10priv = .stopbits2 = CONFIG_LPUART10_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART10_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART10_CTS, + .cts_gpio = PIN_LPUART10_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART10_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART10_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART10_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART10_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART10_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART10_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART10_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART10_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART10_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART10_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART10_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart10port = -{ - .recv = - { - .size = CONFIG_LPUART10_RXBUFSIZE, - .buffer = g_uart10rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART10_TXBUFSIZE, - .buffer = g_uart10txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart10priv, +#ifdef CONFIG_LPUART10_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART210_TX, +#endif +#ifdef CONFIG_LPUART10_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART210_RX, + .rxfifo = g_lpuart10rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART11 -static struct s32k3xx_uart_s g_uart11priv = +static struct s32k3xx_uart_s g_lpuart11priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART11_RXBUFSIZE, + .buffer = g_lpuart11rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART11_TXBUFSIZE, + .buffer = g_lpuart11txbuffer, + }, + #if defined(CONFIG_LPUART11_RXDMA) && defined(CONFIG_LPUART11_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART11_RXDMA) && !defined(CONFIG_LPUART11_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART11_RXDMA) && defined(CONFIG_LPUART11_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart11priv, + }, + .uartbase = S32K3XX_LPUART11_BASE, .baud = CONFIG_LPUART11_BAUD, .irq = S32K3XX_IRQ_LPUART11, @@ -1698,44 +2469,65 @@ static struct s32k3xx_uart_s g_uart11priv = .stopbits2 = CONFIG_LPUART11_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART11_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART11_CTS, + .cts_gpio = PIN_LPUART11_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART11_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART11_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART11_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART11_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART11_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART11_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART11_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART11_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART11_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART11_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART11_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart11port = -{ - .recv = - { - .size = CONFIG_LPUART11_RXBUFSIZE, - .buffer = g_uart11rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART11_TXBUFSIZE, - .buffer = g_uart11txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart11priv, +#ifdef CONFIG_LPUART11_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART311_TX, +#endif +#ifdef CONFIG_LPUART11_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART311_RX, + .rxfifo = g_lpuart11rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART12 -static struct s32k3xx_uart_s g_uart12priv = +static struct s32k3xx_uart_s g_lpuart12priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART12_RXBUFSIZE, + .buffer = g_lpuart12rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART12_TXBUFSIZE, + .buffer = g_lpuart12txbuffer, + }, + #if defined(CONFIG_LPUART12_RXDMA) && defined(CONFIG_LPUART12_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART12_RXDMA) && !defined(CONFIG_LPUART12_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART12_RXDMA) && defined(CONFIG_LPUART12_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart12priv, + }, + .uartbase = S32K3XX_LPUART12_BASE, .baud = CONFIG_LPUART12_BAUD, .irq = S32K3XX_IRQ_LPUART12, @@ -1744,44 +2536,65 @@ static struct s32k3xx_uart_s g_uart12priv = .stopbits2 = CONFIG_LPUART12_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART12_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART12_CTS, + .cts_gpio = PIN_LPUART12_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART12_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART12_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART12_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART12_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART12_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART12_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART12_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART12_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART12_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART12_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART12_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart12port = -{ - .recv = - { - .size = CONFIG_LPUART12_RXBUFSIZE, - .buffer = g_uart12rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART12_TXBUFSIZE, - .buffer = g_uart12txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart12priv, +#ifdef CONFIG_LPUART12_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART412_TX, +#endif +#ifdef CONFIG_LPUART12_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART412_RX, + .rxfifo = g_lpuart12rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART13 -static struct s32k3xx_uart_s g_uart13priv = +static struct s32k3xx_uart_s g_lpuart13priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART13_RXBUFSIZE, + .buffer = g_lpuart13rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART13_TXBUFSIZE, + .buffer = g_lpuart13txbuffer, + }, + #if defined(CONFIG_LPUART13_RXDMA) && defined(CONFIG_LPUART13_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART13_RXDMA) && !defined(CONFIG_LPUART13_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART13_RXDMA) && defined(CONFIG_LPUART13_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart13priv, + }, + .uartbase = S32K3XX_LPUART13_BASE, .baud = CONFIG_LPUART13_BAUD, .irq = S32K3XX_IRQ_LPUART13, @@ -1790,44 +2603,65 @@ static struct s32k3xx_uart_s g_uart13priv = .stopbits2 = CONFIG_LPUART13_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART13_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART13_CTS, + .cts_gpio = PIN_LPUART13_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART13_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART13_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART13_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART13_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART13_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART13_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART13_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART13_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART13_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART13_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART13_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart13port = -{ - .recv = - { - .size = CONFIG_LPUART13_RXBUFSIZE, - .buffer = g_uart13rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART13_TXBUFSIZE, - .buffer = g_uart13txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart13priv, +#ifdef CONFIG_LPUART13_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART513_TX, +#endif +#ifdef CONFIG_LPUART13_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART513_RX, + .rxfifo = g_lpuart13rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART14 -static struct s32k3xx_uart_s g_uart14priv = +static struct s32k3xx_uart_s g_lpuart14priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART14_RXBUFSIZE, + .buffer = g_lpuart14rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART14_TXBUFSIZE, + .buffer = g_lpuart14txbuffer, + }, + #if defined(CONFIG_LPUART14_RXDMA) && defined(CONFIG_LPUART14_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART14_RXDMA) && !defined(CONFIG_LPUART14_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART14_RXDMA) && defined(CONFIG_LPUART14_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart14priv, + }, + .uartbase = S32K3XX_LPUART14_BASE, .baud = CONFIG_LPUART14_BAUD, .irq = S32K3XX_IRQ_LPUART14, @@ -1836,44 +2670,65 @@ static struct s32k3xx_uart_s g_uart14priv = .stopbits2 = CONFIG_LPUART14_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART14_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART14_CTS, + .cts_gpio = PIN_LPUART14_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART14_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART14_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART14_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART14_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART14_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART14_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART14_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART14_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART14_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART14_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART14_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart14port = -{ - .recv = - { - .size = CONFIG_LPUART14_RXBUFSIZE, - .buffer = g_uart14rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART14_TXBUFSIZE, - .buffer = g_uart14txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart14priv, +#ifdef CONFIG_LPUART14_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART614_TX, +#endif +#ifdef CONFIG_LPUART14_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART614_RX, + .rxfifo = g_lpuart14rxfifo, +#endif }; #endif #ifdef CONFIG_S32K3XX_LPUART15 -static struct s32k3xx_uart_s g_uart15priv = +static struct s32k3xx_uart_s g_lpuart15priv = { + .dev = + { + .recv = + { + .size = CONFIG_LPUART15_RXBUFSIZE, + .buffer = g_lpuart15rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART15_TXBUFSIZE, + .buffer = g_lpuart15txbuffer, + }, + #if defined(CONFIG_LPUART15_RXDMA) && defined(CONFIG_LPUART15_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART15_RXDMA) && !defined(CONFIG_LPUART15_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART15_RXDMA) && defined(CONFIG_LPUART15_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + .priv = &g_lpuart15priv, + }, + .uartbase = S32K3XX_LPUART15_BASE, .baud = CONFIG_LPUART15_BAUD, .irq = S32K3XX_IRQ_LPUART15, @@ -1882,38 +2737,35 @@ static struct s32k3xx_uart_s g_uart15priv = .stopbits2 = CONFIG_LPUART15_2STOP, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART15_OFLOWCONTROL) .oflow = 1, - .cts_gpio = GPIO_LPUART15_CTS, + .cts_gpio = PIN_LPUART15_CTS, #endif #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART15_IFLOWCONTROL) .iflow = 1, #endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART15_RS485RTSCONTROL)) || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART15_IFLOWCONTROL))) - .rts_gpio = GPIO_LPUART15_RTS, +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART15_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART15_IFLOWCONTROL))) + .rts_gpio = PIN_LPUART15_RTS, +#endif +#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE + .tx_gpio = PIN_LPUART15_TX, #endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) && defined(CONFIG_LPUART15_INVERTIFLOWCONTROL)) +#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART15_INVERTIFLOWCONTROL) .inviflow = 1, #endif #if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART15_RS485RTSCONTROL) .rs485mode = 1, #endif -}; -static struct uart_dev_s g_uart15port = -{ - .recv = - { - .size = CONFIG_LPUART15_RXBUFSIZE, - .buffer = g_uart15rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART15_TXBUFSIZE, - .buffer = g_uart15txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart15priv, +#ifdef CONFIG_LPUART15_TXDMA + .dma_txreqsrc = DMA_REQ_LPUART715_TX, +#endif +#ifdef CONFIG_LPUART15_RXDMA + .dma_rxreqsrc = DMA_REQ_LPUART715_RX, + .rxfifo = g_lpuart15rxfifo, +#endif }; #endif @@ -1949,6 +2801,24 @@ static inline void s32k3xx_serialout(struct s32k3xx_uart_s *priv, putreg32(value, priv->uartbase + offset); } +/**************************************************************************** + * Name: s32k3xx_dma_nextrx + * + * Description: + * Returns the index into the RX FIFO where the DMA will place the next + * byte that it receives. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static int s32k3xx_dma_nextrx(struct s32k3xx_uart_s *priv) +{ + int dmaresidual = s32k3xx_dmach_getcount(priv->rxdma); + + return RXDMA_BUFFER_SIZE - dmaresidual; +} +#endif + /**************************************************************************** * Name: s32k3xx_disableuartint ****************************************************************************/ @@ -1996,12 +2866,138 @@ static inline void s32k3xx_restoreuartint(struct s32k3xx_uart_s *priv, spin_unlock_irqrestore(NULL, flags); } +/**************************************************************************** + * Name: s32k3xx_dma_setup + * + * Description: + * Configure the LPUART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) +static int s32k3xx_dma_setup(struct uart_dev_s *dev) +{ + struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)dev; +#if defined(SERIAL_HAVE_RXDMA) + struct s32k3xx_edma_xfrconfig_s config; +#endif + int result; + + /* Do the basic UART setup first, unless we are the console */ + + if (!dev->isconsole) + { + result = s32k3xx_setup(dev); + if (result != OK) + { + return result; + } + } + +#if defined(SERIAL_HAVE_TXDMA) + /* Acquire the Tx DMA channel. This should always succeed. */ + + if (priv->dma_txreqsrc != 0) + { + if (priv->txdma == NULL) + { + priv->txdma = s32k3xx_dmach_alloc(priv->dma_txreqsrc | + DMAMUX_CHCFG_ENBL, 0); + if (priv->txdma == NULL) + { + return -EBUSY; + } + + nxsem_init(&priv->txdmasem, 0, 1); + nxsem_set_protocol(&priv->txdmasem, SEM_PRIO_NONE); + } + + /* Enable Tx DMA for the UART */ + + modifyreg32(priv->uartbase + S32K3XX_LPUART_BAUD_OFFSET, + 0, LPUART_BAUD_TDMAE); + } +#endif + +#if defined(SERIAL_HAVE_RXDMA) + /* Acquire the Rx DMA channel. This should always succeed. */ + + if (priv->dma_rxreqsrc != 0) + { + if (priv->rxdma == NULL) + { + priv->rxdma = s32k3xx_dmach_alloc(priv->dma_rxreqsrc | + DMAMUX_CHCFG_ENBL, 0); + + if (priv->rxdma == NULL) + { + return -EBUSY; + } + } + else + { + s32k3xx_dmach_stop(priv->rxdma); + } + + /* Configure for circular DMA reception into the RX FIFO */ + + config.saddr = priv->uartbase + S32K3XX_LPUART_DATA_OFFSET; + config.daddr = (uint32_t) priv->rxfifo; + config.soff = 0; + config.doff = 1; + config.iter = RXDMA_BUFFER_SIZE; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE | + EDMA_CONFIG_LOOPDEST | + EDMA_CONFIG_INTHALF | + EDMA_CONFIG_INTMAJOR; + config.ssize = EDMA_8BIT; + config.dsize = EDMA_8BIT; + config.nbytes = 1; + #ifdef CONFIG_KINETIS_EDMA_ELINK + config.linkch = 0; + #endif + + s32k3xx_dmach_xfrsetup(priv->rxdma , &config); + + /* Reset our DMA shadow pointer and Rx data availability count to + * match the address just programmed above. + */ + + priv->rxdmanext = 0; + + /* Enable receive Rx DMA for the UART */ + + modifyreg32(priv->uartbase + S32K3XX_LPUART_BAUD_OFFSET, + 0, LPUART_BAUD_RDMAE); + + /* Enable itnerrupt on Idel and erros */ + + modifyreg32(priv->uartbase + S32K3XX_LPUART_CTRL_OFFSET, 0, + LPUART_CTRL_PEIE | + LPUART_CTRL_FEIE | + LPUART_CTRL_NEIE | + LPUART_CTRL_ILIE); + + /* Start the DMA channel, and arrange for callbacks at the half and + * full points in the FIFO. This ensures that we have half a FIFO + * worth of time to claim bytes before they are overwritten. + */ + + s32k3xx_dmach_start(priv->rxdma, s32k3xx_dma_rxcallback, (void *)priv); + } +#endif + + return OK; +} +#endif + /**************************************************************************** * Name: s32k3xx_setup * * Description: * Configure the UART baud, bits, parity, fifos, etc. This - * method is called the first time that the serial port is + * method is called the first time that the serial priv is * opened. * ****************************************************************************/ @@ -2023,11 +3019,17 @@ static int s32k3xx_setup(struct uart_dev_s *dev) config.parity = priv->parity; /* 0=none, 1=odd, 2=even */ config.bits = priv->bits; /* Number of bits (5-9) */ config.stopbits2 = priv->stopbits2; /* true: Configure with 2 stop bits instead of 1 */ -#ifdef CONFIG_SERIAL_IFLOWCONTROL - config.usects = priv->iflow; /* Flow control on inbound side */ -#endif #ifdef CONFIG_SERIAL_OFLOWCONTROL - config.userts = priv->oflow; /* Flow control on outbound side */ + config.usects = priv->oflow; /* Flow control on outbound side */ +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + /* Flow control on outbound side if not GPIO based */ + + if ((priv->rts_gpio & _PIN_MODE_MASK) != _PIN_MODE_GPIO) + { + config.userts = priv->iflow; + } + #endif #ifdef CONFIG_SERIAL_RS485CONTROL config.users485 = priv->rs485mode; /* Switch into RS485 mode */ @@ -2054,7 +3056,7 @@ static int s32k3xx_setup(struct uart_dev_s *dev) * * Description: * Disable the UART. This method is called when the serial - * port is closed + * priv is closed * ****************************************************************************/ @@ -2067,17 +3069,66 @@ static void s32k3xx_shutdown(struct uart_dev_s *dev) s32k3xx_serialout(priv, S32K3XX_LPUART_GLOBAL_OFFSET, LPUART_GLOBAL_RST); } +/**************************************************************************** + * Name: s32k3xx_dma_shutdown + * + * Description: + * Disable the LPUART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) +static void s32k3xx_dma_shutdown(struct uart_dev_s *dev) +{ + struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)dev; + + /* Perform the normal UART shutdown */ + + s32k3xx_shutdown(dev); + +#if defined(SERIAL_HAVE_RXDMA) + /* Stop the RX DMA channel */ + + if (priv->dma_rxreqsrc != 0) + { + s32k3xx_dmach_stop(priv->rxdma); + + /* Release the RX DMA channel */ + + s32k3xx_dmach_free(priv->rxdma); + priv->rxdma = NULL; + } +#endif + +#if defined(SERIAL_HAVE_TXDMA) + /* Stop the TX DMA channel */ + + if (priv->dma_txreqsrc != 0) + { + s32k3xx_dmach_stop(priv->txdma); + + /* Release the TX DMA channel */ + + s32k3xx_dmach_free(priv->txdma); + priv->txdma = NULL; + nxsem_destroy(&priv->txdmasem); + } +#endif +} +#endif + /**************************************************************************** * Name: s32k3xx_attach * * Description: * Configure the UART to operation in interrupt driven mode. This method - * is called when the serial port is opened. Normally, this is just after + * is called when the serial priv is opened. Normally, this is just after * the setup() method is called, however, the serial console may operate * in a non-interrupt driven mode during the boot phase. * * RX and TX interrupts are not enabled when by the attach method (unless - * the hardware supports multiple levels of interrupt enabling). The RX + * the hardware supprivs multiple levels of interrupt enabling). The RX * and TX interrupts are not enabled until the txint() and rxint() methods * are called. * @@ -2107,7 +3158,7 @@ static int s32k3xx_attach(struct uart_dev_s *dev) * Name: s32k3xx_detach * * Description: - * Detach UART interrupts. This method is called when the serial port is + * Detach UART interrupts. This method is called when the serial priv is * closed normally just before the shutdown method is called. The * exception is the serial console which is never shutdown. * @@ -2136,15 +3187,15 @@ static int s32k3xx_interrupt(int irq, void *context, void *arg) struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct s32k3xx_uart_s *priv; uint32_t usr; - uint32_t hld; + uint32_t lsr; int passes = 0; bool handled; - DEBUGASSERT(dev != NULL && dev->priv != NULL); + DEBUGASSERT(dev != NULL && dev != NULL); priv = (struct s32k3xx_uart_s *)dev->priv; #if defined(CONFIG_PM) && CONFIG_S32K3XX_PM_SERIAL_ACTIVITY > 0 - /* Report serial activity to the power management logic */ + /* Repriv serial activity to the power management logic */ pm_activity(PM_IDLE_DOMAIN, CONFIG_S32K3XX_PM_SERIAL_ACTIVITY); #endif @@ -2163,26 +3214,65 @@ static int s32k3xx_interrupt(int irq, void *context, void *arg) */ usr = s32k3xx_serialin(priv, S32K3XX_LPUART_STAT_OFFSET); - hld = usr & (LPUART_STAT_MSBF | LPUART_STAT_RXINV | - LPUART_STAT_RWUID | LPUART_STAT_BRK13 | LPUART_STAT_LBKDE | - LPUART_STAT_AME | LPUART_STAT_LBKFE); - usr &= (LPUART_STAT_RDRF | LPUART_STAT_TC | LPUART_STAT_OR | - LPUART_STAT_FE | LPUART_STAT_RXINV); - /* Clear serial overrun and framing errors */ + /* Removed all W1C from the last sr */ + + lsr = usr & ~(LPUART_STAT_LBKDIF | LPUART_STAT_RXEDGIF | + LPUART_STAT_IDLE | LPUART_STAT_OR | + LPUART_STAT_NF | LPUART_STAT_FE | + LPUART_STAT_PF | LPUART_STAT_MA1F | + LPUART_STAT_MA2F); + + /* Keep what we will service */ + + usr &= (LPUART_STAT_RDRF | LPUART_STAT_TDRE | LPUART_STAT_OR | + LPUART_STAT_FE | LPUART_STAT_NF | LPUART_STAT_PF | + LPUART_STAT_IDLE); + + /* Clear serial overrun, parity and framing errors */ if ((usr & LPUART_STAT_OR) != 0) { s32k3xx_serialout(priv, S32K3XX_LPUART_STAT_OFFSET, - LPUART_STAT_OR | hld); + LPUART_STAT_OR | lsr); + } + + if ((usr & LPUART_STAT_NF) != 0) + { + s32k3xx_serialout(priv, S32K3XX_LPUART_STAT_OFFSET, + LPUART_STAT_NF | lsr); + } + + if ((usr & LPUART_STAT_PF) != 0) + { + s32k3xx_serialout(priv, S32K3XX_LPUART_STAT_OFFSET, + LPUART_STAT_PF | lsr); } if ((usr & LPUART_STAT_FE) != 0) { s32k3xx_serialout(priv, S32K3XX_LPUART_STAT_OFFSET, - LPUART_STAT_FE | hld); + LPUART_STAT_FE | lsr); } + if ((usr & (LPUART_STAT_FE | LPUART_STAT_PF | LPUART_STAT_NF)) != 0) + { + /* Discard data */ + + s32k3xx_serialin(priv, S32K3XX_LPUART_DATA_OFFSET); + } + +#ifdef SERIAL_HAVE_RXDMA + /* The line going to idle, deliver any fractions of RX data */ + + if ((usr & LPUART_STAT_IDLE) != 0) + { + s32k3xx_serialout(priv, S32K3XX_LPUART_STAT_OFFSET, + LPUART_STAT_IDLE | lsr); + s32k3xx_dma_rxcallback(priv->rxdma, priv, false, LPUART_STAT_IDLE); + } +#endif + /* Handle incoming, receive bytes */ if ((usr & LPUART_STAT_RDRF) != 0 && @@ -2194,8 +3284,8 @@ static int s32k3xx_interrupt(int irq, void *context, void *arg) /* Handle outgoing, transmit bytes */ - if ((usr & LPUART_STAT_TC) != 0 && - (priv->ie & LPUART_CTRL_TCIE) != 0) + if ((usr & LPUART_STAT_TDRE) != 0 && + (priv->ie & LPUART_CTRL_TIE) != 0) { uart_xmitchars(dev); handled = true; @@ -2218,6 +3308,7 @@ static int s32k3xx_ioctl(struct file *filep, int cmd, unsigned long arg) #if defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || defined(CONFIG_SERIAL_TERMIOS) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; + irqstate_t flags; #endif int ret = OK; @@ -2293,9 +3384,11 @@ static int s32k3xx_ioctl(struct file *filep, int cmd, unsigned long arg) termiosp->c_cflag |= CS8; break; +#if defined(CS9) case 9: - termiosp->c_cflag |= CS8 /* CS9 */; + termiosp->c_cflag |= CS9; break; +#endif } } break; @@ -2347,7 +3440,8 @@ static int s32k3xx_ioctl(struct file *filep, int cmd, unsigned long arg) case CS8: nbits = 8; break; -#if 0 + +#if defined(CS9) case CS9: nbits = 9; break; @@ -2392,13 +3486,15 @@ static int s32k3xx_ioctl(struct file *filep, int cmd, unsigned long arg) * implement TCSADRAIN / TCSAFLUSH */ + flags = spin_lock_irqsave(NULL); s32k3xx_disableuartint(priv, &ie); - ret = s32k3xx_setup(dev); + ret = dev->ops->setup(dev); /* Restore the interrupt state */ s32k3xx_restoreuartint(priv, ie); priv->ie = ie; + spin_unlock_irqrestore(NULL, flags); } } break; @@ -2503,6 +3599,7 @@ static int s32k3xx_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ +#ifndef SERIAL_HAVE_ONLY_RXDMA static int s32k3xx_receive(struct uart_dev_s *dev, unsigned int *status) { struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)dev->priv; @@ -2512,6 +3609,7 @@ static int s32k3xx_receive(struct uart_dev_s *dev, unsigned int *status) *status = rxd >> LPUART_DATA_STATUS_SHIFT; return (rxd & LPUART_DATA_MASK) >> LPUART_DATA_SHIFT; } +#endif /**************************************************************************** * Name: s32k3xx_rxint @@ -2521,6 +3619,7 @@ static int s32k3xx_receive(struct uart_dev_s *dev, unsigned int *status) * ****************************************************************************/ +#ifndef SERIAL_HAVE_ONLY_RXDMA static void s32k3xx_rxint(struct uart_dev_s *dev, bool enable) { struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)dev->priv; @@ -2547,6 +3646,7 @@ static void s32k3xx_rxint(struct uart_dev_s *dev, bool enable) s32k3xx_serialout(priv, S32K3XX_LPUART_CTRL_OFFSET, regval); spin_unlock_irqrestore(NULL, flags); } +#endif /**************************************************************************** * Name: s32k3xx_rxavailable @@ -2556,6 +3656,7 @@ static void s32k3xx_rxint(struct uart_dev_s *dev, bool enable) * ****************************************************************************/ +#ifndef SERIAL_HAVE_ONLY_RXDMA static bool s32k3xx_rxavailable(struct uart_dev_s *dev) { struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)dev->priv; @@ -2566,6 +3667,369 @@ static bool s32k3xx_rxavailable(struct uart_dev_s *dev) regval = s32k3xx_serialin(priv, S32K3XX_LPUART_STAT_OFFSET); return ((regval & LPUART_STAT_RDRF) != 0); } +#endif + +/**************************************************************************** + * Name: s32k3xx_rxflowcontrol + * + * Description: + * Called when Rx buffer is full (or exceeds configured watermark levels + * if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined). + * Return true if UART activated RX flow control to block more incoming + * data + * + * Input Parameters: + * dev - UART device instance + * nbuffered - the number of characters currently buffered + * (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is + * not defined the value will be 0 for an empty buffer or the + * defined buffer size for a full buffer) + * upper - true indicates the upper watermark was crossed where + * false indicates the lower watermark has been crossed + * + * Returned Value: + * true if RX flow control activated. + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool s32k3xx_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper) +{ + struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)dev; + bool use_swhs = false; + +#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) + use_swhs = (priv->rts_gpio & _PIN_MODE_MASK) == _PIN_MODE_GPIO; +#endif + + if (use_swhs && priv->iflow && (priv->rts_gpio != 0)) + { + /* Assert/de-assert nRTS set it high resume/stop sending */ + + s32k3xx_gpiowrite(priv->rts_gpio, upper); + + if (upper) + { + /* With heavy Rx traffic, RXNE might be set and data pending. + * Returning 'true' in such case would cause RXNE left unhandled + * and causing interrupt storm. Sending end might be also be slow + * to react on nRTS, and returning 'true' here would prevent + * processing that data. + * + * Therefore, return 'false' so input data is still being processed + * until sending end reacts on nRTS signal and stops sending more. + */ + + return false; + } + + return upper; + } + else + { + /* Is the RX buffer full? */ + + if (upper) + { + /* Disable Rx interrupt to prevent more data being from + * peripheral. When hardware RTS is enabled, this will + * prevent more data from coming in. + * + * This function is only called when UART recv buffer is full, + * that is: "dev->recv.head + 1 == dev->recv.tail". + * + * Logic in "uart_read" will automatically toggle Rx interrupts + * when buffer is read empty and thus we do not have to re- + * enable Rx interrupts. + */ + + uart_disablerxint(dev); + return true; + } + + /* No.. The RX buffer is empty */ + + else + { + /* We might leave Rx interrupt disabled if full recv buffer was + * read empty. Enable Rx interrupt to make sure that more input is + * received. + */ + + uart_enablerxint(dev); + } + } + + return false; +} +#endif + +/**************************************************************************** + * Name: s32k3xx_dma_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the LPUART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static int s32k3xx_dma_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)dev; + uint32_t nextrx = s32k3xx_dma_nextrx(priv); + int c = 0; + + /* Check if more data is available */ + + if (nextrx != priv->rxdmanext) + { + /* Now read from the DMA buffer */ + + c = priv->rxfifo[priv->rxdmanext]; + + priv->rxdmanext++; + + if (priv->rxdmanext == RXDMA_BUFFER_SIZE) + { + priv->rxdmanext = 0; + } + } + + /* NOTE: If no data is available, then we would return NULL which is, + * of course, valid binary data. The protocol is that the upper half + * driver must call s32k3xx_dma_rxavailable prior to calling this + * function to assure that this never happens. + */ + + return c; +} +#endif + +/**************************************************************************** + * Name: s32k3xx_dma_reenable + * + * Description: + * Call to re-enable RX DMA. + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_RXDMA) && defined(CONFIG_PM) +static void s32k3xx_dma_reenable(struct s32k3xx_uart_s *priv) +{ + struct s32k3xx_edma_xfrconfig_s config; + + /* Stop an reset the RX DMA */ + + s32k3xx_dmach_stop(priv->rxdma); + + /* Configure for circular DMA reception into the RX FIFO */ + + config.saddr = priv->uartbase + S32K3XX_LPUART_DATA_OFFSET; + config.daddr = (uint32_t) priv->rxfifo; + config.soff = 0; + config.doff = 1; + config.iter = RXDMA_BUFFER_SIZE; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE | + EDMA_CONFIG_LOOPDEST | + EDMA_CONFIG_INTHALF | + EDMA_CONFIG_INTMAJOR; + config.ssize = EDMA_8BIT; + config.dsize = EDMA_8BIT; + config.nbytes = 1; +#ifdef CONFIG_KINETIS_EDMA_ELINK + config.linkch = 0; +#endif + + s32k3xx_dmach_xfrsetup(priv->rxdma, &config); + + /* Reset our DMA shadow pointer and Rx data availability count to match + * the address just programmed above. + */ + + priv->rxdmanext = 0; + + /* Start the DMA channel, and arrange for callbacks at the half and + * full points in the FIFO. This ensures that we have half a FIFO + * worth of time to claim bytes before they are overwritten. + */ + + s32k3xx_dmach_start(priv->rxdma, s32k3xx_dma_rxcallback, (void *)priv); + + /* Clear DMA suspended flag. */ + + priv->rxdmasusp = false; +} +#endif + +/**************************************************************************** + * Name: s32k3xx_dma_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static void s32k3xx_dma_rxint(struct uart_dev_s *dev, bool enable) +{ + struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)dev; + + /* Enable/disable DMA reception. + * + * Note that it is not safe to check for available bytes and immediately + * pass them to uart_recvchars as that could potentially recurse back + * to us again. Instead, bytes must wait until the next up_dma_poll or + * DMA event. + */ + + priv->rxenable = enable; +} +#endif + +/**************************************************************************** + * Name: s32k3xx_dma_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static bool s32k3xx_dma_rxavailable(struct uart_dev_s *dev) +{ + struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)dev; + + /* Compare our receive pointer to the current DMA pointer, if they + * do not match, then there are bytes to be received. + */ + + return (s32k3xx_dma_nextrx(priv) != priv->rxdmanext); +} +#endif + +/**************************************************************************** + * Name: s32k3xx_dma_txcallback + * + * Description: + * This function clears dma buffer at complete of DMA transfer and wakes up + * threads waiting for space in buffer. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void s32k3xx_dma_txcallback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)arg; + /* Update 'nbytes' indicating number of bytes actually transferred by DMA. + * This is important to free TX buffer space by 'uart_xmitchars_done'. + */ + + priv->dev.dmatx.nbytes = priv->dev.dmatx.length + priv->dev.dmatx.nlength; + + /* Adjust the pointers */ + + uart_xmitchars_done(&priv->dev); + + /* Release waiter */ + + nxsem_post(&priv->txdmasem); +} +#endif + +/**************************************************************************** + * Name: s32k3xx_dma_txavailable + * + * Description: + * Informs DMA that Tx data is available and is ready for transfer. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void s32k3xx_dma_txavailable(struct uart_dev_s *dev) +{ + struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)dev; + + /* Only send when the DMA is idle */ + + nxsem_wait(&priv->txdmasem); + + uart_xmitchars_dma(dev); +} +#endif + +/**************************************************************************** + * Name: s32k3xx_dma_send + * + * Description: + * Called (usually) from the interrupt level to start DMA transfer. + * (Re-)Configures DMA Stream updating buffer and buffer length. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void s32k3xx_dma_send(struct uart_dev_s *dev) +{ + struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)dev; + struct s32k3xx_edma_xfrconfig_s config; + + /* We need to stop DMA before reconfiguration */ + + s32k3xx_dmach_stop(priv->txdma); + + /* Reset the number sent */ + + dev->dmatx.nbytes = 0; + + /* Make use of setup function to update buffer and its length for next + * transfer + */ + + config.iter = dev->dmatx.length; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; + config.ssize = EDMA_8BIT; + config.dsize = EDMA_8BIT; + config.nbytes = sizeof(dev->dmatx.buffer[0]); + config.saddr = (uint32_t) dev->dmatx.buffer; + config.daddr = priv->uartbase + S32K3XX_LPUART_DATA_OFFSET; + config.soff = sizeof(dev->dmatx.buffer[0]); + config.doff = 0; +#ifdef CONFIG_S32K3XX_EDMA_ELINK + config.linkch = 0; +#endif + + /* Flush the contents of the TX buffer into physical memory */ + + up_clean_dcache((uintptr_t)dev->dmatx.buffer, + (uintptr_t)dev->dmatx.buffer + dev->dmatx.length); + + /* Setup first half */ + + s32k3xx_dmach_xfrsetup(priv->txdma, &config); + + /* Is this a split transfer? */ + + if (dev->dmatx.nbuffer) + { + config.iter = priv->dev.dmatx.nlength; + config.saddr = (uint32_t) priv->dev.dmatx.nbuffer; + + /* Flush the contents of the next TX buffer into physical memory */ + + up_clean_dcache((uintptr_t)dev->dmatx.nbuffer, + (uintptr_t)dev->dmatx.nbuffer + dev->dmatx.nlength); + + s32k3xx_dmach_xfrsetup(priv->txdma, &config); + } + + /* Start transmission with the callback on DMA completion */ + + s32k3xx_dmach_start(priv->txdma, s32k3xx_dma_txcallback, (void *)priv); +} +#endif /**************************************************************************** * Name: s32k3xx_send @@ -2581,6 +4045,28 @@ static void s32k3xx_send(struct uart_dev_s *dev, int ch) s32k3xx_serialout(priv, S32K3XX_LPUART_DATA_OFFSET, (uint32_t)ch); } +/**************************************************************************** + * Name: s32k3xx_dma_txint + * + * Description: + * Call to enable or disable TX interrupts from the UART. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void s32k3xx_dma_txint(struct uart_dev_s *dev, bool enable) +{ + /* Nothing to do. */ + + /* In case of DMA transfer we do not want to make use of UART interrupts. + * Instead, we use DMA interrupts that are activated once during boot + * sequence. Furthermore we can use s32k3xx_dma_txcallback() to handle + * stuff at half DMA transfer or after transfer completion (depending + * on the configuration). + */ +} +#endif + /**************************************************************************** * Name: s32k3xx_txint * @@ -2589,6 +4075,7 @@ static void s32k3xx_send(struct uart_dev_s *dev, int ch) * ****************************************************************************/ +#if !defined(SERIAL_HAVE_ONLY_TXDMA) static void s32k3xx_txint(struct uart_dev_s *dev, bool enable) { struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)dev->priv; @@ -2601,12 +4088,12 @@ static void s32k3xx_txint(struct uart_dev_s *dev, bool enable) if (enable) { #ifndef CONFIG_SUPPRESS_SERIAL_INTS - priv->ie |= LPUART_CTRL_TCIE; + priv->ie |= LPUART_CTRL_TIE; #endif } else { - priv->ie &= ~LPUART_CTRL_TCIE; + priv->ie &= ~LPUART_CTRL_TIE; } regval = s32k3xx_serialin(priv, S32K3XX_LPUART_CTRL_OFFSET); @@ -2615,22 +4102,23 @@ static void s32k3xx_txint(struct uart_dev_s *dev, bool enable) s32k3xx_serialout(priv, S32K3XX_LPUART_CTRL_OFFSET, regval); spin_unlock_irqrestore(NULL, flags); } +#endif /**************************************************************************** * Name: s32k3xx_txready * * Description: - * Return true if the transmit is completed + * Return true if the transmit register is available to be written to * ****************************************************************************/ static bool s32k3xx_txready(struct uart_dev_s *dev) { - struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)dev->priv; + struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)dev; uint32_t regval; regval = s32k3xx_serialin(priv, S32K3XX_LPUART_STAT_OFFSET); - return ((regval & LPUART_STAT_TC) != 0); + return ((regval & LPUART_STAT_TDRE) != 0); } /**************************************************************************** @@ -2650,12 +4138,57 @@ static bool s32k3xx_txempty(struct uart_dev_s *dev) return ((regval & LPUART_STAT_TDRE) != 0); } +/**************************************************************************** + * Name: s32k3xx_dma_rxcallback + * + * Description: + * This function checks the current DMA state and calls the generic + * serial stack when bytes appear to be available. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static void s32k3xx_dma_rxcallback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)arg; + uint32_t sr; + + up_invalidate_dcache((uintptr_t)priv->rxfifo, + (uintptr_t)priv->rxfifo + RXDMA_BUFFER_SIZE); + + if (priv->rxenable && s32k3xx_dma_rxavailable(&priv->dev)) + { + uart_recvchars(&priv->dev); + } + + /* Get the masked LPUART status word to check and clear error flags. + * + * When wake-up from low power mode was not fast enough, UART is resumed + * too late and sometimes exactly when character was coming over UART, + * resulting to frame error. + * If error flag is not cleared, Rx DMA will be stuck. Clearing errors + * will release Rx DMA. + */ + + sr = s32k3xx_serialin(priv, S32K3XX_LPUART_STAT_OFFSET); + + if ((sr & (LPUART_STAT_OR | LPUART_STAT_NF | LPUART_STAT_FE)) != 0) + { + s32k3xx_serialout(priv, S32K3XX_LPUART_STAT_OFFSET, + sr & (LPUART_STAT_OR | + LPUART_STAT_NF | + LPUART_STAT_FE)); + } +} +#endif + /**************************************************************************** * Name: up_pm_notify * * Description: * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. + * all drivers have had the opprivunity to prepare for the new power state. * * Input Parameters: * @@ -2780,8 +4313,8 @@ void s32k3xx_earlyserialinit(void) */ #ifdef CONSOLE_DEV - CONSOLE_DEV.isconsole = true; - s32k3xx_setup(&CONSOLE_DEV); + CONSOLE_DEV.dev.isconsole = true; + s32k3xx_setup(&CONSOLE_DEV.dev); #endif } @@ -2789,7 +4322,7 @@ void s32k3xx_earlyserialinit(void) * Name: arm_serialinit * * Description: - * Register serial console and serial ports. This assumes + * Register serial console and serial privs. This assumes * that s32k3xx_earlyserialinit was called previously. * ****************************************************************************/ @@ -2807,56 +4340,59 @@ void arm_serialinit(void) #endif #ifdef CONSOLE_DEV - uart_register("/dev/console", &CONSOLE_DEV); + uart_register("/dev/console", &CONSOLE_DEV.dev); +#if defined(SERIAL_HAVE_CONSOLE_DMA) + s32k3xx_dma_setup(&CONSOLE_DEV.dev); +#endif #endif /* Register all UARTs */ - uart_register("/dev/ttyS0", &TTYS0_DEV); + uart_register("/dev/ttyS0", &TTYS0_DEV.dev); #ifdef TTYS1_DEV - uart_register("/dev/ttyS1", &TTYS1_DEV); + uart_register("/dev/ttyS1", &TTYS1_DEV.dev); #endif #ifdef TTYS2_DEV - uart_register("/dev/ttyS2", &TTYS2_DEV); + uart_register("/dev/ttyS2", &TTYS2_DEV.dev); #endif #ifdef TTYS3_DEV - uart_register("/dev/ttyS3", &TTYS3_DEV); + uart_register("/dev/ttyS3", &TTYS3_DEV.dev); #endif #ifdef TTYS4_DEV - uart_register("/dev/ttyS4", &TTYS4_DEV); + uart_register("/dev/ttyS4", &TTYS4_DEV.dev); #endif #ifdef TTYS5_DEV - uart_register("/dev/ttyS5", &TTYS5_DEV); + uart_register("/dev/ttyS5", &TTYS5_DEV.dev); #endif #ifdef TTYS6_DEV - uart_register("/dev/ttyS6", &TTYS6_DEV); + uart_register("/dev/ttyS6", &TTYS6_DEV.dev); #endif #ifdef TTYS7_DEV - uart_register("/dev/ttyS7", &TTYS7_DEV); + uart_register("/dev/ttyS7", &TTYS7_DEV.dev); #endif #ifdef TTYS8_DEV - uart_register("/dev/ttyS8", &TTYS8_DEV); + uart_register("/dev/ttyS8", &TTYS8_DEV.dev); #endif #ifdef TTYS9_DEV - uart_register("/dev/ttyS9", &TTYS9_DEV); + uart_register("/dev/ttyS9", &TTYS9_DEV.dev); #endif #ifdef TTYS10_DEV - uart_register("/dev/ttyS10", &TTYS10_DEV); + uart_register("/dev/ttyS10", &TTYS10_DEV.dev); #endif #ifdef TTYS11_DEV - uart_register("/dev/ttyS11", &TTYS11_DEV); + uart_register("/dev/ttyS11", &TTYS11_DEV.dev); #endif #ifdef TTYS12_DEV - uart_register("/dev/ttyS12", &TTYS12_DEV); + uart_register("/dev/ttyS12", &TTYS12_DEV.dev); #endif #ifdef TTYS13_DEV - uart_register("/dev/ttyS13", &TTYS13_DEV); + uart_register("/dev/ttyS13", &TTYS13_DEV.dev); #endif #ifdef TTYS14_DEV - uart_register("/dev/ttyS14", &TTYS14_DEV); + uart_register("/dev/ttyS14", &TTYS14_DEV.dev); #endif #ifdef TTYS15_DEV - uart_register("/dev/ttyS15", &TTYS15_DEV); + uart_register("/dev/ttyS15", &TTYS15_DEV.dev); #endif } @@ -2864,14 +4400,14 @@ void arm_serialinit(void) * Name: up_putc * * Description: - * Provide priority, low-level access to support OS debug writes + * Provide priority, low-level access to suppriv OS debug writes * ****************************************************************************/ int up_putc(int ch) { #ifdef CONSOLE_DEV - struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)CONSOLE_DEV.priv; + struct s32k3xx_uart_s *priv = (struct s32k3xx_uart_s *)&CONSOLE_DEV; uint32_t ie; s32k3xx_disableuartint(priv, &ie); @@ -2898,7 +4434,7 @@ int up_putc(int ch) * Name: up_putc * * Description: - * Provide priority, low-level access to support OS debug writes + * Provide priority, low-level access to suppriv OS debug writes * ****************************************************************************/ diff --git a/arch/arm/src/s32k3xx/s32k3xx_serial.h b/arch/arm/src/s32k3xx/s32k3xx_serial.h index 92b5071d8a..d1712bbaa8 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_serial.h +++ b/arch/arm/src/s32k3xx/s32k3xx_serial.h @@ -36,6 +36,347 @@ * Pre-processor Definitions ****************************************************************************/ +#if defined(CONFIG_S32K3XX_LPUART0) || defined(CONFIG_S32K3XX_LPUART1) || \ + defined(CONFIG_S32K3XX_LPUART2) || defined(CONFIG_S32K3XX_LPUART3) || \ + defined(CONFIG_S32K3XX_LPUART3) || defined(CONFIG_S32K3XX_LPUART5) || \ + defined(CONFIG_S32K3XX_LPUART6) || defined(CONFIG_S32K3XX_LPUART7) || \ + defined(CONFIG_S32K3XX_LPUART8) || defined(CONFIG_S32K3XX_LPUART9) || \ + defined(CONFIG_S32K3XX_LPUART10) || defined(CONFIG_S32K3XX_LPUART11) || \ + defined(CONFIG_S32K3XX_LPUART12) || defined(CONFIG_S32K3XX_LPUART13) || \ + defined(CONFIG_S32K3XX_LPUART14) || defined(CONFIG_S32K3XX_LPUART15) +# define HAVE_UART 1 +#endif + +/* Assume DMA is not used on the console UART */ + +#undef SERIAL_HAVE_CONSOLE_RXDMA +#undef SERIAL_HAVE_CONSOLE_TXDMA + +#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA) +# undef CONFIG_LPUART0_RXDMA +# undef CONFIG_LPUART0_TXDMA +# undef CONFIG_LPUART1_RXDMA +# undef CONFIG_LPUART1_TXDMA +# undef CONFIG_LPUART2_RXDMA +# undef CONFIG_LPUART2_TXDMA +# undef CONFIG_LPUART3_RXDMA +# undef CONFIG_LPUART3_TXDMA +# undef CONFIG_LPUART4_RXDMA +# undef CONFIG_LPUART4_TXDMA +# undef CONFIG_LPUART5_RXDMA +# undef CONFIG_LPUART5_TXDMA +# undef CONFIG_LPUART6_RXDMA +# undef CONFIG_LPUART6_TXDMA +# undef CONFIG_LPUART7_RXDMA +# undef CONFIG_LPUART7_TXDMA +# undef CONFIG_LPUART8_RXDMA +# undef CONFIG_LPUART8_TXDMA +# undef CONFIG_LPUART9_RXDMA +# undef CONFIG_LPUART9_TXDMA +# undef CONFIG_LPUART10_RXDMA +# undef CONFIG_LPUART10_TXDMA +# undef CONFIG_LPUART11_RXDMA +# undef CONFIG_LPUART11_TXDMA +# undef CONFIG_LPUART12_RXDMA +# undef CONFIG_LPUART12_TXDMA +# undef CONFIG_LPUART13_RXDMA +# undef CONFIG_LPUART13_TXDMA +# undef CONFIG_LPUART14_RXDMA +# undef CONFIG_LPUART14_TXDMA +# undef CONFIG_LPUART15_RXDMA +# undef CONFIG_LPUART15_TXDMA +#endif + +/* Disable the DMA configuration on all unused LPUARTs */ + +#ifndef CONFIG_S32K3XX_LPUART1 +# undef CONFIG_LPUART1_RXDMA +# undef CONFIG_LPUART1_TXDMA +#endif + +#ifndef CONFIG_S32K3XX_LPUART2 +# undef CONFIG_LPUART2_RXDMA +# undef CONFIG_LPUART2_TXDMA +#endif + +#ifndef CONFIG_S32K3XX_LPUART3 +# undef CONFIG_LPUART3_RXDMA +# undef CONFIG_LPUART3_TXDMA +#endif + +#ifndef CONFIG_S32K3XX_LPUART4 +# undef CONFIG_LPUART4_RXDMA +# undef CONFIG_LPUART4_TXDMA +#endif + +#ifndef CONFIG_S32K3XX_LPUART5 +# undef CONFIG_LPUART5_RXDMA +# undef CONFIG_LPUART5_TXDMA +#endif + +#ifndef CONFIG_S32K3XX_LPUART6 +# undef CONFIG_LPUART6_RXDMA +# undef CONFIG_LPUART6_TXDMA +#endif + +#ifndef CONFIG_S32K3XX_LPUART7 +# undef CONFIG_LPUART7_RXDMA +# undef CONFIG_LPUART7_TXDMA +#endif + +#ifndef CONFIG_S32K3XX_LPUART8 +# undef CONFIG_LPUART8_RXDMA +# undef CONFIG_LPUART8_TXDMA +#endif + +#ifndef CONFIG_S32K3XX_LPUART9 +# undef CONFIG_LPUART9_RXDMA +# undef CONFIG_LPUART9_TXDMA +#endif + +#ifndef CONFIG_S32K3XX_LPUART10 +# undef CONFIG_LPUART10_RXDMA +# undef CONFIG_LPUART10_TXDMA +#endif + +#ifndef CONFIG_S32K3XX_LPUART11 +# undef CONFIG_LPUART11_RXDMA +# undef CONFIG_LPUART11_TXDMA +#endif + +#ifndef CONFIG_S32K3XX_LPUART12 +# undef CONFIG_LPUART12_RXDMA +# undef CONFIG_LPUART12_TXDMA +#endif + +#ifndef CONFIG_S32K3XX_LPUART13 +# undef CONFIG_LPUART13_RXDMA +# undef CONFIG_LPUART13_TXDMA +#endif + +#ifndef CONFIG_S32K3XX_LPUART14 +# undef CONFIG_LPUART14_RXDMA +# undef CONFIG_LPUART14_TXDMA +#endif + +#ifndef CONFIG_S32K3XX_LPUART15 +# undef CONFIG_LPUART15_RXDMA +# undef CONFIG_LPUART15_TXDMA +#endif + +/* Is RX DMA available on any (enabled) LPUART? */ + +#undef SERIAL_HAVE_RXDMA +#if defined(CONFIG_LPUART0_RXDMA) || defined(CONFIG_LPUART1_RXDMA) || \ + defined(CONFIG_LPUART2_RXDMA) || defined(CONFIG_LPUART3_RXDMA) || \ + defined(CONFIG_LPUART3_RXDMA) || defined(CONFIG_LPUART5_RXDMA) || \ + defined(CONFIG_LPUART6_RXDMA) || defined(CONFIG_LPUART7_RXDMA) || \ + defined(CONFIG_LPUART8_RXDMA) || defined(CONFIG_LPUART9_RXDMA) || \ + defined(CONFIG_LPUART10_RXDMA) || defined(CONFIG_LPUART11_RXDMA) || \ + defined(CONFIG_LPUART12_RXDMA) || defined(CONFIG_LPUART13_RXDMA) || \ + defined(CONFIG_LPUART14_RXDMA) || defined(CONFIG_LPUART15_RXDMA) +# define SERIAL_HAVE_RXDMA 1 +#endif + +/* Is TX DMA available on any (enabled) LPUART? */ +#undef SERIAL_HAVE_TXDMA +#if defined(CONFIG_LPUART0_TXDMA) || defined(CONFIG_LPUART1_TXDMA) || \ + defined(CONFIG_LPUART2_TXDMA) || defined(CONFIG_LPUART3_TXDMA) || \ + defined(CONFIG_LPUART3_TXDMA) || defined(CONFIG_LPUART5_TXDMA) || \ + defined(CONFIG_LPUART6_TXDMA) || defined(CONFIG_LPUART7_TXDMA) || \ + defined(CONFIG_LPUART8_TXDMA) || defined(CONFIG_LPUART9_TXDMA) || \ + defined(CONFIG_LPUART10_TXDMA) || defined(CONFIG_LPUART11_TXDMA) || \ + defined(CONFIG_LPUART12_TXDMA) || defined(CONFIG_LPUART13_TXDMA) || \ + defined(CONFIG_LPUART14_TXDMA) || defined(CONFIG_LPUART15_TXDMA) +# define SERIAL_HAVE_TXDMA 1 +#endif + +/* Is RX DMA used on all (enabled) LPUARTs */ + +#define SERIAL_HAVE_ONLY_RXDMA 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(CONFIG_LPUART0_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(CONFIG_LPUART1_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(CONFIG_LPUART2_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(CONFIG_LPUART3_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(CONFIG_LPUART4_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(CONFIG_LPUART5_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(CONFIG_LPUART6_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(CONFIG_LPUART7_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(CONFIG_LPUART8_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(CONFIG_LPUART9_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(CONFIG_LPUART10_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(CONFIG_LPUART11_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(CONFIG_LPUART12_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(CONFIG_LPUART13_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(CONFIG_LPUART14_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(CONFIG_LPUART15_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#endif + +/* Is TX DMA used on all (enabled) LPUARTs */ + +#define SERIAL_HAVE_ONLY_TXDMA 1 +#if defined(CONFIG_S32K3XX_LPUART0) && !defined(CONFIG_LPUART0_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART1) && !defined(CONFIG_LPUART1_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART2) && !defined(CONFIG_LPUART2_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART3) && !defined(CONFIG_LPUART3_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART4) && !defined(CONFIG_LPUART4_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART5) && !defined(CONFIG_LPUART5_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART6) && !defined(CONFIG_LPUART6_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART7) && !defined(CONFIG_LPUART7_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART8) && !defined(CONFIG_LPUART8_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART9) && !defined(CONFIG_LPUART9_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART10) && !defined(CONFIG_LPUART10_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART11) && !defined(CONFIG_LPUART11_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART12) && !defined(CONFIG_LPUART12_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART13) && !defined(CONFIG_LPUART13_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART14) && !defined(CONFIG_LPUART14_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_S32K3XX_LPUART15) && !defined(CONFIG_LPUART15_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#endif + +#undef SERIAL_HAVE_ONLY_DMA +#if defined(SERIAL_HAVE_ONLY_RXDMA) && defined(SERIAL_HAVE_ONLY_TXDMA) +#define SERIAL_HAVE_ONLY_DMA +#endif + +/* Verify that DMA has been enabled and the DMA channel has been defined. + */ + +# if defined(SERIAL_HAVE_TXDMA) || defined(SERIAL_HAVE_RXDMA) +# ifndef CONFIG_S32K3XX_EDMA +# error IMXRT LPUART receive or transmit DMA requires CONFIG_S32K3XX_EDMA +# endif +# endif + +/* Verify that there are not 2 devices enabled on one DMAMUX input */ + +#if (defined(CONFIG_LPUART0_RXDMA) && defined(CONFIG_LPUART8_RXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART0_RXDMA and CONFIG_LPUART8_RXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART0_TXDMA) && defined(CONFIG_LPUART8_TXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART0_TXDMA and CONFIG_LPUART8_TXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART9_RXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART1_RXDMA and CONFIG_LPUART9_RXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART1_TXDMA) && defined(CONFIG_LPUART9_TXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART1_TXDMA and CONFIG_LPUART9_TXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART10_RXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART2_RXDMA and CONFIG_LPUART10_RXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART2_TXDMA) && defined(CONFIG_LPUART10_TXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART2_TXDMA and CONFIG_LPUART10_TXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART11_RXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART3_RXDMA and CONFIG_LPUART11_RXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART3_TXDMA) && defined(CONFIG_LPUART11_TXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART3_TXDMA and CONFIG_LPUART11_TXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART12_RXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART4_RXDMA and CONFIG_LPUART12_RXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART4_TXDMA) && defined(CONFIG_LPUART12_TXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART4_TXDMA and CONFIG_LPUART12_TXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART13_RXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART5_RXDMA and CONFIG_LPUART13_RXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART5_TXDMA) && defined(CONFIG_LPUART13_TXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART5_TXDMA and CONFIG_LPUART13_TXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART14_RXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART6_RXDMA and CONFIG_LPUART14_RXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART6_TXDMA) && defined(CONFIG_LPUART14_TXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART6_TXDMA and CONFIG_LPUART14_TXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART15_RXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART7_RXDMA and CONFIG_LPUART15_RXDMA can not be set at the same time" +#endif +#if (defined(CONFIG_LPUART7_TXDMA) && defined(CONFIG_LPUART15_TXDMA)) +# error "DMA MUX conflict:CONFIG_LPUART7_TXDMA and CONFIG_LPUART15_TXDMA can not be set at the same time" +#endif +#if defined(SERIAL_HAVE_RXDMA) +/* Currently RS-485 support cannot be enabled when RXDMA is in use due to + * lack of testing. + */ + +# if (defined(CONFIG_LPUART0_RXDMA) && defined(CONFIG_LPUART0_RS485)) || \ + (defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_RS485)) || \ + (defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_RS485)) || \ + (defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_RS485)) || \ + (defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_RS485)) || \ + (defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_RS485)) || \ + (defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_RS485)) || \ + (defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_RS485)) || \ + (defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_RS485)) || \ + (defined(CONFIG_LPUART9_RXDMA) && defined(CONFIG_LPUART9_RS485)) || \ + (defined(CONFIG_LPUART10_RXDMA) && defined(CONFIG_LPUART10_RS485)) || \ + (defined(CONFIG_LPUART11_RXDMA) && defined(CONFIG_LPUART11_RS485)) || \ + (defined(CONFIG_LPUART12_RXDMA) && defined(CONFIG_LPUART12_RS485)) || \ + (defined(CONFIG_LPUART13_RXDMA) && defined(CONFIG_LPUART13_RS485)) || \ + (defined(CONFIG_LPUART14_RXDMA) && defined(CONFIG_LPUART14_RS485)) || \ + (defined(CONFIG_LPUART15_RXDMA) && defined(CONFIG_LPUART15_RS485)) +# error "RXDMA and RS-485 cannot be enabled at the same time for the same LPUART" +# endif +#endif /* SERIAL_HAVE_RXDMA */ + +/* Currently RS-485 support cannot be enabled when TXDMA is in use due to + * lack of testing. + */ + +# if (defined(CONFIG_LPUART0_TXDMA) && defined(CONFIG_LPUART0_RS485)) || \ + (defined(CONFIG_LPUART1_TXDMA) && defined(CONFIG_LPUART1_RS485)) || \ + (defined(CONFIG_LPUART2_TXDMA) && defined(CONFIG_LPUART2_RS485)) || \ + (defined(CONFIG_LPUART3_TXDMA) && defined(CONFIG_LPUART3_RS485)) || \ + (defined(CONFIG_LPUART4_TXDMA) && defined(CONFIG_LPUART4_RS485)) || \ + (defined(CONFIG_LPUART5_TXDMA) && defined(CONFIG_LPUART5_RS485)) || \ + (defined(CONFIG_LPUART6_TXDMA) && defined(CONFIG_LPUART6_RS485)) || \ + (defined(CONFIG_LPUART7_TXDMA) && defined(CONFIG_LPUART7_RS485)) || \ + (defined(CONFIG_LPUART8_TXDMA) && defined(CONFIG_LPUART8_RS485)) || \ + (defined(CONFIG_LPUART9_TXDMA) && defined(CONFIG_LPUART9_RS485)) || \ + (defined(CONFIG_LPUART10_TXDMA) && defined(CONFIG_LPUART10_RS485)) || \ + (defined(CONFIG_LPUART11_TXDMA) && defined(CONFIG_LPUART11_RS485)) || \ + (defined(CONFIG_LPUART12_TXDMA) && defined(CONFIG_LPUART12_RS485)) || \ + (defined(CONFIG_LPUART13_TXDMA) && defined(CONFIG_LPUART13_RS485)) || \ + (defined(CONFIG_LPUART14_TXDMA) && defined(CONFIG_LPUART14_RS485)) || \ + (defined(CONFIG_LPUART15_TXDMA) && defined(CONFIG_LPUART15_RS485)) +# error "TXDMA and RS-485 cannot be enabled at the same time for the same LPUART" +#endif + /**************************************************************************** * Public Types ****************************************************************************/