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Cortex-M7: Add support for enabled the D-Cache in write only mode.

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SAMV7 Ethernet:  I- and D-Cache are now enabled in the netnsh/ configuration.  D-Cache is enabled in write-though mode.  This mode is necessary because the DMA descriptors are each 8-bytes in size but the D-Cache cache line is 32-bits in size. So it is impossible make coherency for every 8-byte DMA descriptor without write-through.
This commit is contained in:
Gregory Nutt 2015-03-29 14:42:03 -06:00
parent ae0b0ca3fd
commit d3beea967d
1 changed files with 2 additions and 2 deletions
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arch/arm/src/samv7/Kconfig
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@ -120,10 +120,10 @@ config SAMV7_EMAC
select ARMV7M_DCACHE_WRITETHROUGH if ARMV7M_DCACHE
---help---
NOTE that write-through caching is automatically selected. This is
to work around issues with the RX and TX descriptors with are 8-bits
to work around issues with the RX and TX descriptors with are 8-bytes
in size. But the D-Cache cache line size is 32-bytes. That means
that you cannot reload, clean or invalidate a descriptor without also
effecting three neighboring desciptors. Setting write through mode
effecting three neighboring descriptors. Setting write through mode
eliminates the need for cleaning. If only reloading and invalidating
are done, then there is no problem.