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Fixes a few more high priority, nested interrupt logic

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This commit is contained in:
Gregory Nutt 2013-12-23 11:13:56 -06:00
parent 22e208dbf9
commit d41bfe4d5b
35 changed files with 142 additions and 299 deletions
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10
ChangeLog
View File

@ -6273,3 +6273,13 @@
(2013-12-22).
* configs/viewtool-stm32f107/scripts: Need to do some special things
in linking of the common vectors are used (2013-12-22).
* arch/arm/include/*/irq*.h: Add definition NR_VECTORS so that the RAM
vector logic can know how many vectors there are. NR_IRQS is often
not equal to NR_VECTORS (2013-12-23).
* arch/arm/src/*_vectors.S: Standardize the name of the vector table
and the name of the common vector handling logic so that the MCU-
independent logic and work with these (2013-12-23).
* configs/viewtool-stm32f107/scripts: Move the RAM vector tables to the
beginning of SRAM. It seems to require this alignament. Also, we
don't need different scripts for the CMNVECTOR case now that the vector
table has a common name.

2
arch/arm/include/kinetis/irq.h
View File

@ -294,7 +294,7 @@
/* Note that the total number of IRQ numbers supported is equal to the number of
* valid interrupt vectors. This is wasteful in that certain tables are sized by
* this value. There are only 97 valid interrupts so, potentially the numver of
* this value. There are only 97 valid interrupts so, potentially the number of
* IRQs to could be reduced to 97. However, equating IRQ numbers with vector numbers
* also simplifies operations on NVIC registers and (at least in my state of mind
* now) seems to justify the waste.

9
arch/arm/include/lm/lm3s_irq.h
View File

@ -118,6 +118,7 @@
# define LM_RESERVED_70 (70) /* Vector 70: Reserved */
# define NR_VECTORS (71)
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
@ -183,7 +184,9 @@
# define LM_RESERVED_70 (70) /* Vector 70: Reserved */
# define NR_VECTORS (71)
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
@ -247,7 +250,9 @@
# define LM_RESERVED_70 (70) /* Vector 70: Reserved */
# define NR_VECTORS (71)
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
@ -312,7 +317,9 @@
# define LM_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */
# define LM_RESERVED_71 (71) /* Vector 71: Reserved */
# define NR_VECTORS (72)
# define NR_IRQS (71) /* (Really less because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
@ -376,7 +383,9 @@
# define LM_RESERVED_70 (70) /* Vector 70: Reserved */
# define NR_VECTORS (71)
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
#else
# error "IRQ Numbers not specified for this Stellaris chip"
#endif

1
arch/arm/include/lm/lm4f_irq.h
View File

@ -211,6 +211,7 @@
# define LM_RESERVED_153 (153) /* Vector 153: Reserved */
# define LM_RESERVED_154 (154) /* Vector 154: Reserved */
# define NR_VECTORS (155)
# define NR_IRQS (123) /* (Really fewer because of reserved vectors) */
#else

1
arch/arm/include/lpc17xx/lpc176x_irq.h
View File

@ -223,6 +223,7 @@
/* Total number of IRQ numbers */
#define NR_VECTORS LPC17_IRQ_NIRQS
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
/****************************************************************************

1
arch/arm/include/lpc17xx/lpc178x_irq.h
View File

@ -269,6 +269,7 @@
/* Total number of IRQ numbers */
#define NR_VECTORS LPC17_IRQ_NIRQS
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
/****************************************************************************

2
arch/arm/include/lpc43xx/irq.h
View File

@ -133,6 +133,7 @@
* supported)
*/
#define NR_VECTORS LPC43M4_IRQ_NIRQS
#define NR_IRQS LPC43M4_IRQ_NIRQS
/* Cortex-M0 External interrupts (vectors >= 16) */
@ -183,6 +184,7 @@
*/
#if 0
#define NR_VECTORS LPC43M0_IRQ_NIRQS
#define NR_IRQS LPC43M0_IRQ_NIRQS
#endif

1
arch/arm/include/sam34/sam3u_irq.h
View File

@ -238,6 +238,7 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)

1
arch/arm/include/sam34/sam3x_irq.h
View File

@ -392,6 +392,7 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \
SAM_NGPIODIRQS + SAM_NGPIOEIRQS + SAM_NGPIOFIRQS)

1
arch/arm/include/sam34/sam4e_irq.h
View File

@ -296,6 +296,7 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \
SAM_NGPIODIRQS + SAM_NGPIOEIRQS)

1
arch/arm/include/sam34/sam4l_irq.h
View File

@ -299,6 +299,7 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)

1
arch/arm/include/sam34/sam4s_irq.h
View File

@ -249,6 +249,7 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)

6
arch/arm/include/stm32/stm32f10xxx_irq.h
View File

@ -128,6 +128,8 @@
# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */
# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 and 5 global interrupt */
# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */
# define NR_VECTORS (77)
# define NR_IRQS (77)
/* Connectivity Line Devices */
@ -201,6 +203,8 @@
# define STM32_IRQ_CAN2RX1 (81) /* 65: CAN2 RX1 interrupt */
# define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */
# define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */
# define NR_VECTORS (84)
# define NR_IRQS (84)
/* Medium and High Density Devices */
@ -266,6 +270,8 @@
# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */
# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */
# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4&5 global interrupt */
# define NR_VECTORS (76)
# define NR_IRQS (76)
/* Convenience definitions for interrupts with multiple functions */

1
arch/arm/include/stm32/stm32f20xxx_irq.h
View File

@ -150,6 +150,7 @@
#define STM32_IRQ_HASH (STM32_IRQ_INTERRUPTS+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_INTERRUPTS+80) /* 80: Hash and Rng global interrupt */
#define NR_VECTORS (STM32_IRQ_INTERRUPTS+81)
#define NR_IRQS (STM32_IRQ_INTERRUPTS+81)
/****************************************************************************************************

1
arch/arm/include/stm32/stm32f30xxx_irq.h
View File

@ -161,6 +161,7 @@
#define STM32_IRQ_RESERVED80 (STM32_IRQ_INTERRUPTS+80) /* 80: Reserved */
#define STM32_IRQ_FPU (STM32_IRQ_INTERRUPTS+81) /* 81: FPU global interrupt */
#define NR_VECTORS (STM32_IRQ_INTERRUPTS+82)
#define NR_IRQS (STM32_IRQ_INTERRUPTS+82)
/****************************************************************************************************

8
arch/arm/include/stm32/stm32f40xxx_irq.h
View File

@ -154,21 +154,29 @@
#define STM32_IRQ_FPU (STM32_IRQ_INTERRUPTS+81) /* 81: FPU global interrupt */
#if !defined(CONFIG_STM32_STM32F427) && !defined(CONFIG_STM32_STM32F429)
# define NR_VECTORS (STM32_IRQ_INTERRUPTS+82)
# define NR_IRQS (STM32_IRQ_INTERRUPTS+82)
#else
# define STM32_IRQ_UART7 (STM32_IRQ_INTERRUPTS+82) /* 82: UART7 interrupt */
# define STM32_IRQ_UART8 (STM32_IRQ_INTERRUPTS+83) /* 83: UART8 interrupt */
# define STM32_IRQ_SPI4 (STM32_IRQ_INTERRUPTS+84) /* 84: SPI4 interrupt */
# define STM32_IRQ_SPI5 (STM32_IRQ_INTERRUPTS+85) /* 85: SPI5 interrupt */
# define STM32_IRQ_SPI6 (STM32_IRQ_INTERRUPTS+86) /* 86: SPI6 interrupt */
#if defined(CONFIG_STM32_STM32F429)
# define STM32_IRQ_SAI1 (STM32_IRQ_INTERRUPTS+87) /* 87: SAI1 interrupt */
# define STM32_IRQ_LTDCINT (STM32_IRQ_INTERRUPTS+88) /* 88: LTDCINT interrupt */
# define STM32_IRQ_LTDCERRINT (STM32_IRQ_INTERRUPTS+89) /* 89: LTDCERRINT interrupt */
# define STM32_IRQ_DMA2D (STM32_IRQ_INTERRUPTS+90) /* 90: DMA2D interrupt */
# define NR_VECTORS (STM32_IRQ_INTERRUPTS+91)
# define NR_IRQS (STM32_IRQ_INTERRUPTS+91)
#else
# define NR_VECTORS (STM32_IRQ_INTERRUPTS+87)
# define NR_IRQS (STM32_IRQ_INTERRUPTS+87)
#endif
#endif

3
arch/arm/include/stm32/stm32l15xxx_irq.h
View File

@ -108,6 +108,7 @@
# define STM32_IRQ_TIM6 (STM32_IRQ_INTERRUPTS+43) /* 43: TIM6 global interrupt */
# define STM32_IRQ_TIM7 (STM32_IRQ_INTERRUPTS+44) /* 44: TIM7 global interrupt */
# define NR_VECTORS (STM32_IRQ_INTERRUPTS+45)
# define NR_IRQS (STM32_IRQ_INTERRUPTS+45)
/* External interrupts (vectors >= 16) medium+ density devices */
@ -170,6 +171,7 @@
# define STM32_IRQ_AES (STM32_IRQ_INTERRUPTS+52) /* 52: AES global interrupt */
# define STM32_IRQ_COMPACQ (STM32_IRQ_INTERRUPTS+53) /* 53: Comparator Channel Acquisition Interrupt */
# define NR_VECTORS (STM32_IRQ_INTERRUPTS+54)
# define NR_IRQS (STM32_IRQ_INTERRUPTS+54)
/* External interrupts (vectors >= 16) high density devices */
@ -235,6 +237,7 @@
# define STM32_IRQ_AES (STM32_IRQ_INTERRUPTS+55) /* 55: AES global interrupt */
# define STM32_IRQ_COMPACQ (STM32_IRQ_INTERRUPTS+56) /* 56: Comparator Channel Acquisition Interrupt */
# define NR_VECTORS (STM32_IRQ_INTERRUPTS+57)
# define NR_IRQS (STM32_IRQ_INTERRUPTS+57)
#else
# error "Unknown STM32L density"

50
arch/arm/src/armv7-m/ram_vectors.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-m/ram_vectors.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
@ -31,48 +31,37 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_ARMV7_M_RAM_VECTORS_H
#define __ARCH_ARM_SRC_COMMON_ARMV7_M_RAM_VECTORS_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <arch/irq.h>
/* If CONFIG_ARMV7M_CMNVECTOR is defined then the number of peripheral interrupts
* is provided in chip.h.
*/
#include "chip.h"
#include "up_internal.h"
#ifdef CONFIG_ARCH_RAMVECTORS
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* This logic currently only works if CONFIG_ARMV7M_CMNVECTOR is defined. That is
* because CONFIG_ARMV7M_CMNVECTOR is needed to induce chip.h into giving us the
* number of peripheral interrupts. "Oh want a tangled web we weave..."
****************************************************************************/
/* This is the size of the vector table (in 4-byte entries). This size
* includes the (1) the peripheral interrupts, (2) space for 15 Cortex-M
* exceptions, and (3) IDLE stack pointer which lies at the beginning of the
* table.
*/
#ifndef CONFIG_ARMV7M_CMNVECTOR
# error "This logic requires CONFIG_ARMV7M_CMNVECTOR"
#endif
#define ARMV7M_VECTAB_SIZE (NR_VECTORS + 16)
/* This, then is the size of the vector table (in 4-byte entries). This size
* includes the (1) the device interrupts, (2) space for 15 Cortex-M excpetions, and
* (3) IDLE stack pointer which lies at the beginning of the table.
*/
#define ARMV7M_VECTAB_SIZE (ARMV7M_PERIPHERAL_INTERRUPTS + 16)
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/* If CONFIG_ARCH_RAMVECTORS is defined, then the ARM logic must provide
* ARM-specific implementations of irq_initialize(), irq_attach(), and
@ -80,15 +69,18 @@
* table resides in RAM, has the name up_ram_vectors, and has been
* properly positioned and aligned in memory by the linker script.
*
* REVISIT: Can this alignment requirement vary from core-to-core?
* REVISIT: Can this alignment requirement vary from core-to-core? Yes, it
* depends on the number of vectors supported by the MCU. The safest thing
* to do is to put the vector table at the beginning of RAM in order toforce
* the highest alignment possible.
*/
extern up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE]
__attribute__ ((section (".ram_vectors"), aligned (128)));
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
/****************************************************************************
* Name: up_ramvec_initialize

2
arch/arm/src/armv7-m/up_ramvec_attach.c
View File

@ -105,7 +105,7 @@ int up_ramvec_attach(int irq, up_vector_t vector)
intvdbg("%s IRQ%d\n", vector ? "Attaching" : "Detaching", irq);
if ((unsigned)irq < (STM32_IRQ_INTERRUPTS + ARMV7M_PERIPHERAL_INTERRUPTS))
if ((unsigned)irq < NR_VECTORS)
{
irqstate_t flags;

5
arch/arm/src/armv7-m/up_ramvec_initialize.c
View File

@ -84,7 +84,10 @@
* table resides in RAM, has the name up_ram_vectors, and has been
* properly positioned and aligned in memory by the linker script.
*
* REVISIT: Can this alignment requirement vary from core-to-core?
* REVISIT: Can this alignment requirement vary from core-to-core? Yes, it
* depends on the number of vectors supported by the MCU. The safest thing
* to do is to put the vector table at the beginning of RAM in order toforce
* the highest alignment possible.
*/
up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE]

2
arch/arm/src/armv7-m/up_vectors.c
View File

@ -76,7 +76,7 @@ extern char _ebss;
* As all exceptions (interrupts) are routed via exception_common, we just need to
* fill this array with pointers to it.
*
* Note that the [ ... ] desginated initialiser is a GCC extension.
* Note that the [ ... ] designated initialiser is a GCC extension.
*/
unsigned _vectors[] __attribute__((section(".vectors"))) =

13
arch/arm/src/kinetis/kinetis_vectors.S
View File

@ -119,7 +119,7 @@
.thumb_func
\label:
mov r0, #\irqno
b kinetis_common
b exception_common
.endm
/************************************************************************************************
@ -129,10 +129,10 @@
.section .vectors, "ax"
.code 16
.align 2
.globl kinetis_vectors
.type kinetis_vectors, function
.globl _vectors
.type _vectors, function
kinetis_vectors:
_vectors:
/* Processor Exceptions *************************************************************************/
@ -614,7 +614,10 @@ handlers:
* We are in handler mode and the current SP is the MSP
*/
kinetis_common:
.globl exception_common
.type exception_common, function
exception_common:
/* Complete the context save */

2
arch/arm/src/lm/lm_start.c
View File

@ -66,7 +66,7 @@
* Public Data
****************************************************************************/
extern void lm_vectors(void);
extern void _vectors(void);
/****************************************************************************
* Private Functions

14
arch/arm/src/lm/lm_vectors.S
View File

@ -126,7 +126,7 @@
.thumb_func
\label:
mov r0, #\irqno
b lm_irqcommon
b exception_common
.endm
/************************************************************************************
@ -136,10 +136,10 @@
.section .vectors, "ax"
.code 16
.align 2
.globl lm_vectors
.type lm_vectors, function
.globl _vectors
.type _vectors, function
lm_vectors:
_vectors:
/* Processor Exceptions */
@ -171,7 +171,7 @@ lm_vectors:
#define UNUSED(i) .word lm_reserved
#include "chip/chip/lm_vectors.h"
.size lm_vectors, .-lm_vectors
.size _vectors, .-_vectors
/************************************************************************************
* .text
@ -218,7 +218,9 @@ handlers:
* We are in handler mode and the current SP is the MSP
*/
lm_irqcommon:
.globl exception_common
.type exception_common, function
exception_common:
/* Complete the context save */

15
arch/arm/src/lpc17xx/lpc17_vectors.S
View File

@ -121,7 +121,7 @@
.thumb_func
\label:
mov r0, #\irqno
b lpc17_common
b exception_common
.endm
/************************************************************************************************
@ -131,10 +131,10 @@
.section .vectors, "ax"
.code 16
.align 2
.globl lpc17_vectors
.type lpc17_vectors, function
.globl _vectors
.type _vectors, function
lpc17_vectors:
_vectors:
/* Processor Exceptions */
@ -171,7 +171,7 @@ lpc17_vectors:
# error "Unrecognized LPC17xx family"
#endif
.size lpc17_vectors, .-lpc17_vectors
.size _vectors, .-_vectors
/************************************************************************************************
* .text
@ -226,7 +226,10 @@ handlers:
* We are in handler mode and the current SP is the MSP
*/
lpc17_common:
.globl exception_common
.type exception_common, function
exception_common:
/* Complete the context save */

4
arch/arm/src/sam34/sam_irq.c
View File

@ -74,6 +74,8 @@
volatile uint32_t *current_regs;
extern uint32_t _vectors[];
/****************************************************************************
* Private Data
****************************************************************************/
@ -345,7 +347,7 @@ void up_irqinitialize(void)
#if defined(CONFIG_ARCH_RAMVECTORS)
up_ramvec_initialize();
#elif defined(CONFIG_SAM_BOOTLOADER)
putreg32((uint32_t)sam_vectors, NVIC_VECTAB);
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#endif
/* Set all interrupts (and exceptions) to the default priority */

15
arch/arm/src/sam34/sam_vectors.S
View File

@ -120,7 +120,7 @@
.thumb_func
\label:
mov r0, #\irqno
b sam_common
b exception_common
.endm
/************************************************************************************************
@ -130,10 +130,10 @@
.section .vectors, "ax"
.code 16
.align 2
.globl sam_vectors
.type sam_vectors, function
.globl _vectors
.type _vectors, function
sam_vectors:
_vectors:
/* Processor Exceptions */
@ -174,7 +174,7 @@ sam_vectors:
# error Unrecognized SAM architecture
#endif
.size sam_vectors, .-sam_vectors
.size _vectors, .-_vectors
/************************************************************************************************
* .text
@ -231,7 +231,10 @@ handlers:
* We are in handler mode and the current SP is the MSP
*/
sam_common:
.globl exception_common
.type exception_common, function
exception_common:
/* Complete the context save */

8
arch/arm/src/stm32/stm32_irq.c
View File

@ -95,7 +95,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
flags = irqsave();
lldbg("NVIC (%s, irq=%d):\n", msg, irq);
lldbg(" INTCTRL: %08x VECTAB: %08x\n",
lldbg(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
lldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
@ -151,7 +151,7 @@ static int stm32_nmi(int irq, FAR void *context)
static int stm32_busfault(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! Bus fault recived\n");
dbg("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
@ -159,7 +159,7 @@ static int stm32_busfault(int irq, FAR void *context)
static int stm32_usagefault(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! Usage fault received\n");
dbg("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
@ -321,7 +321,7 @@ void up_irqinitialize(void)
#if defined(CONFIG_ARCH_RAMVECTORS)
up_ramvec_initialize();
#elif defined(CONFIG_STM32_DFU)
putreg32((uint32_t)stm32_vectors, NVIC_VECTAB);
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#endif
/* Set all interrupts (and exceptions) to the default priority */

2
arch/arm/src/stm32/stm32_rcc.h
View File

@ -83,7 +83,7 @@ extern "C"
* and we will need to set the NVIC vector location to this alternative location.
*/
extern uint32_t stm32_vectors[]; /* See stm32_vectors.S */
extern uint32_t _vectors[]; /* See stm32_vectors.S */
/************************************************************************************
* Inline Functions

15
arch/arm/src/stm32/stm32_vectors.S
View File

@ -127,7 +127,7 @@
.thumb_func
\label:
mov r0, #\irqno
b stm32_common
b exception_common
.endm
/************************************************************************************
@ -137,10 +137,10 @@
.section .vectors, "ax"
.code 16
.align 2
.globl stm32_vectors
.type stm32_vectors, function
.globl _vectors
.type _vectors, function
stm32_vectors:
_vectors:
/* Processor Exceptions */
@ -182,7 +182,7 @@ stm32_vectors:
#else
# error "No vectors for STM32 chip"
#endif
.size stm32_vectors, .-stm32_vectors
.size _vectors, .-_vectors
/************************************************************************************
* .text
@ -241,7 +241,10 @@ handlers:
* We are in handler mode and the current SP is the MSP
*/
stm32_common:
.globl exception_common
.type exception_common, function
exception_common:
/* Complete the context save */

4
configs/viewtool-stm32f107/highpri/Make.defs
View File

@ -38,9 +38,9 @@ include ${TOPDIR}/tools/Config.mk
include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
ifeq ($(CONFIG_STM32_DFU),y)
LDSCRIPT = cmndfu.ld
LDSCRIPT = dfu.ld
else
LDSCRIPT = cmnflash.ld
LDSCRIPT = flash.ld
endif
ifeq ($(WINTOOL),y)

112
configs/viewtool-stm32f107/scripts/cmndfu.ld
View File

@ -1,112 +0,0 @@
/****************************************************************************
* configs/viewtool-stm32f107/scripts/cmndfu.ld
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
MEMORY
{
flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > flash
.ARM.extab : {
*(.ARM.extab*)
} > flash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
/* The STM32F103Z has 64Kb of SRAM beginning at the following address */
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram AT > flash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > sram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

113
configs/viewtool-stm32f107/scripts/cmnflash.ld
View File

@ -1,113 +0,0 @@
/****************************************************************************
* configs/viewtool-stm32f107/scripts/cmnflash.ld
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
MEMORY
{
flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > flash
.ARM.extab : {
*(.ARM.extab*)
} > flash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
/* The STM32F107VC has 64Kb of SRAM beginning at the following address */
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram AT > flash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > sram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

7
configs/viewtool-stm32f107/scripts/dfu.ld
View File

@ -40,6 +40,7 @@ MEMORY
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{
@ -77,7 +78,11 @@ SECTIONS
_eronly = ABSOLUTE(.);
/* The STM32F103Z has 64Kb of SRAM beginning at the following address */
/* The RAM vector table (if present) should lie at the beginning of SRAM */
.ram_vectors : {
*(.ram_vectors)
} > sram
.data : {
_sdata = ABSOLUTE(.);

8
configs/viewtool-stm32f107/scripts/flash.ld
View File

@ -37,10 +37,10 @@ MEMORY
{
flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{
@ -78,7 +78,11 @@ SECTIONS
_eronly = ABSOLUTE(.);
/* The STM32F107VC has 64Kb of SRAM beginning at the following address */
/* The RAM vector table (if present) should lie at the beginning of SRAM */
.ram_vectors : {
*(.ram_vectors)
} > sram
.data : {
_sdata = ABSOLUTE(.);