From 1c518b223d6d7a7331a0d015780826bb118d0be6 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Mon, 27 Feb 2017 13:06:01 -1000 Subject: [PATCH 1/3] Kinetis:Add the configuring SIM_CLKDIV2[USBFRAC, USBDIV] in kinetis_clockconfig If a board.h provides BOARD_SIM_CLKDIV2_FREQ it will configure the SIM_CLKDIV2 based on the additional provided BOARD_SIM_CLKDIV2_USBFRAC and BOARD_SIM_CLKDIV2_USBDIV The reason for doing this globaly is that the output the SIM_CLKDIV2 divisor may be also used for other IP blocks in future configurations (as is done for SIM_CLKDIV3) --- arch/arm/src/kinetis/kinetis_clockconfig.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/src/kinetis/kinetis_clockconfig.c b/arch/arm/src/kinetis/kinetis_clockconfig.c index eba8b4fc65..b954f33be2 100644 --- a/arch/arm/src/kinetis/kinetis_clockconfig.c +++ b/arch/arm/src/kinetis/kinetis_clockconfig.c @@ -360,6 +360,16 @@ void kinetis_pllconfig(void) putreg32(regval32, KINETIS_SIM_SOPT2); #endif +#if defined(BOARD_SIM_CLKDIV2_FREQ) + /* Set up the SIM_CLKDIV2[USBFRAC, USBDIV] */ + + regval32 = getreg32(KINETIS_SIM_CLKDIV2); + regval32 &= ~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK); + regval32 |= (SIM_CLKDIV2_USBFRAC(BOARD_SIM_CLKDIV2_USBFRAC) | + SIM_CLKDIV2_USBDIV(BOARD_SIM_CLKDIV2_USBDIV)); + putreg32(regval32, KINETIS_SIM_CLKDIV2); +#endif + #if defined(BOARD_SIM_CLKDIV3_FREQ) /* Set up the SIM_CLKDIV3 [PLLFLLFRAC, PLLFLLDIV] */ From d0c58fffb38fac8522f3e3c3af497f2a58430137 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Mon, 27 Feb 2017 13:13:24 -1000 Subject: [PATCH 2/3] Kinetis:Refactor clocking in kinetis_usbdev 1) Removed SIM_CLKDIV2[USBFRAC, USBDIV] setting as it is now done in kinetis_clockconfig 2) Use BOARD_USB_CLKSRC to select the clock source to the USB block 3) Removed warning 4) Removed CONFIG_TEENSY_3X_OVERCLOCK from the driver as the board.h will now provide BOARD_SIM_CLKDIV2_USBDIV and BOARD_SIM_CLKDIV2_USBFRAC to the kinetis_clockconfig --- arch/arm/src/kinetis/kinetis_usbdev.c | 29 ++++++++------------------- 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c index 8c126f2ef7..519b2babb9 100644 --- a/arch/arm/src/kinetis/kinetis_usbdev.c +++ b/arch/arm/src/kinetis/kinetis_usbdev.c @@ -4393,37 +4393,24 @@ void up_usbinitialize(void) * it using a pointer to make any future ports to multiple USB controllers * easier. */ -#if 1 -#warning "This code needs to be driven by BOARD_ settings and SIM_SOPT2[PLLFLLSE] needs to be set globally" - /* 1: Select clock source */ + + /* Select clock source: + * SIM_SOPT2[PLLFLLSEL] and SIM_CLKDIV2[USBFRAC, USBDIV] will have been + * configured in kinetis_pllconfig. So here we select between USB_CLKIN + * or the output of SIM_CLKDIV2[USBFRAC, USBDIV] + */ regval = getreg32(KINETIS_SIM_SOPT2); - regval |= SIM_SOPT2_PLLFLLSEL_MCGPLLCLK | SIM_SOPT2_USBSRC; + regval &= ~(SIM_SOPT2_USBSRC); + regval |= BOARD_USB_CLKSRC; putreg32(regval, KINETIS_SIM_SOPT2); - regval = getreg32(KINETIS_SIM_CLKDIV2); - -#if defined(CONFIG_TEENSY_3X_OVERCLOCK) - /* USBFRAC/USBDIV = 1/2 of 96Mhz clock = 48MHz */ - - regval = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1); -#else - /* USBFRAC/USBDIV = 2/3 of 72Mhz clock = 48MHz */ - /* 72Mhz */ - - regval = SIM_CLKDIV2_USBDIV(3) | SIM_CLKDIV2_USBFRAC(2); -#endif - - putreg32(regval, KINETIS_SIM_CLKDIV2); - /* 2: Gate USB clock */ regval = getreg32(KINETIS_SIM_SCGC4); regval |= SIM_SCGC4_USBOTG; putreg32(regval, KINETIS_SIM_SCGC4); -#endif - usbtrace(TRACE_DEVINIT, 0); /* Initialize the driver state structure */ From a6e0d5ed6096b96bc71ec000d7be0f5b2326c00c Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Mon, 27 Feb 2017 13:51:57 -1000 Subject: [PATCH 3/3] Kinetis:Use BOARD_xxxx to drive system clocking 1) Shifted the clock speed of MK20DX128VLH5 to 48 Mhz to be able to uses USB. 2) Set BOARD_OUTDIV3 to 0 - there is no BOARD_OUTDIV3 on a MK20DX128VLH5 or K20DX256VLH7 3) Added BOARD_SOPT2_PLLFLLSEL and BOARD_SOPT2_FREQ along with settings for BOARD_SIM_CLKDIV2_USBFRAC and BOARD_SIM_CLKDIV2_USBDIV base on the BOARD_SOPT2_FREQ. --- configs/teensy-3.x/include/board.h | 56 +++++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 9 deletions(-) diff --git a/configs/teensy-3.x/include/board.h b/configs/teensy-3.x/include/board.h index b67fe21b6c..508d5a811d 100644 --- a/configs/teensy-3.x/include/board.h +++ b/configs/teensy-3.x/include/board.h @@ -74,10 +74,10 @@ * is 72MHz and 50MHz for the MK20DX128VLH5, but according to the PJRC website, * both can be overclocked at 96MHz * - * MK20DX128VLH5 Rated Frequency 50MHz + * MK20DX128VLH5 Rated Frequency 50MHz (selecting 48Mhz to use USB) * * PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/8 = 2MHz - * PLL Output frequency: PLLOUT = PLLIN*VDIV = 2Mhz*25 = 50MHz + * PLL Output frequency: PLLOUT = PLLIN*VDIV = 2Mhz*24 = 48MHz * MCG Frequency: PLLOUT = 48MHz * * MK20DX256VLH7 Rated Frequency 72MHz @@ -102,7 +102,7 @@ # define BOARD_OUTDIV1 1 /* Core = MCG, 96MHz */ # define BOARD_OUTDIV2 2 /* Bus = MCG/2, 48MHz */ -# define BOARD_OUTDIV3 2 /* FlexBus = MCG/2, 48MHz */ +# define BOARD_OUTDIV3 0 /* N/A = No OUTDIV3 */ # define BOARD_OUTDIV4 4 /* Flash clock = MCG/4, 24MHz */ #elif defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) @@ -116,21 +116,21 @@ # define BOARD_OUTDIV1 1 /* Core = MCG, 72MHz */ # define BOARD_OUTDIV2 2 /* Bus = MCG/2, 36MHz */ -# define BOARD_OUTDIV3 2 /* FlexBus = MCG/2, 36MHz */ +# define BOARD_OUTDIV3 0 /* N/A = No OUTDIV3 */ # define BOARD_OUTDIV4 3 /* Flash clock = MCG/3, 72MHz */ #elif defined(CONFIG_ARCH_CHIP_MK20DX128VLH5) /* PLL Configuration */ # define BOARD_PRDIV 8 /* PLL External Reference Divider */ -# define BOARD_VDIV 25 /* PLL VCO Divider (frequency multiplier) */ +# define BOARD_VDIV 24 /* PLL VCO Divider (frequency multiplier) */ /* SIM CLKDIV1 dividers */ -# define BOARD_OUTDIV1 1 /* Core = MCG, 50MHz */ -# define BOARD_OUTDIV2 1 /* Bus = MCG/1, 50MHz */ -# define BOARD_OUTDIV3 1 /* FlexBus = MCG/1, 20MHz */ -# define BOARD_OUTDIV4 2 /* Flash clock = MCG/2, 25MHz */ +# define BOARD_OUTDIV1 1 /* Core = MCG, 48MHz */ +# define BOARD_OUTDIV2 1 /* Bus = MCG/1, 48MHz */ +# define BOARD_OUTDIV3 0 /* N/A = No OUTDIV3 */ +# define BOARD_OUTDIV4 2 /* Flash clock = MCG/2, 24MHz */ #endif #define BOARD_PLLIN_FREQ (BOARD_EXTAL_FREQ / BOARD_PRDIV) @@ -142,6 +142,44 @@ #define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3) #define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4) +/* Use MCGPLLCLK as the output SIM_SOPT2 MUX selected by + * SIM_SOPT2[PLLFLLSEL] + */ + +#define BOARD_SOPT2_PLLFLLSEL SIM_SOPT2_PLLFLLSEL_MCGPLLCLK +#define BOARD_SOPT2_FREQ BOARD_MCG_FREQ + + /* Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ] + * SIM_CLKDIV2_FREQ = BOARD_SOPT2_FREQ × [ (USBFRAC+1) / (USBDIV+1) ] + */ + +#if BOARD_SOPT2_FREQ == 96000000 + /* USBFRAC/USBDIV = 1/2 of 96Mhz clock = 48MHz */ + +# define BOARD_SIM_CLKDIV2_USBFRAC 1 +# define BOARD_SIM_CLKDIV2_USBDIV 2 +#elif BOARD_SOPT2_FREQ == 72000000 + /* USBFRAC/USBDIV = 2/3 of 72Mhz clock = 48MHz */ + +# define BOARD_SIM_CLKDIV2_USBFRAC 2 +# define BOARD_SIM_CLKDIV2_USBDIV 3 +#elif BOARD_SOPT2_FREQ == 48000000 + /* USBFRAC/USBDIV = 1/1 of 48Mhz clock = 48MHz */ + +# define BOARD_SIM_CLKDIV2_USBFRAC 1 +# define BOARD_SIM_CLKDIV2_USBDIV 1 +#endif + +#define BOARD_SIM_CLKDIV2_FREQ (BOARD_SOPT2_FREQ / \ + BOARD_SIM_CLKDIV2_USBDIV * \ + BOARD_SIM_CLKDIV2_USBFRAC) + +/* Use the output of SIM_SOPT2[PLLFLLSEL] as the USB clock source */ + +#define BOARD_USB_CLKSRC SIM_SOPT2_USBSRC +#define BOARD_USB_FREQ BOARD_SIM_CLKDIV2_FREQ + + /* PWM Configuration */ /* FTM0 Channels */