xtensa/esp32: Update bootloader patch to recent ESP-IDF version
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This commit is contained in:
Gustavo Henrique Nihei
Petro Karashchenko
parent
13d823f307
commit
d4e6d9ab77
@ -1,112 +1,56 @@
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From 3ee21d64a48018b33c1db485b5fbfb08145e4f67 Mon Sep 17 00:00:00 2001
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From 851a0b57377238386e8c786faeca422f6e11c911 Mon Sep 17 00:00:00 2001
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From: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
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Date: Wed, 6 Jul 2022 10:03:09 -0300
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Date: Mon, 20 Mar 2023 11:16:52 -0300
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Subject: [PATCH] esp32: Connect Xtensa Instruction RAM1 to Cache
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User application image is executed with PID 5, so it accesses the
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External Flash via virtual address starting from 0x40400000 (Vaddr2).
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See:
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https://github.com/espressif/esp-idf/blob/v4.4.1/components/xtensa/esp32/include/xtensa/config/core-isa.h#L301-L305
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
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---
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.../bootloader_support/src/bootloader_utility.c | 17 ++++++++++++++---
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components/soc/esp32/include/soc/mmu.h | 1 +
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components/spi_flash/cache_utils.c | 2 ++
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components/spi_flash/flash_mmap.c | 8 ++++++++
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4 files changed, 25 insertions(+), 3 deletions(-)
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components/bootloader_support/src/bootloader_utility.c | 2 ++
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components/hal/esp32/include/hal/mmu_ll.h | 9 +++++++++
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2 files changed, 11 insertions(+)
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diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c
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index ad56335253..7e343a551b 100644
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index 4e30ecad1b..15700a1c39 100644
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--- a/components/bootloader_support/src/bootloader_utility.c
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+++ b/components/bootloader_support/src/bootloader_utility.c
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@@ -737,6 +737,14 @@ static void set_cache_and_start_app(
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for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) {
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DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
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@@ -890,12 +890,14 @@ static void set_cache_and_start_app(
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cache_ll_l1_enable_bus(0, bus_mask);
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bus_mask = cache_ll_l1_get_bus(0, irom_load_addr_aligned, irom_size);
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cache_ll_l1_enable_bus(0, bus_mask);
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+ cache_ll_l1_enable_bus(0, CACHE_BUS_IBUS1);
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#if !CONFIG_FREERTOS_UNICORE
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bus_mask = cache_ll_l1_get_bus(1, drom_load_addr_aligned, drom_size);
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cache_ll_l1_enable_bus(1, bus_mask);
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bus_mask = cache_ll_l1_get_bus(1, irom_load_addr_aligned, irom_size);
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cache_ll_l1_enable_bus(1, bus_mask);
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+ cache_ll_l1_enable_bus(1, CACHE_BUS_IBUS1);
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#endif
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//----------------------Enable Cache----------------
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diff --git a/components/hal/esp32/include/hal/mmu_ll.h b/components/hal/esp32/include/hal/mmu_ll.h
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index 8a572a5455..96609fe7ee 100644
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--- a/components/hal/esp32/include/hal/mmu_ll.h
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+++ b/components/hal/esp32/include/hal/mmu_ll.h
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@@ -291,6 +291,15 @@ static inline void mmu_ll_unmap_all(uint32_t mmu_id)
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for (int i = 0; i < MMU_ENTRY_NUM; i++) {
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mmu_ll_set_entry_invalid(mmu_id, i);
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}
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+
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+ /* Xtensa CPU does speculative load/store on VAddr1/2/3 when connected to cache.
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+ * Hence it requires all the pages of VAddr2/3 to be set valid to any physical page.
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+ * Marking any page invalid would stall the CPU
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+ * Marking any page invalid would stall the CPU.
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+ */
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+ for (int i = 64; i < 256; i++) {
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+ DPORT_PRO_FLASH_MMU_TABLE[i] = 0;
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+ }
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#else
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for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) {
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FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
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@@ -793,11 +801,11 @@ static void set_cache_and_start_app(
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rc = cache_flash_mmu_set(1, 0, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count);
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ESP_LOGV(TAG, "rc=%d", rc);
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DPORT_REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG,
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- (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) |
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+ (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1) |
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(DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 |
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DPORT_PRO_CACHE_MASK_DRAM1 );
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DPORT_REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG,
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- (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) |
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+ (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1) |
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(DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 |
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DPORT_APP_CACHE_MASK_DRAM1 );
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#elif CONFIG_IDF_TARGET_ESP32S2
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@@ -815,7 +823,10 @@ static void set_cache_and_start_app(
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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- Cache_Read_Enable(0);
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+ DPORT_REG_SET_BIT(0x3ff43050, 1);
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+ DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
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+
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+ asm("memw");
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#elif CONFIG_IDF_TARGET_ESP32S2
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Cache_Resume_ICache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32S3
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diff --git a/components/soc/esp32/include/soc/mmu.h b/components/soc/esp32/include/soc/mmu.h
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index bde6995516..9fff17ddba 100644
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--- a/components/soc/esp32/include/soc/mmu.h
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+++ b/components/soc/esp32/include/soc/mmu.h
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@@ -32,6 +32,7 @@ extern "C" {
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#define SOC_MMU_ADDR_MASK DPORT_MMU_ADDRESS_MASK
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#define SOC_MMU_PAGE_IN_FLASH(page) (page)
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#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF10000)
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+#define SOC_MMU_DPORT_APP_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF12000)
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#define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW
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#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START)
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#define SOC_MMU_VADDR0_START_ADDR SOC_DROM_LOW
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diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c
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index 7715900055..b29aed2953 100644
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--- a/components/spi_flash/cache_utils.c
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+++ b/components/spi_flash/cache_utils.c
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@@ -308,6 +308,8 @@ static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_st
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while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) {
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;
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}
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+ /* Disconnect from cache */
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+ DPORT_REG_WRITE(DPORT_PRO_CACHE_CTRL1_REG, 0xff);
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DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
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}
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#if !CONFIG_FREERTOS_UNICORE
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diff --git a/components/spi_flash/flash_mmap.c b/components/spi_flash/flash_mmap.c
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index 9523bc7959..c17a9903ef 100644
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--- a/components/spi_flash/flash_mmap.c
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+++ b/components/spi_flash/flash_mmap.c
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@@ -108,7 +108,15 @@ static void IRAM_ATTR spi_flash_mmap_init(void)
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if ((entry_pro & SOC_MMU_INVALID_ENTRY_VAL) == 0 && (i == SOC_MMU_DROM0_PAGES_START || i == SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE || entry_pro != 0)) {
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s_mmap_page_refcnt[i] = 1;
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} else {
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+#if CONFIG_IDF_TARGET_ESP32
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+ /* Due to Xtensa speculative load/store, pages need to be marked valid if VAddr2/VAddr3
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+ * are connected to cache. If marked invalid, CPU will halt
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+ */
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+ SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[i] = 0x00;
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+ SOC_MMU_DPORT_APP_FLASH_MMU_TABLE[i] = 0x00;
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+#else
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SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[i] = SOC_MMU_INVALID_ENTRY_VAL;
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+#endif
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#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32
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DPORT_APP_FLASH_MMU_TABLE[i] = SOC_MMU_INVALID_ENTRY_VAL;
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#endif
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+ for (int i = 64; i < 256; i++) {
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+ mmu_ll_write_entry(mmu_id, i, 0, MMU_TARGET_FLASH0);
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+ }
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}
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/**
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--
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2.34.1
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2.37.2
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