Add support for the STM32F041RE and for the Nucleo-F401RE board. From Frank Bennett

2014-04-20 13:42:23 -06:00 · 2014-04-20 13:42:23 -06:00 · d53c3a2090
commit d53c3a2090
parent 444bc06e17
23 changed files with 4076 additions and 3 deletions
--- a/6
+++ b/6
@ -7214,4 +7214,8 @@
 	* configs/zkit-arm-1769: Refreshed all defconfig files (2014-4-19).
 	* include/nuttx/binfmt/ieee695.h:  Beginning of header file for IEEE
 	  695 OMF header file (2014-4-19).
-
+	* arch/arm/include/stm32/chip.h and src/stm32/Kconfig:  Add support
+	  for the STM401RE.  From Frank Bennett (2014-4-20).
+	* README.txt, Documentation/README.html, configs/Kconfig and README.txt,
+	  configs/nucleo-f401re:  Add support for the Nucleo-F401RE board.  From
+	  Frank Bennett (2014-4-20).
--- a/Documentation/README.html
+++ b/Documentation/README.html
@ -8,7 +8,7 @@
  <tr align="center" bgcolor="#e4e4e4">
    <td>
      <h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
-      <p>Last Updated: March 28, 2014</p>
+      <p>Last Updated: April 20, 2014</p>
    </td>
  </tr>
 </table>
@ -127,6 +127,8 @@
 |   |   |- ntosd-dm320/
 |   |   |   |- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/ntosd-dm320/doc/README.txt">doc/README.txt</a>
 |   |   |   `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/ntosd-dm320/README.txt"><b><i>README.txt</i></b></a>
+ |   |   |- nucleo-f401re/
+ |   |   |   `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/nucleo-f401re/README.txt"><b><i>README.txt</i></b></a>
 |   |   |- nucleus2g/
 |   |   |   `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/nucleus2g/README.txt"><b><i>README.txt</i></b></a>
 |   |   |- nutiny-nuc120/
--- a/README.txt
+++ b/README.txt
@ -991,6 +991,8 @@ nuttx
 |   |- ntosd-dm320/
 |   |   |- doc/README.txt
 |   |   `- README.txt
+ |   |- nucleo-f401re/
+ |   |   `- README.txt
 |   |- nucleus2g/
 |   |   `- README.txt
 |   |- nutiny-nuc120/
--- a/arch/arm/include/stm32/chip.h
+++ b/arch/arm/include/stm32/chip.h
@ -1,7 +1,7 @@
 /************************************************************************************
 * arch/arm/include/stm32/chip.h
 *
- *   Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@ -1192,6 +1192,42 @@
 #  define STM32_NRNG                     1   /* Random number generator (RNG) */
 #  define STM32_NDCMI                    0   /* No digital camera interface (DCMI) */

+#elif defined(CONFIG_ARCH_CHIP_STM32F401RE)  /* LQFP-100 512Kb FLASH 192Kb SRAM */
+#  undef  CONFIG_STM32_STM32L15XX            /* STM32L151xx and STM32L152xx family */
+#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite vamily */
+#  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
+#  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+#  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+#  undef  CONFIG_STM32_HIGHDENSITY           /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
+#  undef  CONFIG_STM32_VALUELINE             /* STM32F100x */
+#  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
+#  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
+#  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx and STM32407xx */
+#  define STM32_NFSMC                    1   /* FSMC */
+#  define STM32_NATIM                    2   /* Two advanced timers TIM1 and 8 */
+#  define STM32_NGTIM                    4   /* 16-bit general timers TIM3 and 4 with DMA
+                                              * 32-bit general timers TIM2 and 5 with DMA */
+#  define STM32_NGTIMNDMA                6   /* 16-bit general timers TIM9-14 without DMA */
+#  define STM32_NBTIM                    2   /* Two basic timers, TIM6-7 */
+#  define STM32_NDMA                     2   /* DMA1-2 */
+#  define STM32_NSPI                     3   /* SPI1-3 */
+#  define STM32_NI2S                     2   /* I2S1-2 (multiplexed with SPI2-3) */
+#  define STM32_NUSART                   6   /* USART1-3 and 6, UART 4-5 */
+#  define STM32_NI2C                     3   /* I2C1-3 */
+#  define STM32_NCAN                     2   /* CAN1-2 */
+#  define STM32_NSDIO                    1   /* SDIO */
+#  define STM32_NLCD                     0   /* No LCD */
+#  define STM32_NUSBOTG                  1   /* USB OTG FS/HS */
+#  define STM32_NGPIO                    139 /* GPIOA-I */
+#  define STM32_NADC                     3   /* 12-bit ADC1-3, 16 channels */
+#  define STM32_NDAC                     0   /* 12-bit DAC1-2 */
+#  define STM32_NCAPSENSE                0   /* No capacitive sensing channels */
+#  define STM32_NCRC                     1   /* CRC */
+#  define STM32_NETHERNET                0   /* 100/100 Ethernet MAC */
+#  define STM32_NRNG                     1   /* Random number generator (RNG) */
+#  define STM32_NDCMI                    1   /* Digital camera interface (DCMI) */
+
 #elif defined(CONFIG_ARCH_CHIP_STM32F407VE)  /* LQFP-100 512Kb FLASH 192Kb SRAM */
 #  undef  CONFIG_STM32_STM32L15XX            /* STM32L151xx and STM32L152xx family */
 #  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite vamily */
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@ -433,6 +433,12 @@ config ARCH_CHIP_STM32F303VC
 	select STM32_STM32F30XX
 	select ARCH_HAVE_FPU

+config ARCH_CHIP_STM32F401RE
+	bool "STM32F401RE"
+	select ARCH_CORTEXM4
+	select STM32_STM32F40XX
+	select ARCH_HAVE_FPU
+
 config ARCH_CHIP_STM32F405RG
 	bool "STM32F405RG"
 	select ARCH_CORTEXM4
--- a/configs/Kconfig
+++ b/configs/Kconfig
@ -515,6 +515,13 @@ config ARCH_BOARD_PX4FMU_V2
 		latest supported configuration available from the PX4 GIT
 		repositories.

+config ARCH_BOARD_NUCLEO_F401RE
+	bool "STM32F401 Nucleo F401RE"
+	depends on ARCH_CHIP_STM32F401RE
+	---help---
+		This is a minimal configuration that supports low-level test of the
+		Nucleo F401RE in the NuttX source tree.
+
 config ARCH_BOARD_QEMU_I486
 	bool "Qemu i486 Mode"
 	depends on ARCH_X86 || ARCH_I486
@ -963,6 +970,7 @@ config ARCH_BOARD
 	default "pirelli_dpl10"       if ARCH_BOARD_PIRELLI_DPL10
 	default "pjrc-8051"           if ARCH_BOARD_PJRC_87C52
 	default "px4fmu-v2_upstream"  if ARCH_BOARD_PX4FMU_V2
+	default "nucleo-f401re"       if ARCH_BOARD_NUCLEO_F401RE
 	default "qemu-i486"           if ARCH_BOARD_QEMU_I486
 	default "rgmp"                if ARCH_BOARD_RGMP
 	default "sama5d3x-ek"         if ARCH_BOARD_SAMA5D3X_EK
@ -1205,6 +1213,9 @@ endif
 if ARCH_BOARD_PJRC_87C52
 source "configs/pjrc-8051/Kconfig"
 endif
+if ARCH_BOARD_NUCLEO_F401RE
+source "configs/nucleo-f401re/Kconfig"
+endif
 if ARCH_BOARD_PX4FMU_V2
 source "configs/px4fmu-v2_upstream/Kconfig"
 endif
--- a/configs/README.txt
+++ b/configs/README.txt
@ -335,6 +335,9 @@ configs/ntosd-dm320
  STATUS: This port is code complete, verified, and included in the
  NuttX 0.2.1 release.

+configs/nucleo-f401re
+  STMicro ST Nucleo F401RE http://mbed.org/platforms/ST-Nucleo-F401RE
+
 configs/nucleus2g
  This port uses the Nucleus 2G board (with Babel CAN board).  This board
  features an NXP LPC1768 processor.  See the 2G website (http://www.2g-eng.com/)
--- a/configs/nucleo-f401re/Kconfig
+++ b/configs/nucleo-f401re/Kconfig
@ -0,0 +1,4 @@
+#
+# For a description of the syntax of this configuration file,
+# see misc/tools/kconfig-language.txt.
+#
--- a/configs/nucleo-f401re/README.txt
+++ b/configs/nucleo-f401re/README.txt
@ -0,0 +1,451 @@
+README
+======
+
+This README discusses issues unique to NuttX configurations for the ST NucleoF401RE board 
+from ST Micro (http://www.st.com/web/catalog/mmc/FM141/SC1169/SS1577/LN1810/PF258797) 
+
+
+  Microprocessor: 32-bit ARM Cortex M4 at 84MHz STM32F104RE  
+  Memory:         512 KB Flash and 96 KB SRAM
+  I/O Pins Out:   37, 17 On the Connector
+  Network:        TI CC3000 Wifi Module
+  ADCs:           1 (at 12-bit resolution)
+  Peripherals:    10 timers, 2 I2Cs, 2 SPI ports, 3 USARTs, 1 led
+  Other:          Sleep, stop, and standby modes; serial wire debug and JTAG interfaces
+
+  It breaks out the Tx, Rx to connect to a FTDI TTL-232RG-VREG3V3-WE for the console and
+  wires in the spark LEDs and serial flash to the same I/O as the sparkcore. It has a Jlink
+  compatible Jtag connector on it.
+
+Contents
+========
+
+  - Development Environment
+  - GNU Toolchain Options
+  - IDEs
+  - NuttX EABI "buildroot" Toolchain
+  - NuttX OABI "buildroot" Toolchain
+  - NXFLAT Toolchain
+  - Hardware
+    - Core Pin out
+    - LED
+    - Button
+    - USARTS and Serial Consoles
+  - LQFP64
+  - DFU and JTAG
+  - Configurations
+
+Development Environment
+=======================
+
+  Either Linux or Cygwin on Windows can be used for the development environment.
+  The source has been built only using the GNU toolchain (see below).  Other
+  toolchains will likely cause problems.
+
+GNU Toolchain Options
+=====================
+
+  Toolchain Configurations
+  ------------------------
+  The NuttX make system has been modified to support the following different
+  toolchain options.
+
+  1. The CodeSourcery GNU toolchain,
+  2. The Atollic Toolchain,
+  3. The devkitARM GNU toolchain,
+  4. Raisonance GNU toolchain, or
+  5. The NuttX buildroot Toolchain (see below).
+
+  All testing has been conducted using the CodeSourcery toolchain for Linux. 
+  To use the Atollic, devkitARM, Raisonance GNU, or NuttX buildroot toolchain,
+  you simply need to add one of the following configuration options to your
+  .config (or defconfig) file:
+
+    CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=n  : CodeSourcery under Windows
+    CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y  : CodeSourcery under Linux
+    CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y        : The Atollic toolchain under Windows
+    CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=n      : devkitARM under Windows
+    CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE=y     : Raisonance RIDE7 under Windows
+    CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=n      : NuttX buildroot under Linux or Cygwin (default)
+
+  If you change the default toolchain, then you may also have to modify the PATH in
+  the setenv.h file if your make cannot find the tools.
+
+  NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are
+  Windows native toolchains.  The CodeSourcey (for Linux) and NuttX buildroot
+  toolchains are Cygwin and/or Linux native toolchains. There are several limitations
+  to using a Windows based toolchain in a Cygwin environment.  The three biggest are:
+
+  1. The Windows toolchain cannot follow Cygwin paths.  Path conversions are
+     performed automatically in the Cygwin makefiles using the 'cygpath' utility
+     but you might easily find some new path problems.  If so, check out 'cygpath -w'
+
+  2. Windows toolchains cannot follow Cygwin symbolic links.  Many symbolic links
+     are used in Nuttx (e.g., include/arch).  The make system works around these
+     problems for the Windows tools by copying directories instead of linking them.
+     But this can also cause some confusion for you:  For example, you may edit
+     a file in a "linked" directory and find that your changes had no effect.
+     That is because you are building the copy of the file in the "fake" symbolic
+     directory.  If you use a Windows toolchain, you should get in the habit of
+     making like this:
+
+       V=1 make clean_context all 2>&1 |tee mout 
+
+     An alias in your .bashrc file might make that less painful.
+
+  3. Dependencies are not made when using Windows versions of the GCC.  This is
+     because the dependencies are generated using Windows pathes which do not
+     work with the Cygwin make.
+
+       MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+
+  The CodeSourcery Toolchain (2009q1)
+  -----------------------------------
+  The CodeSourcery toolchain (2009q1) does not work with default optimization
+  level of -Os (See Make.defs).  It will work with -O0, -O1, or -O2, but not with
+  -Os.
+
+  The Atollic "Pro" and "Lite" Toolchain
+  --------------------------------------
+  One problem that I had with the Atollic toolchains is that the provide a gcc.exe
+  and g++.exe in the same bin/ file as their ARM binaries.  If the Atollic bin/ path
+  appears in your PATH variable before /usr/bin, then you will get the wrong gcc
+  when you try to build host executables.  This will cause to strange, uninterpretable
+  errors build some host binaries in tools/ when you first make.
+
+  Also, the Atollic toolchains are the only toolchains that have built-in support for
+  the FPU in these configurations.  If you plan to use the Cortex-M4 FPU, you will
+  need to use the Atollic toolchain for now.  See the FPU section below for more
+  information.
+
+  The Atollic "Lite" Toolchain
+  ----------------------------
+  The free, "Lite" version of the Atollic toolchain does not support C++ nor
+  does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite"
+  toolchain, you will have to set:
+
+    CONFIG_HAVE_CXX=n
+
+  In order to compile successfully.  Otherwise, you will get errors like:
+
+    "C++ Compiler only available in TrueSTUDIO Professional"
+
+  The make may then fail in some of the post link processing because of some of
+  the other missing tools.  The Make.defs file replaces the ar and nm with
+  the default system x86 tool versions and these seem to work okay.  Disable all
+  of the following to avoid using objcopy:
+
+    CONFIG_RRLOAD_BINARY=n
+    CONFIG_INTELHEX_BINARY=n
+    CONFIG_MOTOROLA_SREC=n
+    CONFIG_RAW_BINARY=n
+
+  devkitARM
+  ---------
+  The devkitARM toolchain includes a version of MSYS make.  Make sure that the
+  the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM
+  path or will get the wrong version of make.
+
+IDEs
+====
+
+  NuttX is built using command-line make.  It can be used with an IDE, but some
+  effort will be required to create the project.
+
+  Makefile Build
+  --------------
+  Under Eclipse, it is pretty easy to set up an "empty makefile project" and
+  simply use the NuttX makefile to build the system.  That is almost for free
+  under Linux.  Under Windows, you will need to set up the "Cygwin GCC" empty
+  makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
+  there is a lot of help on the internet).
+
+  Using Sourcery CodeBench from http://www.mentor.com/embedded-software/sourcery-tools/sourcery-codebench/overview
+    Download and install the latest version (as of this writting it was
+    sourceryg++-2013.05-64-arm-none-eabi)
+
+   Import the  project from git.
+     File->import->Git-URI, then import a Exiting code as a Makefile progject
+     from the working directory the git clone was done to.
+
+   Select the Sourcery CodeBench for ARM EABI. N.B. You must do one command line
+     build, before the make will work in CodeBench.
+
+  Native Build
+  ------------
+  Here are a few tips before you start that effort:
+
+  1) Select the toolchain that you will be using in your .config file
+  2) Start the NuttX build at least one time from the Cygwin command line
+     before trying to create your project.  This is necessary to create
+     certain auto-generated files and directories that will be needed.
+  3) Set up include pathes:  You will need include/, arch/arm/src/stm32,
+     arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
+  4) All assembly files need to have the definition option -D __ASSEMBLY__
+     on the command line.
+
+  Startup files will probably cause you some headaches.  The NuttX startup file
+  is arch/arm/src/stm32/stm32_vectors.S.  With RIDE, I have to build NuttX
+  one time from the Cygwin command line in order to obtain the pre-built
+  startup object needed by RIDE.
+
+NuttX EABI "buildroot" Toolchain
+================================
+
+  A GNU GCC-based toolchain is assumed.  The files */setenv.sh should
+  be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
+  different from the default in your PATH variable).
+
+  If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX
+  SourceForge download site (https://sourceforge.net/projects/nuttx/files/buildroot/).
+  This GNU toolchain builds and executes in the Linux or Cygwin environment.
+
+  1. You must have already configured Nuttx in <some-dir>/nuttx.
+
+     cd tools
+     ./configure.sh stm32_tiny/<sub-dir>
+
+  2. Download the latest buildroot package into <some-dir>
+
+  3. unpack the buildroot tarball.  The resulting directory may
+     have versioning information on it like buildroot-x.y.z.  If so,
+     rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
+
+  4. cd <some-dir>/buildroot
+
+  5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config
+
+  6. make oldconfig
+
+  7. make
+
+  8. Edit setenv.h, if necessary, so that the PATH variable includes
+     the path to the newly built binaries.
+
+  See the file configs/README.txt in the buildroot source tree.  That has more
+  details PLUS some special instructions that you will need to follow if you are
+  building a Cortex-M3 toolchain for Cygwin under Windows.
+
+  NOTE:  Unfortunately, the 4.6.3 EABI toolchain is not compatible with the
+  the NXFLAT tools.  See the top-level TODO file (under "Binary loaders") for
+  more information about this problem. If you plan to use NXFLAT, please do not
+  use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain.
+  See instructions below.
+
+NuttX OABI "buildroot" Toolchain
+================================
+
+  The older, OABI buildroot toolchain is also available.  To use the OABI
+  toolchain:
+
+  1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3
+     configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI
+     configuration such as cortexm3-defconfig-4.3.3
+
+  2. Modify the Make.defs file to use the OABI conventions:
+
+    +CROSSDEV = arm-nuttx-elf-
+    +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft
+    +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections
+    -CROSSDEV = arm-nuttx-eabi-
+    -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+    -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+
+NXFLAT Toolchain
+================
+
+  If you are *not* using the NuttX buildroot toolchain and you want to use
+  the NXFLAT tools, then you will still have to build a portion of the buildroot
+  tools -- just the NXFLAT tools.  The buildroot with the NXFLAT tools can
+  be downloaded from the NuttX SourceForge download site
+  (https://sourceforge.net/projects/nuttx/files/).
+
+  This GNU toolchain builds and executes in the Linux or Cygwin environment.
+
+  1. You must have already configured Nuttx in <some-dir>/nuttx.
+
+     cd tools
+     ./configure.sh lpcxpresso-lpc1768/<sub-dir>
+
+  2. Download the latest buildroot package into <some-dir>
+
+  3. unpack the buildroot tarball.  The resulting directory may
+     have versioning information on it like buildroot-x.y.z.  If so,
+     rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
+
+  4. cd <some-dir>/buildroot
+
+  5. cp configs/cortexm3-defconfig-nxflat .config
+
+  6. make oldconfig
+
+  7. make
+
+  8. Edit setenv.h, if necessary, so that the PATH variable includes
+     the path to the newly builtNXFLAT binaries.
+
+DFU and JTAG
+============
+
+  Enbling Support for the DFU Bootloader
+  --------------------------------------
+  The linker files in these projects can be configured to indicate that you
+  will be loading code using STMicro built-in USB Device Firmware Upgrade (DFU)
+  loader or via some JTAG emulator.  You can specify the DFU bootloader by
+  adding the following line:
+
+    CONFIG_STM32_DFU=y
+
+  to your .config file. Most of the configurations in this directory are set
+  up to use the DFU loader.
+
+  If CONFIG_STM32_DFU is defined, the code will not be positioned at the beginning
+  of FLASH (0x08000000) but will be offset to 0x08005000.  This offset is needed
+  to make space for the DFU loader and 0x08005000 is where the DFU loader expects
+  to find new applications at boot time.  If you need to change that origin for some
+  other bootloader, you will need to edit the file(s) ld.script.dfu for the
+  configuration.
+
+  For Linux or Mac:
+  ----------------
+
+  While on Linux or Mac, 
+
+  $ lsusb
+  Bus 003 Device 061: ID 0483:374b STMicroelectronics
+
+  $ st-flash write nuttx.bin 0x08000000
+
+  Enabling JTAG
+  -------------
+  If you are not using the DFU, then you will probably also need to enable
+  JTAG support.  By default, all JTAG support is disabled but there NuttX
+  configuration options to enable JTAG in various different ways.
+
+  These configurations effect the setting of the SWJ_CFG[2:0] bits in the AFIO
+  MAPR register.  These bits are used to configure the SWJ and trace alternate function I/Os.
+  The SWJ (SerialWire JTAG) supports JTAG or SWD access to the Cortex debug port.
+  The default state in this port is for all JTAG support to be disable.
+
+  CONFIG_STM32_JTAG_FULL_ENABLE - sets SWJ_CFG[2:0] to 000 which enables full
+    SWJ (JTAG-DP + SW-DP)
+
+  CONFIG_STM32_JTAG_NOJNTRST_ENABLE - sets SWJ_CFG[2:0] to 001 which enable
+    full SWJ (JTAG-DP + SW-DP) but without JNTRST.
+
+  CONFIG_STM32_JTAG_SW_ENABLE - sets SWJ_CFG[2:0] to 010 which would set JTAG-DP
+    disabled and SW-DP enabled
+
+  The default setting (none of the above defined) is SWJ_CFG[2:0] set to 100
+  which disable JTAG-DP and SW-DP.
+
+Hardware
+========
+
+Buttons and LEDs
+================
+
+  Buttons
+  -------
+
+  LEDs
+  ----
+
+Serial Consoles
+===============
+
+  USART2
+  -----
+  If you have a 3.3 V TTL to RS-232 convertor then this is the most convenient
+  serial console to use.  UART2 is the default in all of these
+  configurations.
+
+    USART2 RX  PA3   JP1 pin 4
+    USART2 TX  PA2   JP1 pin 3
+    GND              JP1 pin 2
+    V3.3             JP2 pin 1
+
+  Virtual COM Port
+  ----------------
+  Yet another option is to use UART0 and the USB virtual COM port.  This
+  option may be more convenient for long term development, but was
+  painful to use during board bring-up.
+
+Configurations
+==============
+
+  Composite: The composite is a super set of all the functions in nsh,
+  usbserial, usbmsc. (usbnsh has not been rung out).
+
+  Build it with
+
+    make distclean;(cd tools;./configure.sh nucleo-f401re/nsh)    
+
+  then run make menuconfig if you wish to customize things.
+
+  or
+ 
+  $ make qconfig
+
+  N.B. Memory is tight, both Flash and RAM are taxed. If you enable
+  debugging you will need to add -Os following the line -g in the line:
+
+    ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+      ARCHOPTIMIZATION = -g
+
+  in the top level Make.degs or the code will not fit.
+
+  Stack space has been hand optimized using the stack coloring by enabling
+  "Stack usage debug hooks" (CONFIG_DEBUG_STACK) in Build Setup-> Debug
+  Options. I have selected values that have 8-16 bytes of headroom with
+  network debugging on. If you enable more debugging and get a hard fault
+  or any weirdness like commands hanging. Then the Idle, main or Interrupt
+  stack my be too small. Stop the target and have a look a memory for a
+  blown stack: No DEADBEEF at the lowest address of a given stack.
+
+  Given the RAM memory constraints it is not possible to be running the
+  network and USB CDC/ACM and MSC at the same time. But on the bright
+  side, you can export the FLASH memory to the PC. Write files on the
+  Flash. Reboot and mount the FAT FS and run network code that will have
+  access the files.
+
+  You can use the scripts/cdc-acm.inf file to install the windows
+  composite device.
+
+  Network control is facilitated by running the c3b (cc3000basic) application.
+
+  Run c3b from the nsh prompt.
+
+    +-------------------------------------------+
+    |      Nuttx CC3000 Demo Program            |
+    +-------------------------------------------+
+
+      01 - Initialize the CC3000
+      02 - Show RX & TX buffer sizes, & free RAM
+      03 - Start Smart Config
+      04 - Manually connect to AP
+      05 - Manually add connection profile
+      06 - List access points
+      07 - Show CC3000 information
+      08 - Telnet
+
+     Type 01-07 to select above option:
+
+  Select 01. Then use 03 and the TI Smart config application running on an
+  IOS or Android device to configure join your network.
+
+  Use 07 to see the IP address of the device.
+
+  (On the next reboot running c3b 01 the CC3000 will automaticaly rejoin the
+  network after the 01 give it a few seconds and enter 07 or 08)
+
+  Use 08 to start Telnet. Then you can connect to the device using the
+  address listed in command 07.
+
+  qq will exit the c3b with the telnet deamon running (if started)
+
+  Slow.... You will be thinking 300 bps. This is because of packet sizes and
+  how the select thread runs in the telnet session. Telnet is not the best
+  showcase for the CC3000, but simply a proof of network connectivity.
+
+  http POST and GET should be more efficient.
--- a/configs/nucleo-f401re/include/board.h
+++ b/configs/nucleo-f401re/include/board.h
@ -0,0 +1,328 @@
+/************************************************************************************
+ * configs/nucleo-f401re/include/board.h
+ * include/arch/board/board.h
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __CONFIGS_NUCLEO_F401RE_INCLUDE_BOARD_H
+#define __CONFIGS_NUCLEO_F401RE_INCLUDE_BOARD_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+#include <stm32.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Clocking *************************************************************************/
+/* The NUCLEO401RE uses a 24MHz crystal connected to the HSE.
+ *
+ * This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c:
+ *   System Clock source           : PLL (HSE)
+ *   SYSCLK(Hz)                    : 168000000    Determined by PLL configuration
+ *   HCLK(Hz)                      : 168000000    (STM32_RCC_CFGR_HPRE)
+ *   AHB Prescaler                 : 1            (STM32_RCC_CFGR_HPRE)
+ *   APB1 Prescaler                : 4            (STM32_RCC_CFGR_PPRE1)
+ *   APB2 Prescaler                : 2            (STM32_RCC_CFGR_PPRE2)
+ *   HSE Frequency(Hz)             : 24000000     (STM32_BOARD_XTAL)
+ *   PLLM                          : 24           (STM32_PLLCFG_PLLM)
+ *   PLLN                          : 336          (STM32_PLLCFG_PLLN)
+ *   PLLP                          : 2            (STM32_PLLCFG_PLLP)
+ *   PLLQ                          : 7            (STM32_PLLCFG_PPQ)
+ *   Main regulator output voltage : Scale1 mode  Needed for high speed SYSCLK
+ *   Flash Latency(WS)             : 5
+ *   Prefetch Buffer               : OFF
+ *   Instruction cache             : ON
+ *   Data cache                    : ON
+ *   Require 48MHz for USB OTG FS, : Enabled
+ *   SDIO and RNG clock
+ */
+
+/* HSI - 16 MHz RC factory-trimmed
+ * LSI - 32 KHz RC
+ * HSE - On-board crystal frequency is 24MHz
+ * LSE - not installed
+ */
+
+#define STM32_BOARD_XTAL        24000000ul
+
+#define STM32_HSI_FREQUENCY     16000000ul
+#define STM32_LSI_FREQUENCY     32000
+#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+//#define STM32_LSE_FREQUENCY     32768
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE
+ * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
+ *         = (25,000,000 / 25) * 336
+ *         = 336,000,000
+ * SYSCLK  = PLL_VCO / PLLP
+ *         = 336,000,000 / 2 = 168,000,000
+ * USB OTG FS, SDIO and RNG Clock
+ *         =  PLL_VCO / PLLQ
+ *         = 48,000,000
+ */
+
+#define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(24)
+#define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(336)
+#define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP_2
+#define STM32_PLLCFG_PLLQ       RCC_PLLCFG_PLLQ(7)
+
+#define STM32_SYSCLK_FREQUENCY  168000000ul
+
+/* AHB clock (HCLK) is SYSCLK (168MHz) */
+
+#define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK  /* HCLK  = SYSCLK / 1 */
+#define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
+#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY  /* same as above, to satisfy compiler */
+
+/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
+
+#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd4     /* PCLK1 = HCLK / 4 */
+#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/4)
+
+/* Timers driven from APB1 will be twice PCLK1 */
+
+#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM13_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM14_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+
+/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
+
+#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLKd2     /* PCLK2 = HCLK / 2 */
+#define STM32_PCLK2_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
+
+/* Timers driven from APB2 will be twice PCLK2 */
+
+#define STM32_APB2_TIM1_CLKIN   (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN   (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM9_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB2_TIM10_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB2_TIM11_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+
+/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
+ * otherwise frequency is 2xAPBx. 
+ * Note: TIM1,8 are on APB2, others on APB1
+ */
+
+#define STM32_TIM18_FREQUENCY   (2*STM32_PCLK2_FREQUENCY)
+#define STM32_TIM27_FREQUENCY   (2*STM32_PCLK1_FREQUENCY)
+
+/* SDIO dividers.  Note that slower clocking is required when DMA is disabled 
+ * in order to avoid RX overrun/TX underrun errors due to delayed responses
+ * to service FIFOs in interrupt driven mode.  These values have not been
+ * tuned!!!
+ *
+ * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
+ */
+  
+#define SDIO_INIT_CLKDIV        (178 << SDIO_CLKCR_CLKDIV_SHIFT)
+
+/* DMA ON:  HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
+ * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
+ */
+
+#ifdef CONFIG_SDIO_DMA
+#  define SDIO_MMCXFR_CLKDIV    (2 << SDIO_CLKCR_CLKDIV_SHIFT) 
+#else
+#  define SDIO_MMCXFR_CLKDIV    (3 << SDIO_CLKCR_CLKDIV_SHIFT) 
+#endif
+
+/* DMA ON:  HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
+ * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
+ */
+
+#ifdef CONFIG_SDIO_DMA
+#  define SDIO_SDXFR_CLKDIV     (1 << SDIO_CLKCR_CLKDIV_SHIFT)
+#else
+#  define SDIO_SDXFR_CLKDIV     (3 << SDIO_CLKCR_CLKDIV_SHIFT)
+#endif
+
+/* DMA Channl/Stream Selections *****************************************************/
+/* Stream selections are arbitrary for now but might become important in the future
+ * is we set aside more DMA channels/streams.
+ *
+ * SDIO DMA
+ *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA
+ *   DMAMAP_SDIO_2 = Channel 4, Stream 6
+ */
+
+#define DMAMAP_SDIO DMAMAP_SDIO_1
+
+// need to VERIFY fwb
+#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1
+#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1
+#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX
+#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX
+
+/* Alternate function pin selections ************************************************/
+
+/* UARTs */
+
+#define GPIO_USART1_RX   GPIO_USART1_RX_1    /* Console in from IO */
+#define GPIO_USART1_TX   0                   /* USART1 is RX-only */
+
+#define GPIO_USART2_RX   GPIO_USART2_RX_2
+#define GPIO_USART2_TX   GPIO_USART2_TX_2
+#define GPIO_USART2_RTS  GPIO_USART2_RTS_2
+#define GPIO_USART2_CTS  GPIO_USART2_CTS_2
+
+#define GPIO_USART3_RX   GPIO_USART3_RX_3
+#define GPIO_USART3_TX   GPIO_USART3_TX_3
+#define GPIO_USART2_RTS  GPIO_USART2_RTS_2
+#define GPIO_USART2_CTS  GPIO_USART2_CTS_2
+
+#define GPIO_UART4_RX    GPIO_UART4_RX_1
+#define GPIO_UART4_TX    GPIO_UART4_TX_1
+
+#define GPIO_USART6_RX   GPIO_USART6_RX_1
+#define GPIO_USART6_TX   GPIO_USART6_TX_1
+
+#define GPIO_UART7_RX    GPIO_UART7_RX_1
+#define GPIO_UART7_TX    GPIO_UART7_TX_1
+
+/* UART8 has no alternate pin config */
+
+/* UART RX DMA configurations */
+
+#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2
+#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2
+
+/* CAN
+ *
+ * CAN1 is routed to the onboard transceiver. 
+ * CAN2 is routed to the expansion connector.
+ */
+
+#define GPIO_CAN1_RX     GPIO_CAN1_RX_3
+#define GPIO_CAN1_TX     GPIO_CAN1_TX_3
+#define GPIO_CAN2_RX     GPIO_CAN2_RX_1
+#define GPIO_CAN2_TX     GPIO_CAN2_TX_2
+
+/* I2C
+ *
+ * The optional _GPIO configurations allow the I2C driver to manually
+ * reset the bus to clear stuck slaves.  They match the pin configuration,
+ * but are normally-high GPIOs.
+ */
+
+#define GPIO_I2C1_SCL    GPIO_I2C1_SCL_2
+#define GPIO_I2C1_SDA    GPIO_I2C1_SDA_2
+#define GPIO_I2C1_SCL_GPIO \
+   (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_I2C1_SDA_GPIO \
+   (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9)
+
+#define GPIO_I2C2_SCL    GPIO_I2C2_SCL_1
+#define GPIO_I2C2_SDA    GPIO_I2C2_SDA_1
+#define GPIO_I2C2_SCL_GPIO \
+   (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_I2C2_SDA_GPIO \
+   (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11)
+
+/* SPI
+ *
+ * There are sensors on SPI1, and SPI2 is connected to the FRAM.
+ */
+
+#define GPIO_SPI1_MISO   GPIO_SPI1_MISO_1
+#define GPIO_SPI1_MOSI   GPIO_SPI1_MOSI_1
+#define GPIO_SPI1_SCK    GPIO_SPI1_SCK_1
+
+#define GPIO_SPI2_MISO   GPIO_SPI2_MISO_1
+#define GPIO_SPI2_MOSI   GPIO_SPI2_MOSI_1
+#define GPIO_SPI2_SCK    GPIO_SPI2_SCK_2
+
+/* LED Definitions.  Needed if CONFIG_ARCH_LEDs is defined */
+
+#define LED_STARTED      0
+#define LED_HEAPALLOCATE 0
+#define LED_IRQSENABLED  0
+#define LED_STACKCREATED 1
+#define LED_INIRQ        1
+#define LED_SIGNAL       1
+#define LED_ASSERTION    1
+#define LED_PANIC        1
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+/************************************************************************************
+ * Name: stm32_boardinitialize
+ *
+ * Description:
+ *   All STM32 architectures must provide the following entry point.  This entry point
+ *   is called early in the intitialization -- after all memory has been configured
+ *   and mapped but before any devices have been initialized.
+ *
+ ************************************************************************************/
+
+void stm32_boardinitialize(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif  /* __CONFIGS_NUCLEO_F401RE_INCLUDE_BOARD_H */
--- a/configs/nucleo-f401re/nsh/Make.defs
+++ b/configs/nucleo-f401re/nsh/Make.defs
@ -0,0 +1,169 @@
+############################################################################
+# configs/nucleo-f401re/nsh/Make.defs
+#
+#   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(CROSSDEV)ar rcs
+NM = $(CROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCPUFLAGS = -mcpu=cortex-m4 \
+    -mthumb \
+    -march=armv7e-m \
+    -mfpu=fpv4-sp-d16 \
+    -mfloat-abi=hard
+
+# Pull in *just* libm from the toolchain ... this is grody
+
+LIBM = "${shell $(CC) $(ARCHCPUFLAGS) -print-file-name=libm.a}"
+EXTRA_LIBS += $(LIBM)
+
+# Use our linker script
+
+LDSCRIPT = ld.script
+
+ifeq ($(WINTOOL),y)
+  # Windows-native toolchains
+  DIRLINK = $(TOPDIR)/tools/copydir.sh
+  DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+  MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+  ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+  ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+  ifeq ($(PX4_WINTOOL),y)
+    # Windows-native toolchains (MSYS)
+    DIRLINK = $(TOPDIR)/tools/copydir.sh
+    DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+    MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+    ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+    ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+    ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+  else
+    # Linux/Cygwin-native toolchain 
+    MKDEP = $(TOPDIR)/tools/mkdeps.sh
+    ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+    ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+    ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+  endif
+endif
+
+# Tool versions
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+# Optimization flags
+
+ARCHOPTIMIZATION = $(MAXOPTIMIZATION) \
+    -fno-strict-aliasing \
+    -fno-strength-reduce \
+    -fomit-frame-pointer \
+    -funsafe-math-optimizations \
+    -fno-builtin-printf \
+    -ffunction-sections \
+    -fdata-sections
+
+ifeq ("${CONFIG_DEBUG_SYMBOLS}","y")
+ARCHOPTIMIZATION += -g
+endif
+
+ARCHCFLAGS = -std=gnu99
+ARCHCXXFLAGS = -fno-exceptions -fno-rtti -std=gnu++0x
+ARCHWARNINGS = -Wall \
+    -Wextra \
+    -Wdouble-promotion \
+    -Wshadow \
+    -Wfloat-equal \
+    -Wframe-larger-than=1024 \
+    -Wpointer-arith \
+    -Wlogical-op \
+    -Wmissing-declarations \
+    -Wpacked \
+    -Wno-unused-parameter
+#   -Wcast-qual  - generates spurious noreturn attribute warnings, try again later
+#   -Wconversion - would be nice, but too many "risky-but-safe" conversions in the code
+#   -Wcast-align - would help catch bad casts in some cases, but generates too many false positives
+
+ARCHCWARNINGS = $(ARCHWARNINGS) \
+    -Wbad-function-cast \
+    -Wstrict-prototypes \
+    -Wold-style-declaration \
+    -Wmissing-parameter-type \
+    -Wmissing-prototypes \
+    -Wnested-externs
+ARCHWARNINGSXX = $(ARCHWARNINGS) \
+    -Wno-psabi
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+# This seems to be the only way to add linker flags
+
+EXTRA_LIBS += --warn-common \
+    --gc-sections
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHCWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -fno-common
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(INSTRUMENTATIONDEFINES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(INSTRUMENTATIONDEFINES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+# Produce partially-linked $1 from files in $2
+
+define PRELINK
+ @echo "PRELINK: $1"
+ $(Q) $(LD) -Ur -o $1 $2 && $(OBJCOPY) --localize-hidden $1
+endef
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe
+HOSTLDFLAGS =
--- a/configs/nucleo-f401re/nsh/defconfig
+++ b/configs/nucleo-f401re/nsh/defconfig
--- a/configs/nucleo-f401re/nsh/setenv.sh
+++ b/configs/nucleo-f401re/nsh/setenv.sh
@ -0,0 +1,63 @@
+#!/bin/bash
+# configs/nucleo-f401re/nsh/setenv.sh
+#
+#   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$_" = "$0" ] ; then
+  echo "You must source this script, not run it!" 1>&2
+  exit 1
+fi
+
+WD=`pwd`
+if [ ! -x "setenv.sh" ]; then
+  echo "This script must be executed from the top-level NuttX build directory"
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+  export PATH_ORIG="${PATH}"
+fi
+
+# This the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows.  You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin
+
+# This the Cygwin path to the location where I build the buildroot
+# toolchain.
+#export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
--- a/configs/nucleo-f401re/scripts/ld.script
+++ b/configs/nucleo-f401re/scripts/ld.script
@ -0,0 +1,120 @@
+/****************************************************************************
+ * configs/nucleo-f401re/scripts/ld.script
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Librae <librae8226@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The STM32F401RE has 512Kb of FLASH beginning at address 0x0800:0000 and
+ * 96Kb of SRAM beginning at address 0x2000:0000.  When booting from FLASH,
+ * FLASH memory is aliased to address 0x0000:0000 where the code expects to
+ * begin execution by jumping to the entry point in the 0x0800:0000 address
+ * range.
+ */
+
+MEMORY
+{
+    flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+	/* Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM */
+    sram (rwx) : ORIGIN = 0x20000000+0x194, LENGTH = (96K-0x194)
+}
+
+OUTPUT_ARCH(arm)
+ENTRY(_stext)
+SECTIONS
+{
+	.text : {
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		*(.text .text.*)
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		_etext = ABSOLUTE(.);
+	} > flash
+
+	.init_section : {
+		_sinit = ABSOLUTE(.);
+		*(.init_array .init_array.*)
+		_einit = ABSOLUTE(.);
+	} > flash
+
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} > flash
+
+	__exidx_start = ABSOLUTE(.);
+	.ARM.exidx : {
+		*(.ARM.exidx*)
+	} > flash
+	__exidx_end = ABSOLUTE(.);
+
+	_eronly = ABSOLUTE(.);
+
+	/* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */
+
+	.data : {
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+	} > sram AT > flash
+
+	.bss : {
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		_ebss = ABSOLUTE(.);
+	} > sram
+
+	/* Stabs debugging sections. */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
--- a/configs/nucleo-f401re/src/Makefile
+++ b/configs/nucleo-f401re/src/Makefile
@ -0,0 +1,92 @@
+############################################################################
+# configs/nucleo-f401re/src/Makefile
+#
+#   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+CFLAGS += -I$(TOPDIR)/sched
+
+ASRCS = 
+AOBJS = $(ASRCS:.S=$(OBJEXT))
+
+CSRCS = stm32_boot.c stm32_init.c stm32_led.c stm32_spi.c
+
+ifeq ($(CONFIG_WL_CC3000),y)
+CSRCS += stm32_wireless.c
+endif
+
+ifeq ($(CONFIG_CC3000_PROBES),)
+CSRCS += up_io.c
+endif
+
+COBJS = $(CSRCS:.c=$(OBJEXT))
+
+SRCS = $(ASRCS) $(CSRCS)
+OBJS = $(AOBJS) $(COBJS)
+
+ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
+ifeq ($(WINTOOL),y)
+  CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
+            -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
+            -I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
+else
+  CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
+endif
+
+all: libboard$(LIBEXT)
+
+$(AOBJS): %$(OBJEXT): %.S
+	$(call ASSEMBLE, $<, $@)
+
+$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c
+	$(call COMPILE, $<, $@)
+
+libboard$(LIBEXT): $(OBJS)
+	$(call ARCHIVE, $@, $(OBJS))
+
+.depend: Makefile $(SRCS)
+	$(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
+	$(Q) touch $@
+
+depend: .depend
+
+clean:
+	$(call DELFILE, libboard$(LIBEXT))
+	$(call CLEAN)
+
+distclean: clean
+	$(call DELFILE, Make.dep)
+	$(call DELFILE, .depend)
+
+-include Make.dep
--- a/configs/nucleo-f401re/src/board_config.h
+++ b/configs/nucleo-f401re/src/board_config.h
@ -0,0 +1,264 @@
+/****************************************************************************
+ * configs/px4fmu-v2_upstream/src/board_config.h
+ *
+ *   Copyright (c) 2013, 2014 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __CONFIGS_NUCLEO_F401RE_SRC_NUCLEO_F401RE_H
+#define __CONFIGS_NUCLEO_F401RE_SRC_BOARD_CONFIG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+__BEGIN_DECLS
+#endif
+
+/* These headers are not C++ safe */
+
+#include <stm32.h>
+#include <arch/board/board.h>
+
+#define UDID_START        0x1FFF7A10
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* Configuration ************************************************************/
+
+/* PX4IO connection configuration */
+
+#define PX4IO_SERIAL_DEVICE    "/dev/ttyS4"
+#define PX4IO_SERIAL_TX_GPIO    GPIO_USART6_TX
+#define PX4IO_SERIAL_RX_GPIO    GPIO_USART6_RX
+#define PX4IO_SERIAL_BASE       STM32_USART6_BASE    /* hardwired on the board */
+#define PX4IO_SERIAL_VECTOR     STM32_IRQ_USART6
+#define PX4IO_SERIAL_TX_DMAMAP  DMAMAP_USART6_TX_2
+#define PX4IO_SERIAL_RX_DMAMAP  DMAMAP_USART6_RX_2
+#define PX4IO_SERIAL_CLOCK      STM32_PCLK2_FREQUENCY
+#define PX4IO_SERIAL_BITRATE    1500000              /* 1.5Mbps -> max rate for IO */
+
+/* PX4FMU GPIOs *************************************************************/
+/* LEDs */
+
+#define GPIO_LED1 \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN12)
+
+/* External interrupts */
+
+#define GPIO_EXTI_GYRO_DRDY     (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_EXTI_MAG_DRDY      (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_EXTI_ACCEL_DRDY    (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_EXTI_MPU_DRDY      (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTD|GPIO_PIN15)
+
+/* Data ready pins off */
+
+#define GPIO_GYRO_DRDY_OFF      (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_MAG_DRDY_OFF       (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ACCEL_DRDY_OFF     (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_EXTI_MPU_DRDY_OFF  (GPIO_INPUT|GPIO_PULLDOWN|GPIO_EXTI|GPIO_PORTD|GPIO_PIN15)
+
+/* SPI1 off */
+
+#define GPIO_SPI1_SCK_OFF       (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_SPI1_MISO_OFF      (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_SPI1_MOSI_OFF      (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTA|GPIO_PIN7)
+
+/* SPI1 chip selects off */
+
+#define GPIO_SPI_CS_GYRO_OFF \
+  (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTC|GPIO_PIN13)
+#define GPIO_SPI_CS_ACCEL_MAG_OFF \
+  (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTC|GPIO_PIN15)
+#define GPIO_SPI_CS_BARO_OFF \
+  (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTD|GPIO_PIN7)
+#define GPIO_SPI_CS_MPU_OFF \
+  (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTC|GPIO_PIN2)
+
+/* SPI chip selects */
+
+#define GPIO_SPI_CS_GYRO \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN13)
+#define GPIO_SPI_CS_ACCEL_MAG \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN15)
+#define GPIO_SPI_CS_BARO \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN7)
+#define GPIO_SPI_CS_FRAM \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN10)
+#define GPIO_SPI_CS_MPU \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN2)
+
+/* Use these in place of the spi_dev_e enumeration to select a specific SPI
+ * device on SPI1
+ */
+
+#define PX4_SPIDEV_GYRO         1
+#define PX4_SPIDEV_ACCEL_MAG    2
+#define PX4_SPIDEV_BARO         3
+#define PX4_SPIDEV_MPU          4
+
+/* I2C busses */
+#define PX4_I2C_BUS_EXPANSION   1
+#define PX4_I2C_BUS_LED         2
+
+/* Devices on the onboard bus.
+ *
+ * Note that these are unshifted addresses.
+ */
+
+#define PX4_I2C_OBDEV_LED       0x55
+#define PX4_I2C_OBDEV_HMC5883   0x1e
+
+/* User GPIOs
+ *
+ * GPIO0-5 are the PWM servo outputs.
+ */
+
+#define GPIO_GPIO0_INPUT        (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN14)
+#define GPIO_GPIO1_INPUT        (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN13)
+#define GPIO_GPIO2_INPUT        (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN11)
+#define GPIO_GPIO3_INPUT        (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN9)
+#define GPIO_GPIO4_INPUT        (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTD|GPIO_PIN13)
+#define GPIO_GPIO5_INPUT        (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTD|GPIO_PIN14)
+#define GPIO_GPIO0_OUTPUT \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN14)
+#define GPIO_GPIO1_OUTPUT \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN13)
+#define GPIO_GPIO2_OUTPUT \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN11)
+#define GPIO_GPIO3_OUTPUT \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN9)
+#define GPIO_GPIO4_OUTPUT \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN13)
+#define GPIO_GPIO5_OUTPUT \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN14)
+
+/* Power supply control and monitoring GPIOs */
+
+#define GPIO_VDD_5V_PERIPH_EN \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_VDD_BRICK_VALID    (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_VDD_SERVO_VALID    (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_VDD_3V3_SENSORS_EN \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3)
+#define GPIO_VDD_5V_HIPOWER_OC  (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN10)
+#define GPIO_VDD_5V_PERIPH_OC   (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN15)
+
+/* Tone alarm output */
+
+#define TONE_ALARM_TIMER        2    /* timer 2 */
+#define TONE_ALARM_CHANNEL      1    /* channel 1 */
+#define GPIO_TONE_ALARM_IDLE \
+  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_TONE_ALARM \
+  (GPIO_ALT|GPIO_AF1|GPIO_SPEED_2MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15)
+
+/* PWM
+ *
+ * Six PWM outputs are configured.
+ *
+ * Pins:
+ *
+ * CH1 : PE14 : TIM1_CH4
+ * CH2 : PE13 : TIM1_CH3
+ * CH3 : PE11 : TIM1_CH2
+ * CH4 : PE9  : TIM1_CH1
+ * CH5 : PD13 : TIM4_CH2
+ * CH6 : PD14 : TIM4_CH3
+ */
+
+#define GPIO_TIM1_CH1OUT        GPIO_TIM1_CH1OUT_2
+#define GPIO_TIM1_CH2OUT        GPIO_TIM1_CH2OUT_2
+#define GPIO_TIM1_CH3OUT        GPIO_TIM1_CH3OUT_2
+#define GPIO_TIM1_CH4OUT        GPIO_TIM1_CH4OUT_2
+#define GPIO_TIM4_CH2OUT        GPIO_TIM4_CH2OUT_2
+#define GPIO_TIM4_CH3OUT        GPIO_TIM4_CH3OUT_2
+
+/* USB OTG FS
+ *
+ * PA9  OTG_FS_VBUS VBUS sensing (also connected to the green LED)
+ */
+
+#define GPIO_OTGFS_VBUS \
+  (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
+
+/* High-resolution timer */
+
+#define HRT_TIMER               8    /* Use timer8 for the HRT */
+#define HRT_TIMER_CHANNEL       1    /* Use capture/compare channel */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_spiinitialize
+ *
+ * Description:
+ *   Called to configure SPI chip select GPIO pins for the PX4FMU board.
+ *
+ ****************************************************************************/
+
+void stm32_spiinitialize(void);
+
+/* Ideally we'd be able to get these from up_internal.h,  but since we want
+ * to be able to disable the NuttX use of leds for system indication at will
+ * and there is no separate switch, we need to build independent of the
+ * CONFIG_ARCH_LEDS configuration switch.
+ */
+
+void led_init(void);
+void led_on(int led);
+void led_off(int led);
+void led_toggle(int led);
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __cplusplus
+__END_DECLS
+#endif
+
+#endif  /* __CONFIGS_NUCLEO_F401RE_SRC_BOARD_CONFIG_H */
--- a/configs/nucleo-f401re/src/nucleo-f401re.h
+++ b/configs/nucleo-f401re/src/nucleo-f401re.h
@ -0,0 +1,83 @@
+/************************************************************************************
+ * configs/nucleo-f401re/src/nucleo-f401re.h
+ *
+ ************************************************************************************/
+
+#ifndef __CONFIGS_NUCLEO_F401RE_SRC_NUCLEO_F401RE_H
+#define __CONFIGS_NUCLEO_F401RE_SRC_NUCLEO_F401RE_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+#include <stdint.h>
+
+/*
+ The shield uses the following pins:
+
+    +5V
+    GND
+    Digital pin  3: IRQ for WiFi
+    Digital pin  4: Card Select for SD card
+    Digital pin  5: WiFi enable
+    Digital pin 10: Chip Select for WiFi
+    Digital pins 11, 12, 13 for SPI communication (both WiFi and SD). 
+    Digital pin 11:
+    Digital pin 12:
+    Digital pin 13:
+    Even if optional 6-pin SPI header is used, these pins are unavailable for other use.
+ */
+
+#define GPIO_WIFI_INT (GPIO_PORTB | GPIO_PIN3  | GPIO_INPUT        | GPIO_PULLUP | GPIO_EXTI)
+#define GPIO_WIFI_EN  (GPIO_PORTB | GPIO_PIN4  | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
+#define GPIO_WIFI_CS  (GPIO_PORTB | GPIO_PIN6  | GPIO_OUTPUT_SET   | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
+
+#define GPIO_LED1     (GPIO_PORTA | GPIO_PIN13 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
+
+#if defined(CONFIG_CC3000_PROBES)
+#define GPIO_D0       (GPIO_PORTB | GPIO_PIN7  | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
+#define GPIO_D1       (GPIO_PORTB | GPIO_PIN6  | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
+#else
+#define GPIO_D0       (GPIO_PORTA | GPIO_PIN3  | GPIO_INPUT        | GPIO_PULLUP | GPIO_EXTI)
+#define GPIO_D1       (GPIO_PORTA | GPIO_PIN2  | GPIO_INPUT        | GPIO_PULLUP | GPIO_EXTI)
+#define GPIO_D2       (GPIO_PORTA | GPIO_PIN10 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
+
+#define GPIO_D8       (GPIO_PORTA | GPIO_PIN9  | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
+
+#define GPIO_A0       (GPIO_PORTA | GPIO_PIN0  | GPIO_OUTPUT_SET   | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
+#define GPIO_A1       (GPIO_PORTA | GPIO_PIN1  | GPIO_OUTPUT_SET   | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
+#define GPIO_A2       (GPIO_PORTA | GPIO_PIN4  | GPIO_INPUT        | GPIO_PULLUP )
+#define GPIO_A3       (GPIO_PORTB | GPIO_PIN0  | GPIO_INPUT        | GPIO_PULLUP )
+#endif
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_spiinitialize
+ *
+ * Description:
+ *   Called to configure SPI chip select GPIO pins.
+ *
+ ************************************************************************************/
+
+void stm32_spiinitialize(void);
+
+/************************************************************************************
+ * Name: stm32_usbinitialize
+ *
+ * Description:
+ *   Called to setup USB-related GPIO pins.
+ *
+ ************************************************************************************/
+
+void stm32_usbinitialize(void);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __CONFIGS_NUCLEO_F401RE_SRC_NUCLEO_F401RE_H */
+
--- a/configs/nucleo-f401re/src/stm32_boot.c
+++ b/configs/nucleo-f401re/src/stm32_boot.c
@ -0,0 +1,129 @@
+/************************************************************************************
+ * configs/nucleo-f401re/src/stm32_boot.c
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Librae <librae8226@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/spi/spi.h>
+#include <debug.h>
+
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "nucleo-f401re.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_boardinitialize
+ *
+ * Description:
+ *   All STM32 architectures must provide the following entry point.  This entry point
+ *   is called early in the initialization -- after all memory has been configured
+ *   and mapped but before any devices have been initialized.
+ *
+ ************************************************************************************/
+
+void stm32_boardinitialize(void)
+{
+  /* Configure on-board LEDs if LED support has been selected. */
+
+#ifdef CONFIG_ARCH_LEDS
+  board_led_initialize();
+#endif
+
+#ifdef CONFIG_ARCH_HAVE_BUTTONS
+  board_button_initialize();
+#endif
+
+  /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak function
+   * stm32_spiinitialize() has been brought into the link.
+   */
+
+#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3)
+  stm32_spiinitialize();
+#endif
+
+
+  /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not
+   * disabled, and 3) the weak function stm32_usbinitialize() has been brought
+   * into the build.
+   */
+
+#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB)
+  stm32_usbinitialize();
+#endif
+}
+
+/****************************************************************************
+ * Name: board_initialize
+ *
+ * Description:
+ *   If CONFIG_BOARD_INITIALIZE is selected, then an additional
+ *   initialization call will be performed in the boot-up sequence to a
+ *   function called board_initialize().  board_initialize() will be
+ *   called immediately after up_intiialize() is called and just before the
+ *   initial application is started.  This additional initialization phase
+ *   may be used, for example, to initialize board-specific device drivers.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BOARD_INITIALIZE
+void board_initialize(void)
+{
+  /* Perform NSH initialization here instead of from the NSH.  This
+   * alternative NSH initialization is necessary when NSH is ran in user-space
+   * but the initialization function must run in kernel space.
+   */
+
+#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_NSH_ARCHINIT)
+      nsh_archinitialize();
+      wireless_archinitialize(0);
+#endif
+}
+#endif
--- a/configs/nucleo-f401re/src/stm32_init.c
+++ b/configs/nucleo-f401re/src/stm32_init.c
@ -0,0 +1,296 @@
+/****************************************************************************
+ * configs/nucleo-f401re/src/stm32_init.c
+ *
+ * PX4FMU-specific early startup code.  This file implements the
+ * nsh_archinitialize() function that is called early by nsh during startup.
+ *
+ * Code here is run before the rcS script is invoked; it should start
+ * required subsystems and perform board-specific initialisation.
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <math.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/spi/spi.h>
+#include <nuttx/i2c.h>
+#include <nuttx/sdio.h>
+#include <nuttx/mmcsd.h>
+#include <nuttx/analog/adc.h>
+#include <nuttx/gran.h>
+
+#include <stm32.h>
+#include "board_config.h"
+#include <stm32_uart.h>
+
+#include <arch/board/board.h>
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#ifdef CONFIG_FAT_DMAMEMORY
+# if !defined(CONFIG_GRAN) || !defined(CONFIG_FAT_DMAMEMORY)
+#  error microSD DMA support requires CONFIG_GRAN
+# endif
+#endif
+
+/* PX4 LED colour codes */
+
+#define LED_AMBER      1
+#define LED_RED        1  /* Some boards have red rather than amber */
+#define LED_BLUE       0
+#define LED_SAFETY     2
+
+/* Debug ********************************************************************/
+
+#ifdef CONFIG_CPP_HAVE_VARARGS
+#  ifdef CONFIG_DEBUG
+#    define message(...) lowsyslog(__VA_ARGS__)
+#  else
+#    define message(...) printf(__VA_ARGS__)
+#  endif
+#else
+#  ifdef CONFIG_DEBUG
+#    define message lowsyslog
+#  else
+#    define message printf
+#  endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_FAT_DMAMEMORY
+static GRAN_HANDLE dma_allocator;
+
+/* The DMA heap size constrains the total number of things that can be
+ * ready to do DMA at a time.
+ *
+ * For example, FAT DMA depends on one sector-sized buffer per filesystem plus
+ * one sector-sized buffer per file.
+ *
+ * We use a fundamental alignment / granule size of 64B; this is sufficient
+ * to guarantee alignment for the largest STM32 DMA burst (16 beats x 32bits).
+ */
+
+static uint8_t g_dma_heap[8192] __attribute__((aligned(64)));
+#endif
+
+static struct spi_dev_s *spi1;
+static struct spi_dev_s *spi2;
+static struct sdio_dev_s *sdio;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_FAT_DMAMEMORY
+static void dma_alloc_init(void)
+{
+  dma_allocator =
+    gran_initialize(g_dma_heap,
+                    sizeof(g_dma_heap),
+                    7,  /* 128B granule - must be > alignment (XXX bug?) */
+                    6); /* 64B alignment */
+
+  if (dma_allocator == NULL)
+    {
+      message("[boot] DMA allocator setup FAILED");
+    }
+}
+#else
+# define dma_alloc_init()
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_FAT_DMAMEMORY
+/* DMA-aware allocator stubs for the FAT filesystem. */
+
+void *fat_dma_alloc(size_t size)
+{
+  return gran_alloc(dma_allocator, size);
+}
+
+void fat_dma_free(FAR void *memory, size_t size)
+{
+  gran_free(dma_allocator, memory, size);
+}
+
+#endif
+
+void up_netinitialize(void)
+{
+}
+
+/****************************************************************************
+ * Name: nsh_archinitialize
+ *
+ * Description:
+ *   Perform architecture specific initialization
+ *
+ ****************************************************************************/
+
+int nsh_archinitialize(void)
+{
+#ifdef CONFIG_MMCSD
+  int ret;
+#endif
+
+  /* Configure ADC pins */
+
+  stm32_configgpio(GPIO_ADC1_IN2);   /* BATT_VOLTAGE_SENS */
+  stm32_configgpio(GPIO_ADC1_IN3);   /* BATT_CURRENT_SENS */
+  stm32_configgpio(GPIO_ADC1_IN4);   /* VDD_5V_SENS */
+//stm32_configgpio(GPIO_ADC1_IN10);  /* used by VBUS valid */
+//stm32_configgpio(GPIO_ADC1_IN11);  /* unused */
+//stm32_configgpio(GPIO_ADC1_IN12);  /* used by MPU6000 CS */
+  stm32_configgpio(GPIO_ADC1_IN13);  /* FMU_AUX_ADC_1 */
+  stm32_configgpio(GPIO_ADC1_IN14);  /* FMU_AUX_ADC_2 */
+  stm32_configgpio(GPIO_ADC1_IN15);  /* PRESSURE_SENS */
+
+  /* Configure power supply control/sense pins */
+
+  stm32_configgpio(GPIO_VDD_5V_PERIPH_EN);
+  stm32_configgpio(GPIO_VDD_3V3_SENSORS_EN);
+  stm32_configgpio(GPIO_VDD_BRICK_VALID);
+  stm32_configgpio(GPIO_VDD_SERVO_VALID);
+  stm32_configgpio(GPIO_VDD_5V_HIPOWER_OC);
+  stm32_configgpio(GPIO_VDD_5V_PERIPH_OC);
+
+  /* Configure the DMA allocator */
+
+  dma_alloc_init();
+
+  /* Configure CPU load estimation */
+
+#ifdef CONFIG_SCHED_INSTRUMENTATION
+  cpuload_initialize_once();
+#endif
+
+  /* Initial LED state */
+
+  led_off(LED_AMBER);
+
+  /* Configure SPI-based devices */
+
+  spi1 = up_spiinitialize(1);
+  if (!spi1)
+    {
+      message("[boot] FAILED to initialize SPI port 1\n");
+      board_led_on(LED_AMBER);
+      return -ENODEV;
+    }
+
+  /* Default SPI1 to 1MHz and de-assert the known chip selects. */
+
+  SPI_SETFREQUENCY(spi1, 10000000);
+  SPI_SETBITS(spi1, 8);
+  SPI_SETMODE(spi1, SPIDEV_MODE3);
+  SPI_SELECT(spi1, PX4_SPIDEV_GYRO, false);
+  SPI_SELECT(spi1, PX4_SPIDEV_ACCEL_MAG, false);
+  SPI_SELECT(spi1, PX4_SPIDEV_BARO, false);
+  SPI_SELECT(spi1, PX4_SPIDEV_MPU, false);
+  up_udelay(20);
+
+  message("[boot] Initialized SPI port 1 (SENSORS)\n");
+
+  /* Get the SPI port for the FRAM */
+
+  spi2 = up_spiinitialize(2);
+  if (!spi2)
+    {
+      message("[boot] FAILED to initialize SPI port 2\n");
+      board_led_on(LED_AMBER);
+      return -ENODEV;
+    }
+
+  /* Default SPI2 to 37.5 MHz (40 MHz rounded to nearest valid divider, F4 max)
+   * and de-assert the known chip selects.
+   */
+
+  // XXX start with 10.4 MHz in FRAM usage and go up to 37.5 once validated
+
+  SPI_SETFREQUENCY(spi2, 12 * 1000 * 1000);
+  SPI_SETBITS(spi2, 8);
+  SPI_SETMODE(spi2, SPIDEV_MODE3);
+  SPI_SELECT(spi2, SPIDEV_FLASH, false);
+
+  message("[boot] Initialized SPI port 2 (RAMTRON FRAM)\n");
+
+#ifdef CONFIG_MMCSD
+  /* First, get an instance of the SDIO interface */
+
+  sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO);
+  if (!sdio)
+    {
+      message("[boot] Failed to initialize SDIO slot %d\n",
+              CONFIG_NSH_MMCSDSLOTNO);
+      return -ENODEV;
+    }
+
+  /* Now bind the SDIO interface to the MMC/SD driver */
+
+  ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio);
+  if (ret != OK)
+    {
+      message("[boot] Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
+      return ret;
+    }
+
+  /* Then let's guess and say that there is a card in the slot. There is no
+   * card detect GPIO.
+   */
+
+  sdio_mediachange(sdio, true);
+
+  message("[boot] Initialized SDIO\n");
+#endif
+
+  return OK;
+}
--- a/configs/nucleo-f401re/src/stm32_io.c
+++ b/configs/nucleo-f401re/src/stm32_io.c
@ -0,0 +1,195 @@
+/****************************************************************************
+ * configs/nucleo-f401re/src/stm32_io.c
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <arch/board/board.h>
+#include "chip/stm32_tim.h"
+
+#include "nucleo-f401re.h"
+
+#ifndef CONFIG_CC3000_PROBES
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_leds
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void up_leds(int r, int g ,int b, int freqs)
+{
+  long fosc = 72000000;
+  long prescale = 2048;
+  long p1s = fosc/prescale;
+  long p0p5s  = p1s/2;
+  long p;
+
+  static struct stm32_tim_dev_s *tim1 = 0;
+
+  if (tim1 == 0)
+    {
+      tim1 = stm32_tim_init(1);
+      STM32_TIM_SETMODE(tim1, STM32_TIM_MODE_UP);
+      STM32_TIM_SETCLOCK(tim1, p1s-8);
+      STM32_TIM_SETPERIOD(tim1, p1s);
+      STM32_TIM_SETCOMPARE(tim1, 1, 0);
+      STM32_TIM_SETCOMPARE(tim1, 2, 0);
+      STM32_TIM_SETCOMPARE(tim1, 3, 0);
+      STM32_TIM_SETCHANNEL(tim1, 1, STM32_TIM_CH_OUTPWM | STM32_TIM_CH_POLARITY_NEG);
+      STM32_TIM_SETCHANNEL(tim1, 2, STM32_TIM_CH_OUTPWM | STM32_TIM_CH_POLARITY_NEG);
+      STM32_TIM_SETCHANNEL(tim1, 3, STM32_TIM_CH_OUTPWM | STM32_TIM_CH_POLARITY_NEG);
+    }
+
+  p = freqs == 0 ? p1s : p1s / freqs;
+  STM32_TIM_SETPERIOD(tim1, p);
+
+  p = freqs == 0 ? p1s + 1 : p0p5s / freqs;
+
+  STM32_TIM_SETCOMPARE(tim1, 2, (r * p) / 255);
+  STM32_TIM_SETCOMPARE(tim1, 1, (b * p) / 255);
+  STM32_TIM_SETCOMPARE(tim1, 3, (g * p) / 255);
+}
+
+/****************************************************************************
+ * Name: up_ioinit
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void up_ioinit(void)
+{
+  /* Configure the GPIO pins as inputs.  NOTE that EXTI interrupts are 
+   * configured for all pins.
+   */
+
+  up_leds(0,0,0,0);
+  stm32_configgpio(GPIO_A0); /* Probes */
+  stm32_configgpio(GPIO_A1); /* Probes */
+  stm32_configgpio(GPIO_A2); /* Smart Config */
+  stm32_configgpio(GPIO_A3); /* not used */
+  stm32_configgpio(GPIO_D0); /* Sw 1 */
+  stm32_configgpio(GPIO_D1); /* Sw 2 */
+  stm32_configgpio(GPIO_D2); /* Activate */
+}
+
+/****************************************************************************
+ * Name: up_read_inputs
+ *
+ * N.B The return state in true logic, the button polarity is dealt here in
+ *
+ ****************************************************************************/
+
+uint8_t up_read_inputs(void)
+{
+  uint8_t bits = 0;
+  bits |= stm32_gpioread(GPIO_D0) == 0 ? 1 : 0;
+  bits |= stm32_gpioread(GPIO_D1) == 0 ? 2 : 0;
+  bits |= stm32_gpioread(GPIO_A2) == 0 ? 4 : 0;
+  bits |= stm32_gpioread(GPIO_A3) == 0 ? 8 : 0;
+  return bits;
+}
+
+/****************************************************************************
+ * Name: up_write_outputs
+ *
+ * N.B The return state in true logic, the button polarity is dealt here in
+ *
+ ****************************************************************************/
+
+void up_write_outputs(int id, bool bits)
+{
+  if (id == 2)
+    {
+      stm32_gpiowrite(GPIO_D2, bits);
+    }
+  else if (id == 0)
+    {
+      stm32_gpiowrite(GPIO_A0, bits);
+    }
+  else if (id == 1)
+    {
+      stm32_gpiowrite(GPIO_A1, bits);
+    }
+}
+
+/****************************************************************************
+ * Name: up_irqio
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+xcpt_t up_irqio(int id, xcpt_t irqhandler)
+{
+  xcpt_t oldhandler = NULL;
+
+  /* The following should be atomic */
+
+  if (id == 0)
+    {
+      oldhandler = stm32_gpiosetevent(GPIO_D0, true, true, true, irqhandler);
+    }
+  else if (id == 1)
+    {
+      oldhandler = stm32_gpiosetevent(GPIO_D1, true, true, true, irqhandler);
+    }
+
+  return oldhandler;
+}
+#endif /* CONFIG_CC3000_PROBES */
--- a/configs/nucleo-f401re/src/stm32_led.c
+++ b/configs/nucleo-f401re/src/stm32_led.c
@ -0,0 +1,92 @@
+/****************************************************************************
+ * configs/nucleo-f401re/src/stm32_led.c
+ *
+ *   Copyright (c) 2013 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+
+#include "stm32.h"
+#include "board_config.h"
+
+#include <arch/board/board.h>
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void led_init()
+{
+  /* Configure LED1 GPIO for output */
+
+  stm32_configgpio(GPIO_LED1);
+}
+
+void led_on(int led)
+{
+  if (led == 1)
+    {
+      /* Pull down to switch on */
+
+      stm32_gpiowrite(GPIO_LED1, false);
+    }
+}
+
+void led_off(int led)
+{
+  if (led == 1)
+    {
+      /* Pull up to switch off */
+
+      stm32_gpiowrite(GPIO_LED1, true);
+    }
+}
+
+void led_toggle(int led)
+{
+  if (led == 1)
+    {
+      if (stm32_gpioread(GPIO_LED1))
+        {
+          stm32_gpiowrite(GPIO_LED1, false);
+        }
+      else
+        {
+          stm32_gpiowrite(GPIO_LED1, true);
+        }
+    }
+}
--- a/configs/nucleo-f401re/src/stm32_spi.c
+++ b/configs/nucleo-f401re/src/stm32_spi.c
@ -0,0 +1,302 @@
+/****************************************************************************
+ * configs/nucleo-f401re/src/stm32_spi.c
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/spi/spi.h>
+#include <arch/board/board.h>
+
+#include <up_arch.h>
+#include <chip.h>
+#include <stm32.h>
+#include "board_config.h"
+
+#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3)
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Enables debug output from this file */
+
+#ifndef CONFIG_DEBUG
+#  undef CONFIG_DEBUG_SPI
+#  undef CONFIG_DEBUG_VERBOSE
+#endif
+
+#ifdef CONFIG_DEBUG_SPI
+#  define spidbg  lldbg
+#  ifdef CONFIG_DEBUG_VERBOSE
+#    define spivdbg lldbg
+#  else
+#    define spivdbg(x...)
+#  endif
+#else
+#  define spidbg(x...)
+#  define spivdbg(x...)
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_spiinitialize
+ *
+ * Description:
+ *   Called to configure SPI chip select GPIO pins for the PX4FMU board.
+ *
+ ************************************************************************************/
+
+void weak_function stm32_spiinitialize(void)
+{
+#ifdef CONFIG_STM32_SPI1
+  stm32_configgpio(GPIO_SPI_CS_GYRO);
+  stm32_configgpio(GPIO_SPI_CS_ACCEL_MAG);
+  stm32_configgpio(GPIO_SPI_CS_BARO);
+  stm32_configgpio(GPIO_SPI_CS_MPU);
+
+  /* De-activate all peripherals, required for some peripheral state machines */
+
+  stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1);
+  stm32_gpiowrite(GPIO_SPI_CS_ACCEL_MAG, 1);
+  stm32_gpiowrite(GPIO_SPI_CS_BARO, 1);
+  stm32_gpiowrite(GPIO_SPI_CS_MPU, 1);
+
+  stm32_configgpio(GPIO_EXTI_GYRO_DRDY);
+  stm32_configgpio(GPIO_EXTI_MAG_DRDY);
+  stm32_configgpio(GPIO_EXTI_ACCEL_DRDY);
+  stm32_configgpio(GPIO_EXTI_MPU_DRDY);
+#endif
+
+#ifdef CONFIG_STM32_SPI2
+  stm32_configgpio(GPIO_SPI_CS_FRAM);
+  stm32_gpiowrite(GPIO_SPI_CS_FRAM, 1);
+
+  /* Setup CS, EN & IRQ line IOs */
+
+#ifdef CONFIG_WL_CC3000
+  stm32_configgpio(GPIO_WIFI_CS);
+  stm32_configgpio(GPIO_WIFI_EN);
+  stm32_configgpio(GPIO_WIFI_INT);
+#endif
+
+#ifdef CONFIG_MTD_SST25
+  stm32_configgpio(GPIO_MEM_CS);    /* FLASH chip select */
+#endif
+#endif
+}
+
+/****************************************************************************
+ * Name:  stm32_spi1/2/3select and stm32_spi1/2/3status
+ *
+ * Description:
+ *   The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be
+ *   provided by board-specific logic.  They are implementations of the select
+ *   and status methods of the SPI interface defined by struct spi_ops_s (see
+ *   include/nuttx/spi/spi.h). All other methods (including up_spiinitialize())
+ *   are provided by common STM32 logic.  To use this common SPI logic on your
+ *   board:
+ *
+ *   1. Provide logic in stm32_boardinitialize() to configure SPI chip select
+ *      pins.
+ *   2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your
+ *      board-specific logic.  These functions will perform chip selection and
+ *      status operations using GPIOs in the way your board is configured.
+ *   3. Add a calls to up_spiinitialize() in your low level application
+ *      initialization logic
+ *   4. The handle returned by up_spiinitialize() may then be used to bind the
+ *      SPI driver to higher level logic (e.g., calling
+ *      mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ *      the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32_SPI1
+void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+  spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+
+  /* SPI select is active low, so write !selected to select the device */
+
+  switch (devid)
+    {
+    case PX4_SPIDEV_GYRO:
+      /* Making sure the other peripherals are not selected */
+
+      stm32_gpiowrite(GPIO_SPI_CS_GYRO, !selected);
+      stm32_gpiowrite(GPIO_SPI_CS_ACCEL_MAG, 1);
+      stm32_gpiowrite(GPIO_SPI_CS_BARO, 1);
+      stm32_gpiowrite(GPIO_SPI_CS_MPU, 1);
+      break;
+
+    case PX4_SPIDEV_ACCEL_MAG:
+      /* Making sure the other peripherals are not selected */
+
+      stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1);
+      stm32_gpiowrite(GPIO_SPI_CS_ACCEL_MAG, !selected);
+      stm32_gpiowrite(GPIO_SPI_CS_BARO, 1);
+      stm32_gpiowrite(GPIO_SPI_CS_MPU, 1);
+      break;
+
+    case PX4_SPIDEV_BARO:
+      /* Making sure the other peripherals are not selected */
+
+      stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1);
+      stm32_gpiowrite(GPIO_SPI_CS_ACCEL_MAG, 1);
+      stm32_gpiowrite(GPIO_SPI_CS_BARO, !selected);
+      stm32_gpiowrite(GPIO_SPI_CS_MPU, 1);
+      break;
+
+    case PX4_SPIDEV_MPU:
+      /* Making sure the other peripherals are not selected */
+
+      stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1);
+      stm32_gpiowrite(GPIO_SPI_CS_ACCEL_MAG, 1);
+      stm32_gpiowrite(GPIO_SPI_CS_BARO, 1);
+      stm32_gpiowrite(GPIO_SPI_CS_MPU, !selected);
+      break;
+
+    default:
+      break;
+    }
+}
+
+uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+  return 0;
+}
+#endif
+
+#ifdef CONFIG_STM32_SPI2
+void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+  spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+
+#if defined(CONFIG_MTD_SST25)
+
+  if (devid == SPIDEV_FLASH)
+    {
+      stm32_gpiowrite(GPIO_MEM_CS, !selected);
+    }
+  else
+#endif
+
+#if defined(CONFIG_WL_CC3000)
+  if (devid == SPIDEV_WIRELESS)
+    {
+      stm32_gpiowrite(GPIO_WIFI_CS, !selected);
+    }
+  else
+#endif
+    {
+      /* There can only be one device on this bus, so always select it */
+
+      stm32_gpiowrite(GPIO_SPI_CS_FRAM, !selected);
+    }
+}
+
+uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+  return 0;
+}
+#endif
+
+#ifdef CONFIG_STM32_SPI3
+void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+
+  spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+}
+
+uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+  return 0;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_spi1cmddata
+ *
+ * Description:
+ *   Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true)
+ *   or command (false). This function must be provided by platform-specific
+ *   logic. This is an implementation of the cmddata method of the SPI
+ *   interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
+ *
+ * Input Parameters:
+ *
+ *   spi - SPI device that controls the bus the device that requires the CMD/
+ *         DATA selection.
+ *   devid - If there are multiple devices on the bus, this selects which one
+ *         to select cmd or data.  NOTE:  This design restricts, for example,
+ *         one one SPI display per SPI bus.
+ *   cmd - true: select command; false: select data
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_CMDDATA
+#ifdef CONFIG_STM32_SPI1
+int stm32_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
+{
+  return -ENODEV;
+}
+#endif
+
+#ifdef CONFIG_STM32_SPI2
+int stm32_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
+{
+  return OK;
+}
+#endif
+
+#ifdef CONFIG_STM32_SPI3
+int stm32_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
+{
+  return OK;
+}
+#endif
+#endif /* CONFIG_SPI_CMDDATA */
+
+#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */
--- a/configs/nucleo-f401re/src/stm32_wireless.c
+++ b/configs/nucleo-f401re/src/stm32_wireless.c
@ -0,0 +1,363 @@
+/************************************************************************************
+ * configs/nucleo-f401re/src/stm32_wireless.c
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Laurent Latil <laurent@latil.nom.fr>
+ *           David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/spi/spi.h>
+#include <nuttx/wireless/wireless.h>
+#include <nuttx/wireless/cc3000.h>
+#include <nuttx/wireless/cc3000/include/cc3000_upif.h>
+
+#include "stm32.h"
+#include "nucleo-f401re.h"
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+/* Configuration ************************************************************/
+
+#ifdef CONFIG_WL_CC3000
+#ifndef CONFIG_WIRELESS
+#  error "Wireless support requires CONFIG_WIRELESS"
+#endif
+
+#ifndef CONFIG_STM32_SPI2
+#  error "CC3000 Wireless support requires CONFIG_STM32_SPI2"
+#endif
+
+#ifndef CC3000_SPI_FREQUENCY
+#  define CC3000_SPI_FREQUENCY 16000000
+#endif
+
+#ifndef CC3000_SPIDEV
+#  define CC3000_SPIDEV 2
+#endif
+
+#if CC3000_SPIDEV != 2
+#  error "CC3000_SPIDEV must be 2"
+#endif
+
+#ifndef CC3000_DEVMINOR
+#  define CC3000_DEVMINOR 0
+#endif
+
+#ifndef CONFIG_CC3000_RX_BUFFER_SIZE
+#define CONFIG_CC3000_RX_BUFFER_SIZE 132
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct stm32_config_s
+{
+  struct cc3000_config_s dev;
+  xcpt_t handler;
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* IRQ/GPIO access callbacks.  These operations all hidden behind callbacks
+ * to isolate the CC3000 driver from differences in GPIO interrupt handling
+ * by varying boards and MCUs.  If possible, interrupts should be configured
+ * on falling edges to detect the Ready Condition At T2: The normal master
+ * SPI write sequence is SPI_CS low, followed by SPI_IRQ low CC3000 to host,
+ * indicating that the CC3000 core module is ready to accept data. T2
+ * duration is approximately 7 ms.
+ *
+ *   irq_attach         - Attach the CC3000 interrupt handler to the GPIO interrupt
+ *   irq_enable         - Enable or disable the GPIO interrupt
+ *   clear_irq          - Acknowledge/clear any pending GPIO interrupt
+ *   power_enable       - Enable or disable Module enable.
+ *   chip_chip_select   - The Chip Select
+ *   wl_read_irq        - Return the state of the interrupt GPIO input
+ */
+
+static int  wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler);
+static void wl_enable_irq(FAR struct cc3000_config_s *state, bool enable);
+static void wl_clear_irq(FAR struct cc3000_config_s *state);
+static void wl_select(FAR struct cc3000_config_s *state, bool enable);
+static void wl_enable_power(FAR struct cc3000_config_s *state, bool enable);
+static bool wl_read_irq(FAR struct cc3000_config_s *state);
+#ifdef CONFIG_CC3000_PROBES
+static bool probe(FAR struct cc3000_config_s *state,int n, bool s);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* A reference to a structure of this type must be passed to the CC3000
+ * driver.  This structure provides information about the configuration
+ * of the CC3000 and provides some board-specific hooks.
+ *
+ * Memory for this structure is provided by the caller.  It is not copied
+ * by the driver and is presumed to persist while the driver is active. The
+ * memory must be writable because, under certain circumstances, the driver
+ * may modify frequency or X plate resistance values.
+ */
+
+static struct stm32_config_s g_cc3000_info =
+{
+  .dev.spi_frequency    = CONFIG_CC3000_SPI_FREQUENCY,
+  .dev.spi_mode         = CONFIG_CC3000_SPI_MODE,
+  .dev.max_rx_size      = 0,
+  .dev.irq_attach       = wl_attach_irq,
+  .dev.irq_enable       = wl_enable_irq,
+  .dev.irq_clear        = wl_clear_irq,
+  .dev.power_enable     = wl_enable_power,
+  .dev.chip_chip_select = wl_select,
+  .dev.irq_read         = wl_read_irq,
+#ifdef CONFIG_CC3000_PROBES
+  .dev.probe            = probe, /* This is used for debugging */
+#endif
+  .handler              = NULL,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/* IRQ/GPIO access callbacks.  These operations all hidden behind
+ * callbacks to isolate the CC3000 driver from differences in GPIO
+ * interrupt handling by varying boards and MCUs.  If possible,
+ * interrupts should be configured on both rising and falling edges
+ * so that contact and loss-of-contact events can be detected.
+ *
+ * attach  - Attach the CC3000 interrupt handler to the GPIO interrupt
+ * enable  - Enable or disable the GPIO interrupt
+ * clear   - Acknowledge/clear any pending GPIO interrupt
+ * pendown - Return the state of the pen down GPIO input
+ */
+
+static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler)
+{
+  FAR struct stm32_config_s *priv = (FAR struct stm32_config_s *)state;
+
+  /* Just save the handler for use when the interrupt is enabled */
+
+  priv->handler = handler;
+  return OK;
+}
+
+static void wl_enable_irq(FAR struct cc3000_config_s *state, bool enable)
+{
+  FAR struct stm32_config_s *priv = (FAR struct stm32_config_s *)state;
+
+  /* The caller should not attempt to enable interrupts if the handler
+   * has not yet been 'attached'
+   */
+
+  DEBUGASSERT(priv->handler || !enable);
+
+  /* Attach and enable, or detach and disable */
+
+  ivdbg("enable:%d\n", enable);
+  if (enable)
+    {
+      (void)stm32_gpiosetevent(GPIO_WIFI_INT, false, true, false, priv->handler);
+    }
+  else
+    {
+      (void)stm32_gpiosetevent(GPIO_WIFI_INT, false, false, false, NULL);
+    }
+}
+
+static void wl_enable_power(FAR struct cc3000_config_s *state, bool enable)
+{
+  ivdbg("enable:%d\n", enable);
+
+  /* Active high enable */
+
+  stm32_gpiowrite(GPIO_WIFI_EN, enable);
+}
+
+static void wl_select(FAR struct cc3000_config_s *state, bool enable)
+{
+  ivdbg("enable:%d\n", enable);
+
+  /* Active high enable */
+
+  stm32_gpiowrite(GPIO_WIFI_CS, enable);
+}
+
+static void wl_clear_irq(FAR struct cc3000_config_s *state)
+{
+  /* Does nothing */
+}
+
+static bool wl_read_irq(FAR struct cc3000_config_s *state)
+{
+  /* Active low*/
+
+  return  stm32_gpioread(GPIO_WIFI_INT) ? false : true;
+}
+
+#ifdef CONFIG_CC3000_PROBES
+static bool probe(FAR struct cc3000_config_s *state,int n, bool s)
+{
+  if (n == 0)
+    {
+      stm32_gpiowrite(GPIO_D0, s);
+    }
+
+  if (n == 1)
+    {
+      stm32_gpiowrite(GPIO_D1, s);
+    }
+
+  return true;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arch_wlinitialize
+ *
+ * Description:
+ *   Each board that supports a wireless device must provide this function.
+ *   This function is called by application-specific, setup logic to
+ *   configure the wireless device.  This function will register the driver
+ *   as /dev/wirelessN where N is the minor device number.
+ *
+ *
+ * Returned Value:
+ *   Zero is returned on success.  Otherwise, a negated errno value is
+ *   returned to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int wireless_archinitialize(size_t max_rx_size)
+{
+  FAR struct spi_dev_s *spi;
+
+  /* Init SPI bus */
+
+  idbg("minor %d\n", minor);
+  DEBUGASSERT(CONFIG_CC3000_DEVMINOR == 0);
+
+#ifdef CONFIG_CC3000_PROBES
+  stm32_configgpio(GPIO_D0);
+  stm32_configgpio(GPIO_D1);
+  stm32_gpiowrite(GPIO_D0, 1);
+  stm32_gpiowrite(GPIO_D1, 1);
+#endif
+
+  /* Get an instance of the SPI interface */
+
+  spi = up_spiinitialize(CONFIG_CC3000_SPIDEV);
+  if (!spi)
+    {
+      idbg("Failed to initialize SPI bus %d\n", CONFIG_CC3000_SPIDEV);
+      return -ENODEV;
+    }
+
+  /* Initialize and register the SPI CC3000 device */
+
+  g_cc3000_info.dev.max_rx_size = max_rx_size ? max_rx_size : CONFIG_CC3000_RX_BUFFER_SIZE;
+  int ret = cc3000_register(spi, &g_cc3000_info.dev, CONFIG_CC3000_DEVMINOR);
+  if (ret < 0)
+    {
+      idbg("Failed to initialize SPI bus %d\n", CONFIG_CC3000_SPIDEV);
+      return -ENODEV;
+    }
+
+  return OK;
+}
+
+/*****************************************************************************
+ * Name: C3000_wlan_init
+ *
+ * Description:
+ *   Initialize wlan driver
+ *
+ *   Warning: This function must be called before ANY other wlan driver
+ *   function
+ *
+ * Input Parameters:
+ *   sWlanCB   Asynchronous events callback.
+ *             0 no event call back.
+ *             - Call back parameters:
+ *               1) event_type: HCI_EVNT_WLAN_UNSOL_CONNECT connect event,
+ *                  HCI_EVNT_WLAN_UNSOL_DISCONNECT disconnect event,
+ *                  HCI_EVNT_WLAN_ASYNC_SIMPLE_CONFIG_DONE config done,
+ *                  HCI_EVNT_WLAN_UNSOL_DHCP dhcp report,
+ *                  HCI_EVNT_WLAN_ASYNC_PING_REPORT ping report OR
+ *                  HCI_EVNT_WLAN_KEEPALIVE keepalive.
+ *               2) data: pointer to extra data that received by the event
+ *                  (NULL no data).
+ *               3) length: data length.
+ *              - Events with extra data:
+ *                  HCI_EVNT_WLAN_UNSOL_DHCP: 4 bytes IP, 4 bytes Mask,
+ *                    4 bytes default gateway, 4 bytes DHCP server and 4 bytes
+ *                    for DNS server.
+ *                  HCI_EVNT_WLAN_ASYNC_PING_REPORT: 4 bytes Packets sent,
+ *                    4 bytes Packets received, 4 bytes Min round time,
+ *                    4 bytes Max round time and 4 bytes for Avg round time.
+ *
+ *     sFWPatches  0 no patch or pointer to FW patches
+ *     sDriverPatches  0 no patch or pointer to driver patches
+ *     sBootLoaderPatches  0 no patch or pointer to bootloader patches
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void cc3000_wlan_init(size_t max_tx_len,
+                      tWlanCB sWlanCB,
+                      tFWPatches sFWPatches, tDriverPatches
+                      sDriverPatches,  tBootLoaderPatches sBootLoaderPatches)
+{
+  wlan_init(max_tx_len, sWlanCB, sFWPatches, sDriverPatches, sBootLoaderPatches);
+}
+
+#endif /* CONFIG_WL_CC3000 */