SAMV7 MCAN: Finishes most of the initalization logic
This commit is contained in:
Gregory Nutt
parent
cabe75a51d
commit
d53f6b9353
@ -67,7 +67,7 @@
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#define SAM_MCAN_ECR_OFFSET 0x0040 /* Error Counter Register */
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#define SAM_MCAN_PSR_OFFSET 0x0044 /* Protocol Status Register */
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/* 0x0048-0x004c Reserved */
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#define SAM_MCAN_IR_OFFSET 0x0050 /* Interrupt Register*/
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#define SAM_MCAN_IR_OFFSET 0x0050 /* Interrupt Register*/
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#define SAM_MCAN_IE_OFFSET 0x0054 /* Interrupt Enable Register */
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#define SAM_MCAN_ILS_OFFSET 0x0058 /* Interrupt Line Select Register */
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#define SAM_MCAN_ILE_OFFSET 0x005c /* Interrupt Line Enable Register */
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@ -360,7 +360,7 @@
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/* Common bit definitions for Interrupt Register, Interrupt Enable Register, Interrupt
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* Line Select Register
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*/
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*/
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#define MCAN_INT_RF0N (1 << 0) /* Bit 0: Receive FIFO 0 New Message */
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#define MCAN_INT_RF0W (1 << 1) /* Bit 1: Receive FIFO 0 Watermark Reached */
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@ -393,6 +393,8 @@
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#define MCAN_INT_FOE (1 << 30) /* Bit 30: Format Error */
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#define MCAN_INT_STE (1 << 31) /* Bit 31: Stuff Error */
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#define MCAN_INT_ALL (0xffcfffff)
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/* Interrupt Line Enable Register */
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#define MCAN_ILE_EINT0 (1 << 0) /* Bit 0: Enable Interrupt Line 0 */
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@ -535,6 +537,7 @@
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#define MCAN_RXESC_F0DS_SHIFT (0) /* Bits 0-2: Receive FIFO 0 Data Field Size */
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#define MCAN_RXESC_F0DS_MASK (7 << MCAN_RXESC_F0DS_SHIFT)
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# define MCAN_RXESC_F0DS(n) ((uint32_t)(n) << MCAN_RXESC_F0DS_SHIFT)
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# define MCAN_RXESC_F0DS_8B (0 << MCAN_RXESC_F0DS_SHIFT) /* 8-byte data field */
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# define MCAN_RXESC_F0DS_12B (1 << MCAN_RXESC_F0DS_SHIFT) /* 12-byte data field */
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# define MCAN_RXESC_F0DS_16B (2 << MCAN_RXESC_F0DS_SHIFT) /* 16-byte data field */
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@ -545,6 +548,7 @@
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# define MCAN_RXESC_F0DS_64B (7 << MCAN_RXESC_F0DS_SHIFT) /* 64-byte data field */
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#define MCAN_RXESC_F1DS_SHIFT (4) /* Bits 4-6: Receive FIFO 1 Data Field Size */
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#define MCAN_RXESC_F1DS_MASK (7 << MCAN_RXESC_F1DS_SHIFT)
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# define MCAN_RXESC_F1DS(n) ((uint32_t)(n) << MCAN_RXESC_F1DS_SHIFT)
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# define MCAN_RXESC_F1DS_8B (0 << MCAN_RXESC_F1DS_SHIFT) /* 8-byte data field */
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# define MCAN_RXESC_F1DS_12B (1 << MCAN_RXESC_F1DS_SHIFT) /* 12-byte data field */
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# define MCAN_RXESC_F1DS_16B (2 << MCAN_RXESC_F1DS_SHIFT) /* 16-byte data field */
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@ -555,6 +559,7 @@
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# define MCAN_RXESC_F1DS_64B (7 << MCAN_RXESC_F1DS_SHIFT) /* 64-byte data field */
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#define MCAN_RXESC_RBDS_SHIFT (8) /* Bits 8-10: Receive Buffer Data Field Size */
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#define MCAN_RXESC_RBDS_MASK (7 << MCAN_RXESC_RBDS_SHIFT)
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# define MCAN_RXESC_RBDS(n) ((uint32_t)(n) << MCAN_RXESC_RBDS_SHIFT)
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# define MCAN_RXESC_RBDS_8B (0 << MCAN_RXESC_RBDS_SHIFT) /* 8-byte data field */
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# define MCAN_RXESC_RBDS_12B (1 << MCAN_RXESC_RBDS_SHIFT) /* 12-byte data field */
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# define MCAN_RXESC_RBDS_16B (2 << MCAN_RXESC_RBDS_SHIFT) /* 16-byte data field */
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@ -594,6 +599,7 @@
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#define MCAN_TXESC_TBDS_SHIFT (0) /* Bits 0-2: Tx Buffer Data Field Size */
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#define MCAN_TXESC_TBDS_MASK (7 << MCAN_TXESC_TBDS_SHIFT)
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# define MCAN_TXESC_TBDS(n) ((uint32_t)(n) << MCAN_TXESC_TBDS_SHIFT)
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# define MCAN_TXESC_TBDS_8B (0 << MCAN_TXESC_TBDS_SHIFT) /* 8-byte data field */
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# define MCAN_TXESC_TBDS_12B (1 << MCAN_TXESC_TBDS_SHIFT) /* 12-byte data field */
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# define MCAN_TXESC_TBDS_16B (2 << MCAN_TXESC_TBDS_SHIFT) /* 16-byte data field */
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@ -661,6 +667,137 @@
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#define MCAN_TXEFA_MASK 0x0000001f /* Event fifo acknowledge index mask */
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/* Message RAM Definitions **************************************************************/
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/* Common Buffer and FIFO element bit definitions:
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*
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* --------------- ------------------- --------------------------------
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* RESOURCE R0 R1
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* --------------- ------------------- --------------------------------
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* RX Buffer: ESI, XTD, RTR, ID, ANMF, FIDX, EDL, BRS, DLC, RXTS
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* RX FIFO: ESI, XTD, RTR, ID, ANMF, FIDX, EDL, BRS, DLC, RXTS
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* TX buffer: XTD, RTR, ID, MM, EFC, DLC
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* TX Event FIFO: ESI, XTD, RTR, ID, MM, ET, EDL, BRS, DLC, TXTS
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* --------------- ------------------- --------------------------------
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*/
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/* Common */
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#define BUFFER_R0_EXTID_SHIFT (0) /* Bits 0-28: Extended identifer */
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#define BUFFER_R0_EXTID_MASK (0x1fffffff << BUFFER_R0_EXTID_SHIFT)
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# define BUFFER_R0_EXTID(n) ((uint32_t)(n) << BUFFER_R0_EXTID_SHIFT)
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#define BUFFER_R0_STDID_SHIFT (18) /* Bits 18-28: Standard idendifier */
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#define BUFFER_R0_STDID_MASK (0x1ffc << BUFFER_R0_STDID_SHIFT)
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# define BUFFER_R0_STDID_(n) ((uint32_t)(n) << BUFFER_R0_STDID_SHIFT)
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#define BUFFER_R0_RTR (1 << 29) /* Bit 29: Remote Transmission Request */
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#define BUFFER_R0_XTD (1 << 30) /* Bit 30: Extended Identifier */
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#define BUFFER_R0_ESI (1 << 31) /* Bit 31: Error State Indicator */
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/* Common */
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#define BUFFER_R1_DLC_SHIFT (16) /* Bits 16-19: Date length code */
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#define BUFFER_R1_DLC_MASK (15 << BUFFER_R1_DLC_SHIFT)
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# define BUFFER_R1_DLC(n) ((uint32_t)(n) << BUFFER_R1_DLC_SHIFT)
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#define BUFFER_R1_BRS (1 << 20) /* Bit 20: Bit Rate Switch */
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#define BUFFER_R1_EDL (1 << 21) /* Bit 21: Extended Data Length */
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/* RX buffer/RX FIFOs */
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#define BUFFER_R1_RXTS_SHIFT (0) /* Bits 0-15: RX Timestamp */
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#define BUFFER_R1_RXTS_MASK (0xffff << BUFFER_R1_RXTS_SHIFT)
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# define BUFFER_R1_RXTS(n) ((uint32_t)(n) << BUFFER_R1_RXTS_SHIFT)
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#define BUFFER_R1_FIDX_SHIFT (24) /* Bits 24-30: Filter index */
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#define BUFFER_R1_FIDX_MASK (0x7f << BUFFER_R1_FIDX_SHIFT)
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# define BUFFER_R1_FIDX(n) ((uint32_t)(n) << BUFFER_R1_FIDX_SHIFT)
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#define BUFFER_R1_ANMF (1 << 31) /* Bit 31: Accepted Non-matching Frame */
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/* TX buffer/TX Event FIFO */
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#define BUFFER_R1_MM_SHIFT (24) /* Bits 24-31: Message Marker */
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#define BUFFER_R1_MM_MASK (0xffff << BUFFER_R1_MM_SHIFT)
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# define BUFFER_R1_MM(n) ((uint32_t)(n) << BUFFER_R1_MM_SHIFT)
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/* TX buffer */
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#define BUFFER_R1_EFC (1 << 23) /* Bit 23: Event FIFO Control */
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/* TX Event FIFO */
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#define BUFFER_R1_TXTS_SHIFT (0) /* Bits 0-15: TX Timestamp */
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#define BUFFER_R1_TXTS_MASK (0xffff << BUFFER_R1_TXTS_SHIFT)
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# define BUFFER_R1_TXTS(n) ((uint32_t)(n) << BUFFER_R1_TXTS_SHIFT)
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#define BUFFER_R1_ET_SHIFT (22) /* Bits 22-23: Event Type */
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#define BUFFER_R1_ET_MASK (15 << BUFFER_R1_ET_SHIFT)
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# define BUFFER_R1_ET_TXEVENT (1 << BUFFER_R1_ET_SHIFT) /* Tx event */
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# define BUFFER_R1_ET_TXCANCEL (2 << BUFFER_R1_ET_SHIFT) /* Transmission despite cancellation */
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/* Standard Message ID Filter Element */
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#define STDFILTER_S0_SFID2_SHIFT (0) /* Bits 0-10: Standard Filter ID 2 */
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#define STDFILTER_S0_SFID2_MASK (0x3ff << STDFILTER_S0_SFID2_SHIFT)
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# define STDFILTER_S0_SFID2(n) ((uint32_t)(n) << STDFILTER_S0_SFID2_SHIFT)
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#define STDFILTER_S0_BUFFER_SHIFT (0) /* Bits 0-5: RX buffer start address */
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#define STDFILTER_S0_BUFFER_MASK (0x3f << STDFILTER_S0_BUFFER_SHIFT)
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# define STDFILTER_S0_BUFFER(n) ((uint32_t)(n) << STDFILTER_S0_BUFFER_SHIFT)
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#define STDFILTER_S0_ACTION_SHIFT (9) /* Bits 9-10: Action taken */
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#define STDFILTER_S0_ACTION_MASK (3 << STDFILTER_S0_ACTION_SHIFT)
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# define STDFILTER_S0_RXBUFFER (0 << STDFILTER_S0_ACTION_SHIFT) /* Store message in a Rx buffer */
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# define STDFILTER_S0_DEBUGA (1 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message A */
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# define STDFILTER_S0_DEBUGB (2 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message B */
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# define STDFILTER_S0_DEBUGC (3 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message C */
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#define STDFILTER_S0_SFID1_SHIFT (16) /* Bits 16-26: Standard Filter ID 2 */
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#define STDFILTER_S0_SFID1_MASK (0x3ff << STDFILTER_S0_SFID1_SHIFT)
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# define STDFILTER_S0_SFID1(n) ((uint32_t)(n) << STDFILTER_S0_SFID1_SHIFT)
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#define STDFILTER_S0_SFEC_SHIFT (17) /* Bits 27-29: Standard Filter Element Configuration */
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#define STDFILTER_S0_SFEC_MASK (7 << STDFILTER_S0_SFEC_SHIFT)
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# define STDFILTER_S0_SFEC_DISABLE (0 << STDFILTER_S0_SFEC_SHIFT) /* Disable filter element */
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# define STDFILTER_S0_SFEC_FIFO0 (1 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 0 on match */
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# define STDFILTER_S0_SFEC_FIFO1 (2 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 1 on match */
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# define STDFILTER_S0_SFEC_REJECT (3 << STDFILTER_S0_SFEC_SHIFT) /* Reject ID on match */
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# define STDFILTER_S0_SFEC_PRIORITY (4 << STDFILTER_S0_SFEC_SHIFT) /* Set priority ion match */
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# define STDFILTER_S0_SFEC_PRIOFIFO0 (5 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 0 on match */
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# define STDFILTER_S0_SFEC_PRIOFIFO1 (6 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 1 on match */
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# define STDFILTER_S0_SFEC_BUFFER (7 << STDFILTER_S0_SFEC_SHIFT) /* Store into Rx Buffer or as debug message */
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#define STDFILTER_S0_SFT_SHIFT (30) /* Bits 30-31: Standard Filter Type */
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#define STDFILTER_S0_SFT_MASK (3 << STDFILTER_S0_SFT_SHIFT)
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# define STDFILTER_S0_SFT_RANGE (0 << STDFILTER_S0_SFT_SHIFT) /* Range filter from SF1ID to SF2ID */
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# define STDFILTER_S0_SFT_DUAL (1 << STDFILTER_S0_SFT_SHIFT) /* Dual ID filter for SF1ID or SF2ID */
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# define STDFILTER_S0_SFT_CLASSIC (2 << STDFILTER_S0_SFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */
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/* Extended Message ID Filter Element */
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#define EXTFILTER_F0_EFID1_SHIFT (0) /* Bits 0-28: Extended Filter ID 1 */
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#define EXTFILTER_F0_EFID1_MASK (0x1fffffff << EXTFILTER_F0_EFID1_SHIFT)
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# define EXTFILTER_F0_EFID1(n) ((uint32_t)(n) << EXTFILTER_F0_EFID1_SHIFT)
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#define EXTFILTER_F0_EFEC_SHIFT (29) /* Bits 29-31: Extended Filter Element Configuration */
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#define EXTFILTER_F0_EFEC_MASK (7 << EXTFILTER_F0_EFEC_SHIFT)
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# define EXTFILTER_F0_EFEC_DISABLE (0 << EXTFILTER_F0_EFEC_SHIFT) /* Disable filter element */
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# define EXTFILTER_F0_EFEC_FIFO0 (1 << EXTFILTER_F0_EFEC_SHIFT) /* Store in Rx FIFO 0 on match */
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# define EXTFILTER_F0_EFEC_FIFO1 (2 << EXTFILTER_F0_EFEC_SHIFT) /* Store in Rx FIFO 1 on match */
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# define EXTFILTER_F0_EFEC_REJECT (3 << EXTFILTER_F0_EFEC_SHIFT) /* Reject ID on match */
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# define EXTFILTER_F0_EFEC_PRIORITY (4 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority on match */
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# define EXTFILTER_F0_EFEC_PRIOFIFO0 (5 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority and store in FIFO 0 on match */
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# define EXTFILTER_F0_EFEC_PRIOFIFO1 (6 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority and store in FIFO 1 on match */
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# define EXTFILTER_F0_EFEC_BUFFER (7 << EXTFILTER_F0_EFEC_SHIFT) /* Store into Rx Buffer or as debug message */
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#define EXTFILTER_F1_EFID2_SHIFT (0) /* Bits 0-28: Extended Filter ID 2 */
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#define EXTFILTER_F1_EFID2_MASK (0x1fffffff << EXTFILTER_F1_EFID2_SHIFT)
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# define EXTFILTER_F1_EFID2(n) ((uint32_t)(n) << EXTFILTER_F1_EFID2_SHIFT)
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#define EXTFILTER_F1_BUFFER_SHIFT (0) /* Bits 0-5: RX buffer start address */
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#define EXTFILTER_F1_BUFFER_MASK (0x3f << EXTFILTER_F1_BUFFER_SHIFT)
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# define EXTFILTER_F1_BUFFER(n) ((uint32_t)(n) << EXTFILTER_F1_BUFFER_SHIFT)
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#define EXTFILTER_F1_ACTION_SHIFT (9) /* Bits 9-10: Action taken */
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#define EXTFILTER_F1_ACTION_MASK (3 << EXTFILTER_F1_ACTION_SHIFT)
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# define EXTFILTER_F1_RXBUFFER (0 << EXTFILTER_F1_ACTION_SHIFT) /* Store message in a Rx buffer */
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# define EXTFILTER_F1_DEBUGA (1 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message A */
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# define EXTFILTER_F1_DEBUGB (2 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message B */
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# define EXTFILTER_F1_DEBUGC (3 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message C */
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#define EXTFILTER_F1_EFT_SHIFT (30) /* Bits 30-31: Extended Filter Type */
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#define EXTFILTER_F1_EFT_MASK (3 << EXTFILTER_F1_EFT_SHIFT)
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# define EXTFILTER_F1_EFT_RANGE (0 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from SF1ID to SF2ID */
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# define EXTFILTER_F1_EFT_DUAL (1 << EXTFILTER_F1_EFT_SHIFT) /* Dual ID filter for SF1ID or SF2ID */
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# define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */
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# define EXTFILTER_F1_EFT_NOXIDAM (2 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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@ -570,7 +570,9 @@
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#endif /* CONFIG_SAMV7_MCAN1 */
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/* Interrupts ***************************************************************/
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/* MCAN helpers *************************************************************/
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#define MAILBOX_ADDRESS(a) ((uint32_t)(a) & 0x0000fffc)
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/* Debug ********************************************************************/
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/* Non-standard debug that may be enabled just for testing CAN */
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@ -1247,7 +1249,7 @@ static void mcan_mbfree(FAR struct sam_mcan_s *priv, int mbndx)
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*
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* Assumptions:
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* Caller has exclusive access to the CAN data structures
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* CAN interrupts are disabled at the AIC
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* CAN interrupts are disabled at the NVIC
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*
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****************************************************************************/
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@ -1442,7 +1444,8 @@ static int mcan_setup(FAR struct can_dev_s *dev)
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mcan_dumpctrlregs(priv, "After receive setup");
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mcan_dumpmbregs(priv, NULL);
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/* Enable the interrupts at the AIC. */
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/* Enable the interrupts at the NVIC (they are still disabled at the MCAN
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* peripheral). */
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up_enable_irq(config->irq);
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mcan_semgive(priv);
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@ -2319,8 +2322,10 @@ static int mcan_bittiming(struct sam_mcan_s *priv)
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static int mcan_hwinitialize(struct sam_mcan_s *priv)
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{
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FAR const struct sam_config_s *config = priv->config;
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FAR uint32_t *msgram;
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uint32_t regval;
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uint32_t mck;
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uint32_t cntr;
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uint32_t cmr;
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int ret;
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canllvdbg("CAN%d\n", config->port);
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@ -2370,45 +2375,167 @@ static int mcan_hwinitialize(struct sam_mcan_s *priv)
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sam_enableperiph1(config->pid);
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#if 0 // REVISIT -- may apply only to SAMA5
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/* Disable all CAN interrupts */
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/* Enable the Initialization state */
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mcan_putreg(priv, SAM_CAN_IDR_OFFSET, CAN_INT_ALL);
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regval = sam_getreg(priv, SAM_MCAN_CCCR_OFFSET)
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regval |= MCAN_CCCR_INIT;
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sam_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval);
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/* Configure bit timing. */
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/* Wait for initialization mode to take effect */
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ret = mcan_bittiming(priv);
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if (ret < 0)
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while ((sam_getreg(priv, SAM_MCAN_CCCR_OFFSET) & MCAN_CCCR_INIT) == 0);
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/* Enable writing to configuration registers */
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regval = sam_getreg(priv, SAM_MCAN_CCCR_OFFSET)
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regval |= MCAN_CCCR_INIT | MCAN_CCCR_CCE;
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sam_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval);
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/* Global Filter Configuration: Reject remote frames, reject non-matching
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* frames.
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*/
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regval = MCAN_GFC_RRFE | MCAN_GFC_RRFS | MCAN_GFC_ANFE_REJECTED |
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MCAN_GFC_ANFS_REJECTED;
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sam_putreg(priv, SAM_MCAN_GFC_OFFSET, regval);
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/* Extended ID Filter AND mask */
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sam_putreg(priv, SAM_MCAN_XIDAM_OFFSET, 0x1fffffff);
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/* Disable all interrupts */
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sam_putreg(priv, SAM_MCAN_IE_OFFSET, 0);
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sam_putreg(priv, SAM_MCAN_TXBTIE_OFFSET, 0);
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/* All interrupts directed to Line 0. But disable bot interrupt line 0
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* and 1 for now.
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*/
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sam_putreg(priv, SAM_MCAN_ILS_OFFSET, 0);
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sam_putreg(priv, SAM_MCAN_ILE_OFFSET, 0);
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/* Clear all pending interrupts. */
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sam_putreg(priv, SAM_MCAN_IR_OFFSET, MCAN_INT_ALL);
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/* Configure MCAN bit timing */
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sam_putreg(priv, SAM_MCAN_BTP_OFFSET, config->btp);
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sam_putreg(priv, SAM_MCAN_FBTP_OFFSET, config->fbtp);
|
||||
|
||||
/* Configure message RAM starting addresses and sizes. */
|
||||
|
||||
regval = MAILBOX_ADDRESS(config->msgram.stdfilters) |
|
||||
MCAN_SIDFC_LSS(config->nstdfilters);
|
||||
sam_putreg(priv, SAM_MCAN_SIDFC_OFFSET, regval);
|
||||
|
||||
regval = MAILBOX_ADDRESS(config->msgram.extfilters) |
|
||||
MCAN_XIDFC_LSE(config->nextfilters);
|
||||
sam_putreg(priv, SAM_MCAN_XIDFC_OFFSET, regval);
|
||||
|
||||
/* Configure RX FIFOs */
|
||||
|
||||
regval = MAILBOX_ADDRESS(config->msgram.rxfifo0) |
|
||||
MCAN_RXF0C_F0S(config->nfifo0);
|
||||
sam_putreg(priv, SAM_MCAN_RXF0C_OFFSET, regval);
|
||||
|
||||
regval = MAILBOX_ADDRESS(config->msgram.rxfifo1) |
|
||||
MCAN_RXF1C_F1S(config->nfifo1);
|
||||
sam_putreg(priv, SAM_MCAN_RXF1C_OFFSET, regval);
|
||||
|
||||
/* Watermark interrupt off, blocking mode */
|
||||
|
||||
regval = MAILBOX_ADDRESS(config->msgram.rxdedicated);
|
||||
sam_putreg(priv, SAM_MCAN_RXBC_OFFSET, regval);
|
||||
|
||||
regval = MAILBOX_ADDRESS(config->msgram.txeventfifo) |
|
||||
MCAN_TXEFC_EFS(config->ntxeventfifo);
|
||||
sam_putreg(priv, SAM_MCAN_TXEFC_OFFSET, regval);
|
||||
|
||||
/* Watermark interrupt off */
|
||||
|
||||
regval = MAILBOX_ADDRESS(config->msgram.txdedicated) |
|
||||
MCAN_TXBC_NDTB(config->ntxdedicated) |
|
||||
MCAN_TXBC_TFQS(config->ntxfifoq);
|
||||
sam_putreg(priv, SAM_MCAN_TXBC_OFFSET, regval);
|
||||
|
||||
regval = MCAN_RXESC_RBDS(config->rxbufferecode) |
|
||||
MCAN_RXESC_F1DS(config->rxfifo1ecode) |
|
||||
MCAN_RXESC_F0DS(config->rxfifo0ecode)
|
||||
sam_putreg(priv, SAM_MCAN_RXESC_OFFSET, regval);
|
||||
|
||||
regval = MCAN_TXESC_TBDS(config->txbufferesize);
|
||||
sam_putreg(priv, SAM_MCAN_TXESC_OFFSET, regval);
|
||||
|
||||
/* Configure Message Filters */
|
||||
/* Disable all standard filters */
|
||||
|
||||
msgram = config->msgram.stdfilters;
|
||||
cntr = config->nstdfilters;
|
||||
while (cntr > 0)
|
||||
{
|
||||
candbg("ERROR: Failed to set bit timing: %d\n", ret);
|
||||
return ret;
|
||||
*msgram++ = STDFILTER_S0_SFEC_DISABLE;
|
||||
cntr--;
|
||||
}
|
||||
#endif
|
||||
# error Missing SAMV71 MCAN initialization logic
|
||||
|
||||
/* Select FD mode with or without fast bit rate switching */
|
||||
/* Disable all extended filters */
|
||||
|
||||
msgram = config->msgram.extfilters;
|
||||
cntr = config->nextfilters;
|
||||
while (cntr > 0)
|
||||
{
|
||||
*msgram = EXTFILTER_F0_EFEC_DISABLE;
|
||||
msgram = msgram + 2;
|
||||
cntr--;
|
||||
}
|
||||
|
||||
/* Clear new RX data flags */
|
||||
|
||||
sam_putreg(priv, SAM_MCAN_NDAT1_OFFSET, 0xffffffff);
|
||||
sam_putreg(priv, SAM_MCAN_NDAT2_OFFSET, 0xffffffff);
|
||||
|
||||
/* Select ISO11898-1 mode or FD mode with or without fast bit rate
|
||||
* switching
|
||||
*/
|
||||
|
||||
regval = sam_getreg(priv, SAM_MCAN_CCCR_OFFSET);
|
||||
regval &= ~MCAN_CCCR_CME_MASK;
|
||||
regval &= ~(MCAN_CCCR_CME_MASK | MCAN_CCCR_CMR_MASK);
|
||||
|
||||
switch (priv->mode)
|
||||
{
|
||||
default:
|
||||
case CONFIG_MCAN_ISO11898_1_MODE:
|
||||
regval |= MCAN_CCCR_CME_ISO11898_1;
|
||||
cmr = MCAN_CCCR_CMR_ISO11898_1;
|
||||
break;
|
||||
|
||||
case CONFIG_MCAN_FD_MODE:
|
||||
regval |= MCAN_CCCR_CME_FD;
|
||||
cmr = MCAN_CCCR_CMR_FD;
|
||||
break;
|
||||
|
||||
case CONFIG_MCAN_FD_BSW_MODE:
|
||||
regval |= MCAN_CCCR_CME_FD_BSW;
|
||||
cmr = MCAN_CCCR_CMR_FD_BSW;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Set the initial CAN mode */
|
||||
|
||||
sam_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval);
|
||||
|
||||
/* Request the mode change */
|
||||
|
||||
regval |= cmr;
|
||||
sam_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval);
|
||||
|
||||
#if 0 /* Not necessary in initialization mode */
|
||||
/* Wait for the mode to take effect */
|
||||
|
||||
while ((sam_getreg(priv, SAM_MCAN_CCCR_OFFSET) & (MCAN_CCCR_FDBS | MCAN_CCCR_FDO)) != 0);
|
||||
#endif
|
||||
|
||||
/* Enable FIFO/Queue mode */
|
||||
|
||||
regval = sam_getreg(priv, SAM_MCAN_TXBC_OFFSET);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user