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TMS570: A little more selftest logic

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This commit is contained in:
Gregory Nutt 2015-12-26 12:05:32 -06:00
parent a27cd8e54e
commit d592b2824e
4 changed files with 68 additions and 10 deletions
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14
arch/arm/src/tms570/tms570_boot.c
View File

@ -268,15 +268,23 @@ void arm_boot(void)
);
/* Test the CPU ECC mechanism for RAM accesses. */
#warning Missing logic
tms570_cpuecc_selftest();
/* Wait for the memory test to complete */
ASSERT(tms570_memtest_complete() == OK);
#endif /* CONFIG_TMS570_SELFTEST */
/* Release the MibSPI1 modules from local reset. */
#warning Missing logic
#ifdef CONFIG_TMS570_MIBASPI1
/* Release the MibSPI1 modules from local reset.
*
* This will cause the MibSPI1 RAMs to be initialized along with the
* parity memory.
*/
putreg32(MIBSPI_GCR0_RESET, TMS570_MIBSPI_GCR0);
#endif
/* Initialize all on-chip SRAMs except for MibSPIx RAMs.
*

14
arch/arm/src/tms570/tms570_irq.c
View File

@ -207,10 +207,11 @@ uint32_t *arm_decodeirq(uint32_t *regs)
{
int vector;
/* Check for a VRAM parity error. This is not to critical in this
* implementation since VIM RAM is not used.
/* Check for a VRAM parity error.
*
* REVISIT: This is not to critical in this implementation since VIM RAM
* is not used.
*/
#warning Missing logic
/* Get the interrupting vector number from the IRQINDEX register. Zero,
* the "phantom" vector will returned.
@ -249,10 +250,11 @@ uint32_t *arm_decodefiq(FAR uint32_t *regs)
{
int vector;
/* Check for a VRAM parity error. This is not to critical in this
* implementation since VIM RAM is not used.
/* Check for a VRAM parity error.
*
* REVISIT: This is not to critical in this implementation since VIM RAM
* is not used.
*/
#warning Missing logic
/* Get the interrupting vector number from the FIQINDEX register. Zero,
* the "phantom" vector will returned.

29
arch/arm/src/tms570/tms570_selftest.c
View File

@ -321,7 +321,34 @@ void tms570_efc_selftest_start(void)
int tms570_efc_selftest_complete(void)
{
#warning Missing Logic
return 0;
return OK;
}
/****************************************************************************
* Name: tms570_cpuecc_selftest
*
* Description:
* Test the CPU ECC mechanism for RAM accesses.
*
* Cause single-bit and double-bit errors in TCRAM accesses by corrupting
* 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit
* error in the ECC causes a data abort exception. The data abort handler
* must include logic written to look for deliberately caused exception and
* to return the code execution to the instruction following the one that
* caused the abort.
*
* Returned Value:
* Zero (OK) if the test passed; A negated errno value is returned on
* any failure.
*
****************************************************************************/
#if 0 /* Needs change to data abort handler */
int tms570_cpuecc_selftest(void)
{
#warning Missing Logic
return OK;
}
#endif
#endif /* CONFIG_TMS570_SELFTEST */

21
arch/arm/src/tms570/tms570_selftest.h
View File

@ -138,6 +138,27 @@ void tms570_efc_selftest_start(void);
int tms570_efc_selftest_complete(void);
/****************************************************************************
* Name: tms570_cpuecc_selftest
*
* Description:
* Test the CPU ECC mechanism for RAM accesses.
*
* Cause single-bit and double-bit errors in TCRAM accesses by corrupting
* 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit
* error in the ECC causes a data abort exception. The data abort handler
* must include logic written to look for deliberately caused exception and
* to return the code execution to the instruction following the one that
* caused the abort.
*
* Returned Value:
* Zero (OK) if the test passed; A negated errno value is returned on
* any failure.
*
****************************************************************************/
#define tms570_cpuecc_selftest()
#undef EXTERN
#if defined(__cplusplus)
}