From d592b2824ecdc47737edb624546446707547f50e Mon Sep 17 00:00:00 2001
From: Gregory Nutt <gnutt@nuttx.org>
Date: Sat, 26 Dec 2015 12:05:32 -0600
Subject: [PATCH] TMS570: A little more selftest logic

---
 arch/arm/src/tms570/tms570_boot.c     | 14 ++++++++++---
 arch/arm/src/tms570/tms570_irq.c      | 14 +++++++------
 arch/arm/src/tms570/tms570_selftest.c | 29 ++++++++++++++++++++++++++-
 arch/arm/src/tms570/tms570_selftest.h | 21 +++++++++++++++++++
 4 files changed, 68 insertions(+), 10 deletions(-)

diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c
index fb893b8eec..46008432f8 100644
--- a/arch/arm/src/tms570/tms570_boot.c
+++ b/arch/arm/src/tms570/tms570_boot.c
@@ -268,15 +268,23 @@ void arm_boot(void)
                       );
 
   /* Test the CPU ECC mechanism for RAM accesses. */
-#warning Missing logic
+
+  tms570_cpuecc_selftest();
 
   /* Wait for the memory test to complete */
 
   ASSERT(tms570_memtest_complete() == OK);
 #endif /* CONFIG_TMS570_SELFTEST */
 
-  /* Release the MibSPI1 modules from local reset. */
-#warning Missing logic
+#ifdef CONFIG_TMS570_MIBASPI1
+  /* Release the MibSPI1 modules from local reset.
+   *
+   * This will cause the MibSPI1 RAMs to be initialized along with the
+   * parity memory.
+   */
+
+  putreg32(MIBSPI_GCR0_RESET, TMS570_MIBSPI_GCR0);
+#endif
 
   /* Initialize all on-chip SRAMs except for MibSPIx RAMs.
    *
diff --git a/arch/arm/src/tms570/tms570_irq.c b/arch/arm/src/tms570/tms570_irq.c
index dad8c10fd0..4ef3f0d231 100644
--- a/arch/arm/src/tms570/tms570_irq.c
+++ b/arch/arm/src/tms570/tms570_irq.c
@@ -207,10 +207,11 @@ uint32_t *arm_decodeirq(uint32_t *regs)
 {
   int vector;
 
-  /* Check for a VRAM parity error.  This is not to critical in this
-   * implementation since VIM RAM is not used.
+  /* Check for a VRAM parity error.
+   *
+   * REVISIT: This is not to critical in this implementation since VIM RAM
+   * is not used.
    */
-#warning Missing logic
 
   /* Get the interrupting vector number from the IRQINDEX register.  Zero,
    * the "phantom" vector will returned.
@@ -249,10 +250,11 @@ uint32_t *arm_decodefiq(FAR uint32_t *regs)
 {
   int vector;
 
-  /* Check for a VRAM parity error.  This is not to critical in this
-   * implementation since VIM RAM is not used.
+  /* Check for a VRAM parity error.
+   *
+   * REVISIT: This is not to critical in this implementation since VIM RAM
+   * is not used.
    */
-#warning Missing logic
 
   /* Get the interrupting vector number from the FIQINDEX register.  Zero,
    * the "phantom" vector will returned.
diff --git a/arch/arm/src/tms570/tms570_selftest.c b/arch/arm/src/tms570/tms570_selftest.c
index 2739ffd3dc..3abb8d7122 100644
--- a/arch/arm/src/tms570/tms570_selftest.c
+++ b/arch/arm/src/tms570/tms570_selftest.c
@@ -321,7 +321,34 @@ void tms570_efc_selftest_start(void)
 int tms570_efc_selftest_complete(void)
 {
 #warning Missing Logic
-  return 0;
+  return OK;
 }
 
+/****************************************************************************
+ * Name: tms570_cpuecc_selftest
+ *
+ * Description:
+ *   Test the CPU ECC mechanism for RAM accesses.
+ *
+ *   Cause single-bit and double-bit errors in TCRAM accesses by corrupting
+ *   1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit
+ *   error in the ECC causes a data abort exception. The data abort handler
+ *   must include logic written to look for deliberately caused exception and
+ *   to return the code execution to the instruction following the one that
+ *   caused the abort.
+ *
+ * Returned Value:
+ *   Zero (OK) if the test passed; A negated errno value is returned on
+ *   any failure.
+ *
+ ****************************************************************************/
+
+#if 0 /* Needs change to data abort handler */
+int tms570_cpuecc_selftest(void)
+{
+#warning Missing Logic
+  return OK;
+}
+#endif
+
 #endif /* CONFIG_TMS570_SELFTEST */
diff --git a/arch/arm/src/tms570/tms570_selftest.h b/arch/arm/src/tms570/tms570_selftest.h
index bfc2bd4130..696bc54fe3 100644
--- a/arch/arm/src/tms570/tms570_selftest.h
+++ b/arch/arm/src/tms570/tms570_selftest.h
@@ -138,6 +138,27 @@ void tms570_efc_selftest_start(void);
 
 int tms570_efc_selftest_complete(void);
 
+/****************************************************************************
+ * Name: tms570_cpuecc_selftest
+ *
+ * Description:
+ *   Test the CPU ECC mechanism for RAM accesses.
+ *
+ *   Cause single-bit and double-bit errors in TCRAM accesses by corrupting
+ *   1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit
+ *   error in the ECC causes a data abort exception. The data abort handler
+ *   must include logic written to look for deliberately caused exception and
+ *   to return the code execution to the instruction following the one that
+ *   caused the abort.
+ *
+ * Returned Value:
+ *   Zero (OK) if the test passed; A negated errno value is returned on
+ *   any failure.
+ *
+ ****************************************************************************/
+
+#define tms570_cpuecc_selftest()
+
 #undef EXTERN
 #if defined(__cplusplus)
 }