arch/arm: fix leaving from critical section

Signed-off-by: chao.an <anchao@xiaomi.com>

arch/arm/src/a1x/a1x_pio.c

@@ -246,6 +246,7 @@ int a1x_pio_config(pio_pinset_t cfgset)
         break;
 
       default:
+        leave_critical_section(flags);
         return -EINVAL;
     }
 
@@ -286,6 +287,7 @@ int a1x_pio_config(pio_pinset_t cfgset)
         break;
 
       default:
+        leave_critical_section(flags);
         return -EINVAL;
     }
 

arch/arm/src/imxrt/imxrt_lpspi.c

@@ -1695,7 +1695,6 @@ FAR struct spi_dev_s *imxrt_lpspibus_initialize(int bus)
 #endif
     {
       spierr("ERROR: Unsupported SPI bus: %d\n", bus);
-      return NULL;
     }
 
   leave_critical_section(flags);

arch/arm/src/kinetis/kinetis_pwm.c

@@ -712,6 +712,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
 
       default:
         pwmerr("ERROR: No such channel: %d\n", priv->channel);
+        leave_critical_section(flags);
         return -EINVAL;
     }
 

arch/arm/src/kl/kl_pwm.c

@@ -642,6 +642,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
 
       default:
         pwmerr("ERROR: No such channel: %d\n", priv->channel);
+        leave_critical_section(flags);
         return -EINVAL;
     }
 

arch/arm/src/lc823450/lc823450_adc.c

@@ -211,7 +211,6 @@ static void lc823450_adc_start(FAR struct lc823450_adc_inst_s *inst)
   uint32_t pclk;  /* APB clock in Hz */
   uint8_t i;
   uint32_t div;
-  int ret;
 
 #ifdef CONFIG_ADC_POLLED
   irqstate_t flags;
@@ -248,11 +247,7 @@ static void lc823450_adc_start(FAR struct lc823450_adc_inst_s *inst)
   while ((getreg32(ADCSTS) & ADCSTS_ADCMPL) == 0)
     ;
 #else
-  ret = nxsem_wait_uninterruptible(&inst->sem_isr);
-  if (ret < 0)
-    {
-      return;
-    }
+  nxsem_wait_uninterruptible(&inst->sem_isr);
 
 #endif
 

arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c

@@ -610,6 +610,7 @@ struct i2c_master_s *lpc17_40_i2cbus_initialize(int port)
 #endif
     {
       i2cerr("ERROR: LPC I2C Only supports ports 0, 1 and 2\n");
+      leave_critical_section(flags);
       return NULL;
     }
 

arch/arm/src/lpc2378/lpc23xx_i2c.c

@@ -573,6 +573,7 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port)
   else
 #endif
     {
+      leave_critical_section(flags);
       return NULL;
     }
 

arch/arm/src/lpc43xx/lpc43_i2c.c

@@ -521,6 +521,7 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
   else
 #endif
     {
+      leave_critical_section(flags);
       return NULL;
     }
 

arch/arm/src/lpc54xx/lpc54_ethernet.c

@@ -2246,6 +2246,7 @@ static int lpc54_eth_ifdown(struct net_driver_s *dev)
   if (ret < 0)
     {
       nerr("ERROR: lpc54_phy_reset failed: %d\n", ret);
+      leave_critical_section(flags);
       return ret;
     }
 

arch/arm/src/lpc54xx/lpc54_i2c_master.c

@@ -1187,6 +1187,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
 #endif
     {
       i2cerr("ERROR: Unsupported port=%d\n", port);
+      leave_critical_section(flags);
       return NULL;
     }
 

arch/arm/src/lpc54xx/lpc54_spi_master.c

@@ -2006,6 +2006,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
   else
 #endif
     {
+      leave_critical_section(flags);
       return NULL;
     }
 

arch/arm/src/max326xx/max32660/max32660_spim.c

@@ -1516,7 +1516,6 @@ struct spi_dev_s *max326_spibus_initialize(int bus)
 #endif
     {
       spierr("ERROR: Unsupported SPI bus: %d\n", bus);
-      return NULL;
     }
 
   leave_critical_section(flags);

arch/arm/src/s32k1xx/s32k1xx_lpspi.c

@@ -2345,7 +2345,6 @@ FAR struct spi_dev_s *s32k1xx_lpspibus_initialize(int bus)
 #endif
     {
       spierr("ERROR: Unsupported SPI bus: %d\n", bus);
-      return NULL;
     }
 
   leave_critical_section(flags);

arch/arm/src/s32k1xx/s32k1xx_pwm.c

@@ -698,6 +698,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
 
       default:
         pwmerr("ERROR: No such channel: %d\n", priv->channel);
+        leave_critical_section(flags);
         return -EINVAL;
     }
 

arch/arm/src/sama5/sam_hsmci.c

@@ -2260,6 +2260,7 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev,
           /* Some fatal error has occurred */
 
           lcderr("ERROR: sr %08" PRIx32 "\n", sr);
+          leave_critical_section(flags);
           return -EIO;
         }
       else if ((sr & HSMCI_INT_TXRDY) != 0)

arch/arm/src/samd2l2/sam_i2c_master.c

@@ -1199,6 +1199,7 @@ static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, uint32_t frequency)
     {
       i2cerr
        ("ERROR: Cannot initialize I2C because it is already initialized!\n");
+      leave_critical_section(flags);
       return;
     }
 
@@ -1208,6 +1209,7 @@ static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, uint32_t frequency)
   if (regval & I2C_CTRLA_SWRST)
     {
       i2cerr("ERROR: Module is in RESET process!\n");
+      leave_critical_section(flags);
       return;
     }
 

arch/arm/src/samd5e5/sam_i2c_master.c

@@ -1210,6 +1210,7 @@ static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, uint32_t frequency)
     {
       i2cerr("ERROR: Cannot initialize I2C "
              "because it is already initialized!\n");
+      leave_critical_section(flags);
       return;
     }
 
@@ -1219,6 +1220,7 @@ static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, uint32_t frequency)
   if (regval & I2C_CTRLA_SWRST)
     {
       i2cerr("ERROR: Module is in RESET process!\n");
+      leave_critical_section(flags);
       return;
     }
 

arch/arm/src/samd5e5/sam_wdt.c

@@ -364,7 +364,10 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
   /* check whether overflow */
 
   if (tmp >> 32)
-  return -ERANGE;
+    {
+      leave_critical_section(flags);
+      return -ERANGE;
+    }
 
   period_cycles = (uint32_t)tmp;
 

arch/arm/src/samv7/sam_hsmci.c

@@ -2248,6 +2248,7 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev,
           /* Some fatal error has occurred */
 
           mcerr("ERROR: sr %08" PRIx32 "\n", sr);
+          leave_critical_section(flags);
           return -EIO;
         }
       else if ((sr & HSMCI_INT_TXRDY) != 0)

arch/arm/src/stm32/stm32_i2s.c

@@ -2625,6 +2625,7 @@ FAR struct i2s_dev_s *stm32_i2sbus_initialize(int port)
 #endif
     {
       i2serr("ERROR: Unsupported I2S port: %d\n", port);
+      leave_critical_section(flags);
       return NULL;
     }
 
@@ -2646,6 +2647,7 @@ FAR struct i2s_dev_s *stm32_i2sbus_initialize(int port)
   /* Failure exits */
 
 errout_with_alloc:
+  leave_critical_section(flags);
   nxsem_destroy(&priv->exclsem);
   kmm_free(priv);
   return NULL;

arch/arm/src/stm32/stm32_qencoder.c

@@ -1133,6 +1133,7 @@ static int stm32_shutdown(FAR struct qe_lowerhalf_s *lower)
         break;
 #endif
       default:
+        leave_critical_section(flags);
         return -EINVAL;
     }
 

arch/arm/src/stm32/stm32_serial.c

@@ -2958,6 +2958,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
 #  ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
       if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
         {
+          leave_critical_section(flags);
           return;
         }
 #  endif

arch/arm/src/stm32/stm32_usbdev.c

@@ -3253,6 +3253,7 @@ static int stm32_epstall(struct usbdev_ep_s *ep, bool resume)
           priv->ep0state = EP0STATE_STALLED;
         }
 
+      leave_critical_section(flags);
       return -ENODEV;
     }
 

arch/arm/src/stm32f0l0g0/stm32_adc.c

@@ -1342,6 +1342,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
 #ifdef HAVE_ADC_CMN_DATA
   if (adccmn_lock(priv, true) < 0)
     {
+      leave_critical_section(flags);
       return;
     }
 

arch/arm/src/stm32f0l0g0/stm32_pwm.c

@@ -2111,6 +2111,7 @@ static int stm32pwm_stop(FAR struct pwm_lowerhalf_s *dev)
 #endif
 
       default:
+        leave_critical_section(flags);
         return -EINVAL;
     }
 

arch/arm/src/stm32f0l0g0/stm32_serial_v1.c

@@ -2216,6 +2216,7 @@ static void stm32serial_txint(FAR struct uart_dev_s *dev, bool enable)
 #  ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
       if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
         {
+          leave_critical_section(flags);
           return;
         }
 #  endif

arch/arm/src/stm32f0l0g0/stm32_serial_v2.c

@@ -1635,6 +1635,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
 #  ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
       if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
         {
+          leave_critical_section(flags);
           return;
         }
 #  endif

arch/arm/src/stm32f0l0g0/stm32_usbdev.c

@@ -3181,6 +3181,7 @@ static int stm32_epstall(struct usbdev_ep_s *ep, bool resume)
           priv->ep0state = EP0STATE_STALLED;
         }
 
+      leave_critical_section(flags);
       return -ENODEV;
     }
 

arch/arm/src/stm32f7/stm32_qencoder.c

@@ -972,6 +972,7 @@ static int stm32_shutdown(FAR struct qe_lowerhalf_s *lower)
         break;
 #endif
       default:
+        leave_critical_section(flags);
         return -EINVAL;
     }
 

arch/arm/src/stm32f7/stm32_serial.c

@@ -3330,6 +3330,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
 #  ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
       if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
         {
+          leave_critical_section(flags);
           return;
         }
 #  endif

arch/arm/src/stm32f7/stm32_spi.c

@@ -2391,7 +2391,6 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus)
 #endif
     {
       spierr("ERROR: Unsupported SPI bus: %d\n", bus);
-      return NULL;
     }
 
   leave_critical_section(flags);

arch/arm/src/stm32h7/stm32_qencoder.c

@@ -973,6 +973,7 @@ static int stm32_shutdown(FAR struct qe_lowerhalf_s *lower)
         break;
 #endif
       default:
+        leave_critical_section(flags);
         return -EINVAL;
     }
 

arch/arm/src/stm32h7/stm32_serial.c

@@ -3525,6 +3525,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
 #  ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
       if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
         {
+          leave_critical_section(flags);
           return;
         }
 #  endif

arch/arm/src/stm32h7/stm32_spi_slave.c

@@ -1810,6 +1810,7 @@ FAR struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus)
 #endif
     {
       spierr("ERROR: Unsupported SPI bus: %d\n", bus);
+      leave_critical_section(flags);
       return NULL;
     }
 

arch/arm/src/stm32l4/stm32l4_qencoder.c

@@ -977,6 +977,7 @@ static int stm32l4_shutdown(FAR struct qe_lowerhalf_s *lower)
         break;
 #endif
       default:
+        leave_critical_section(flags);
         return -EINVAL;
     }
 

arch/arm/src/stm32l4/stm32l4_serial.c

@@ -2808,6 +2808,7 @@ static void stm32l4serial_txint(FAR struct uart_dev_s *dev, bool enable)
 #  ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT
       if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
         {
+          leave_critical_section(flags);
           return;
         }
 #  endif

arch/arm/src/stm32l4/stm32l4_spi.c

@@ -1901,7 +1901,6 @@ FAR struct spi_dev_s *stm32l4_spibus_initialize(int bus)
 #endif
     {
       spierr("ERROR: Unsupported SPI bus: %d\n", bus);
-      return NULL;
     }
 
   leave_critical_section(flags);

arch/arm/src/stm32l4/stm32l4_usbdev.c

@@ -3192,6 +3192,7 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume)
           priv->ep0state = EP0STATE_STALLED;
         }
 
+      leave_critical_section(flags);
       return -ENODEV;
     }
 

arch/arm/src/stm32l5/stm32l5_serial.c

@@ -2741,6 +2741,7 @@ static void stm32l5serial_txint(FAR struct uart_dev_s *dev, bool enable)
 #  ifdef CONFIG_STM32L5_SERIALBRK_BSDCOMPAT
       if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
         {
+          leave_critical_section(flags);
           return;
         }
 #  endif

arch/arm/src/stm32l5/stm32l5_spi.c

@@ -1905,7 +1905,6 @@ FAR struct spi_dev_s *stm32l5_spibus_initialize(int bus)
 #endif
     {
       spierr("ERROR: Unsupported SPI bus: %d\n", bus);
-      return NULL;
     }
 
   leave_critical_section(flags);