diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c
index adda863cca..5e2ba73b1f 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -95,10 +95,10 @@ static inline void rcc_reset(void)
 
   putreg32(0x00000000, STM32_RCC_CFGR);
 
-  /* Reset HSEON, CSSON and PLLON bits */
+  /* Reset HSION, HSEON, CSSON and PLLON bits */
 
   regval  = getreg32(STM32_RCC_CR);
-  regval &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
+  regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
   putreg32(regval, STM32_RCC_CR);
 
   /* Reset PLLCFGR register to reset default */
@@ -619,6 +619,11 @@ static void stm32_stdclockconfig(void)
   volatile int32_t timeout;
 
 #ifdef STM32_BOARD_USEHSI
+  /* Enable Internal High-Speed Clock (HSI) */
+
+  regval  = getreg32(STM32_RCC_CR);
+  regval |= RCC_CR_HSION;           /* Enable HSI */
+  putreg32(regval, STM32_RCC_CR);
 
   /* Wait until the HSI is ready (or until a timeout elapsed) */