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STM32F7: Clone GPIO support from the STM32 F4

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This commit is contained in:
Gregory Nutt 2015-07-18 08:34:07 -06:00
parent 36d01979be
commit d5ebc0ae79
9 changed files with 1323 additions and 62 deletions
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63
arch/arm/include/stm32f7/stm32f74xx75xx_irq.h
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@ -168,68 +168,9 @@
#define NR_INTERRUPTS 98
#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
/* EXTI events */
/* EXTI interrupts (Do not use IRQ numbers) */
#define STM32_EVENT_PIN0 0 /* Port n, pin 0 */
#define STM32_EVENT_PIN1 1 /* Port n, pin 1 */
#define STM32_EVENT_PIN2 2 /* Port n, pin 2 */
#define STM32_EVENT_PIN3 3 /* Port n, pin 3 */
#define STM32_EVENT_PIN4 4 /* Port n, pin 4 */
#define STM32_EVENT_PIN5 5 /* Port n, pin 5 */
#define STM32_EVENT_PIN6 6 /* Port n, pin 6 */
#define STM32_EVENT_PIN7 7 /* Port n, pin 7 */
#define STM32_EVENT_PIN8 8 /* Port n, pin 8 */
#define STM32_EVENT_PIN9 9 /* Port n, pin 9 */
#define STM32_EVENT_PIN10 10 /* Port n, pin 10 */
#define STM32_EVENT_PIN11 11 /* Port n, pin 11 */
#define STM32_EVENT_PIN12 12 /* Port n, pin 12 */
#define STM32_EVENT_PIN13 13 /* Port n, pin 13 */
#define STM32_EVENT_PIN14 14 /* Port n, pin 14 */
#define STM32_EVENT_PIN15 15 /* Port n, pin 15 */
#define STM32_EVENT_PVD 16 /* PVD output */
#define STM32_EVENT_RTCALM 17 /* RTC Alarm event */
#define STM32_EVENT_OTGFSWU 18 /* USB OTG FS Wakeup event */
#define STM32_EVENT_ETHWU 19 /* Ethernet Wakeup event */
#define STM32_EVENT_OTGHSWU 20 /* USB OTG HS (FS mode) Wakeup event */
#define STM32_EVENT_TAMPER 21 /* RTC Tamper and TimeStamp events */
#define STM32_EVENT_TIMESTAP 21 /* RTC Tamper and TimeStamp events */
#define STM32_EVENT_RTCWU 22 /* RTC Wakeup event */
#define STM32_EVENT_LPTIM1 23 /* LPTIM1 asynchronous event */
#define NR_EVENTS 24
/* EXTI interrupts */
#define STM32_IRQ_EXTI NR_VECTORS
#define STM32_IRQ_PIN0 (STM32_IRQ_EXTI+0) /* 98: Port n, pin 0 */
#define STM32_IRQ_PIN1 (STM32_IRQ_EXTI+1) /* 99: Port n, pin 1 */
#define STM32_IRQ_PIN2 (STM32_IRQ_EXTI+2) /* 100: Port n, pin 2 */
#define STM32_IRQ_PIN3 (STM32_IRQ_EXTI+3) /* 101: Port n, pin 3 */
#define STM32_IRQ_PIN4 (STM32_IRQ_EXTI+4) /* 102: Port n, pin 4 */
#define STM32_IRQ_PIN5 (STM32_IRQ_EXTI+5) /* 103: Port n, pin 5 */
#define STM32_IRQ_PIN6 (STM32_IRQ_EXTI+6) /* 104: Port n, pin 6 */
#define STM32_IRQ_PIN7 (STM32_IRQ_EXTI+7) /* 105: Port n, pin 7 */
#define STM32_IRQ_PIN8 (STM32_IRQ_EXTI+8) /* 106: Port n, pin 8 */
#define STM32_IRQ_PIN9 (STM32_IRQ_EXTI+9) /* 107: Port n, pin 9 */
#define STM32_IRQ_PIN10 (STM32_IRQ_EXTI+10) /* 108: Port n, pin 10 */
#define STM32_IRQ_PIN11 (STM32_IRQ_EXTI+11) /* 109: Port n, pin 11 */
#define STM32_IRQ_PIN12 (STM32_IRQ_EXTI+12) /* 110: Port n, pin 12 */
#define STM32_IRQ_PIN13 (STM32_IRQ_EXTI+13) /* 111: Port n, pin 13 */
#define STM32_IRQ_PIN14 (STM32_IRQ_EXTI+14) /* 112: Port n, pin 14 */
#define STM32_IRQ_PIN15 (STM32_IRQ_EXTI+15) /* 113: Port n, pin 15 */
#define STM32_IRQ_PVD (STM32_IRQ_EXTI+16) /* 114: PVD output */
#define STM32_IRQ_RTCALM (STM32_IRQ_EXTI+17) /* 115: RTC Alarm event */
#define STM32_IRQ_OTGFSWU (STM32_IRQ_EXTI+18) /* 116: USB OTG FS Wakeup event */
#define STM32_IRQ_ETHWU (STM32_IRQ_EXTI+19) /* 117: Ethernet Wakeup event */
#define STM32_IRQ_OTGHSWU (STM32_IRQ_EXTI+20) /* 118: USB OTG HS (FS mode) Wakeup event */
#define STM32_IRQ_TAMPER (STM32_IRQ_EXTI+21) /* 119: RTC Tamper and TimeStamp events */
#define STM32_IRQ_TIMESTAP (STM32_IRQ_EXTI+21) /* 119: RTC Tamper and TimeStamp events */
#define STM32_IRQ_RTCWU (STM32_IRQ_EXTI+22) /* 120: RTC Wakeup event */
#define STM32_IRQ_LPTIM1 (STM32_IRQ_EXTI+23) /* 121: LPTIM1 asynchronous event */
#define NR_IRQS (NR_VECTORS+NR_EVENTS)
#define NR_IRQS NR_VECTORS
/****************************************************************************************************
* Public Types

7
arch/arm/src/stm32f7/Make.defs
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@ -107,4 +107,9 @@ endif
# Required STM32F7 files
CHIP_ASRCS =
CHIP_CSRCS = stm32_irq.c stm32_rcc.c stm32_start.c stm32_timerisr.c
CHIP_CSRCS = stm32_exti_gpio.c stm32_gpio.c stm32_irq.c stm32_rcc.c
CHIP_CSRCS += stm32_start.c stm32_timerisr.c
ifeq ($(CONFIG_DEBUG),y)
CHIP_CSRCS += stm32_dumpgpio.c
endif

131
arch/arm/src/stm32f7/chip/stm32_exti.h Normal file
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@ -0,0 +1,131 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32_exti.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_EXTI_H
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_EXTI_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/* Content of this file requires verification before it is used with other
* families
*/
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#define STM32_NEXTI 24
#define STM32_EXTI_MASK 0x00ffffff
#define STM32_EXTI_BIT(n) (1 << (n))
/* Register Offsets *****************************************************************/
#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */
#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */
#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */
#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */
#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */
#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */
/* Register Addresses ***************************************************************/
#define STM32_EXTI_IMR (STM32_EXTI_BASE+STM32_EXTI_IMR_OFFSET)
#define STM32_EXTI_EMR (STM32_EXTI_BASE+STM32_EXTI_EMR_OFFSET)
#define STM32_EXTI_RTSR (STM32_EXTI_BASE+STM32_EXTI_RTSR_OFFSET)
#define STM32_EXTI_FTSR (STM32_EXTI_BASE+STM32_EXTI_FTSR_OFFSET)
#define STM32_EXTI_SWIER (STM32_EXTI_BASE+STM32_EXTI_SWIER_OFFSET)
#define STM32_EXTI_PR (STM32_EXTI_BASE+STM32_EXTI_PR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* EXTI linex < 16 are associated with GPIO pins 0-15.
* EXTI lines > 15 are associated with internal devices:
*/
#define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 = PVD output */
#define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 = RTC Alarm event */
#define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 = USB OTG FS Wakeup event */
#define EXTI_ETH_WAKEUP (1 << 19) /* EXTI line 19 = Ethernet Wakeup event */
#define EXTI_OTGHS_WAKEUP (1 << 20) /* EXTI line 20 = USB OTG HS (FS mode) Wakeup eventt */
#define EXTI_RTC_TAMPER (1 << 21) /* EXTI line 21 = RTC Tamper and TimeStamp events */
#define EXTI_RTC_TIMESTAMP (1 << 21) /* EXTI line 21 = RTC Tamper and TimeStamp events */
#define EXTI_RTC_WAKEUP (1 << 22) /* EXTI line 22 = RTC Wakeup event */
#define EXTI_RTC_WAKEUP (1 << 23) /* EXTI line 23 = LPTIM1 asynchronous event */
/* Interrupt mask register */
#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */
#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
#define EXTI_IMR_MASK STM32_EXTI_MASK
/* Event mask register */
#define EXTI_EMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Event request from line x is not mask */
#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
#define EXTI_EMR_MASK STM32_EXTI_MASK
/* Rising Trigger selection register */
#define EXTI_RTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
#define EXTI_RTSR_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
#define EXTI_RTSR_MASK STM32_EXTI_MASK
/* Falling Trigger selection register */
#define EXTI_FTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
#define EXTI_FTSR_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
#define EXTI_FTSR_MASK STM32_EXTI_MASK
/* Software interrupt event register */
#define EXTI_SWIER_BIT(n) STM32_EXTI_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
#define EXTI_SWIER_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
#define EXTI_SWIER_MASK STM32_EXTI_MASK
/* Pending register */
#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Selected trigger request occurred */
#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
#define EXTI_IMR_MASK STM32_EXTI_MASK
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_EXTI_H */

157
arch/arm/src/stm32f7/stm32_dumpgpio.c Normal file
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@ -0,0 +1,157 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_gpio.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <debug.h>
#include <arch/stm32f7/chip.h>
#include "up_arch.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_rcc.h"
#ifdef CONFIG_DEBUG
/* Content of this file requires verification before it is used with other
* families
*/
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
/****************************************************************************
* Private Data
****************************************************************************/
/* Port letters for prettier debug output */
#ifdef CONFIG_DEBUG
static const char g_portchar[STM32F7_NGPIO] =
{
#if STM32F7_NGPIO > 11
# error "Additional support required for this number of GPIOs"
#elif STM32F7_NGPIO > 10
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K'
#elif STM32F7_NGPIO > 9
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J'
#elif STM32F7_NGPIO > 8
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'
#elif STM32F7_NGPIO > 7
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H'
#elif STM32F7_NGPIO > 6
'A', 'B', 'C', 'D', 'E', 'F', 'G'
#elif STM32F7_NGPIO > 5
'A', 'B', 'C', 'D', 'E', 'F'
#elif STM32F7_NGPIO > 4
'A', 'B', 'C', 'D', 'E'
#elif STM32F7_NGPIO > 3
'A', 'B', 'C', 'D'
#elif STM32F7_NGPIO > 2
'A', 'B', 'C'
#elif STM32F7_NGPIO > 1
'A', 'B'
#elif STM32F7_NGPIO > 0
'A'
#else
# error "Bad number of GPIOs"
#endif
};
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: stm32_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the provided pin configuration
*
****************************************************************************/
int stm32_dumpgpio(uint32_t pinset, const char *msg)
{
irqstate_t flags;
uint32_t base;
unsigned int port;
/* Get the base address associated with the GPIO port */
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
base = g_gpiobase[port];
/* The following requires exclusive access to the GPIO registers */
flags = irqsave();
DEBUGASSERT(port < STM32F7_NGPIO);
lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0)
{
lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + STM32_GPIO_MODER_OFFSET),
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
lldbg(" IDR: %04x ODR: %04x LCKR: %05x\n",
getreg32(base + STM32_GPIO_IDR_OFFSET),
getreg32(base + STM32_GPIO_ODR_OFFSET),
getreg32(base + STM32_GPIO_LCKR_OFFSET));
lldbg(" AFRH: %08x AFRL: %08x\n",
getreg32(base + STM32_GPIO_AFRH_OFFSET),
getreg32(base + STM32_GPIO_AFRL_OFFSET));
}
else
{
lldbg(" GPIO%c not enabled: AHB1ENR: %08x\n",
g_portchar[port], getreg32(STM32_RCC_AHB1ENR));
}
irqrestore(flags);
return OK;
}
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* CONFIG_DEBUG */

119
arch/arm/src/stm32f7/stm32_exti.h Normal file
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@ -0,0 +1,119 @@
/************************************************************************************
* arch/arm/src/stm32f7/stm32_exti.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_EXTI_H
#define __ARCH_ARM_SRC_STM32F7_STM32_EXTI_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include "chip.h"
#include "chip/stm32_exti.h"
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: stm32_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
*
* Parameters:
* - pinset: gpio pin configuration
* - rising/falling edge: enables
* - event: generate event when set
* - func: when non-NULL, generate interrupt
*
* Returns:
* The previous value of the interrupt handler function pointer. This value may,
* for example, be used to restore the previous handler when multiple handlers are
* used.
*
************************************************************************************/
xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func);
/************************************************************************************
* Name: stm32_exti_alarm
*
* Description:
* Sets/clears EXTI alarm interrupt.
*
* Parameters:
* - rising/falling edge: enables interrupt on rising/falling edges
* - event: generate event when set
* - func: when non-NULL, generate interrupt
*
* Returns:
* The previous value of the interrupt handler function pointer. This value may,
* for example, be used to restore the previous handler when multiple handlers are
* used.
*
************************************************************************************/
#ifdef CONFIG_RTC_ALARM
xcpt_t stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_EXTI_H */

375
arch/arm/src/stm32f7/stm32_exti_gpio.c Normal file
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@ -0,0 +1,375 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_exti_gpio.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Based on EXTI GPIO logic from the Cortex-M3/4 which includes contributions
* from Uros Patise:
*
* Copyright (C) 2009, 2011-2012, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Uros Platise <uros.platise@isotel.eu>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <arch/irq.h>
#include "up_arch.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_exti.h"
/* Content of this file requires verification before it is used with other
* families
*/
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
/****************************************************************************
* Private Data
****************************************************************************/
/* Interrupt handlers attached to each EXTI */
static xcpt_t stm32_exti_callbacks[16];
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Interrupt Service Routines - Dispatchers
****************************************************************************/
static int stm32_exti0_isr(int irq, void *context)
{
int ret = OK;
/* Clear the pending interrupt */
putreg32(0x0001, STM32_EXTI_PR);
/* And dispatch the interrupt to the handler */
if (stm32_exti_callbacks[0])
{
ret = stm32_exti_callbacks[0](irq, context);
}
return ret;
}
static int stm32_exti1_isr(int irq, void *context)
{
int ret = OK;
/* Clear the pending interrupt */
putreg32(0x0002, STM32_EXTI_PR);
/* And dispatch the interrupt to the handler */
if (stm32_exti_callbacks[1])
{
ret = stm32_exti_callbacks[1](irq, context);
}
return ret;
}
static int stm32_exti2_isr(int irq, void *context)
{
int ret = OK;
/* Clear the pending interrupt */
putreg32(0x0004, STM32_EXTI_PR);
/* And dispatch the interrupt to the handler */
if (stm32_exti_callbacks[2])
{
ret = stm32_exti_callbacks[2](irq, context);
}
return ret;
}
static int stm32_exti3_isr(int irq, void *context)
{
int ret = OK;
/* Clear the pending interrupt */
putreg32(0x0008, STM32_EXTI_PR);
/* And dispatch the interrupt to the handler */
if (stm32_exti_callbacks[3])
{
ret = stm32_exti_callbacks[3](irq, context);
}
return ret;
}
static int stm32_exti4_isr(int irq, void *context)
{
int ret = OK;
/* Clear the pending interrupt */
putreg32(0x0010, STM32_EXTI_PR);
/* And dispatch the interrupt to the handler */
if (stm32_exti_callbacks[4])
{
ret = stm32_exti_callbacks[4](irq, context);
}
return ret;
}
static int stm32_exti_multiisr(int irq, void *context, int first, int last)
{
uint32_t pr;
int pin;
int ret = OK;
/* Examine the state of each pin in the group */
pr = getreg32(STM32_EXTI_PR);
/* And dispatch the interrupt to the handler */
for (pin = first; pin <= last; pin++)
{
/* Is an interrupt pending on this pin? */
uint32_t mask = (1 << pin);
if ((pr & mask) != 0)
{
/* Clear the pending interrupt */
putreg32(mask, STM32_EXTI_PR);
/* And dispatch the interrupt to the handler */
if (stm32_exti_callbacks[pin])
{
int tmp = stm32_exti_callbacks[pin](irq, context);
if (tmp != OK)
{
ret = tmp;
}
}
}
}
return ret;
}
static int stm32_exti95_isr(int irq, void *context)
{
return stm32_exti_multiisr(irq, context, 5, 9);
}
static int stm32_exti1510_isr(int irq, void *context)
{
return stm32_exti_multiisr(irq, context, 10, 15);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
*
* Parameters:
* - pinset: gpio pin configuration
* - rising/falling edge: enables
* - event: generate event when set
* - func: when non-NULL, generate interrupt
*
* Returns:
* The previous value of the interrupt handler function pointer. This value may,
* for example, be used to restore the previous handler when multiple handlers are
* used.
*
****************************************************************************/
xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func)
{
uint32_t pin = pinset & GPIO_PIN_MASK;
uint32_t exti = STM32_EXTI_BIT(pin);
int irq;
xcpt_t handler;
xcpt_t oldhandler = NULL;
int nshared;
xcpt_t *shared_cbs;
int i;
/* Select the interrupt handler for this EXTI pin */
if (pin < 5)
{
irq = pin + STM32_IRQ_EXTI0;
nshared = 1;
shared_cbs = &stm32_exti_callbacks[pin];
switch (pin)
{
case 0:
handler = stm32_exti0_isr;
break;
case 1:
handler = stm32_exti1_isr;
break;
case 2:
handler = stm32_exti2_isr;
break;
case 3:
handler = stm32_exti3_isr;
break;
default:
handler = stm32_exti4_isr;
break;
}
}
else if (pin < 10)
{
irq = STM32_IRQ_EXTI95;
handler = stm32_exti95_isr;
shared_cbs = &stm32_exti_callbacks[5];
nshared = 5;
}
else
{
irq = STM32_IRQ_EXTI1510;
handler = stm32_exti1510_isr;
shared_cbs = &stm32_exti_callbacks[10];
nshared = 6;
}
/* Get the previous GPIO IRQ handler; Save the new IRQ handler. */
oldhandler = stm32_exti_callbacks[pin];
stm32_exti_callbacks[pin] = func;
/* Install external interrupt handlers */
if (func)
{
irq_attach(irq, handler);
up_enable_irq(irq);
}
else
{
/* Only disable IRQ if shared handler does not have any active
* callbacks.
*/
for (i = 0; i < nshared; i++)
{
if (shared_cbs[i] != NULL)
{
break;
}
}
if (i == nshared)
{
up_disable_irq(irq);
}
}
/* Configure GPIO, enable EXTI line enabled if event or interrupt is
* enabled.
*/
if (event || func)
{
pinset |= GPIO_EXTI;
}
stm32_configgpio(pinset);
/* Configure rising/falling edges */
modifyreg32(STM32_EXTI_RTSR,
risingedge ? 0 : exti,
risingedge ? exti : 0);
modifyreg32(STM32_EXTI_FTSR,
fallingedge ? 0 : exti,
fallingedge ? exti : 0);
/* Enable Events and Interrupts */
modifyreg32(STM32_EXTI_EMR,
event ? 0 : exti,
event ? exti : 0);
modifyreg32(STM32_EXTI_IMR,
func ? 0 : exti,
func ? exti : 0);
/* Return the old IRQ handler */
return oldhandler;
}
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */

454
arch/arm/src/stm32f7/stm32_gpio.c Normal file
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/****************************************************************************
* arch/arm/src/stm32f7/stm32_gpio.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <arch/irq.h>
#include <arch/stm32f7/chip.h>
#include "up_arch.h"
#include "stm32_gpio.h"
/* Content of this file requires verification before it is used with other
* families
*/
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
/****************************************************************************
* Public Data
****************************************************************************/
/* Base addresses for each GPIO block */
const uint32_t g_gpiobase[STM32F7_NGPIO] =
{
#if STM32F7_NGPIO > 0
STM32_GPIOA_BASE,
#endif
#if STM32F7_NGPIO > 1
STM32_GPIOB_BASE,
#endif
#if STM32F7_NGPIO > 2
STM32_GPIOC_BASE,
#endif
#if STM32F7_NGPIO > 3
STM32_GPIOD_BASE,
#endif
#if STM32F7_NGPIO > 4
STM32_GPIOE_BASE,
#endif
#if STM32F7_NGPIO > 5
STM32_GPIOF_BASE,
#endif
#if STM32F7_NGPIO > 6
STM32_GPIOG_BASE,
#endif
#if STM32F7_NGPIO > 7
STM32_GPIOH_BASE,
#endif
#if STM32F7_NGPIO > 8
STM32_GPIOI_BASE,
#endif
#if STM32F7_NGPIO > 9
STM32_GPIOJ_BASE,
#endif
#if STM32F7_NGPIO > 10
STM32_GPIOK_BASE,
#endif
};
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: stm32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from stm32_start().
*
* Assumptions:
* This function is called early in the initialization sequence so that
* no mutual exclusion is necessary.
*
****************************************************************************/
void stm32_gpioinit(void)
{
}
/****************************************************************************
* Name: stm32_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with stm32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returns:
* OK on success
* A negated errono value on invalid port, or when pin is locked as ALT
* function.
*
* To-Do: Auto Power Enable
****************************************************************************/
int stm32_configgpio(uint32_t cfgset)
{
uintptr_t base;
uint32_t regval;
uint32_t setting;
unsigned int regoffset;
unsigned int port;
unsigned int pin;
unsigned int pos;
unsigned int pinmode;
irqstate_t flags;
/* Verify that this hardware supports the select GPIO port */
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port >= STM32F7_NGPIO)
{
return -EINVAL;
}
/* Get the port base address */
base = g_gpiobase[port];
/* Get the pin number and select the port configuration register for that
* pin
*/
pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
/* Set up the mode register (and remember whether the pin mode) */
switch (cfgset & GPIO_MODE_MASK)
{
default:
case GPIO_INPUT: /* Input mode */
pinmode = GPIO_MODER_INPUT;
break;
case GPIO_OUTPUT: /* General purpose output mode */
pinmode = GPIO_MODER_OUTPUT;
break;
case GPIO_ALT: /* Alternate function mode */
pinmode = GPIO_MODER_ALT;
break;
case GPIO_ANALOG: /* Analog mode */
pinmode = GPIO_MODER_ANALOG;
break;
}
/* Interrupts must be disabled from here on out so that we have mutually
* exclusive access to all of the GPIO configuration registers.
*/
flags = irqsave();
/* Now apply the configuration to the mode register */
regval = getreg32(base + STM32_GPIO_MODER_OFFSET);
regval &= ~GPIO_MODER_MASK(pin);
regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin));
putreg32(regval, base + STM32_GPIO_MODER_OFFSET);
/* Set up the pull-up/pull-down configuration (all but analog pins) */
setting = GPIO_PUPDR_NONE;
if (pinmode != GPIO_MODER_ANALOG)
{
switch (cfgset & GPIO_PUPD_MASK)
{
default:
case GPIO_FLOAT: /* No pull-up, pull-down */
break;
case GPIO_PULLUP: /* Pull-up */
setting = GPIO_PUPDR_PULLUP;
break;
case GPIO_PULLDOWN: /* Pull-down */
setting = GPIO_PUPDR_PULLDOWN;
break;
}
}
regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET);
regval &= ~GPIO_PUPDR_MASK(pin);
regval |= (setting << GPIO_PUPDR_SHIFT(pin));
putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET);
/* Set the alternate function (Only alternate function pins) */
if (pinmode == GPIO_MODER_ALT)
{
setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT;
}
else
{
setting = 0;
}
if (pin < 8)
{
regoffset = STM32_GPIO_AFRL_OFFSET;
pos = pin;
}
else
{
regoffset = STM32_GPIO_AFRH_OFFSET;
pos = pin - 8;
}
regval = getreg32(base + regoffset);
regval &= ~GPIO_AFR_MASK(pos);
regval |= (setting << GPIO_AFR_SHIFT(pos));
putreg32(regval, base + regoffset);
/* Set speed (Only outputs and alternate function pins) */
if (pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT)
{
switch (cfgset & GPIO_SPEED_MASK)
{
default:
case GPIO_SPEED_2MHz: /* 2 MHz Low speed output */
setting = GPIO_OSPEED_2MHz;
break;
case GPIO_SPEED_25MHz: /* 25 MHz Medium speed output */
setting = GPIO_OSPEED_25MHz;
break;
case GPIO_SPEED_50MHz: /* 50 MHz Fast speed output */
setting = GPIO_OSPEED_50MHz;
break;
case GPIO_SPEED_100MHz: /* 100 MHz High speed output */
setting = GPIO_OSPEED_100MHz;
break;
}
}
else
{
setting = 0;
}
regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET);
regval &= ~GPIO_OSPEED_MASK(pin);
regval |= (setting << GPIO_OSPEED_SHIFT(pin));
putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET);
/* Set push-pull/open-drain (Only outputs and alternate function pins) */
regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET);
setting = GPIO_OTYPER_OD(pin);
if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) &&
(cfgset & GPIO_OPENDRAIN) != 0)
{
regval |= setting;
}
else
{
regval &= ~setting;
}
putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET);
/* If it is an output... set the pin to the correct initial state. */
if (pinmode == GPIO_MODER_OUTPUT)
{
bool value = ((cfgset & GPIO_OUTPUT_SET) != 0);
stm32_gpiowrite(cfgset, value);
}
/* Otherwise, it is an input pin. Should it configured as an EXTI interrupt? */
else if ((cfgset & GPIO_EXTI) != 0)
{
/* "In STM32 F1 the selection of the EXTI line source is performed through
* the EXTIx bits in the AFIO_EXTICRx registers, while in F2 series this
* selection is done through the EXTIx bits in the SYSCFG_EXTICRx registers.
*
* "Only the mapping of the EXTICRx registers has been changed, without any
* changes to the meaning of the EXTIx bits. However, the range of EXTI
* bits values has been extended to 0b1000 to support the two ports added
* in F2, port H and I (in F1 series the maximum value is 0b0110)."
*/
uint32_t regaddr;
int shift;
/* Set the bits in the SYSCFG EXTICR register */
regaddr = STM32_SYSCFG_EXTICR(pin);
regval = getreg32(regaddr);
shift = SYSCFG_EXTICR_EXTI_SHIFT(pin);
regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift);
regval |= (((uint32_t)port) << shift);
putreg32(regval, regaddr);
}
irqrestore(flags);
return OK;
}
/****************************************************************************
* Name: stm32_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set it
* into default HiZ state (and possibly mark it's unused) and unlock it whether
* it was previously selected as alternative function (GPIO_ALT|GPIO_CNF_AFPP|...).
*
* This is a safety function and prevents hardware from schocks, as unexpected
* write to the Timer Channel Output GPIO to fixed '1' or '0' while it should
* operate in PWM mode could produce excessive on-board currents and trigger
* over-current/alarm function.
*
* Returns:
* OK on success
* A negated errno value on invalid port
*
* To-Do: Auto Power Disable
****************************************************************************/
int stm32_unconfiggpio(uint32_t cfgset)
{
/* Reuse port and pin number and set it to default HiZ INPUT */
cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK;
cfgset |= GPIO_INPUT | GPIO_FLOAT;
/* To-Do: Mark its unuse for automatic power saving options */
return stm32_configgpio(cfgset);
}
/****************************************************************************
* Name: stm32_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void stm32_gpiowrite(uint32_t pinset, bool value)
{
uint32_t base;
uint32_t bit;
unsigned int port;
unsigned int pin;
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port < STM32F7_NGPIO)
{
/* Get the port base address */
base = g_gpiobase[port];
/* Get the pin number */
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
/* Set or clear the output on the pin */
if (value)
{
bit = GPIO_BSRR_SET(pin);
}
else
{
bit = GPIO_BSRR_RESET(pin);
}
putreg32(bit, base + STM32_GPIO_BSRR_OFFSET);
}
}
/****************************************************************************
* Name: stm32_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool stm32_gpioread(uint32_t pinset)
{
uint32_t base;
unsigned int port;
unsigned int pin;
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port < STM32F7_NGPIO)
{
/* Get the port base address */
base = g_gpiobase[port];
/* Get the pin number and return the input state of that pin */
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
}
return 0;
}
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */

78
arch/arm/src/stm32f7/stm32_lowputc.h Normal file
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@ -0,0 +1,78 @@
/************************************************************************************
* arch/arm/src/stm32f7/stm32_lowputc.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_LOWPUTC_H
#define __ARCH_ARM_SRC_STM32F7_STM32_LOWPUTC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Name: stm32_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level initialization
* of serial console.
*
************************************************************************************/
void stm32_lowsetup(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_LOWPUTC_H */

1
arch/arm/src/stm32f7/stm32_start.c
View File

@ -56,6 +56,7 @@
#include "stm32_rcc.h"
#include "stm32_userspace.h"
#include "stm32_lowputc.h"
#include "stm32_start.h"
/****************************************************************************