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Xtensa: Fix some compilation issues

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This commit is contained in:
Gregory Nutt 2016-10-25 12:34:23 -06:00
parent 2a59205ffa
commit d5fceadacd
9 changed files with 46 additions and 38 deletions
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8
arch/xtensa/src/common/xtensa_cpuint.S
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@ -37,10 +37,8 @@
* Included Files
****************************************************************************/
#include <xtensa/hal.h>
#include <xtensa/config/core.h>
#include "xtensa_context.h"
#include <nuttx/config.h>
#include <arch/chip/core-isa.h>
#if XCHAL_HAVE_INTERRUPTS
@ -104,7 +102,7 @@ xtensa_enable_cpuint:
****************************************************************************/
.text
.globa xtensa_disable_cpuint
.global xtensa_disable_cpuint
.type xtensa_disable_cpuint, @function
.align 4

12
arch/xtensa/src/common/xtensa_dumpstate.c
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@ -150,12 +150,24 @@ void xtensa_dumpstate(void)
uint32_t istacksize;
#endif
#ifdef CONFIG_SMP
/* Show the CPU number */
_alert("CPU%d:\n", up_cpu_index());
#endif
/* Get the limits on the user stack memory */
if (rtcb->pid == 0)
{
#warning REVISIT: Need top of IDLE stack
#if 0
ustackbase = g_idle_topstack - 4;
ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
#else
ustackbase = sp + 128;
ustacksize = 128;
#endif
}
else
{

2
arch/xtensa/src/common/xtensa_inthandlers.S
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@ -62,9 +62,9 @@
#include <arch/irq.h>
#include <arch/chip/core-isa.h>
#include <arch/xtensa/xtensa_specregs.h>
#include <arch/chip/chip_macros.h>
#include "xtensa_macros.h"
#include "chip_macros.h"
#include "xtensa_timer.h"
/****************************************************************************

2
arch/xtensa/src/common/xtensa_nmihandler.S
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@ -61,8 +61,8 @@
#include <arch/chip/core-isa.h>
#include <arch/xtensa/xtensa_specregs.h>
#include <arch/chip/chip_macros.h>
#include "chip_macros.h"
#include "xtensa_macros.h"
/****************************************************************************

20
arch/xtensa/src/esp32/Make.defs
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@ -40,16 +40,15 @@ HEAD_CSRC = esp32_start.c
# Common XTENSA files (arch/xtensa/src/common)
CMN_ASRCS = xtensa_context.S xtensa_vectors.S xtensa_inthandlers.S
CMN_ASRCS += xtensa_nmihandler.S
CMN_ASRCS = xtensa_context.S xtensa_cpuint.S xtensa_vectors.S
CMN_ASRCS += xtensa_inthandlers.S xtensa_nmihandler.S
CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c
CMN_CSRCS += xtens_cpuint.c xtensa_createstack.c xtensa_exit.c
CMN_CSRCS += xtensa_idle.c xtensa_initialize.c xtensa_initialstate.c
CMN_CSRCS += xtensa_interruptcontext.c xtensa_irqdispatch.c
CMN_CSRCS += xtensa_lowputs.c xtensa_mdelay.c xtensa_modifyreg8.c
CMN_CSRCS += xtensa_modifyreg16.c xtensa_modifyreg32.c xtensa_puts.c
CMN_CSRCS += xtensa_releasepending.c xtensa_releasestack.c
CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c
CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c
CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c
CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c
CMN_CSRCS += xtensa_puts.c xtensa_releasepending.c xtensa_releasestack.c
CMN_CSRCS += xtensa_reprioritizertr.c xtensa_schedsigaction.c
CMN_CSRCS += xtensa_sigdeliver.c xtensa_stackframe.c xtensa_udelay.c
CMN_CSRCS += xtensa_unblocktask.c xtensa_usestack.c
@ -78,8 +77,9 @@ endif
# Required ESP32 files (arch/xtensa/src/lx6)
CHIP_ASRCS =
CHIP_CSRCS = esp32_allocateheap.c esp32_cpuint.c esp32_intdecode.c
CHIP_CSRCS += esp32_irq.c esp32_region.c esp32_start.c esp32_timerisr.c
CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_cpuint.c
CHIP_CSRCS += esp32_intdecode.c esp32_irq.c esp32_region.c esp32_start.c
CHIP_CSRCS += esp32_timerisr.c
# Configuration-dependent ESP32 files

12
arch/xtensa/src/esp32/esp32_clockconfig.c
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@ -13,7 +13,7 @@
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
@ -26,21 +26,24 @@
/****************************************************************************
* Included Files
****************************************************************************
****************************************************************************/
#include <stdint.h>
#include "xtensa.h"
#ifndef CONFIG_SUPPRESS_CLOCK_CONFIG
#warning REVISIT ... function prototypes
void phy_get_romfunc_addr(void);
void rtc_init_lite(void);
void rtc_set_cpu_freq(xtal_freq_t xtal_freq, enum xtal_freq_e cpu_freq);
#endif
/****************************************************************************
* Private Types
****************************************************************************
****************************************************************************/
#ifndef CONFIG_SUPPRESS_CLOCK_CONFIG
enum xtal_freq_e
{
XTAL_40M = 40,
@ -55,10 +58,11 @@ enum xtal_freq_e
CPU_160M = 2,
CPU_240M = 3,
};
#endif
/****************************************************************************
* Public Functions
****************************************************************************
****************************************************************************/
/****************************************************************************
* Name: esp32_clockconfig

17
arch/xtensa/src/esp32/esp32_cpuint.c
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@ -41,6 +41,7 @@
#include <stdint.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/arch.h>
@ -67,18 +68,18 @@
#ifdef CONFIG_SMP
static uint32_t *g_intenable[CONFIG_SMP_NCPUS];
static uint32_t g_intenable[CONFIG_SMP_NCPUS];
#else
static uint32_t *g_intenable[1];
static uint32_t g_intenable[1];
#endif
/* Bitsets for free, unallocated CPU interrupts */
status uint32_t g_level_ints = ESP32_LEVEL_SET;
status uint32_t g_edge_ints = ESP32_EDGE_SET;
static uint32_t g_level_ints = ESP32_LEVEL_SET;
static uint32_t g_edge_ints = ESP32_EDGE_SET;
/****************************************************************************
* Private Functions
@ -106,9 +107,9 @@ void up_disable_irq(int cpuint)
#ifdef CONFIG_SMP
cpu = up_cpu_index();
(void)xtensa_disable_cpuint(&g_intenable[cpu], (1ul << cpuint))
(void)xtensa_disable_cpuint(&g_intenable[cpu], (1ul << cpuint));
#else
(void)xtensa_disable_cpuint(&g_intenable[0], (1ul << cpuint))
(void)xtensa_disable_cpuint(&g_intenable[0], (1ul << cpuint));
#endif
}
@ -130,9 +131,9 @@ void up_enable_irq(int cpuint)
#ifdef CONFIG_SMP
cpu = up_cpu_index();
(void)xtensa_enable_cpuint(&g_intenable[cpu], (1ul << cpuint))
(void)xtensa_enable_cpuint(&g_intenable[cpu], (1ul << cpuint));
#else
(void)xtensa_enable_cpuint(&g_intenable[0], (1ul << cpuint))
(void)xtensa_enable_cpuint(&g_intenable[0], (1ul << cpuint));
#endif
}

3
arch/xtensa/src/esp32/esp32_intdecode.c
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@ -91,6 +91,7 @@ uint32_t *xtensa_int_decode(uint32_t *regs)
int regndx;
int bit;
int baseirq;
int nirqs;
#ifdef CONFIG_SMP
int cpu;
@ -122,7 +123,7 @@ uint32_t *xtensa_int_decode(uint32_t *regs)
/* Set up the search */
baseirq = g_baseirq[regndx];
nirqs = g_nirqs[regndx]
nirqs = g_nirqs[regndx];
/* Decode and dispatch each pending bit in the interrupt status
* register.

8
arch/xtensa/src/esp32/esp32_timerisr.c
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@ -51,14 +51,6 @@
#include "xtensa_timer.h"
#include "xtensa.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if XT_TIMER_INTEN != ESP32_CPUINT_TIMER0
# error Mismatch in irq.h and xtensa_timer.h
#endif
/****************************************************************************
* Private data
****************************************************************************/