nrf52: add workaround to SPI Master 1 Byte transfer anomaly
This commit is contained in:
raiden00pl
patacongo
parent
8b20b97d26
commit
d66cb505a5
@ -90,6 +90,14 @@ config NRF52_UART
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bool
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default n
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config NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER
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bool "SPI Master 1 Byte transfer anomaly workaround"
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depends on NRF52_SPI_MASTER && ARCH_FAMILY_NRF52832
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default y
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---help---
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Enable the workaround to fix SPI Master 1 byte transfer bug
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which occurs in NRF52832 revision 1 and revision 2.
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menu "NRF52 Peripheral Selection"
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config NRF52_I2C0_MASTER
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63
arch/arm/src/nrf52/hardware/nrf52_ppi.h
Normal file
63
arch/arm/src/nrf52/hardware/nrf52_ppi.h
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@ -0,0 +1,63 @@
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/****************************************************************************
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* arch/arm/src/nrf52/hardware/nrf52_ppi.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_PPI_H
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#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_PPI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/nrf52_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets for PPI *************************************************/
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#define NRF52_PPI_TASK_CHGEN_OFFSET(x) (0x000 + (x * 0x8)) /* Enable channel group x */
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#define NRF52_PPI_TASK_CHGDIS_OFFSET(x) (0x004 + (x * 0x8)) /* Disable channel group x */
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#define NRF52_PPI_CHEN_OFFSET (0x500) /* Channel enable register */
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#define NRF52_PPI_CHENSET_OFFSET (0x504) /* Channel enable set register */
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#define NRF52_PPI_CHENCLR_OFFSET (0x508) /* Channel enable clear register*/
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#define NRF52_PPI_CHEEP_OFFSET(x) (0x510 + (x * 0x8)) /* Channel x event end-point */
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#define NRF52_PPI_CHTEP_OFFSET(x) (0x514 + (x * 0x8)) /* Channel x task end-point */
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#define NRF52_PPI_CHG_OFFSET(x) (0x800 + (x * 0x4)) /* Channel group x */
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#define NRF52_PPI_FORKTEP_OFFSET(x) (0x910 + (x * 0x4)) /* Channel x task end-point */
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/* Register addresses for PPI ***********************************************/
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#define NRF52_PPI_TASK_CHGEN(x) (NRF52_PPI_BASE + NRF52_PPI_TASK_CHGEN_OFFSET(x))
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#define NRF52_PPI_TASK_CHGDIS(x) (NRF52_PPI_BASE + NRF52_PPI_TASK_CHGDIS_OFFSET(x))
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#define NRF52_PPI_CHEN (NRF52_PPI_BASE + NRF52_PPI_CHEN_OFFSET)
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#define NRF52_PPI_CHENSET (NRF52_PPI_BASE + NRF52_PPI_CHENSET_OFFSET)
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#define NRF52_PPI_CHENCLR (NRF52_PPI_BASE + NRF52_PPI_CHENCLR_OFFSET)
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#define NRF52_PPI_CHEEP(x) (NRF52_PPI_BASE + NRF52_PPI_CHEEP_OFFSET(x))
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#define NRF52_PPI_CHTEP(x) (NRF52_PPI_BASE + NRF52_PPI_CHTEP_OFFSET(x))
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#define NRF52_PPI_CHG(x) (NRF52_PPI_BASE + NRF52_PPI_CHG_OFFSET(x))
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#define NRF52_PPI_FORKTEP(x) (NRF52_PPI_BASE + NRF52_PPI_FORKTEP_OFFSET(x))
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/* Register Bitfield Definitions for PPI ************************************/
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#define PPI_CHEN_CH(x) (1 << x) /* Enable or disable channel x */
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#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_PPI_H */
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@ -54,6 +54,11 @@
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#include "hardware/nrf52_spi.h"
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#ifdef CONFIG_NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER
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# include "hardware/nrf52_gpiote.h"
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# include "hardware/nrf52_ppi.h"
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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@ -67,6 +72,13 @@
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# error Unsupported configuration I2C1 + SPI1
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#endif
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/* Reserve PPI channel and GPIOTE channel for 1 byte transfer workaround */
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#ifdef CONFIG_NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER
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# define SPI_1B_WORKAROUND_PPI_CHAN (18)
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# define SPI_1B_WORKAROUND_GPIOTE_CHAN (7)
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -771,6 +783,71 @@ static uint32_t nrf52_spi_send(FAR struct spi_dev_s *dev, uint32_t wd)
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return ret;
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}
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#ifdef CONFIG_NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER
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/****************************************************************************
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* Name: n4f52_spi_1b_workaround
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*
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* Description:
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* Workaround to fix SPI Master 1 byte transfer for NRF52832.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* enable - Enable/disable workaround
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void nrf52_spi_1b_workaround(FAR struct spi_dev_s *dev, bool enable)
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{
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FAR struct nrf52_spidev_s *priv = (FAR struct nrf52_spidev_s *)dev;
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uint32_t pin = 0;
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uint32_t port = 0;
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pin = (priv->sck_pin & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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port = (priv->sck_pin & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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if (enable == true)
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{
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/* Create an event when SCK toggles */
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putreg32((GPIOTE_CONFIG_MODE_EV |
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pin << GPIOTE_CONFIG_PSEL_SHIFT |
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port << GPIOTE_CONFIG_PORT_SHIFT |
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GPIOTE_CONFIG_POL_TG),
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NRF52_GPIOTE_CONFIG(SPI_1B_WORKAROUND_GPIOTE_CHAN));
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/* Stop the SPIM instance when SCK toggles */
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putreg32(NRF52_GPIOTE_EVENTS_IN(SPI_1B_WORKAROUND_GPIOTE_CHAN),
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NRF52_PPI_CHEEP(SPI_1B_WORKAROUND_PPI_CHAN));
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putreg32((priv->base + NRF52_SPIM_TASK_STOP_OFFSET),
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NRF52_PPI_CHTEP(SPI_1B_WORKAROUND_PPI_CHAN));
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/* Enable PPI channel */
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modifyreg32(NRF52_PPI_CHEN, 0,
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PPI_CHEN_CH(SPI_1B_WORKAROUND_PPI_CHAN));
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}
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else
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{
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/* Disable event */
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putreg32(0, NRF52_GPIOTE_CONFIG(SPI_1B_WORKAROUND_GPIOTE_CHAN));
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putreg32(0, NRF52_PPI_CHEEP(SPI_1B_WORKAROUND_PPI_CHAN));
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putreg32(0, NRF52_PPI_CHTEP(SPI_1B_WORKAROUND_PPI_CHAN));
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/* Disable PPI channel */
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modifyreg32(NRF52_PPI_CHEN,
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PPI_CHEN_CH(SPI_1B_WORKAROUND_PPI_CHAN), 0);
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}
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}
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#endif
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/****************************************************************************
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* Name: nrf52_spi_exchange
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*
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@ -797,6 +874,13 @@ static void nrf52_spi_exchange(FAR struct spi_dev_s *dev,
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FAR struct nrf52_spidev_s *priv = (FAR struct nrf52_spidev_s *)dev;
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uint32_t regval = 0;
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#ifdef CONFIG_NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER
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if (nwords <= 1)
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{
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nrf52_spi_1b_workaround(dev, true);
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}
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#endif
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if (rxbuffer != NULL)
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{
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/* Write RXD data pointer */
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@ -859,6 +943,13 @@ static void nrf52_spi_exchange(FAR struct spi_dev_s *dev,
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nrf52_spi_putreg(priv, NRF52_SPIM_RXDMAXCNT_OFFSET, 0);
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nrf52_spi_putreg(priv, NRF52_SPIM_TXDPTR_OFFSET, 0);
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nrf52_spi_putreg(priv, NRF52_SPIM_TXDMAXCNT_OFFSET, 0);
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#ifdef CONFIG_NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER
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if (nwords <= 1)
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{
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nrf52_spi_1b_workaround(dev, false);
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}
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#endif
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}
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#ifndef CONFIG_SPI_EXCHANGE
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