SAMA5 SSC: Frame Synch Delay is now configurable
This commit is contained in:
Gregory Nutt
parent
c2c2921901
commit
d68a6059e0
@ -2154,6 +2154,15 @@ config SAMA5_SSC0_RX_RKOUTPUT_XFR
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endchoice # Receiver output clock
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endif # !SAMA5_SSC0_RX_RKINPUT
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config SAMA5_SSC0_RX_FSLEN
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int "Receive Frame Sync Length"
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default 1
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range 1 255
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---help---
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This setting determines the pulse length of the Receive Frame Sync
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signal in units of receive clock periods.
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endif # SAMA5_SSC0_RX
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config SAMA5_SSC0_TX
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@ -2204,6 +2213,17 @@ config SAMA5_SSC0_TX_TKOUTPUT_XFR
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endchoice # Receiver output clock
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endif # !SAMA5_SSC0_TX_TKINPUT
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config SAMA5_SSC0_TX_FSLEN
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int "Transmit Frame Sync Length"
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default 1
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range 0 255
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---help---
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This setting define the length of the Transmit Frame Sync signal in
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units of transmit clock periods. A value of zero disables this
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feature. In that case the TD line is driven with the default value
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during the Transmit Frame Sync signal.
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endif # SAMA5_SSC0_TX
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config SAMA5_SSC0_MCKDIV_SAMPLERATE
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@ -2288,7 +2308,16 @@ config SAMA5_SSC1_RX_RKOUTPUT_XFR
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endchoice # Receiver output clock
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endif # !SAMA5_SSC1_RX_RKINPUT
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endif # SAMA5_SSC0_RX
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config SAMA5_SSC1_RX_FSLEN
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int "Receive Frame Sync Length"
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default 1
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range 1 255
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---help---
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This setting determines the pulse length of the Receive Frame Sync
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signal in units of receive clock periods.
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endif # SAMA5_SSC1_RX
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config SAMA5_SSC1_TX
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bool "Enable I2C transmitter"
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@ -2338,6 +2367,17 @@ config SAMA5_SSC1_TX_TKOUTPUT_XFR
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endchoice # Receiver output clock
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endif # !SAMA5_SSC1_TX_TKINPUT
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config SAMA5_SSC1_TX_FSLEN
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int "Receive Frame Sync Length"
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default 1
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range 0 255
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---help---
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This setting define the length of the Transmit Frame Sync signal in
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units of transmit clock periods. A value of zero disables this
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feature. In that case the TD line is driven with the default value
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during the Transmit Frame Sync signal.
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endif # SAMA5_SSC1_TX
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config SAMA5_SSC1_MCKDIV_SAMPLERATE
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@ -88,7 +88,15 @@
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# define SAMA5_SSC_MAXINFLIGHT 16
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#endif
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/* Assume no RX/TX support */
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#undef SSC_HAVE_RX
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#undef SSC_HAVE_TX
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/* Check for SSC0 support */
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#if defined(CONFIG_SAMA5_SSC0)
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# if defined(CONFIG_SAMA5_HAVE_XDMA)
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# if !defined(CONFIG_SAMA5_XDMAC0) && !defined(CONFIG_SAMA5_XDMAC1)
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# error CONFIG_SAMA5_XDMAC1 (or XDMAC0) required by SSC0
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@ -98,9 +106,49 @@
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# error CONFIG_SAMA5_DMAC0 required by SSC0
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# endif
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# endif
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# ifndef CONFIG_SAMA5_SSC0_DATALEN
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# define CONFIG_SAMA5_SSC0_DATALEN 16
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# endif
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# if CONFIG_SAMA5_SSC0_DATALEN < 2 || CONFIG_SAMA5_SSC0_DATALEN > 32
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# error Invalid value for CONFIG_SAMA5_SSC0_DATALEN
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# endif
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/* Check for SSC0 RX support */
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# if (defined(CONFIG_SAMA5_SSC0) && defined(CONFIG_SAMA5_SSC0_RX))
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# define SSC_HAVE_RX 1
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# ifndef CONFIG_SSC0_RX_FSLEN
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# define CONFIG_SSC0_RX_FSLEN 1
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# endif
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# if CONFIG_SSC0_RX_FSLEN < 1 || CONFIG_SSC0_RX_FSLEN > 255
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# error Invalid value for CONFIG_SSC0_RX_FSLEN
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# endif
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# endif
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/* Check for SSC0 TX support */
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# if (defined(CONFIG_SAMA5_SSC0) && defined(CONFIG_SAMA5_SSC0_TX))
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# define SSC_HAVE_TX 1
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# ifndef CONFIG_SSC0_TX_FSLEN
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# define CONFIG_SSC0_TX_FSLEN 0
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# endif
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# if CONFIG_SSC0_TX_FSLEN < 0 || CONFIG_SSC0_TX_FSLEN > 255
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# error Invalid value for CONFIG_SSC0_TX_FSLEN
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# endif
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# endif
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#endif
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/* Check for SSC1 support */
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#if defined(CONFIG_SAMA5_SSC1)
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# if defined(CONFIG_SAMA5_HAVE_XDMA)
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# if !defined(CONFIG_SAMA5_XDMAC0) && !defined(CONFIG_SAMA5_XDMAC1)
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# error CONFIG_SAMA5_XDMAC1 (or XDMAC0) required by SSC1
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@ -110,14 +158,43 @@
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# error CONFIG_SAMA5_DMAC0 required by SSC1
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# endif
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# endif
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#endif
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#ifndef CONFIG_SAMA5_SSC0_DATALEN
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# define CONFIG_SAMA5_SSC0_DATALEN 16
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#endif
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# ifndef CONFIG_SAMA5_SSC1_DATALEN
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# define CONFIG_SAMA5_SSC1_DATALEN 16
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# endif
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# if CONFIG_SAMA5_SSC1_DATALEN < 2 || CONFIG_SAMA5_SSC1_DATALEN > 32
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# error Invalid value for CONFIG_SAMA5_SSC1_DATALEN
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# endif
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/* Check for SSC1 RX support */
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# if (defined(CONFIG_SAMA5_SSC1) && defined(CONFIG_SAMA5_SSC1_RX))
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# define SSC_HAVE_RX 1
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# ifndef CONFIG_SSC1_RX_FSLEN
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# define CONFIG_SSC1_RX_FSLEN 1
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# endif
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# if CONFIG_SSC1_RX_FSLEN < 1 || CONFIG_SSC1_RX_FSLEN > 255
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# error Invalid value for CONFIG_SSC1_RX_FSLEN
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# endif
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# endif
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/* Check for SSC0 TX support */
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# if (defined(CONFIG_SAMA5_SSC1) && defined(CONFIG_SAMA5_SSC1_TX))
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# define SSC_HAVE_TX 1
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# ifndef CONFIG_SSC1_TX_FSLEN
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# define CONFIG_SSC1_TX_FSLEN 0
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# endif
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# if CONFIG_SSC1_TX_FSLEN < 0 || CONFIG_SSC1_TX_FSLEN > 255
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# error Invalid value for CONFIG_SSC1_TX_FSLEN
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# endif
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# endif
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#if CONFIG_SAMA5_SSC0_DATALEN < 2 || CONFIG_SAMA5_SSC0_DATALEN > 32
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# error Invalid value for CONFIG_SAMA5_SSC0_DATALEN
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#endif
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#ifndef CONFIG_AUDIO
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@ -126,19 +203,6 @@
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/* Check if we need to build RX and/or TX support */
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#undef SSC_HAVE_RX
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#undef SSC_HAVE_TX
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#if (defined(CONFIG_SAMA5_SSC0) && defined(CONFIG_SAMA5_SSC0_RX)) || \
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(defined(CONFIG_SAMA5_SSC1) && defined(CONFIG_SAMA5_SSC1_RX))
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# define SSC_HAVE_RX
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#endif
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#if (defined(CONFIG_SAMA5_SSC0) && defined(CONFIG_SAMA5_SSC0_TX)) || \
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(defined(CONFIG_SAMA5_SSC1) && defined(CONFIG_SAMA5_SSC1_TX))
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# define SSC_HAVE_TX
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#endif
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#if defined(SSC_HAVE_RX) || defined(SSC_HAVE_TX)
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/* Check if we need the sample rate to set MCK/2 divider */
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@ -172,17 +236,17 @@
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* |<-----DATALEN * DATNB----->|
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*
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* TK/RK is assumed to be a negative pulse
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* DATALEN is configurable: CONFIG_SAMA5_SSC0_DATALEN
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* DATALEN is configurable: CONFIG_SAMA5_SSCx_DATALEN
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* FSLEN is configuration: CONFIG_SAMA5_SSCx_RX/TX_FSLEN
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* FSLEN and STTDLY are fixed at two clocks
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* DATNB is fixed a one work
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*
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* REVISIT: These will probably need to be configurable
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*/
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#define SSC_FSLEN (2) /* TF/RF plus width in clocks */
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#define SSC_STTDLY (2) /* Delay to data start in clocks (same as FSLEN) */
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#define SSC_DATNB (1) /* Number words per per frame */
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#define SCC_PERIOD (SSC_FSLEN + CONFIG_SAMA5_SSC0_DATALEN * SSC_DATNB)
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#define SSC_STTDLY(f) (f) /* Delay to data start in clocks (same as FSLEN) */
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#define SSC_DATNB (1) /* Number words per per frame */
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#define SCC_PERIOD(s,d) ((s) + (d) * SSC_DATNB)
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/* Clocking *****************************************************************/
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@ -341,14 +405,16 @@ struct sam_ssc_s
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sem_t exclsem; /* Assures mutually exclusive acess to SSC */
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uint8_t datalen; /* Data width (2-32) */
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uint8_t pid; /* Peripheral ID */
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uint16_t rxenab:1; /* True: RX transfers enabled */
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uint16_t txenab:1; /* True: TX transfers enabled */
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uint16_t loopback:1; /* True: Loopback mode */
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uint16_t sscno:1; /* SSC controller number (0 or 1) */
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uint16_t rxclk:2; /* Receiver clock source. See SSC_CLKSRC_* definitions */
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uint16_t txclk:2; /* Transmitter clock source. See SSC_CLKSRC_* definitions */
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uint16_t rxout:2; /* Receiver clock output. See SSC_CLKOUT_* definitions */
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uint16_t txout:2; /* Transmitter clock output. See SSC_CLKOUT_* definitions */
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uint8_t rxfslen; /* RX frame sync length */
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uint8_t txfslen; /* TX frame sync length */
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uint8_t rxenab:1; /* True: RX transfers enabled */
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uint8_t txenab:1; /* True: TX transfers enabled */
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uint8_t loopback:1; /* True: Loopback mode */
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uint8_t sscno:1; /* SSC controller number (0 or 1) */
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uint8_t rxclk:2; /* Receiver clock source. See SSC_CLKSRC_* definitions */
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uint8_t txclk:2; /* Transmitter clock source. See SSC_CLKSRC_* definitions */
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uint8_t rxout:2; /* Receiver clock output. See SSC_CLKOUT_* definitions */
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uint8_t txout:2; /* Transmitter clock output. See SSC_CLKOUT_* definitions */
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uint32_t frequency; /* SSC clock frequency */
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#ifdef SSC_HAVE_MCK2
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uint32_t samplerate; /* Data sample rate (determines only MCK/2 divider) */
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@ -1593,12 +1659,12 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
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DEBUGASSERT(bfcontainer && bfcontainer->apb);
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apb = bfcontainer->apb;
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DEBUGASSERT(((uintptr_t)apb->samp & 3) == 0);
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/* Get the transfer information, accounting for any data offset */
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samp = (uintptr_t)&apb->samp[apb->curbyte];
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nbytes = apb->nbytes - apb->curbyte;
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DEBUGASSERT((samp & 3) == 0 && (nbytes & 3) == 0); /* REVISIT */
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/* Physical address of the SSC THR register and of the buffer location
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* in RAM.
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@ -2235,11 +2301,16 @@ static int ssc_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
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int ret;
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#endif
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DEBUGASSERT(priv && apb && ((uintptr_t)apb->samp & 3) == 0);
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i2svdbg("apb=%p nbytes=%d arg=%p timeout=%d\n",
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apb, apb->nbytes, arg, timeout);
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/* Make sure that we have valid pointers that that the data has uint32_t
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* alignment.
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*/
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ssc_dump_buffer("Sending", apb->samp, apb->nbytes);
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DEBUGASSERT(priv && apb && ((uintptr_t)&apb->samp[apb->curbyte] & 3) == 0);
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i2svdbg("apb=%p nbytes=%d arg=%p timeout=%d\n",
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apb, apb->nbytes - apb->curbyte, arg, timeout);
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ssc_dump_buffer("Sending", &apb->samp[apb->curbyte],
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apb->nbytes - apb->curbyte);
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#ifdef SSC_HAVE_TX
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/* Allocate a buffer container in advance */
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@ -2318,9 +2389,26 @@ static int ssc_rx_configure(struct sam_ssc_s *priv)
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{
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#ifdef SSC_HAVE_RX
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uint32_t regval;
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uint32_t fslen;
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uint32_t sttdly;
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/* Get transfer waveform. First get the RX sync time (in RX clocks) */
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DEBUGASSERT(priv->rxfslen > 0);
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fslen = priv->rxfslen - 1;
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/* Start delay extends to sometime after RX synch */
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sttdly = SSC_STTDLY(fslen);
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if (sttdly > 0)
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{
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/* Decrement as need by the register file */
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sttdly--;
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}
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/* RCMR settings */
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/* Configure the receiver input clock */
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/* Configure the receiver input clock */
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regval = 0;
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switch (priv->rxclk)
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@ -2382,7 +2470,7 @@ static int ssc_rx_configure(struct sam_ssc_s *priv)
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*/
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regval |= (SSC_RCMR_CKI | SSC_RCMR_CKG_CONT | SSC_RCMR_START_EDGE |
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SSC_RCMR_STTDLY(SSC_STTDLY - 1) | SSC_RCMR_PERIOD(0));
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SSC_RCMR_STTDLY(sttdly) | SSC_RCMR_PERIOD(0));
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ssc_putreg(priv, SAM_SSC_RCMR_OFFSET, regval);
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/* RFMR settings. Some of these settings will need to be configurable as well.
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@ -2392,15 +2480,19 @@ static int ssc_rx_configure(struct sam_ssc_s *priv)
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* SSC_RFMR_LOOP Determined by configuration
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* SSC_RFMR_MSBF Most significant bit first
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* SSC_RFMR_DATNB(n) Data number 'n' per frame (hard-coded)
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* SSC_RFMR_FSLEN Set to LS 4 bits of (CONFIG_SSCx_RX_FSLEN-1)
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* SSC_RFMR_FSLEN(1) Pulse length = FSLEN + (FSLEN_EXT * 16) + 1 = 2 clocks
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* SSC_RFMR_FSOS_NONE RF pin is always in input
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* SSC_RFMR_FSEDGE_POS Positive frame sync edge detection
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* SSC_RFMR_FSLENEXT(0) FSLEN field extension = 0
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* SSC_RFMR_FSLENEXT I Set to MS 4 bits of (CONFIG_SSCx_TX_FSLEN-1)
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*/
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regval = (SSC_RFMR_DATLEN(CONFIG_SAMA5_SSC0_DATALEN - 1) | SSC_RFMR_MSBF |
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SSC_RFMR_DATNB(SSC_DATNB - 1) | SSC_RFMR_FSLEN(SSC_FSLEN - 1) |
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SSC_RFMR_FSOS_NONE | SSC_RFMR_FSLENEXT(0));
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SSC_RFMR_DATNB(SSC_DATNB - 1) | SSC_RFMR_FSOS_NONE);
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/* Set the RX frame synch */
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regval |= (SSC_RFMR_FSLEN(fslen & 0x0f) | SSC_RFMR_FSLENEXT((fslen >> 4) & 0x0f));
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/* Loopback mode? */
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@ -2427,6 +2519,28 @@ static int ssc_tx_configure(struct sam_ssc_s *priv)
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{
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#ifdef SSC_HAVE_TX
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uint32_t regval;
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uint32_t fslen;
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uint32_t period;
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uint32_t sttdly;
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/* Get transfer waveform. Get the TX synch in (in TX clocks) */
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fslen = priv->txfslen > 0 ? priv->txfslen - 1 : 0;
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/* Start delay extends to sometime after the TX synch */
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sttdly = SSC_STTDLY(fslen);
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/* From these, we can get the full period of the waveform */
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period = SCC_PERIOD(sttdly, priv->datalen);
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/* Decrement the start delay as required by the register field */
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if (sttdly > 0)
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{
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sttdly--;
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}
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/* TCMR settings */
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/* Configure the transmitter input clock */
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@ -2477,7 +2591,7 @@ static int ssc_tx_configure(struct sam_ssc_s *priv)
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}
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/* REVISIT: Some of these settings will need to be configurable as well.
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* Currently hardcoded to:
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* Currently hard-coded to:
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*
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* SSC_RCMR_CKI No transmitter clock inversion
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* SSC_RCMR_CKG_CONT No transmit clock gating
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@ -2498,28 +2612,26 @@ static int ssc_tx_configure(struct sam_ssc_s *priv)
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if (priv->txclk == SSC_CLKSRC_MCKDIV)
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{
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regval |= (SSC_TCMR_CKG_CONT | SSC_TCMR_START_CONT |
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SSC_TCMR_STTDLY(SSC_STTDLY - 1) |
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SSC_TCMR_PERIOD(SCC_PERIOD / 2 - 1));
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SSC_TCMR_STTDLY(sttdly) | SSC_TCMR_PERIOD(period / 2 - 1));
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}
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else
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{
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regval |= (SSC_TCMR_CKG_CONT | SSC_TCMR_START_EDGE |
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SSC_TCMR_STTDLY(SSC_STTDLY - 1) |
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SSC_TCMR_PERIOD(0));
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SSC_TCMR_STTDLY(sttdly) | SSC_TCMR_PERIOD(0));
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}
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ssc_putreg(priv, SAM_SSC_TCMR_OFFSET, regval);
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/* TFMR settings. Some of these settings will need to be configurable as well.
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* Currently hardcoded to:
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* Currently set to:
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*
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* SSC_TFMR_DATLEN(n) 'n' deterimined by configuration
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* SSC_TFMR_DATLEN(n) 'n' determined by configuration
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* SSC_TFMR_DATDEF Data default = 0
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* SSC_TFMR_MSBF Most significant bit first
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* SSC_TFMR_DATNB(n) Data number 'n' per frame (hard-coded)
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||||
* SSC_TFMR_FSDEN Frame sync data is enabled
|
||||
* SSC_TFMR_FSLEN(1) Pulse length = + (FSLEN_EXT * 16) + 1 = 2 TX clocks
|
||||
* SSC_TFMR_FSLENEXT(0) FSLEN field extension = 0
|
||||
* SSC_TFMR_FSDEN Enabled if CONFIG_SSCx_TX_FSLEN > 0
|
||||
* SSC_TFMR_FSLEN If enabled, set to LS 4 bits of (CONFIG_SSCx_TX_FSLEN-1)
|
||||
* SSC_TFMR_FSLENEXT If enabled, set to MS 4 bits of (CONFIG_SSCx_TX_FSLEN-1)
|
||||
*
|
||||
* If master (i.e., provides clocking):
|
||||
* SSC_TFMR_FSOS_NEGATIVE Negative pulse TF output
|
||||
@ -2530,18 +2642,27 @@ static int ssc_tx_configure(struct sam_ssc_s *priv)
|
||||
|
||||
if (priv->txclk == SSC_CLKSRC_MCKDIV)
|
||||
{
|
||||
regval = (SSC_TFMR_DATLEN(CONFIG_SAMA5_SSC0_DATALEN - 1) |
|
||||
regval = (SSC_TFMR_DATLEN(priv->datalen - 1) |
|
||||
SSC_TFMR_MSBF | SSC_TFMR_DATNB(SSC_DATNB - 1) |
|
||||
SSC_TFMR_FSLEN(SSC_FSLEN - 1) | SSC_TFMR_FSOS_NEGATIVE |
|
||||
SSC_TFMR_FSDEN | SSC_TFMR_FSLENEXT(0));
|
||||
SSC_TFMR_FSOS_NEGATIVE);
|
||||
}
|
||||
else
|
||||
{
|
||||
regval = (SSC_TFMR_DATLEN(CONFIG_SAMA5_SSC0_DATALEN - 1) |
|
||||
regval = (SSC_TFMR_DATLEN(priv->datalen - 1) |
|
||||
SSC_TFMR_MSBF | SSC_TFMR_DATNB(SSC_DATNB - 1) |
|
||||
SSC_TFMR_FSLEN(SSC_FSLEN - 1) | SSC_TFMR_FSOS_NONE |
|
||||
SSC_TFMR_FSDEN | SSC_TFMR_FSLENEXT(0));
|
||||
SSC_TFMR_FSOS_NONE);
|
||||
}
|
||||
dbg("##### TFMR BEFORE: datalen=%d regval=%08x txfslen=%02x\n", priv->datalen, regval, priv->txfslen);
|
||||
/* Is the TX frame synch enabled? */
|
||||
|
||||
if (priv->txfslen > 0)
|
||||
{
|
||||
/* Yes.. Set the FSDEN bit and the FSLEN field */
|
||||
|
||||
regval |= (SSC_TFMR_FSDEN | SSC_TFMR_FSLEN(fslen & 0x0f) |
|
||||
SSC_TFMR_FSLENEXT((fslen >> 4) & 0x0f));
|
||||
}
|
||||
dbg("##### TFMR AFTER: regval=%08x\n", regval);
|
||||
|
||||
ssc_putreg(priv, SAM_SSC_TFMR_OFFSET, regval);
|
||||
|
||||
@ -2917,6 +3038,10 @@ static void ssc0_configure(struct sam_ssc_s *priv)
|
||||
|
||||
#endif
|
||||
|
||||
/* Remember the configured RX frame synch length */
|
||||
|
||||
priv->rxfslen = CONFIG_SSC0_RX_FSLEN;
|
||||
|
||||
/* Remember the configured RX clock output */
|
||||
|
||||
#if defined(CONFIG_SAMA5_SSC0_RX_RKOUTPUT_CONT)
|
||||
@ -2983,6 +3108,10 @@ static void ssc0_configure(struct sam_ssc_s *priv)
|
||||
|
||||
#endif /* CONFIG_SAMA5_SSC0_TX */
|
||||
|
||||
/* Remember the configured TX frame synch length */
|
||||
|
||||
priv->txfslen = CONFIG_SSC0_TX_FSLEN;
|
||||
|
||||
/* Set/clear loopback mode */
|
||||
|
||||
#if defined(CONFIG_SAMA5_SSC0_RX) && defined(CONFIG_SAMA5_SSC0_TX) && \
|
||||
@ -3045,6 +3174,10 @@ static void ssc1_configure(struct sam_ssc_s *priv)
|
||||
|
||||
#endif
|
||||
|
||||
/* Remember the configured RX frame synch length */
|
||||
|
||||
priv->rxfslen = CONFIG_SSC1_RX_FSLEN;
|
||||
|
||||
/* Remember the configured RX clock output */
|
||||
|
||||
#if defined(CONFIG_SAMA5_SSC1_RX_RKOUTPUT_CONT)
|
||||
@ -3111,6 +3244,10 @@ static void ssc1_configure(struct sam_ssc_s *priv)
|
||||
|
||||
#endif /* CONFIG_SAMA5_SSC1_TX */
|
||||
|
||||
/* Remember the configured TX frame synch length */
|
||||
|
||||
priv->txfslen = CONFIG_SSC1_TX_FSLEN;
|
||||
|
||||
/* Set/clear loopback mode */
|
||||
|
||||
#if defined(CONFIG_SAMA5_SSC1_RX) && defined(CONFIG_SAMA5_SSC1_TX) && \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user