Add RTC and QEI bit definitions
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2721 42af7a65-404d-4744-a932-0658087f49c3
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@ -114,97 +114,66 @@
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#define LPC17_QEI_SET (LPC17_QEI_BASE+LPC17_QEI_SET_OFFSET)
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/* Register bit definitions *********************************************************/
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/* Control registers */
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/* The following registers hold 32-bit integer values and have no bit fields defined
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* in this section:
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*
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* Position register (POS)
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* Maximum position register (MAXPOS)
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* Position compare register 0 (CMPOS0)
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* Position compare register 1 (CMPOS)
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* Position compare register 2 (CMPOS2)
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* Index count register (INXCNT)
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* Index compare register (INXCMP)
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* Velocity timer reload register (LOAD)
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* Velocity timer register (TIME)
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* Velocity counter register (VEL)
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* Velocity capture register (CAP)
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* Velocity compare register (VELCOMP)
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* Digital filter register (FILTER)
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*/
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/* Control registers */
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/* Control register */
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#define QEI_CON_
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#define QEI_CON_RESP (1 << 0) /* Bit 0: Reset position counter */
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#define QEI_CON_RESPI (1 << 1) /* Bit 1: Reset position counter on index */
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#define QEI_CON_RESV (1 << 2) /* Bit 2: Reset velocity */
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#define QEI_CON_RESI (1 << 3) /* Bit 3: Reset index counter */
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/* Bits 4-31: reserved */
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/* Encoder status register */
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#define QEI_STAT_
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#define QEI_STAT_DIR (1 << 0) /* Bit 0: Direction bit */
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/* Bits 1-31: reserved */
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/* Configuration register */
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#define QEI_CONF_
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/* Position, index, and timer registers */
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/* Position register */
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#define QEI_POS_
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/* Maximum position register */
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#define QEI_MAXPOS_
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/* Position compare register */
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#define QEI_CMPOS0_
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/* Position compare register */
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#define QEI_CMPOS1_
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/* Position compare register */
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#define QEI_CMPOS2_
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/* Index count register */
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#define QEI_INXCNT_
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/* Index compare register */
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#define QEI_INXCMP_
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/* Velocity timer reload register */
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#define QEI_LOAD_
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/* Velocity timer register */
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#define QEI_TIME_
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/* Velocity counter register */
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#define QEI_VEL_
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/* Velocity capture register */
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#define QEI_CAP_
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/* Velocity compare register */
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#define QEI_VELCOMP_
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/* Digital filter register */
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#define QEI_FILTER_
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#define QEI_CONF_DIRINV (1 << 0) /* Bit 0: Direction invert */
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#define QEI_CONF_SIGMODE (1 << 1) /* Bit 1: Signal Mode */
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#define QEI_CONF_CAPMODE (1 << 2) /* Bit 2: Capture Mode */
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#define QEI_CONF_INVINX (1 << 3) /* Bit 3: Invert Index */
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/* Bits 4-31: reserved */
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/* Position, index, and timer registers (all 32-bit integer values with not bit fields */
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/* Interrupt registers */
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/* Interrupt enable clear register */
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/* Interrupt enable clear register (IEC), Interrupt enable set register (IES),
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* Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt
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* status clear register (CLR), and Interrupt status set register (SET) common
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* bit definitions.
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*/
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#define QEI_IEC_
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/* Interrupt enable set register */
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#define QEI_IES_
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/* Interrupt status register */
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#define QEI_INTSTAT_
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/* Interrupt enable register */
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#define QEI_IE_
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/* Interrupt status clear register */
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#define QEI_CLR_
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/* Interrupt status set register */
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#define QEI_SET_
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#define QEI_INT_INX (1 << 0) /* Bit 0: Index pulse detected */
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#define QEI_INT_TIM (1 << 1) /* Bit 1: Velocity timer overflow occurred */
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#define QEI_INT_VELC (1 << 2) /* Bit 2: Captured velocity less than compare velocity */
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#define QEI_INT_DIR (1 << 3) /* Bit 3: Change of direction detected */
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#define QEI_INT_ERR (1 << 4) /* Bit 4: Encoder phase error detected */
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#define QEI_INT_ENCLK (1 << 5) /* Bit 5: Eencoder clock pulse detected */
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#define QEI_INT_POS0 (1 << 6) /* Bit 6: Position 0 compare equal to current position */
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#define QEI_INT_POS1 (1 << 7) /* Bit 7: Position 1 compare equal to current position */
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#define QEI_INT_POS2 (1 << 8) /* Bit 8: Position 2 compare equal to current position */
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#define QEI_INT_REV (1 << 9) /* Bit 9: Index compare value equal to current index count */
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#define QEI_INT_POS0REV (1 << 10) /* Bit 10: Combined position 0 and revolution count interrupt */
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#define QEI_INT_POS1REV (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */
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#define QEI_INT_POS2REV (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */
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/* Bits 13-31: reserved */
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/************************************************************************************
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* Public Types
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@ -144,134 +144,116 @@
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#define LPC17_RTC_ALYEAR (LPC17_RTC_BASE+LPC17_RTC_ALYEAR_OFFSET)
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/* Register bit definitions *********************************************************/
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/* The following registers hold 32-bit values and have no bit fields to be defined:
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*
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* General Purpose Register 0
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* General Purpose Register 1
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* General Purpose Register 2
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* General Purpose Register 3
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* General Purpose Register 4
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*/
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/* Miscellaneous registers */
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/* Interrupt Location Register */
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#define RTC_ILR_
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#define RTC_ILR_RTCCIF (1 << 0) /* Bit 0: Counter Increment Interrupt */
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#define RTC_ILR_RTCALF (1 << 1) /* Bit 1: Alarm interrupt */
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/* Bits 2-31: Reserved */
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/* Clock Control Register */
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#define RTC_CCR_
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#define RTC_CCR_CLKEN (1 << 0) /* Bit 0: Clock Enable */
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#define RTC_CCR_CTCRST (1 << 1) /* Bit 1: CTC Reset */
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/* Bits 2-3: Internal test mode controls */
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#define RTC_CCR_CCALEN (1 << 4) /* Bit 4: Calibration counter enable */
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/* Bits 5-31: Reserved */
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/* Counter Increment Interrupt Register */
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#define RTC_CIIR_
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#define RTC_CIIR_IMSEC (1 << 0) /* Bit 0: Second interrupt */
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#define RTC_CIIR_IMMIN (1 << 1) /* Bit 1: Minute interrupt */
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#define RTC_CIIR_IMHOUR (1 << 2) /* Bit 2: Hour interrupt */
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#define RTC_CIIR_IMDOM (1 << 3) /* Bit 3: Day of Month value interrupt */
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#define RTC_CIIR_IMDOW (1 << 4) /* Bit 4: Day of Week value interrupt */
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#define RTC_CIIR_IMDOY (1 << 5) /* Bit 5: Day of Year interrupt */
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#define RTC_CIIR_IMMON (1 << 6) /* Bit 6: Month interrupt */
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#define RTC_CIIR_IMYEAR (1 << 7) /* Bit 7: Yearinterrupt */
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/* Bits 8-31: Reserved */
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/* Alarm Mask Register */
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#define RTC_AMR_
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#define RTC_AMR_SEC (1 << 0) /* Bit 0: Second not compared for alarm */
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#define RTC_AMR_MIN (1 << 1) /* Bit 1: Minutes not compared for alarm */
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#define RTC_AMR_HOUR (1 << 2) /* Bit 2: Hour not compared for alarm */
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#define RTC_AMR_DOM (1 << 3) /* Bit 3: Day of Monthnot compared for alarm */
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#define RTC_AMR_DOW (1 << 4) /* Bit 4: Day of Week not compared for alarm */
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#define RTC_AMR_DOY (1 << 5) /* Bit 5: Day of Year not compared for alarm */
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#define RTC_AMR_MON (1 << 6) /* Bit 6: Month not compared for alarm */
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#define RTC_AMR_YEAR (1 << 7) /* Bit 7: Year not compared for alarm */
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/* Bits 8-31: Reserved */
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/* RTC Auxiliary Enable register */
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#define RTC_AUXEN_
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/* Bits 0-3: Reserved */
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#define RTC_AUXEN_RTCOSCF (1 << 4) /* Bit 4: RTC Oscillator Fail detect flag */
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/* Bits 5-31: Reserved */
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/* RTC Auxiliary control register */
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#define RTC_AUX_
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/* Bits 0-3: Reserved */
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#define RTC_AUX_OSCFEN (1 << 4) /* Bit 4: Oscillator Fail Detect interrupt enable */
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/* Bits 5-31: Reserved */
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/* Consolidated time registers */
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/* Consolidated Time Register 0 */
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#define RTC_CTIME0_
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#define RTC_CTIME0_SEC_SHIFT (0) /* Bits 0-5: Seconds */
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#define RTC_CTIME0_SEC_MASK (63 << RTC_CTIME0_SEC_SHIFT)
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/* Bits 6-7: Reserved */
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#define RTC_CTIME0_MIN_SHIFT (8) /* Bits 8-13: Minutes */
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#define RTC_CTIME0_MIN_MASK (63 << RTC_CTIME0_MIN_SHIFT)
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/* Bits 14-15: Reserved */
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#define RTC_CTIME0_HOURS_SHIFT (16) /* Bits 16-20: Hours */
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#define RTC_CTIME0_HOURS_MASK (31 << RTC_CTIME0_HOURS_SHIFT)
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/* Bits 21-23: Reserved */
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#define RTC_CTIME0_DOW_SHIFT (24) /* Bits 24-26: Day of Week */
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#define RTC_CTIME0_DOW_MASK (7 << RTC_CTIME0_DOW_SHIFT)
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/* Bits 27-31: Reserved */
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/* Consolidated Time Register 1 */
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#define RTC_CTIME1_
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/* Consolidated Time Register 2 */
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#define RTC_CTIME2_
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#define RTC_CTIME1_DOM_SHIFT (0) /* Bits 0-4: Day of Month */
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#define RTC_CTIME1_DOM_MASK (31 << RTC_CTIME1_DOM_SHIFT)
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/* Bits 5-7: Reserved */
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#define RTC_CTIME1_MON_SHIFT (8) /* Bits 8-11: Month */
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#define RTC_CTIME1_MON_MASK (15 << RTC_CTIME1_MON_SHIFT)
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/* Bits 12-15: Reserved */
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#define RTC_CTIME1_YEAR_SHIFT (16) /* Bits 16-27: Year */
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#define RTC_CTIME1_YEAR_MASK (0x0fff << RTC_CTIME1_YEAR_SHIFT)
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/* Bits 28-31: Reserved */
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/* Consolidated Time Register 2 (Shouldn't DOY width be 9 bits?) */
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#define RTC_CTIME2_DOY_SHIFT (0) /* Bits 0-11: Day of Year */
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#define RTC_CTIME2_DOY_MASK (0x0fff << RTC_CTIME2_DOY_SHIFT)
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/* Bits 12-31: Reserved */
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/* Time counter registers */
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/* Seconds Counter */
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#define RTC_SEC_
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/* Minutes Register */
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#define RTC_MIN_
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/* Hours Register */
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#define RTC_HOUR_
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/* Day of Month Register */
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#define RTC_DOM_
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/* Day of Week Register */
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#define RTC_DOW_
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/* Day of Year Register */
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#define RTC_DOY_
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/* Months Register */
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#define RTC_MONTH_
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/* Years Register */
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#define RTC_YEAR_
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#define RTC_SEC_MASK (0x003f)
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#define RTC_MIN_MASK (0x003f)
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#define RTC_HOUR_MASK (0x001f)
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#define RTC_DOM_MASK (0x001f)
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#define RTC_DOW_MASK (0x0007)
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#define RTC_DOY_MASK (0x01ff)
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#define RTC_MONTH_MASK (0x000f)
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#define RTC_YEAR_MASK (0x0fff)
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/* Calibration Value Register */
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#define RTC_CALIB_
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/* General purpose registers */
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/* General Purpose Register 0 */
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#define RTC_GPREG0_
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/* General Purpose Register 1 */
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#define RTC_GPREG1_
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/* General Purpose Register 2 */
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#define RTC_GPREG2_
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/* General Purpose Register 3 */
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#define RTC_GPREG3_
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/* General Purpose Register 4 */
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#define RTC_GPREG4_
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#define RTC_CALIB_CALVAL_SHIFT (0) /* Bits 0-16: calibration counter counts to this value */
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#define RTC_CALIB_CALVAL_MASK (0xffff << RTC_CALIB_CALVAL_SHIFT)
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#define RTC_CALIB_CALDIR (1 << 17) /* Bit 17: Calibration direction */
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/* Bits 12-31: Reserved */
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/* Alarm register group */
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/* Alarm value for Seconds */
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#define RTC_ALSEC_
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/* Alarm value for Minutes */
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#define RTC_ALMIN_
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/* Alarm value for Hours */
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#define RTC_ALHOUR_
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/* Alarm value for Day of Month */
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#define RTC_ALDOM_
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/* Alarm value for Day of Week */
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#define RTC_ALDOW_
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/* Alarm value for Day of Year */
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#define RTC_ALDOY_
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/* Alarm value for Months */
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#define RTC_ALMON_
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/* Alarm value for Year */
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#define RTC_ALYEAR_
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#define RTC_ALSEC_MASK (0x003f)
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#define RTC_ALMIN_MASK (0x003f)
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#define RTC_ALHOUR_MASK (0x001f)
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#define RTC_ALDOM_MASK (0x001f)
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#define RTC_ALDOW_MASK (0x0007)
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#define RTC_ALDOY_MASK (0x01ff)
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#define RTC_ALMON_MASK (0x000f)
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#define RTC_ALYEAR_MASK (0x0fff)
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/************************************************************************************
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* Public Types
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