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arch/arm/src/lpc54xx: Add fragmenenty skeleon of SPI driver just as a starting point.

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This commit is contained in:
Gregory Nutt 2017-12-11 14:50:54 -06:00
parent 11ca2c3847
commit d74d9be429
3 changed files with 1130 additions and 49 deletions
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122
arch/arm/src/lpc54xx/lpc54_i2c_master.c
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@ -66,6 +66,8 @@
#include "lpc54_config.h"
#include "lpc54_i2c_master.h"
#include <arch/board/board.h>
#ifdef HAVE_SPI_MASTER_DEVICE
/****************************************************************************
@ -79,9 +81,9 @@
struct lpc54_i2cdev_s
{
struct i2c_master_s dev; /* Generic I2C device */
unsigned int base; /* Base address of registers */
uint16_t irqid; /* IRQ for this device */
uint32_t inclck; /* I2C input clock frequency */
uintptr_t base; /* Base address of Flexcomm registers */
uint16_t irq; /* Flexcomm IRQ number */
uint32_t fclock; /* Flexcomm function clock frequency */
sem_t exclsem; /* Only one thread can access at a time */
sem_t waitsem; /* Supports wait for state machine completion */
@ -96,13 +98,6 @@ struct lpc54_i2cdev_s
uint16_t rdcnt; /* number of bytes read from rx fifo */
};
#ifdef CONFIG_LPC54_I2C0_MASTER
static struct lpc54_i2cdev_s g_i2c0_dev;
#endif
#ifdef CONFIG_LPC54_I2C1_MASTER
static struct lpc54_i2cdev_s g_i2c1_dev;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -131,6 +126,37 @@ struct i2c_ops_s lpc54_i2c_ops =
#endif
};
#ifdef CONFIG_LPC54_I2C0_MASTER
static struct lpc54_i2cdev_s g_i2c0_dev;
#endif
#ifdef CONFIG_LPC54_I2C1_MASTER
static struct lpc54_i2cdev_s g_i2c1_dev;
#endif
#ifdef CONFIG_LPC54_I2C2_MASTER
static struct lpc54_i2cdev_s g_i2c2_dev;
#endif
#ifdef CONFIG_LPC54_I2C3_MASTER
static struct lpc54_i2cdev_s g_i2c3_dev;
#endif
#ifdef CONFIG_LPC54_I2C4_MASTER
static struct lpc54_i2cdev_s g_i2c4_dev;
#endif
#ifdef CONFIG_LPC54_I2C5_MASTER
static struct lpc54_i2cdev_s g_i2c5_dev;
#endif
#ifdef CONFIG_LPC54_I2C6_MASTER
static struct lpc54_i2cdev_s g_i2c6_dev;
#endif
#ifdef CONFIG_LPC54_I2C7_MASTER
static struct lpc54_i2cdev_s g_i2c7_dev;
#endif
#ifdef CONFIG_LPC54_I2C8_MASTER
static struct lpc54_i2cdev_s g_i2c8_dev;
#endif
#ifdef CONFIG_LPC54_I2C9_MASTER
static struct lpc54_i2cdev_s g_i2c9_dev;
#endif
/****************************************************************************
* Name: lpc54_i2c_setfrequency
*
@ -149,7 +175,7 @@ static void lpc54_i2c_setfrequency(struct lpc54_i2cdev_s *priv,
/* Yes.. instantiate the new I2C frequency */
#warning Missing logic
priv->frequency = frequency;
priv->frequency = frequency;
}
}
@ -364,8 +390,8 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
priv = &g_i2c0_dev;
priv->base = LPC54_FLEXCOMM0_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM0;
priv->inclck = BOARD_FLEXCOMM0_FCLK;
priv->irq = LPC54_IRQ_FLEXCOMM0;
priv->fclock = BOARD_FLEXCOMM0_FCLK;
/* Configure I2C pins (defined in board.h) */
@ -374,7 +400,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
/* Set up the FLEXCOMM0 function clock */
putreg32(BOARD_FLEXCOMM2_CLKSEL, LPC54_SYSCON_FCLKSEL2);
putreg32(BOARD_FLEXCOMM0_CLKSEL, LPC54_SYSCON_FCLKSEL0);
/* Set the default I2C frequency */
@ -400,8 +426,8 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
priv = &g_i2c1_dev;
priv->base = LPC54_FLEXCOMM1_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM1;
priv->inclck = BOARD_FLEXCOMM1_FCLK;
priv->irq = LPC54_IRQ_FLEXCOMM1;
priv->fclock = BOARD_FLEXCOMM1_FCLK;
/* Configure I2C pins (defined in board.h) */
@ -410,7 +436,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
/* Set up the FLEXCOMM1 function clock */
putreg32(BOARD_FLEXCOMM2_CLKSEL, LPC54_SYSCON_FCLKSEL2);
putreg32(BOARD_FLEXCOMM1_CLKSEL, LPC54_SYSCON_FCLKSEL1);
/* Set the default I2C frequency */
@ -436,8 +462,8 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
priv = &g_i2c2_dev;
priv->base = LPC54_FLEXCOMM2_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM2;
priv->inclck = BOARD_FLEXCOMM2_FCLK;
priv->irq = LPC54_IRQ_FLEXCOMM2;
priv->fclock = BOARD_FLEXCOMM2_FCLK;
/* Configure I2C pins (defined in board.h) */
@ -472,8 +498,8 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
priv = &g_i2c3_dev;
priv->base = LPC54_FLEXCOMM3_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM3;
priv->inclck = BOARD_FLEXCOMM3_FCLK;
priv->irq = LPC54_IRQ_FLEXCOMM3;
priv->fclock = BOARD_FLEXCOMM3_FCLK;
/* Configure I2C pins (defined in board.h) */
@ -482,7 +508,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
/* Set up the FLEXCOMM3 function clock */
putreg32(BOARD_FLEXCOMM2_CLKSEL, LPC54_SYSCON_FCLKSEL2);
putreg32(BOARD_FLEXCOMM3_CLKSEL, LPC54_SYSCON_FCLKSEL3);
/* Set the default I2C frequency */
@ -508,8 +534,8 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
priv = &g_i2c4_dev;
priv->base = LPC54_FLEXCOMM4_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM4;
priv->inclck = BOARD_FLEXCOMM4_FCLK;
priv->irq = LPC54_IRQ_FLEXCOMM4;
priv->fclock = BOARD_FLEXCOMM4_FCLK;
/* Configure I2C pins (defined in board.h) */
@ -518,7 +544,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
/* Set up the FLEXCOMM4 function clock */
putreg32(BOARD_FLEXCOMM2_CLKSEL, LPC54_SYSCON_FCLKSEL2);
putreg32(BOARD_FLEXCOMM4_CLKSEL, LPC54_SYSCON_FCLKSEL4);
/* Set the default I2C frequency */
@ -544,8 +570,8 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
priv = &g_i2c5_dev;
priv->base = LPC54_FLEXCOMM5_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM5;
priv->inclck = BOARD_FLEXCOMM5_FCLK;
priv->irq = LPC54_IRQ_FLEXCOMM5;
priv->fclock = BOARD_FLEXCOMM5_FCLK;
/* Configure I2C pins (defined in board.h) */
@ -554,7 +580,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
/* Set up the FLEXCOMM5 function clock */
putreg32(BOARD_FLEXCOMM2_CLKSEL, LPC54_SYSCON_FCLKSEL2);
putreg32(BOARD_FLEXCOMM5_CLKSEL, LPC54_SYSCON_FCLKSEL5);
/* Set the default I2C frequency */
@ -580,8 +606,8 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
priv = &g_i2c6_dev;
priv->base = LPC54_FLEXCOMM6_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM6;
priv->inclck = BOARD_FLEXCOMM6_FCLK;
priv->irq = LPC54_IRQ_FLEXCOMM6;
priv->fclock = BOARD_FLEXCOMM6_FCLK;
/* Configure I2C pins (defined in board.h) */
@ -590,7 +616,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
/* Set up the FLEXCOMM6 function clock */
putreg32(BOARD_FLEXCOMM2_CLKSEL, LPC54_SYSCON_FCLKSEL2);
putreg32(BOARD_FLEXCOMM6_CLKSEL, LPC54_SYSCON_FCLKSEL6);
/* Set the default I2C frequency */
@ -616,8 +642,8 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
priv = &g_i2c7_dev;
priv->base = LPC54_FLEXCOMM7_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM7;
priv->inclck = BOARD_FLEXCOMM7_FCLK;
priv->irq = LPC54_IRQ_FLEXCOMM7;
priv->fclock = BOARD_FLEXCOMM7_FCLK;
/* Configure I2C pins (defined in board.h) */
@ -626,7 +652,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
/* Set up the FLEXCOMM7 function clock */
putreg32(BOARD_FLEXCOMM2_CLKSEL, LPC54_SYSCON_FCLKSEL2);
putreg32(BOARD_FLEXCOMM7_CLKSEL, LPC54_SYSCON_FCLKSEL7);
/* Set the default I2C frequency */
@ -652,8 +678,8 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
priv = &g_i2c8_dev;
priv->base = LPC54_FLEXCOMM8_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM8;
priv->inclck = BOARD_FLEXCOMM8_FCLK;
priv->irq = LPC54_IRQ_FLEXCOMM8;
priv->fclock = BOARD_FLEXCOMM8_FCLK;
/* Configure I2C pins (defined in board.h) */
@ -662,7 +688,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
/* Set up the FLEXCOMM8 function clock */
putreg32(BOARD_FLEXCOMM2_CLKSEL, LPC54_SYSCON_FCLKSEL2);
putreg32(BOARD_FLEXCOMM8_CLKSEL, LPC54_SYSCON_FCLKSEL8);
/* Set the default I2C frequency */
@ -688,8 +714,8 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
priv = &g_i2c9_dev;
priv->base = LPC54_FLEXCOMM9_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM9;
priv->inclck = BOARD_FLEXCOMM9_FCLK;
priv->irq = LPC54_IRQ_FLEXCOMM9;
priv->fclock = BOARD_FLEXCOMM9_FCLK;
/* Configure I2C pins (defined in board.h) */
@ -698,7 +724,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
/* Set up the FLEXCOMM9 function clock */
putreg32(BOARD_FLEXCOMM2_CLKSEL, LPC54_SYSCON_FCLKSEL2);
putreg32(BOARD_FLEXCOMM9_CLKSEL, LPC54_SYSCON_FCLKSEL9);
/* Set the default I2C frequency */
@ -737,11 +763,11 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
/* Attach Interrupt Handler */
irq_attach(priv->irqid, lpc54_i2c_interrupt, priv);
irq_attach(priv->irq, lpc54_i2c_interrupt, priv);
/* Enable Interrupt Handler */
up_enable_irq(priv->irqid);
up_enable_irq(priv->irq);
/* Install our operations */
@ -764,15 +790,13 @@ int lpc54_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
/* Disable I2C interrupts */
#warning Missing logic
/* Disable the I2C perifpheral */
/* Disable the I2C peripheral */
#warning Missing logic
putreg32(0, base + LPC54_USART_CFG_OFFSET);
#warning Missing logic
/* Disable the Flexcomm interface at the NVIC and detach the interrupt. */
/* Disables the Flexcomm interface at the NVIC and detach the interrupt. */
up_disable_irq(priv->irqid);
irq_detach(priv->irqid);
up_disable_irq(priv->irq);
irq_detach(priv->irq);
return OK;
}

877
arch/arm/src/lpc54xx/lpc54_spi_master.c Normal file
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@ -0,0 +1,877 @@
/****************************************************************************
* arch/arm/src/lpc54xx/lpc54_spi.c
*
* Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <semaphore.h>
#include <errno.h>
#include <debug.h>
#include <arch/board/board.h>
#include <nuttx/arch.h>
#include <nuttx/spi/spi.h>
#include "up_internal.h"
#include "up_arch.h"
#include "chip/lpc54_pinmux.h"
#include "chip/lpc54_syscon.h"
#include "chip/lpc54_flexcomm.h"
#include "chip/lpc54_spi.h"
#include "lpc54_config.h"
#include "lpc54_spi_master.h"
#ifdef HAVE_SPI_MASTER_DEVICE
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure descibes the state of the SSP driver */
struct lpc54_spidev_s
{
struct spi_dev_s dev; /* Externally visible part of the SPI interface */
uintptr_t base; /* Base address of Flexcomm registers */
sem_t exclsem; /* Held while chip is selected for mutual exclusion */
uint32_t fclock; /* Flexcomm function clock frequency */
uint32_t frequency; /* Requested clock frequency */
uint32_t actual; /* Actual clock frequency */
uint16_t irq; /* Flexcomm IRQ number */
uint8_t nbits; /* Width of word in bits (8 to 16) */
uint8_t mode; /* Mode 0,1,2,3 */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* SPI methods */
static int lpc54_spi_lock(FAR struct spi_dev_s *dev, bool lock);
static void lpc54_spi_select(FAR struct spi_dev_s *dev, uint32_t devid,
bool selected);
static uint32_t lpc54_spi_setfrequency(FAR struct spi_dev_s *dev,
uint32_t frequency);
static void lpc54_spi_setmode(FAR struct spi_dev_s *dev,
enum spi_mode_e mode);
static void lpc54_spi_setbits(FAR struct spi_dev_s *dev, int nbits);
static uint16_t lpc54_spi_send(FAR struct spi_dev_s *dev, uint16_t ch);
static void lpc54_spi_sndblock(FAR struct spi_dev_s *dev,
FAR const void *buffer, size_t nwords);
static void lpc54_spi_recvblock(FAR struct spi_dev_s *dev,
FAR void *buffer, size_t nwords);
/****************************************************************************
* Private Data
****************************************************************************/
static const struct spi_ops_s g_spi_ops =
{
.lock = lpc54_spi_lock,
.select = lpc54_spiselect,
.setfrequency = lpc54_spi_setfrequency,
.setmode = lpc54_spi_setmode,
.setbits = lpc54_spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = 0, /* Not supported */
#endif
.status = lpc54_spistatus,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = lpc54_spicmddata,
#endif
.send = lpc54_spi_send,
.sndblock = lpc54_spi_sndblock,
.recvblock = lpc54_spi_recvblock,
#ifdef CONFIG_SPI_CALLBACK
.registercallback = lpc54_spiregister, /* Provided externally */
#else
.registercallback = 0, /* Not implemented */
#endif
};
#ifdef CONFIG_LPC54_I2C0_MASTER
static struct lpc54_spidev_s g_spi0_dev;
#endif
#ifdef CONFIG_LPC54_I2C1_MASTER
static struct lpc54_spidev_s g_spi1_dev;
#endif
#ifdef CONFIG_LPC54_I2C2_MASTER
static struct lpc54_spidev_s g_spi2_dev;
#endif
#ifdef CONFIG_LPC54_I2C3_MASTER
static struct lpc54_spidev_s g_spi3_dev;
#endif
#ifdef CONFIG_LPC54_I2C4_MASTER
static struct lpc54_spidev_s g_spi4_dev;
#endif
#ifdef CONFIG_LPC54_I2C5_MASTER
static struct lpc54_spidev_s g_spi5_dev;
#endif
#ifdef CONFIG_LPC54_I2C6_MASTER
static struct lpc54_spidev_s g_spi6_dev;
#endif
#ifdef CONFIG_LPC54_I2C7_MASTER
static struct lpc54_spidev_s g_spi7_dev;
#endif
#ifdef CONFIG_LPC54_I2C8_MASTER
static struct lpc54_spidev_s g_spi8_dev;
#endif
#ifdef CONFIG_LPC54_I2C9_MASTER
static struct lpc54_spidev_s g_spi9_dev;
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: lpc54_spi_lock
*
* Description:
* On SPI busses where there are multiple devices, it will be necessary to
* lock SPI to have exclusive access to the busses for a sequence of
* transfers. The bus should be locked before the chip is selected. After
* locking the SPI bus, the caller should then also call the setfrequency,
* setbits, and setmode methods to make sure that the SPI is properly
* configured for the device. If the SPI buss is being shared, then it
* may have been left in an incompatible state.
*
* Input Parameters:
* dev - Device-specific state data
* lock - true: Lock spi bus, false: unlock SPI bus
*
* Returned Value:
* None
*
****************************************************************************/
static int lpc54_spi_lock(FAR struct spi_dev_s *dev, bool lock)
{
FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev;
int ret;
if (lock)
{
/* Take the semaphore (perhaps waiting) */
do
{
ret = nxsem_wait(&priv->exclsem);
/* The only case that an error should occur here is if the wait
* was awakened by a signal.
*/
DEBUGASSERT(ret == OK || ret == -EINTR);
}
while (ret == -EINTR);
}
else
{
(void)nxsem_post(&priv->exclsem);
ret = OK;
}
return ret;
}
/****************************************************************************
* Name: lpc54_spi_setfrequency
*
* Description:
* Set the SPI frequency.
*
* Input Parameters:
* dev - Device-specific state data
* frequency - The SPI frequency requested
*
* Returned Value:
* Returns the actual frequency selected
*
****************************************************************************/
static uint32_t lpc54_spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
{
FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev;
uint32_t actual;
/* Check if the requested frequence is the same as the frequency selection */
DEBUGASSERT(priv && frequency <= priv->fclock / 2);
if (priv->frequency == frequency)
{
/* We are already at this frequency. Return the actual. */
return priv->actual;
}
/* Set the new SPI frequency */
#warning Missing logic
/* Save the frequency setting */
priv->frequency = frequency;
priv->actual = actual;
spiinfo("Frequency %d->%d\n", frequency, actual);
return actual;
}
/****************************************************************************
* Name: lpc54_spi_setmode
*
* Description:
* Set the SPI mode. Optional. See enum spi_mode_e for mode definitions
*
* Input Parameters:
* dev - Device-specific state data
* mode - The SPI mode requested
*
* Returned Value:
* none
*
****************************************************************************/
static void lpc54_spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
{
FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev;
uint32_t regval;
/* Has the mode changed? */
if (mode != priv->mode)
{
/* Yes... Set the new mode */
#warning Missing logic
switch (mode)
{
case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
#warning Missing logic
break;
case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
#warning Missing logic
break;
case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
#warning Missing logic
break;
case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
#warning Missing logic
break;
default:
DEBUGPANIC();
return;
}
#warning Missing logic
/* Save the mode so that subsequent re-configuratins will be faster */
priv->mode = mode;
}
}
/****************************************************************************
* Name: lpc54_spi_setbits
*
* Description:
* Set the number if bits per word.
*
* Input Parameters:
* dev - Device-specific state data
* nbits - The number of bits requests
*
* Returned Value:
* none
*
****************************************************************************/
static void lpc54_spi_setbits(FAR struct spi_dev_s *dev, int nbits)
{
FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev;
uint32_t regval;
/* Has the number of bits changed? */
DEBUGASSERT(priv && nbits > 7 && nbits < 17);
if (nbits != priv->nbits)
{
/* Yes... Set the number word width */
#warning Missing logic
/* Save the selection so the subsequence re-configurations will be faster */
priv->nbits = nbits;
}
}
/****************************************************************************
* Name: lpc54_spi_send
*
* Description:
* Exchange one word on SPI
*
* Input Parameters:
* dev - Device-specific state data
* wd - The word to send. the size of the data is determined by the
* number of bits selected for the SPI interface.
*
* Returned Value:
* response
*
****************************************************************************/
static uint16_t lpc54_spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
{
uint16_t ret;
/* Write the data to transmitted to the SPI Data Register */
#warning Missing logic
/* Read the SPI Status Register again to clear the status bit */
#warning Missing logic
return ret;
}
/****************************************************************************
* Name: lpc54_spi_sndblock
*
* Description:
* Send a block of data on SPI
*
* Input Parameters:
* dev - Device-specific state data
* buffer - A pointer to the buffer of data to be sent
* nwords - the length of data to send from the buffer in number of words.
* The wordsize is determined by the number of bits-per-word
* selected for the SPI interface. If nbits <= 8, the data is
* packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
*
* Returned Value:
* None
*
****************************************************************************/
static void lpc54_spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
{
FAR uint8_t *ptr = (FAR uint8_t *)buffer;
uint8_t data;
spiinfo("nwords: %d\n", nwords);
while (nwords > 0)
{
/* Write the data to transmitted to the SPI Data Register */
#warning Missing logic
/* Read the SPI Status Register again to clear the status bit */
#warning Missing logic
nwords--;
}
}
/****************************************************************************
* Name: lpc54_spi_recvblock
*
* Description:
* Revice a block of data from SPI
*
* Input Parameters:
* dev - Device-specific state data
* buffer - A pointer to the buffer in which to recieve data
* nwords - the length of data that can be received in the buffer in number
* of words. The wordsize is determined by the number of bits-per-word
* selected for the SPI interface. If nbits <= 8, the data is
* packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
*
* Returned Value:
* None
*
****************************************************************************/
static void lpc54_spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
{
FAR uint8_t *ptr = (FAR uint8_t *)buffer;
spiinfo("nwords: %d\n", nwords);
while (nwords)
{
/* Write some dummy data to the SPI Data Register in order to clock the
* read data.
*/
#warning Missing logic
/* Read the received data from the SPI Data Register */
#warning Missing logic
nwords--;
}
}
/****************************************************************************
* Name: lpc54_spidev_initialize
*
* Description:
* Initialize the SPI port
*
* Input Parameter:
* priv - The private data structure for the SPI device
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
static void lpc54_spidev_initialize(FAR struct lpc54_spidev_s *priv)
{
/* Configure 8-bit SPI mode and master mode */
#warning Missing logic
/* Set the initial SPI configuration */
priv->frequency = 0;
priv->nbits = 8;
priv->mode = SPIDEV_MODE0;
priv->dev.ops = &g_spi_ops;
/* Select a default frequency of approx. 400KHz */
lpc54_spi_setfrequency((FAR struct spi_dev_s *)priv, 400000);
/* Initialize the SPI semaphore that enforces mutually exclusive access */
nxsem_init(&priv->exclsem, 0, 1);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: lpc54_spibus_initialize
*
* Description:
* Initialize the selected SPI port
* 0 - SPI
* 1 - SSP0
* 2 - SSP1
*
* Input Parameter:
* Port number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
{
struct lpc54_spidev_s *priv;
irqstate_t flags;
flags = enter_critical_section();
/* Configure the requestin SPI peripheral */
/* NOTE: The basic FLEXCOMM initialization was performed in
* lpc54_lowputc.c.
*/
#ifdef CONFIG_LPC54_I2C0_MASTER
if (port == 0)
{
/* Attach 12 MHz clock to FLEXCOMM0 */
putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM0, LPC54_SYSCON_AHBCLKCTRLSET1);
/* Set FLEXCOMM0 to the SPI peripheral, locking that configuration
* in place.
*/
putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK,
LPC54_FLEXCOMM0_PSELID);
/* Initialize the state structure */
priv = &g_spi0_dev;
priv->base = LPC54_FLEXCOMM0_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM0;
priv->fclock = BOARD_FLEXCOMM0_FCLK;
/* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C0_SCK);
lpc54_gpio_config(GPIO_I2C0_MOSI);
lpc54_gpio_config(GPIO_I2C0_MISO);
/* Set up the FLEXCOMM0 function clock */
putreg32(BOARD_FLEXCOMM0_CLKSEL, LPC54_SYSCON_FCLKSEL0);
}
else
#endif
#ifdef CONFIG_LPC54_I2C1_MASTER
if (port == 1)
{
/* Attach 12 MHz clock to FLEXCOMM1 */
putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM1, LPC54_SYSCON_AHBCLKCTRLSET1);
/* Set FLEXCOMM1 to the SPI peripheral, locking that configuration
* in place.
*/
putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK,
LPC54_FLEXCOMM1_PSELID);
/* Initialize the state structure */
priv = &g_spi1_dev;
priv->base = LPC54_FLEXCOMM1_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM1;
priv->fclock = BOARD_FLEXCOMM1_FCLK;
/* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C1_SCK);
lpc54_gpio_config(GPIO_I2C1_MOSI);
lpc54_gpio_config(GPIO_I2C1_MISO);
/* Set up the FLEXCOMM1 function clock */
putreg32(BOARD_FLEXCOMM1_CLKSEL, LPC54_SYSCON_FCLKSEL1);
}
else
#endif
#ifdef CONFIG_LPC54_I2C2_MASTER
if (port == 2)
{
/* Attach 12 MHz clock to FLEXCOMM2 */
putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM2, LPC54_SYSCON_AHBCLKCTRLSET1);
/* Set FLEXCOMM2 to the SPI peripheral, locking that configuration
* in place.
*/
putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK,
LPC54_FLEXCOMM2_PSELID);
/* Initialize the state structure */
priv = &g_spi2_dev;
priv->base = LPC54_FLEXCOMM2_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM2;
priv->fclock = BOARD_FLEXCOMM2_FCLK;
/* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C2_SCK);
lpc54_gpio_config(GPIO_I2C2_MOSI);
lpc54_gpio_config(GPIO_I2C2MISO);
/* Set up the FLEXCOMM2 function clock */
putreg32(BOARD_FLEXCOMM2_CLKSEL, LPC54_SYSCON_FCLKSEL2);
}
else
#endif
#ifdef CONFIG_LPC54_I2C3_MASTER
if (port == 3)
{
/* Attach 12 MHz clock to FLEXCOMM3 */
putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM3, LPC54_SYSCON_AHBCLKCTRLSET1);
/* Set FLEXCOMM3 to the SPI peripheral, locking that configuration
* in place.
*/
putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK,
LPC54_FLEXCOMM3_PSELID);
/* Initialize the state structure */
priv = &g_spi3_dev;
priv->base = LPC54_FLEXCOMM3_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM3;
priv->fclock = BOARD_FLEXCOMM3_FCLK;
/* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C3_SCK);
lpc54_gpio_config(GPIO_I2C3_MOSI);
lpc54_gpio_config(GPIO_I2C3_MISO);
/* Set up the FLEXCOMM3 function clock */
putreg32(BOARD_FLEXCOMM3_CLKSEL, LPC54_SYSCON_FCLKSEL3);
}
else
#endif
#ifdef CONFIG_LPC54_I2C4_MASTER
if (port == 4)
{
/* Attach 12 MHz clock to FLEXCOMM4 */
putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM4, LPC54_SYSCON_AHBCLKCTRLSET1);
/* Set FLEXCOMM4 to the SPI peripheral, locking that configuration
* in place.
*/
putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK,
LPC54_FLEXCOMM4_PSELID);
/* Initialize the state structure */
priv = &g_spi4_dev;
priv->base = LPC54_FLEXCOMM4_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM4;
priv->fclock = BOARD_FLEXCOMM4_FCLK;
/* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C4_SCK);
lpc54_gpio_config(GPIO_I2C4_MOSI);
lpc54_gpio_config(GPIO_I2C4_MISO);
/* Set up the FLEXCOMM4 function clock */
putreg32(BOARD_FLEXCOMM4_CLKSEL, LPC54_SYSCON_FCLKSEL4);
}
else
#endif
#ifdef CONFIG_LPC54_I2C5_MASTER
if (port == 5)
{
/* Attach 12 MHz clock to FLEXCOMM5 */
putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM5, LPC54_SYSCON_AHBCLKCTRLSET1);
/* Set FLEXCOMM5 to the SPI peripheral, locking that configuration
* in place.
*/
putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK,
LPC54_FLEXCOMM5_PSELID);
/* Initialize the state structure */
priv = &g_spi5_dev;
priv->base = LPC54_FLEXCOMM5_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM5;
priv->fclock = BOARD_FLEXCOMM5_FCLK;
/* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C5_SCK);
lpc54_gpio_config(GPIO_I2C5_MOSI);
lpc54_gpio_config(GPIO_I2C5_MISO);
/* Set up the FLEXCOMM5 function clock */
putreg32(BOARD_FLEXCOMM5_CLKSEL, LPC54_SYSCON_FCLKSEL5);
}
else
#endif
#ifdef CONFIG_LPC54_I2C6_MASTER
if (port == 6)
{
/* Attach 12 MHz clock to FLEXCOMM6 */
putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM6, LPC54_SYSCON_AHBCLKCTRLSET1);
/* Set FLEXCOMM6 to the SPI peripheral, locking that configuration
* in place.
*/
putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK,
LPC54_FLEXCOMM6_PSELID);
/* Initialize the state structure */
priv = &g_spi6_dev;
priv->base = LPC54_FLEXCOMM6_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM6;
priv->fclock = BOARD_FLEXCOMM6_FCLK;
/* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C6_SCK);
lpc54_gpio_config(GPIO_I2C6_MOSI);
lpc54_gpio_config(GPIO_I2C6_MISO);
/* Set up the FLEXCOMM6 function clock */
putreg32(BOARD_FLEXCOMM6_CLKSEL, LPC54_SYSCON_FCLKSEL6);
}
else
#endif
#ifdef CONFIG_LPC54_I2C7_MASTER
if (port == 7)
{
/* Attach 12 MHz clock to FLEXCOMM7 */
putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM7, LPC54_SYSCON_AHBCLKCTRLSET1);
/* Set FLEXCOMM7 to the SPI peripheral, locking that configuration
* in place.
*/
putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK,
LPC54_FLEXCOMM7_PSELID);
/* Initialize the state structure */
priv = &g_spi7_dev;
priv->base = LPC54_FLEXCOMM7_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM7;
priv->fclock = BOARD_FLEXCOMM7_FCLK;
/* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C7_SCK);
lpc54_gpio_config(GPIO_I2C7_MOSI);
lpc54_gpio_config(GPIO_I2C7_MISO);
/* Set up the FLEXCOMM7 function clock */
putreg32(BOARD_FLEXCOMM7_CLKSEL, LPC54_SYSCON_FCLKSEL7);
}
else
#endif
#ifdef CONFIG_LPC54_I2C8_MASTER
if (port == 8)
{
/* Attach 12 MHz clock to FLEXCOMM8 */
putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM8, LPC54_SYSCON_AHBCLKCTRLSET1);
/* Set FLEXCOMM8 to the SPI peripheral, locking that configuration
* in place.
*/
putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK,
LPC54_FLEXCOMM8_PSELID);
/* Initialize the state structure */
priv = &g_spi8_dev;
priv->base = LPC54_FLEXCOMM8_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM8;
priv->fclock = BOARD_FLEXCOMM8_FCLK;
/* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C8_SCK);
lpc54_gpio_config(GPIO_I2C8_MOSI);
lpc54_gpio_config(GPIO_I2C8_MISO);
/* Set up the FLEXCOMM8 function clock */
putreg32(BOARD_FLEXCOMM8_CLKSEL, LPC54_SYSCON_FCLKSEL8);
}
else
#endif
#ifdef CONFIG_LPC54_I2C9_MASTER
if (port == 9)
{
/* Attach 12 MHz clock to FLEXCOMM9 */
putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM9, LPC54_SYSCON_AHBCLKCTRLSET1);
/* Set FLEXCOMM9 to the SPI peripheral, locking that configuration
* in place.
*/
putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK,
LPC54_FLEXCOMM9_PSELID);
/* Initialize the state structure */
priv = &g_spi9_dev;
priv->base = LPC54_FLEXCOMM9_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM9;
priv->fclock = BOARD_FLEXCOMM9_FCLK;
/* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C9_SCK);
lpc54_gpio_config(GPIO_I2C9_MOSI);
lpc54_gpio_config(GPIO_I2C9_MISO);
/* Set up the FLEXCOMM9 function clock */
putreg32(BOARD_FLEXCOMM9_CLKSEL, LPC54_SYSCON_FCLKSEL9);
}
else
#endif
{
return NULL;
}
leave_critical_section(flags);
/* Enable the SPI peripheral and configure master mode */
(void)lpc54_spidev_initialize(priv);
return &priv->dev;
}
#endif /* HAVE_SPI_MASTER_DEVICE */

180
arch/arm/src/lpc54xx/lpc54_spi_master.h Normal file
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@ -0,0 +1,180 @@
/************************************************************************************
* arch/arm/src/lpc54xx/lpc54_spi_master.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC54XX_SPI_MASTER_H
#define __ARCH_ARM_SRC_LPC54XX_SPI_MASTER_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/spi/spi.h>
#ifdef HAVE_SPI_MASTER_DEVICE
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* This header file defines interfaces to common SPI logic. To use this common SPI
* logic on your board:
*
* 1. Provide logic in lpc54_boardinitialize() to configure SPI chip select pins.
* 2. Provide the lpc54_spiselect() and lpc54_spistatus() functions in your
* board-specific logic. These functions will perform chip selection
* and status operations using GPIOs in the way your board is configured.
* 3. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
* lpc54_spicmddata() functions in your board-specific logic. This
* function will perform cmd/data selection operations using GPIOs in the
* way your board is configured.
* 4. Your low level board initialization logic should call lpc54_spibus_initialize.
* 5. The handle returned by lpc54_spibus_initialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(),
* for example, will bind the SPI driver to the SPI MMC/SD driver).
*/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Name: lpc54_spibus_initialize
*
* Description:
* Initialize the selected SPI port
* 0 - SPI0
* 1 - SPI1
* ...
* 9 - SPI9
*
* Input Parameter:
* port - SPI peripheral number, 0.. 9.
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
FAR struct spi_dev_s *lpc54_spibus_initialize(int port);
/************************************************************************************
* Name: lpc54_spiselect, lpc54_spistatus, and lpc54_spicmddata
*
* Description:
* These functions must be provided in your board-specific logic. The
* lpc54_spiselect function will perform chip selection and the lpc54_spistatus
* will perform status operations using GPIOs in the way your board is configured.
*
* If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, then
* lpc54_spicmddata must also be provided. This functions performs cmd/data
* selection operations using GPIOs in the way your board is configured.
*
************************************************************************************/
void lpc54_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
uint8_t lpc54_spistatus(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int lpc54_spicmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
/************************************************************************************
* Name: spi_flush
*
* Description:
* Flush and discard any words left in the RX fifo. This can be called from
* spiselect after a device is deselected (if you worry about such things).
*
* Input Parameters:
* dev - Device-specific state data
*
* Returned Value:
* None
*
************************************************************************************/
void spi_flush(FAR struct spi_dev_s *dev);
/************************************************************************************
* Name: lpc54_spi/spiregister
*
* Description:
* If the board supports a card detect callback to inform the SPI-based MMC/SD
* driver when an SD card is inserted or removed, then CONFIG_SPI_CALLBACK should
* be defined and the following function(s) must must be implemented. These
* functions implements the registercallback method of the SPI interface (see
* include/nuttx/spi/spi.h for details)
*
* Input Parameters:
* dev - Device-specific state data
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:
* 0 on success; negated errno on failure.
*
************************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
int lpc54_spiregister(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* HAVE_SPI_MASTER_DEVICE */
#endif /* __ARCH_ARM_SRC_LPC54XX_SPI_MASTER_H */