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Two r's and only two r's in the word interrupt

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This commit is contained in:
Gregory Nutt 2015-04-23 14:04:43 -06:00
parent aaeb9843d6
commit d77a19f0a2
42 changed files with 74 additions and 74 deletions
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2
arch/arm/include/lpc17xx/lpc176x_irq.h
View File

@ -148,7 +148,7 @@
*/
#ifdef CONFIG_GPIO_IRQ
# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrrupt set */
# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrupt set */
# define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */
/* Set 1: 12 interrupts p0.0-p0.11 */

2
arch/arm/include/lpc17xx/lpc178x_irq.h
View File

@ -167,7 +167,7 @@
*/
#ifdef CONFIG_GPIO_IRQ
# define LPC17_VALID_GPIOINT0 (0xfffffffful) /* GPIO port 0 interrrupt set */
# define LPC17_VALID_GPIOINT0 (0xfffffffful) /* GPIO port 0 interrupt set */
# define LPC17_VALID_GPIOINT2 (0xfffffffful) /* GPIO port 2 interrupt set */
/* Set 1: 16 interrupts p0.0-p0.15 */

2
arch/arm/src/a1x/chip/a10_piocfg.h
View File

@ -191,7 +191,7 @@
#define PIO_ETXEN (PIO_PERIPH2 | PIO_PORT_PIOA | PIO_PIN13)
#define PIO_ETXERR (PIO_PERIPH2 | PIO_PORT_PIOA | PIO_PIN16)
/* External PIO interrrupts */
/* External PIO interrupts */
#define PIO_EINT0 (PIO_EINT | PIO_PORT_PIOH | PIO_PIN0)
#define PIO_EINT1 (PIO_EINT | PIO_PORT_PIOH | PIO_PIN1)

2
arch/arm/src/dm320/dm320_irq.c
View File

@ -204,7 +204,7 @@ void up_enable_irq(int irq)
* Name: up_ack_irq
*
* Description:
* Acknowledge the interupt
* Acknowledge the interrupt
*
************************************************************************/

2
arch/arm/src/efm32/efm32_usbdev.c
View File

@ -2672,7 +2672,7 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv)
efm32_epout(priv, epno);
}
/* Endpoint disabled interrupt (ignored because this interrrupt is
/* Endpoint disabled interrupt (ignored because this interrupt is
* used in polled mode by the endpoint disable logic).
*/
#if 1

10
arch/arm/src/efm32/efm32_usbhost.c
View File

@ -857,7 +857,7 @@ static void efm32_chan_halt(FAR struct efm32_usbhost_s *priv, int chidx,
uint32_t eptype;
unsigned int avail;
/* Save the reason for the halt. We need this in the channel halt interrrupt
/* Save the reason for the halt. We need this in the channel halt interrupt
* handling logic to know what to do next.
*/
@ -1806,7 +1806,7 @@ static inline void efm32_gint_hcinisr(FAR struct efm32_usbhost_s *priv,
if ((pending & USB_HC_INT_FRMOVRUN) != 0)
{
/* Halt the channel -- the CHH interrrupt is expected next */
/* Halt the channel -- the CHH interrupt is expected next */
efm32_chan_halt(priv, chidx, CHREASON_FRMOR);
@ -1827,7 +1827,7 @@ static inline void efm32_gint_hcinisr(FAR struct efm32_usbhost_s *priv,
if (chan->eptype == EFM32_USB_EPTYPE_CTRL || chan->eptype == EFM32_USB_EPTYPE_BULK)
{
/* Halt the channel -- the CHH interrrupt is expected next */
/* Halt the channel -- the CHH interrupt is expected next */
efm32_chan_halt(priv, chidx, CHREASON_XFRC);
@ -2050,7 +2050,7 @@ static inline void efm32_gint_hcoutisr(FAR struct efm32_usbhost_s *priv,
priv->chan[chidx].buflen -= priv->chan[chidx].inflight;
priv->chan[chidx].inflight = 0;
/* Halt the channel -- the CHH interrrupt is expected next */
/* Halt the channel -- the CHH interrupt is expected next */
efm32_chan_halt(priv, chidx, CHREASON_XFRC);
@ -2078,7 +2078,7 @@ static inline void efm32_gint_hcoutisr(FAR struct efm32_usbhost_s *priv,
else if ((pending & USB_HC_INT_NAK) != 0)
{
/* Halt the channel -- the CHH interrrupt is expected next */
/* Halt the channel -- the CHH interrupt is expected next */
efm32_chan_halt(priv, chidx, CHREASON_NAK);

4
arch/arm/src/kinetis/kinetis_sdhc.c
View File

@ -1952,7 +1952,7 @@ static int kinetis_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buff
kinetis_dataconfig(priv, true, nbytes, 1, SDHC_DVS_DATATIMEOUT);
/* Enable TX interrrupts */
/* Enable TX interrupts */
kinetis_configxfrints(priv, SDHC_SNDDONE_INTS);
kinetis_sample(priv, SAMPLENDX_AFTER_SETUP);
@ -2662,7 +2662,7 @@ static int kinetis_dmasendsetup(FAR struct sdio_dev_s *dev,
kinetis_sample(priv, SAMPLENDX_AFTER_SETUP);
/* Enable TX interrrupts */
/* Enable TX interrupts */
kinetis_configxfrints(priv, SDHC_DMADONE_INTS);
return OK;

2
arch/arm/src/lpc17xx/Kconfig
View File

@ -967,7 +967,7 @@ config USBHOST_BULK_DISABLE
Disable support for bulk endpoints.
config USBHOST_INT_DISABLE
bool "Disable interupt EPs"
bool "Disable interrupt EPs"
default n
---help---
Disable support for interrupt endpoints.

18
arch/arm/src/lpc17xx/chip/lpc17_pwm.h
View File

@ -118,16 +118,16 @@
/* Interrupt Register */
#define PWM_IR_MR0 (1 << 0) /* Bit 0: PWM match channel 0 interrrupt */
#define PWM_IR_MR1 (1 << 1) /* Bit 1: PWM match channel 1 interrrupt */
#define PWM_IR_MR2 (1 << 2) /* Bit 2: PWM match channel 2 interrrupt */
#define PWM_IR_MR3 (1 << 3) /* Bit 3: PWM match channel 3 interrrupt */
#define PWM_IR_CAP0 (1 << 4) /* Bit 4: Capture input 0 interrrupt */
#define PWM_IR_CAP1 (1 << 5) /* Bit 5: Capture input 1 interrrupt */
#define PWM_IR_MR0 (1 << 0) /* Bit 0: PWM match channel 0 interrupt */
#define PWM_IR_MR1 (1 << 1) /* Bit 1: PWM match channel 1 interrupt */
#define PWM_IR_MR2 (1 << 2) /* Bit 2: PWM match channel 2 interrupt */
#define PWM_IR_MR3 (1 << 3) /* Bit 3: PWM match channel 3 interrupt */
#define PWM_IR_CAP0 (1 << 4) /* Bit 4: Capture input 0 interrupt */
#define PWM_IR_CAP1 (1 << 5) /* Bit 5: Capture input 1 interrupt */
/* Bits 6-7: Reserved */
#define PWM_IR_MR4 (1 << 8) /* Bit 8: PWM match channel 4 interrrupt */
#define PWM_IR_MR5 (1 << 9) /* Bit 9: PWM match channel 5 interrrupt */
#define PWM_IR_MR6 (1 << 10) /* Bit 10: PWM match channel 6 interrrupt */
#define PWM_IR_MR4 (1 << 8) /* Bit 8: PWM match channel 4 interrupt */
#define PWM_IR_MR5 (1 << 9) /* Bit 9: PWM match channel 5 interrupt */
#define PWM_IR_MR6 (1 << 10) /* Bit 10: PWM match channel 6 interrupt */
/* Bits 11-31: Reserved */
/* Timer Control Register */

4
arch/arm/src/lpc17xx/lpc17_sdcard.c
View File

@ -1804,7 +1804,7 @@ static int lpc17_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer
dblocksize = lpc17_log2(nbytes) << SDCARD_DCTRL_DBLOCKSIZE_SHIFT;
lpc17_dataconfig(SDCARD_DTIMER_DATATIMEOUT, nbytes, dblocksize);
/* Enable TX interrrupts */
/* Enable TX interrupts */
lpc17_configxfrints(priv, SDCARD_SEND_MASK);
lpc17_sample(priv, SAMPLENDX_AFTER_SETUP);
@ -2558,7 +2558,7 @@ static int lpc17_dmasendsetup(FAR struct sdio_dev_s *dev,
lpc17_dmastart(priv->dma, lpc17_dmacallback, priv);
lpc17_sample(priv, SAMPLENDX_AFTER_SETUP);
/* Enable TX interrrupts */
/* Enable TX interrupts */
lpc17_configxfrints(priv, SDCARD_DMASEND_MASK);
}

2
arch/arm/src/lpc214x/lpc214x_i2c.h
View File

@ -73,7 +73,7 @@
/* Control Set Register (CONSET) */
#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */
#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrrupt flag */
#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */
#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */
#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */
#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */

2
arch/arm/src/lpc214x/lpc214x_serial.c
View File

@ -362,7 +362,7 @@ static int up_setup(struct uart_dev_s *dev)
(LPC214X_FCR_FIFO_TRIG8|LPC214X_FCR_TX_FIFO_RESET|\
LPC214X_FCR_RX_FIFO_RESET|LPC214X_FCR_FIFO_ENABLE));
/* The NuttX serial driver waits for the first THRE interrrupt before
/* The NuttX serial driver waits for the first THRE interrupt before
* sending serial data... However, it appears that the lpc214x hardware
* does not generate that interrupt until a transition from not-empty
* to empty. So, the current kludge here is to send one NULL at

2
arch/arm/src/lpc2378/lpc23xx_serial.c
View File

@ -483,7 +483,7 @@ static int up_setup(struct uart_dev_s *dev)
(FCR_FIFO_TRIG8 | FCR_TX_FIFO_RESET |
FCR_RX_FIFO_RESET | FCR_FIFO_ENABLE));
/* The NuttX serial driver waits for the first THRE interrrupt before sending
/* The NuttX serial driver waits for the first THRE interrupt before sending
* serial data... However, it appears that the LPC2378 hardware too does not
* generate that interrupt until a transition from not-empty to empty. So,
* the current kludge here is to send one NULL at startup to kick things off.

2
arch/arm/src/lpc31xx/lpc31_lowputc.c
View File

@ -328,7 +328,7 @@ void lpc31_lowsetup(void)
UART_FCR_RXFIFORST|UART_FCR_FIFOENABLE),
LPC31_UART_FCR);
/* The NuttX serial driver waits for the first THRE interrrupt before
/* The NuttX serial driver waits for the first THRE interrupt before
* sending serial data... However, it appears that the lpc313x hardware
* does not generate that interrupt until a transition from not-empty
* to empty. So, the current kludge here is to send one NULL at

2
arch/arm/src/lpc31xx/lpc31_serial.c
View File

@ -396,7 +396,7 @@ static int up_setup(struct uart_dev_s *dev)
UART_FCR_RXFIFORST|UART_FCR_FIFOENABLE),
LPC31_UART_FCR);
/* The NuttX serial driver waits for the first THRE interrrupt before
/* The NuttX serial driver waits for the first THRE interrupt before
* sending serial data... However, it appears that the lpc313x hardware
* does not generate that interrupt until a transition from not-empty
* to empty. So, the current kludge here is to send one NULL at

2
arch/arm/src/lpc31xx/lpc31_spi.h
View File

@ -235,7 +235,7 @@
#define SPI_INT_TX (1 << 3) /* Bit 3: Transmit threshold level interrupt bit */
#define SPI_INT_RX (1 << 2) /* Bit 3: Receive threshold level interrupt bit */
#define SPI_INT_TO (1 << 1) /* Bit 1: Receive timeout interrupt bit */
#define SPI_INT_OV (1 << 0) /* Bit 0: Receive overrtun interrrupt bit */
#define SPI_INT_OV (1 << 0) /* Bit 0: Receive overrtun interrupt bit */
/************************************************************************************************
* Public Types

2
arch/arm/src/lpc43xx/lpc43_rgu.c
View File

@ -117,7 +117,7 @@ void lpc43_softreset(void)
up_mdelay(20);
/* Clear all pending interupts */
/* Clear all pending interrupts */
putreg32(0xffffffff, NVIC_IRQ0_31_CLRPEND);
putreg32(0xffffffff, NVIC_IRQ32_63_CLRPEND);

2
arch/arm/src/nuc1xx/chip/nuc_clk.h
View File

@ -88,7 +88,7 @@
#define CLK_PWRCON_OSC10K_EN (1 << 3) /* Bit 3: Internal 10KHz low speed oscillator enable */
#define CLK_PWRCON_PD_WU_DLY (1 << 4) /* Bit 4: Enable the wake-up delay counter */
#define CLK_PWRCON_PD_WU_INT_EN (1 << 5) /* Bit 5: Power down mode wake-up interrupt status */
#define CLK_PWRCON_PD_WU_STS (1 << 6) /* Bit 6: Power down mode wake-up interupt status */
#define CLK_PWRCON_PD_WU_STS (1 << 6) /* Bit 6: Power down mode wake-up interrupt status */
#define CLK_PWRCON_PWR_DOWN_EN (1 << 7) /* Bit 7: System power down enable bit */
#define CLK_PWRCON_PD_WAIT_CPU (1 << 8) /* Bit 8: Power down entry condition */

2
arch/arm/src/sam34/sam4l_gpio.c
View File

@ -416,7 +416,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
if ((cfgset & GPIO_PERIPH_EVENTS) != 0)
{
/* Rising only.. disable interrrupts on the falling edge */
/* Rising only.. disable interrupts on the falling edge */
putreg32(pin, base + SAM_GPIO_EVERS_OFFSET);
}

4
arch/arm/src/sama5/sam_ssc.c
View File

@ -1478,7 +1478,7 @@ static void ssc_rx_worker(void *arg)
while (sq_peek(&priv->rx.done) != NULL)
{
/* Remove the buffer container from the rx.done queue. NOTE that
* interupts must be enabled to do this because the rx.done queue is
* interrupts must be enabled to do this because the rx.done queue is
* also modified from the interrupt level.
*/
@ -1890,7 +1890,7 @@ static void ssc_tx_worker(void *arg)
while (sq_peek(&priv->tx.done) != NULL)
{
/* Remove the buffer container from the tx.done queue. NOTE that
* interupts must be enabled to do this because the tx.done queue is
* interrupts must be enabled to do this because the tx.done queue is
* also modified from the interrupt level.
*/

4
arch/arm/src/samv7/sam_ssc.c
View File

@ -1452,7 +1452,7 @@ static void ssc_rx_worker(void *arg)
while (sq_peek(&priv->rx.done) != NULL)
{
/* Remove the buffer container from the rx.done queue. NOTE that
* interupts must be enabled to do this because the rx.done queue is
* interrupts must be enabled to do this because the rx.done queue is
* also modified from the interrupt level.
*/
@ -1868,7 +1868,7 @@ static void ssc_tx_worker(void *arg)
while (sq_peek(&priv->tx.done) != NULL)
{
/* Remove the buffer container from the tx.done queue. NOTE that
* interupts must be enabled to do this because the tx.done queue is
* interrupts must be enabled to do this because the tx.done queue is
* also modified from the interrupt level.
*/

2
arch/arm/src/stm32/Kconfig
View File

@ -3772,7 +3772,7 @@ config STM32_USB_ITRMP
---help---
The legacy USB in the F1 series shared interrupt lines with USB
device and CAN1. In the F3 series, a hardware options was added to
either retain the legacy F1 behavior or to map the USB interupts to
either retain the legacy F1 behavior or to map the USB interrupts to
there own dedicated vectors. The option is available only for the
F3 family and selects the use of the dedicated USB interrupts.

2
arch/arm/src/stm32/stm32_otgfsdev.c
View File

@ -2668,7 +2668,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv)
stm32_epout(priv, epno);
}
/* Endpoint disabled interrupt (ignored because this interrrupt is
/* Endpoint disabled interrupt (ignored because this interrupt is
* used in polled mode by the endpoint disable logic).
*/
#if 1

10
arch/arm/src/stm32/stm32_otgfshost.c
View File

@ -862,7 +862,7 @@ static void stm32_chan_halt(FAR struct stm32_usbhost_s *priv, int chidx,
uint32_t eptype;
unsigned int avail;
/* Save the reason for the halt. We need this in the channel halt interrrupt
/* Save the reason for the halt. We need this in the channel halt interrupt
* handling logic to know what to do next.
*/
@ -1811,7 +1811,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
if ((pending & OTGFS_HCINT_FRMOR) != 0)
{
/* Halt the channel -- the CHH interrrupt is expected next */
/* Halt the channel -- the CHH interrupt is expected next */
stm32_chan_halt(priv, chidx, CHREASON_FRMOR);
@ -1832,7 +1832,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
if (chan->eptype == OTGFS_EPTYPE_CTRL || chan->eptype == OTGFS_EPTYPE_BULK)
{
/* Halt the channel -- the CHH interrrupt is expected next */
/* Halt the channel -- the CHH interrupt is expected next */
stm32_chan_halt(priv, chidx, CHREASON_XFRC);
@ -2055,7 +2055,7 @@ static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv,
priv->chan[chidx].buflen -= priv->chan[chidx].inflight;
priv->chan[chidx].inflight = 0;
/* Halt the channel -- the CHH interrrupt is expected next */
/* Halt the channel -- the CHH interrupt is expected next */
stm32_chan_halt(priv, chidx, CHREASON_XFRC);
@ -2083,7 +2083,7 @@ static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv,
else if ((pending & OTGFS_HCINT_NAK) != 0)
{
/* Halt the channel -- the CHH interrrupt is expected next */
/* Halt the channel -- the CHH interrupt is expected next */
stm32_chan_halt(priv, chidx, CHREASON_NAK);

2
arch/arm/src/stm32/stm32_otghsdev.c
View File

@ -2668,7 +2668,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv)
stm32_epout(priv, epno);
}
/* Endpoint disabled interrupt (ignored because this interrrupt is
/* Endpoint disabled interrupt (ignored because this interrupt is
* used in polled mode by the endpoint disable logic).
*/
#if 1

10
arch/arm/src/stm32/stm32_otghshost.c
View File

@ -862,7 +862,7 @@ static void stm32_chan_halt(FAR struct stm32_usbhost_s *priv, int chidx,
uint32_t eptype;
unsigned int avail;
/* Save the reason for the halt. We need this in the channel halt interrrupt
/* Save the reason for the halt. We need this in the channel halt interrupt
* handling logic to know what to do next.
*/
@ -1811,7 +1811,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
if ((pending & OTGHS_HCINT_FRMOR) != 0)
{
/* Halt the channel -- the CHH interrrupt is expected next */
/* Halt the channel -- the CHH interrupt is expected next */
stm32_chan_halt(priv, chidx, CHREASON_FRMOR);
@ -1832,7 +1832,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
if (chan->eptype == OTGHS_EPTYPE_CTRL || chan->eptype == OTGHS_EPTYPE_BULK)
{
/* Halt the channel -- the CHH interrrupt is expected next */
/* Halt the channel -- the CHH interrupt is expected next */
stm32_chan_halt(priv, chidx, CHREASON_XFRC);
@ -2055,7 +2055,7 @@ static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv,
priv->chan[chidx].buflen -= priv->chan[chidx].inflight;
priv->chan[chidx].inflight = 0;
/* Halt the channel -- the CHH interrrupt is expected next */
/* Halt the channel -- the CHH interrupt is expected next */
stm32_chan_halt(priv, chidx, CHREASON_XFRC);
@ -2083,7 +2083,7 @@ static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv,
else if ((pending & OTGHS_HCINT_NAK) != 0)
{
/* Halt the channel -- the CHH interrrupt is expected next */
/* Halt the channel -- the CHH interrupt is expected next */
stm32_chan_halt(priv, chidx, CHREASON_NAK);

4
arch/arm/src/stm32/stm32_sdio.c
View File

@ -1906,7 +1906,7 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer
dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, nbytes, dblocksize);
/* Enable TX interrrupts */
/* Enable TX interrupts */
stm32_configxfrints(priv, SDIO_SEND_MASK);
stm32_sample(priv, SAMPLENDX_AFTER_SETUP);
@ -2711,7 +2711,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
stm32_dmastart(priv->dma, stm32_dmacallback, priv, false);
stm32_sample(priv, SAMPLENDX_AFTER_SETUP);
/* Enable TX interrrupts */
/* Enable TX interrupts */
stm32_configxfrints(priv, SDIO_DMASEND_MASK);

2
arch/arm/src/stm32/stm32_tim.h
View File

@ -164,7 +164,7 @@ struct stm32_tim_ops_s
int (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare);
int (*getcapture)(FAR struct stm32_tim_dev_s *dev, uint8_t channel);
/* Timer interupts */
/* Timer interrupts */
int (*setisr)(FAR struct stm32_tim_dev_s *dev, int (*handler)(int irq, void *context), int source);
void (*enableint)(FAR struct stm32_tim_dev_s *dev, int source);

2
arch/arm/src/stm32/stm32f30xxx_i2c.c
View File

@ -108,7 +108,7 @@
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
/* CONFIG_I2C_POLLED may be set so that I2C interrrupts will not be used. Instead,
/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. Instead,
* CPU-intensive polling will be used.
*/

2
arch/arm/src/str71x/str71x_eic.h
View File

@ -156,7 +156,7 @@
#define STR71X_EICFIR_FIE (0x00000001) /* Bit 0: FIQ channel 1/0 enable */
#define STR71X_EICFIR_FIP (0x00000002) /* Bit 1: channel 1/0 FIQ pending */
/* Source interrrupt register definitions */
/* Source interrupt register definitions */
#define STR71X_EICSIR_SIPLMASK (0x0000000f) /* Bits 0-3: Source interrupt priority level */
#define STR71X_EICSIR_SIVMASK (0xffff0000) /* Bits 16-31: Source interrupt vector */

2
arch/arm/src/str71x/str71x_irq.c
View File

@ -198,7 +198,7 @@ void up_ack_irq(int irq)
*
* Description:
* Set interrupt priority. Note, there is no way to prioritize
* individual XTI interrrupts.
* individual XTI interrupts.
*
****************************************************************************/

2
arch/avr/src/avr32/up_exceptions.S
View File

@ -296,7 +296,7 @@ avr32_common:
mov r11, sp
/* Switch to the interrrupt stack if so configured. Move the current */
/* Switch to the interrupt stack if so configured. Move the current */
/* stack pointer into a preserved register (r7) and set the interrupt */
/* stack pointer. */

4
arch/mips/src/pic32mx/pic32mx-head.S
View File

@ -84,10 +84,10 @@
* 6) Optional interrupt stack
* Start: _ebss+CONFIG_IDLETHREAD_STACKSIZE
* End(+1): _ebss+CONFIG_IDLETHREAD_STACKSIZE+(CONFIG_ARCH_INTERRUPTSTACK & ~3)
* 6a) Heap (without interupt stack)
* 6a) Heap (without interrupt stack)
* Start: _ebss+CONFIG_IDLETHREAD_STACKSIZE
* End(+1): to the end of memory
* 6b) Heap (with interupt stack)
* 6b) Heap (with interrupt stack)
* Start: _ebss+CONFIG_IDLETHREAD_STACKSIZE+(CONFIG_ARCH_INTERRUPTSTACK & ~3)
* End(+1): to the end of memory
*/

2
arch/mips/src/pic32mx/pic32mx-internal.h
View File

@ -244,7 +244,7 @@ void pic32mx_boardinitialize(void);
* Name: pic32mx_decodeirq
*
* Description:
* Called from assembly language logic when an interrrupt exception occurs. This
* Called from assembly language logic when an interrupt exception occurs. This
* function decodes and dispatches the interrupt.
*
************************************************************************************/

2
arch/mips/src/pic32mx/pic32mx-serial.c
View File

@ -500,7 +500,7 @@ static int up_interrupt(int irq, void *context)
/* Clear the pending error interrupt */
up_clrpend_irq(priv->irqe);
lldbg("ERROR: interrrupt STA: %08x\n",
lldbg("ERROR: interrupt STA: %08x\n",
up_serialin(priv, PIC32MX_UART_STA_OFFSET));
handled = true;
}

4
arch/mips/src/pic32mz/pic32mz-head.S
View File

@ -84,10 +84,10 @@
* 6) Optional interrupt stack
* Start: _ebss+CONFIG_IDLETHREAD_STACKSIZE
* End(+1): _ebss+CONFIG_IDLETHREAD_STACKSIZE+(CONFIG_ARCH_INTERRUPTSTACK & ~3)
* 6a) Heap (without interupt stack)
* 6a) Heap (without interrupt stack)
* Start: _ebss+CONFIG_IDLETHREAD_STACKSIZE
* End(+1): to the end of memory
* 6b) Heap (with interupt stack)
* 6b) Heap (with interrupt stack)
* Start: _ebss+CONFIG_IDLETHREAD_STACKSIZE+(CONFIG_ARCH_INTERRUPTSTACK & ~3)
* End(+1): to the end of memory
*/

2
arch/mips/src/pic32mz/pic32mz-serial.c
View File

@ -758,7 +758,7 @@ static int up_interrupt(struct uart_dev_s *dev)
/* Clear the pending error interrupt */
up_clrpend_irq(priv->irqe);
lldbg("ERROR: interrrupt STA: %08x\n",
lldbg("ERROR: interrupt STA: %08x\n",
up_serialin(priv, PIC32MZ_UART_STA_OFFSET));
handled = true;
}

2
arch/z80/src/ez80/ez80_emac.c
View File

@ -2077,7 +2077,7 @@ static int ez80_emacinitialize(void)
/* Software reset */
outp(EZ80_EMAC_ISTAT, 0xff); /* Clear any pending interupts */
outp(EZ80_EMAC_ISTAT, 0xff); /* Clear any pending interrupts */
regval = inp(EZ80_EMAC_RST);
regval |= EMAC_RST_SRST;
outp(EZ80_EMAC_RST, regval);

8
arch/z80/src/ez80/ez80_serial.c
View File

@ -85,7 +85,7 @@ static int ez80_setup(struct uart_dev_s *dev);
static void ez80_shutdown(struct uart_dev_s *dev);
static int ez80_attach(struct uart_dev_s *dev);
static void ez80_detach(struct uart_dev_s *dev);
static int ez80_interrrupt(int irq, void *context);
static int ez80_interrupt(int irq, void *context);
static int ez80_ioctl(struct file *filep, int cmd, unsigned long arg);
static int ez80_receive(struct uart_dev_s *dev, unsigned int *status);
static void ez80_rxint(struct uart_dev_s *dev, bool enable);
@ -438,7 +438,7 @@ static int ez80_attach(struct uart_dev_s *dev)
/* Attach the IRQ */
return irq_attach(priv->irq, ez80_interrrupt);
return irq_attach(priv->irq, ez80_interrupt);
}
/****************************************************************************
@ -459,7 +459,7 @@ static void ez80_detach(struct uart_dev_s *dev)
}
/****************************************************************************
* Name: ez80_interrrupt
* Name: ez80_interrupt
*
* Description:
* This is the UART interrupt handler. It will be invoked
@ -471,7 +471,7 @@ static void ez80_detach(struct uart_dev_s *dev)
*
****************************************************************************/
static int ez80_interrrupt(int irq, void *context)
static int ez80_interrupt(int irq, void *context)
{
struct uart_dev_s *dev = NULL;
struct ez80_dev_s *priv;

2
arch/z80/src/z180/switch.h
View File

@ -192,7 +192,7 @@ extern volatile chipreg_t *current_regs;
/* This holds the value of the MMU's CBR register. This value is set to the
* interrupted tasks's CBR on interrupt entry, changed to the new task's CBR if
* an interrrupt level context switch occurs, and restored on interrupt exit. In
* an interrupt level context switch occurs, and restored on interrupt exit. In
* this way, the CBR is always correct on interrupt exit.
*/

2
arch/z80/src/z180/z180_irq.c
View File

@ -66,7 +66,7 @@ volatile chipreg_t *current_regs;
/* This holds the value of the MMU's CBR register. This value is set to the
* interrupted tasks's CBR on interrupt entry, changed to the new task's CBR if
* an interrrupt level context switch occurs, and restored on interrupt exit. In
* an interrupt level context switch occurs, and restored on interrupt exit. In
* this way, the CBR is always correct on interrupt exit.
*/

6
arch/z80/src/z180/z180_scc.c
View File

@ -89,7 +89,7 @@ static int z180_setup(struct uart_dev_s *dev);
static void z180_shutdown(struct uart_dev_s *dev);
static int z180_attach(struct uart_dev_s *dev);
static void z180_detach(struct uart_dev_s *dev);
static int z180_interrrupt(int irq, void *context);
static int z180_interrupt(int irq, void *context);
static int z180_ioctl(struct file *filep, int cmd, unsigned long arg);
static int z180_receive(struct uart_dev_s *dev, unsigned int *status);
static void z180_rxint(struct uart_dev_s *dev, bool enable);
@ -438,7 +438,7 @@ static void z180_detach(struct uart_dev_s *dev)
}
/****************************************************************************
* Name: z180_interrrupt
* Name: z180_interrupt
*
* Description:
* This is the UART interrupt handler. It will be invoked
@ -450,7 +450,7 @@ static void z180_detach(struct uart_dev_s *dev)
*
****************************************************************************/
static int z180_interrrupt(int irq, void *context)
static int z180_interrupt(int irq, void *context)
{
#warning "Missing logic"
}