sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

STM32L152: Better LOOPSPERMSEC; Need to set higher performance VOS

Browse Source
This commit is contained in:
Gregory Nutt 2013-05-20 15:51:37 -06:00
parent 78457c51a4
commit d77d2a3325
2 changed files with 70 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

129
configs/stm32ldiscovery/include/board.h
View File

@ -75,21 +75,21 @@
* Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins.
*/
#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/
#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/
#define STM32_HSI_FREQUENCY 16000000ul /* Approximately 16MHz */
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_MSI_FREQUENCY 2097000 /* Default is approximately 2.097Mhz */
#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */
#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
#define STM32_HSI_FREQUENCY 16000000ul /* Approximately 16MHz */
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_MSI_FREQUENCY 2097000 /* Default is approximately 2.097Mhz */
#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */
#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
/* PLL Configuration
*
* - PLL source is HSI -> 16MHz input (nominal)
* - PLL multipler is 4 -> 64MHz PLL VCO clock output
* - PLL output divider 2 -> 32MHz divided down PLL VCO clock output
* - PLL multipler is 6 -> 96MHz PLL VCO clock output (for USB)
* - PLL output divider 3 -> 32MHz divided down PLL VCO clock output
*
* Resulting SYSCLK frequency is 16MHz x 4 / 2 = 32MHz
* Resulting SYSCLK frequency is 16MHz x 6 / 3 = 32MHz
*
* USB/SDIO:
* If the USB or SDIO interface is used in the application, the PLL VCO
@ -106,50 +106,60 @@
* The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source).
*/
#define STM32_CFGR_PLLSRC 0 /* Source is 16MHz HSI */
#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx4 /* PLLMUL = 4 */
#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 /* PLLDIV = 2 */
#define STM32_PLL_FREQUENCY (4*STM32_HSE_FREQUENCY) /* PLL VCO Frequency is 64MHz */
#define STM32_CFGR_PLLSRC 0 /* Source is 16MHz HSI */
#ifdef CONFIG_STM32_USB
# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx6 /* PLLMUL = 6 */
# define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */
# define STM32_PLL_FREQUENCY (6*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 96MHz */
#else
# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx4 /* PLLMUL = 4 */
# define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 /* PLLDIV = 2 */
# define STM32_PLL_FREQUENCY (4*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 64MHz */
#endif
/* Use the PLL and set the SYSCLK source to be the diveded down PLL VCO output
/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output
* frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value).
*/
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
#define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/2) /* SYSCLK frequence is 64MHz/PLLDIV = 32MHz */
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
#ifdef CONFIG_STM32_USB
# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/3) /* SYSCLK frequence is 96MHz/PLLDIV = 32MHz */
#else
# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/2) /* SYSCLK frequence is 64MHz/PLLDIV = 32MHz */
#endif
/* AHB clock (HCLK) is SYSCLK (32MHz) */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (32MHz) */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY)
/* APB2 timers 9, 10, and 11 will receive PCLK2. */
#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
/* APB1 clock (PCLK1) is HCLK (32MHz) */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY)
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY)
/* APB1 timers 2-7 will receive PCLK1 */
#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
/* LED definitions ******************************************************************/
/* The STM32L-Discovery board has four LEDs. Two of these are controlled by
@ -172,14 +182,14 @@
/* LED index values for use with stm32_setled() */
#define BOARD_LED1 0 /* User LD3 */
#define BOARD_LED2 1 /* User LD4 */
#define BOARD_NLEDS 2
#define BOARD_LED1 0 /* User LD3 */
#define BOARD_LED2 1 /* User LD4 */
#define BOARD_NLEDS 2
/* LED bits for use with stm32_setleds() */
#define BOARD_LED1_BIT (1 << BOARD_LED1)
#define BOARD_LED2_BIT (1 << BOARD_LED2)
#define BOARD_LED1_BIT (1 << BOARD_LED1)
#define BOARD_LED2_BIT (1 << BOARD_LED2)
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on board the
* STM32L-Discovery. The following definitions describe how NuttX controls the LEDs:
@ -198,14 +208,14 @@
* LED_IDLE STM32 is is sleep mode Not used
*/
#define LED_STARTED 0
#define LED_HEAPALLOCATE 0
#define LED_IRQSENABLED 0
#define LED_STACKCREATED 1
#define LED_INIRQ 2
#define LED_SIGNAL 2
#define LED_ASSERTION 2
#define LED_PANIC 3
#define LED_STARTED 0
#define LED_HEAPALLOCATE 0
#define LED_IRQSENABLED 0
#define LED_STACKCREATED 1
#define LED_INIRQ 2
#define LED_SIGNAL 2
#define LED_ASSERTION 2
#define LED_PANIC 3
/* Button definitions ***************************************************************/
/* The STM32L-Discovery supports two buttons; only one button is controllable by
@ -215,13 +225,12 @@
* B2 RESET: pushbutton connected to NRST is used to RESET the STM32L152RBT6.
*/
#define BUTTON_USER 0
#define BUTTON_USER 0
#define NUM_BUTTONS 1
#define NUM_BUTTONS 1
#define BUTTON_USER_BIT (1 << BUTTON_USER)
#define BUTTON_USER_BIT (1 << BUTTON_USER)
/* Alternat Pin Functions **********************************************************/
/* Alternate Pin Functions **********************************************************/
/* The STM32L-Discovery has no on-board RS-232 driver. Further, there are no USART
* pins that do not conflict with the on board resources, in particular, the LCD:
* Most USART pins are available if the LCD is enabled; USART2 may be used if either
@ -244,25 +253,25 @@
#if !defined(CONFIG_STM32_LCD)
/* Select PA9 and PA10 if the LCD is not enabled */
# define GPIO_USART1_RX GPIO_USART1_RX_1
# define GPIO_USART1_TX GPIO_USART1_TX_1
# define GPIO_USART1_RX GPIO_USART1_RX_1
# define GPIO_USART1_TX GPIO_USART1_TX_1
/* This there are no other options for USART1 on this part */
# define GPIO_USART2_RX GPIO_USART2_RX_1
# define GPIO_USART2_TX GPIO_USART2_TX_1
# define GPIO_USART2_RX GPIO_USART2_RX_1
# define GPIO_USART2_TX GPIO_USART2_TX_1
/* Arbirtrarily select PB10 and PB11 */
# define GPIO_USART3_RX GPIO_USART3_RX_1
# define GPIO_USART3_TX GPIO_USART3_TX_1
# define GPIO_USART3_RX GPIO_USART3_RX_1
# define GPIO_USART3_TX GPIO_USART3_TX_1
#elif !defined(CONFIG_ARCH_LEDS)
/* Select PB6 and PB7 if the LEDs are not enabled */
# define GPIO_USART1_RX GPIO_USART1_RX_2
# define GPIO_USART1_TX GPIO_USART1_TX_2
# define GPIO_USART1_RX GPIO_USART1_RX_2
# define GPIO_USART1_TX GPIO_USART1_TX_2
#endif

2
configs/stm32ldiscovery/nsh/defconfig
View File

@ -266,7 +266,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
#
# Board Settings
#
CONFIG_BOARD_LOOPSPERMSEC=2500
CONFIG_BOARD_LOOPSPERMSEC=2796
# CONFIG_ARCH_CALIBRATION is not set
CONFIG_DRAM_START=0x20000000
CONFIG_DRAM_SIZE=16384