sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

STM32L4 ADC: correct EXTSEL macros

Browse Source
This commit is contained in:
Juha Niskanen 2017-08-22 06:49:48 -06:00 committed by Gregory Nutt
parent 6b1ccef2f9
commit d7ae3d74c3
3 changed files with 200 additions and 133 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

84
arch/arm/src/stm32l4/Kconfig
View File

@ -2585,7 +2585,7 @@ config STM32L4_TIM2_ADC
default n
depends on STM32L4_TIM2 && STM32L4_ADC
---help---
Reserve timer 1 for use by ADC
Reserve timer 2 for use by ADC
Timer devices may be used for different purposes. If STM32L4_TIM2 is
defined then the following may also be defined to indicate that the
@ -2627,7 +2627,7 @@ config STM32L4_TIM3_ADC
default n
depends on STM32L4_TIM3 && STM32L4_ADC
---help---
Reserve timer 1 for use by ADC
Reserve timer 3 for use by ADC
Timer devices may be used for different purposes. If STM32L4_TIM3 is
defined then the following may also be defined to indicate that the
@ -2669,7 +2669,7 @@ config STM32L4_TIM4_ADC
default n
depends on STM32L4_TIM4 && STM32L4_ADC
---help---
Reserve timer 1 for use by ADC
Reserve timer 4 for use by ADC
Timer devices may be used for different purposes. If STM32L4_TIM4 is
defined then the following may also be defined to indicate that the
@ -2706,14 +2706,14 @@ config STM32L4_TIM4_ADC3
endchoice
config STM32L4_TIM5_ADC
bool "TIM5 ADC"
config STM32L4_TIM6_ADC
bool "TIM6 ADC"
default n
depends on STM32L4_TIM5 && STM32L4_ADC
depends on STM32L4_TIM6 && STM32L4_ADC
---help---
Reserve timer 1 for use by ADC
Reserve timer 6 for use by ADC
Timer devices may be used for different purposes. If STM32L4_TIM5 is
Timer devices may be used for different purposes. If STM32L4_TIM6 is
defined then the following may also be defined to indicate that the
timer is intended to be used for ADC conversion. Note that ADC usage
requires two definition: Not only do you have to assign the timer
@ -2721,30 +2721,30 @@ config STM32L4_TIM5_ADC
channel it is assigned to.
choice
prompt "Select TIM5 ADC channel"
default STM32L4_TIM5_ADC1
depends on STM32L4_TIM5_ADC
prompt "Select TIM6 ADC channel"
default STM32L4_TIM6_ADC1
depends on STM32L4_TIM6_ADC
config STM32L4_TIM5_ADC1
bool "TIM5 ADC channel 1"
config STM32L4_TIM6_ADC1
bool "TIM6 ADC channel 1"
depends on STM32L4_ADC1
select HAVE_ADC1_TIMER
---help---
Reserve TIM5 to trigger ADC1
Reserve TIM6 to trigger ADC1
config STM32L4_TIM5_ADC2
bool "TIM5 ADC channel 2"
config STM32L4_TIM6_ADC2
bool "TIM6 ADC channel 2"
depends on STM32L4_ADC2
select HAVE_ADC2_TIMER
---help---
Reserve TIM5 to trigger ADC2
Reserve TIM6 to trigger ADC2
config STM32L4_TIM5_ADC3
bool "TIM5 ADC channel 3"
config STM32L4_TIM6_ADC3
bool "TIM6 ADC channel 3"
depends on STM32L4_ADC3
select HAVE_ADC3_TIMER
---help---
Reserve TIM5 to trigger ADC3
Reserve TIM6 to trigger ADC3
endchoice
@ -2753,7 +2753,7 @@ config STM32L4_TIM8_ADC
default n
depends on STM32L4_TIM8 && STM32L4_ADC
---help---
Reserve timer 1 for use by ADC
Reserve timer 8 for use by ADC
Timer devices may be used for different purposes. If STM32L4_TIM8 is
defined then the following may also be defined to indicate that the
@ -2790,6 +2790,48 @@ config STM32L4_TIM8_ADC3
endchoice
config STM32L4_TIM15_ADC
bool "TIM15 ADC"
default n
depends on STM32L4_TIM15 && STM32L4_ADC
---help---
Reserve timer 15 for use by ADC
Timer devices may be used for different purposes. If STM32L4_TIM15 is
defined then the following may also be defined to indicate that the
timer is intended to be used for ADC conversion. Note that ADC usage
requires two definition: Not only do you have to assign the timer
for used by the ADC, but then you also have to configure which ADC
channel it is assigned to.
choice
prompt "Select TIM15 ADC channel"
default STM32L4_TIM15_ADC1
depends on STM32L4_TIM15_ADC
config STM32L4_TIM15_ADC1
bool "TIM15 ADC channel 1"
depends on STM32L4_ADC1
select HAVE_ADC1_TIMER
---help---
Reserve TIM15 to trigger ADC1
config STM32L4_TIM15_ADC2
bool "TIM15 ADC channel 2"
depends on STM32L4_ADC2
select HAVE_ADC2_TIMER
---help---
Reserve TIM15 to trigger ADC2
config STM32L4_TIM15_ADC3
bool "TIM15 ADC channel 3"
depends on STM32L4_ADC3
select HAVE_ADC3_TIMER
---help---
Reserve TIM15 to trigger ADC3
endchoice
config HAVE_ADC1_TIMER
bool

26
arch/arm/src/stm32l4/chip/stm32l4_adc.h
View File

@ -230,6 +230,30 @@
#define ADC_CFGR_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */
#define ADC_CFGR_EXTSEL_MASK (15 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC_CFGR_EXTSEL(event) ((event) << ADC_CFGR_EXTSEL_SHIFT) /* Event = 0..15 */
# define ADC_CFGR_EXTSEL_T1CC1 (0x0 << ADC_CFGR_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */
# define ADC_CFGR_EXTSEL_T1CC2 (0x01 << ADC_CFGR_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
# define ADC_CFGR_EXTSEL_T1CC3 (0x02 << ADC_CFGR_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
# define ADC_CFGR_EXTSEL_T2CC2 (0x03 << ADC_CFGR_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
# define ADC_CFGR_EXTSEL_T3TRGO (0x04 << ADC_CFGR_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */
# if !defined(CONFIG_STM32L4_STM32L4X3)
# define ADC_CFGR_EXTSEL_T4CC4 (0x05 << ADC_CFGR_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */
# endif
# define ADC_CFGR_EXTSEL_EXTI11 (0x06 << ADC_CFGR_EXTSEL_SHIFT) /* 0110: EXTI line 11 */
# if !defined(CONFIG_STM32L4_STM32L4X3)
# define ADC_CFGR_EXTSEL_T8TRGO (0x07 << ADC_CFGR_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */
# define ADC_CFGR_EXTSEL_T8TRGO2 (0x08 << ADC_CFGR_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */
# endif
# define ADC_CFGR_EXTSEL_T1TRGO (0x09 << ADC_CFGR_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */
# define ADC_CFGR_EXTSEL_T1TRGO2 (0x0a << ADC_CFGR_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */
# define ADC_CFGR_EXTSEL_T2TRGO (0x0b << ADC_CFGR_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */
# if !defined(CONFIG_STM32L4_STM32L4X3)
# define ADC_CFGR_EXTSEL_T4TRGO (0x0c << ADC_CFGR_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */
# endif
# define ADC_CFGR_EXTSEL_T6TRGO (0x0d << ADC_CFGR_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */
# define ADC_CFGR_EXTSEL_T15TRGO (0x0e << ADC_CFGR_EXTSEL_SHIFT) /* 1110: Timer 15 TRGO event */
# if !defined(CONFIG_STM32L4_STM32L4X3)
# define ADC_CFGR_EXTSEL_T3CC4 (0x0f << ADC_CFGR_EXTSEL_SHIFT) /* 1111: Timer 3 CC4 event */
# endif
#define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */
#define ADC_CFGR_EXTEN_MASK (3 << ADC_CFGR_EXTEN_SHIFT)
# define ADC_CFGR_EXTEN_NONE (0 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */
@ -513,7 +537,7 @@
# define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */
# define ADC_CCR_MDMA_MASK (3 << ADC_CCR_MDMA_SHIFT)
# define ADC_CCR_MDMA_DISABLE (0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */
# define ADC_CCR_MDMA_ 10_12 (2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */
# define ADC_CCR_MDMA_10_12 (2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */
# define ADC_CCR_MDMA_6_8 (3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */
#endif
#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */

223
arch/arm/src/stm32l4/stm32l4_adc.h
View File

@ -291,123 +291,124 @@
* to this simplification.
*/
#define ADC1_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1
#define ADC1_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2
#define ADC1_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3
#define ADC1_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4
#define ADC1_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO
#define ADC1_EXTSEL_T1TRGO2 ADC_CR2_EXTSEL_T1TRGO2
#define ADC2_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1
#define ADC2_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2
#define ADC2_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3
#define ADC2_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4
#define ADC2_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO
#define ADC2_EXTSEL_T1TRGO2 ADC_CR2_EXTSEL_T1TRGO2
#define ADC3_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1
#define ADC3_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2
#define ADC3_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3
#define ADC3_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4
#define ADC3_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO
#define ADC3_EXTSEL_T1TRGO2 ADC_CR2_EXTSEL_T1TRGO2
#define ADC1_EXTSEL_T1CC1 ADC_CFGR_EXTSEL_T1CC1
#define ADC1_EXTSEL_T1CC2 ADC_CFGR_EXTSEL_T1CC2
#define ADC1_EXTSEL_T1CC3 ADC_CFGR_EXTSEL_T1CC3
#define ADC1_EXTSEL_T1CC4 ADC_CFGR_EXTSEL_T1CC4
#define ADC1_EXTSEL_T1TRGO ADC_CFGR_EXTSEL_T1TRGO
#define ADC1_EXTSEL_T1TRGO2 ADC_CFGR_EXTSEL_T1TRGO2
#define ADC2_EXTSEL_T1CC1 ADC_CFGR_EXTSEL_T1CC1
#define ADC2_EXTSEL_T1CC2 ADC_CFGR_EXTSEL_T1CC2
#define ADC2_EXTSEL_T1CC3 ADC_CFGR_EXTSEL_T1CC3
#define ADC2_EXTSEL_T1CC4 ADC_CFGR_EXTSEL_T1CC4
#define ADC2_EXTSEL_T1TRGO ADC_CFGR_EXTSEL_T1TRGO
#define ADC2_EXTSEL_T1TRGO2 ADC_CFGR_EXTSEL_T1TRGO2
#define ADC3_EXTSEL_T1CC1 ADC_CFGR_EXTSEL_T1CC1
#define ADC3_EXTSEL_T1CC2 ADC_CFGR_EXTSEL_T1CC2
#define ADC3_EXTSEL_T1CC3 ADC_CFGR_EXTSEL_T1CC3
#define ADC3_EXTSEL_T1CC4 ADC_CFGR_EXTSEL_T1CC4
#define ADC3_EXTSEL_T1TRGO ADC_CFGR_EXTSEL_T1TRGO
#define ADC3_EXTSEL_T1TRGO2 ADC_CFGR_EXTSEL_T1TRGO2
#define ADC1_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1
#define ADC1_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2
#define ADC1_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3
#define ADC1_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4
#define ADC1_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO
#define ADC2_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1
#define ADC2_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2
#define ADC2_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3
#define ADC2_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4
#define ADC2_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO
#define ADC3_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1
#define ADC3_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2
#define ADC3_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3
#define ADC3_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4
#define ADC3_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO
#define ADC1_EXTSEL_T2CC1 ADC_CFGR_EXTSEL_T2CC1
#define ADC1_EXTSEL_T2CC2 ADC_CFGR_EXTSEL_T2CC2
#define ADC1_EXTSEL_T2CC3 ADC_CFGR_EXTSEL_T2CC3
#define ADC1_EXTSEL_T2CC4 ADC_CFGR_EXTSEL_T2CC4
#define ADC1_EXTSEL_T2TRGO ADC_CFGR_EXTSEL_T2TRGO
#define ADC2_EXTSEL_T2CC1 ADC_CFGR_EXTSEL_T2CC1
#define ADC2_EXTSEL_T2CC2 ADC_CFGR_EXTSEL_T2CC2
#define ADC2_EXTSEL_T2CC3 ADC_CFGR_EXTSEL_T2CC3
#define ADC2_EXTSEL_T2CC4 ADC_CFGR_EXTSEL_T2CC4
#define ADC2_EXTSEL_T2TRGO ADC_CFGR_EXTSEL_T2TRGO
#define ADC3_EXTSEL_T2CC1 ADC_CFGR_EXTSEL_T2CC1
#define ADC3_EXTSEL_T2CC2 ADC_CFGR_EXTSEL_T2CC2
#define ADC3_EXTSEL_T2CC3 ADC_CFGR_EXTSEL_T2CC3
#define ADC3_EXTSEL_T2CC4 ADC_CFGR_EXTSEL_T2CC4
#define ADC3_EXTSEL_T2TRGO ADC_CFGR_EXTSEL_T2TRGO
#define ADC1_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1
#define ADC1_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2
#define ADC1_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3
#define ADC1_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4
#define ADC1_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO
#define ADC2_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1
#define ADC2_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2
#define ADC2_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3
#define ADC2_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4
#define ADC2_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO
#define ADC3_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1
#define ADC3_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2
#define ADC3_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3
#define ADC3_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4
#define ADC3_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO
#define ADC1_EXTSEL_T3CC1 ADC_CFGR_EXTSEL_T3CC1
#define ADC1_EXTSEL_T3CC2 ADC_CFGR_EXTSEL_T3CC2
#define ADC1_EXTSEL_T3CC3 ADC_CFGR_EXTSEL_T3CC3
#define ADC1_EXTSEL_T3CC4 ADC_CFGR_EXTSEL_T3CC4
#define ADC1_EXTSEL_T3TRGO ADC_CFGR_EXTSEL_T3TRGO
#define ADC2_EXTSEL_T3CC1 ADC_CFGR_EXTSEL_T3CC1
#define ADC2_EXTSEL_T3CC2 ADC_CFGR_EXTSEL_T3CC2
#define ADC2_EXTSEL_T3CC3 ADC_CFGR_EXTSEL_T3CC3
#define ADC2_EXTSEL_T3CC4 ADC_CFGR_EXTSEL_T3CC4
#define ADC2_EXTSEL_T3TRGO ADC_CFGR_EXTSEL_T3TRGO
#define ADC3_EXTSEL_T3CC1 ADC_CFGR_EXTSEL_T3CC1
#define ADC3_EXTSEL_T3CC2 ADC_CFGR_EXTSEL_T3CC2
#define ADC3_EXTSEL_T3CC3 ADC_CFGR_EXTSEL_T3CC3
#define ADC3_EXTSEL_T3CC4 ADC_CFGR_EXTSEL_T3CC4
#define ADC3_EXTSEL_T3TRGO ADC_CFGR_EXTSEL_T3TRGO
#define ADC1_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1
#define ADC1_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2
#define ADC1_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3
#define ADC1_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4
#define ADC1_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO
#define ADC2_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1
#define ADC2_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2
#define ADC2_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3
#define ADC2_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4
#define ADC2_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO
#define ADC3_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1
#define ADC3_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2
#define ADC3_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3
#define ADC3_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4
#define ADC3_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO
#define ADC1_EXTSEL_T4CC1 ADC_CFGR_EXTSEL_T4CC1
#define ADC1_EXTSEL_T4CC2 ADC_CFGR_EXTSEL_T4CC2
#define ADC1_EXTSEL_T4CC3 ADC_CFGR_EXTSEL_T4CC3
#define ADC1_EXTSEL_T4CC4 ADC_CFGR_EXTSEL_T4CC4
#define ADC1_EXTSEL_T4TRGO ADC_CFGR_EXTSEL_T4TRGO
#define ADC2_EXTSEL_T4CC1 ADC_CFGR_EXTSEL_T4CC1
#define ADC2_EXTSEL_T4CC2 ADC_CFGR_EXTSEL_T4CC2
#define ADC2_EXTSEL_T4CC3 ADC_CFGR_EXTSEL_T4CC3
#define ADC2_EXTSEL_T4CC4 ADC_CFGR_EXTSEL_T4CC4
#define ADC2_EXTSEL_T4TRGO ADC_CFGR_EXTSEL_T4TRGO
#define ADC3_EXTSEL_T4CC1 ADC_CFGR_EXTSEL_T4CC1
#define ADC3_EXTSEL_T4CC2 ADC_CFGR_EXTSEL_T4CC2
#define ADC3_EXTSEL_T4CC3 ADC_CFGR_EXTSEL_T4CC3
#define ADC3_EXTSEL_T4CC4 ADC_CFGR_EXTSEL_T4CC4
#define ADC3_EXTSEL_T4TRGO ADC_CFGR_EXTSEL_T4TRGO
#define ADC1_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1
#define ADC1_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2
#define ADC1_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3
#define ADC1_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4
#define ADC1_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO
#define ADC2_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1
#define ADC2_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2
#define ADC2_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3
#define ADC2_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4
#define ADC2_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO
#define ADC3_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1
#define ADC3_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2
#define ADC3_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3
#define ADC3_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4
#define ADC3_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO
#define ADC1_EXTSEL_T6CC1 ADC_CFGR_EXTSEL_T6CC1
#define ADC1_EXTSEL_T6CC2 ADC_CFGR_EXTSEL_T6CC2
#define ADC1_EXTSEL_T6CC3 ADC_CFGR_EXTSEL_T6CC3
#define ADC1_EXTSEL_T6CC4 ADC_CFGR_EXTSEL_T6CC4
#define ADC1_EXTSEL_T6TRGO ADC_CFGR_EXTSEL_T6TRGO
#define ADC2_EXTSEL_T6CC1 ADC_CFGR_EXTSEL_T6CC1
#define ADC2_EXTSEL_T6CC2 ADC_CFGR_EXTSEL_T6CC2
#define ADC2_EXTSEL_T6CC3 ADC_CFGR_EXTSEL_T6CC3
#define ADC2_EXTSEL_T6CC4 ADC_CFGR_EXTSEL_T6CC4
#define ADC2_EXTSEL_T6TRGO ADC_CFGR_EXTSEL_T6TRGO
#define ADC3_EXTSEL_T6CC1 ADC_CFGR_EXTSEL_T6CC1
#define ADC3_EXTSEL_T6CC2 ADC_CFGR_EXTSEL_T6CC2
#define ADC3_EXTSEL_T6CC3 ADC_CFGR_EXTSEL_T6CC3
#define ADC3_EXTSEL_T6CC4 ADC_CFGR_EXTSEL_T6CC4
#define ADC3_EXTSEL_T6TRGO ADC_CFGR_EXTSEL_T6TRGO
#define ADC1_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1
#define ADC1_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2
#define ADC1_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3
#define ADC1_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4
#define ADC1_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO
#define ADC2_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1
#define ADC2_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2
#define ADC2_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3
#define ADC2_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4
#define ADC2_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO
#define ADC3_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1
#define ADC3_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2
#define ADC3_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3
#define ADC3_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4
#define ADC3_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO
#define ADC1_EXTSEL_T8CC1 ADC_CFGR_EXTSEL_T8CC1
#define ADC1_EXTSEL_T8CC2 ADC_CFGR_EXTSEL_T8CC2
#define ADC1_EXTSEL_T8CC3 ADC_CFGR_EXTSEL_T8CC3
#define ADC1_EXTSEL_T8CC4 ADC_CFGR_EXTSEL_T8CC4
#define ADC1_EXTSEL_T8TRGO ADC_CFGR_EXTSEL_T8TRGO
#define ADC1_EXTSEL_T8TRGO2 ADC_CFGR_EXTSEL_T8TRGO2
#define ADC2_EXTSEL_T8CC1 ADC_CFGR_EXTSEL_T8CC1
#define ADC2_EXTSEL_T8CC2 ADC_CFGR_EXTSEL_T8CC2
#define ADC2_EXTSEL_T8CC3 ADC_CFGR_EXTSEL_T8CC3
#define ADC2_EXTSEL_T8CC4 ADC_CFGR_EXTSEL_T8CC4
#define ADC2_EXTSEL_T8TRGO ADC_CFGR_EXTSEL_T8TRGO
#define ADC2_EXTSEL_T8TRGO2 ADC_CFGR_EXTSEL_T8TRGO2
#define ADC3_EXTSEL_T8CC1 ADC_CFGR_EXTSEL_T8CC1
#define ADC3_EXTSEL_T8CC2 ADC_CFGR_EXTSEL_T8CC2
#define ADC3_EXTSEL_T8CC3 ADC_CFGR_EXTSEL_T8CC3
#define ADC3_EXTSEL_T8CC4 ADC_CFGR_EXTSEL_T8CC4
#define ADC3_EXTSEL_T8TRGO ADC_CFGR_EXTSEL_T8TRGO
#define ADC3_EXTSEL_T8TRGO2 ADC_CFGR_EXTSEL_T8TRGO2
#define ADC1_EXTSEL_T15CC1 ADC_CFGR_EXTSEL_T15CC1
#define ADC1_EXTSEL_T15CC2 ADC_CFGR_EXTSEL_T15CC2
#define ADC1_EXTSEL_T15CC3 ADC_CFGR_EXTSEL_T15CC3
#define ADC1_EXTSEL_T15CC4 ADC_CFGR_EXTSEL_T15CC4
#define ADC1_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO
#define ADC2_EXTSEL_T15CC1 ADC_CFGR_EXTSEL_T15CC1
#define ADC2_EXTSEL_T15CC2 ADC_CFGR_EXTSEL_T15CC2
#define ADC2_EXTSEL_T15CC3 ADC_CFGR_EXTSEL_T15CC3
#define ADC2_EXTSEL_T15CC4 ADC_CFGR_EXTSEL_T15CC4
#define ADC2_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO
#define ADC3_EXTSEL_T15CC1 ADC_CFGR_EXTSEL_T15CC1
#define ADC3_EXTSEL_T15CC2 ADC_CFGR_EXTSEL_T15CC2
#define ADC3_EXTSEL_T15CC3 ADC_CFGR_EXTSEL_T15CC3
#define ADC3_EXTSEL_T15CC4 ADC_CFGR_EXTSEL_T15CC4
#define ADC3_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO
#define ADC1_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1
#define ADC1_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2
#define ADC1_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3
#define ADC1_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4
#define ADC1_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO
#define ADC1_EXTSEL_T8TRGO2 ADC_CR2_EXTSEL_T8TRGO2
#define ADC2_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1
#define ADC2_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2
#define ADC2_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3
#define ADC2_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4
#define ADC2_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO
#define ADC2_EXTSEL_T8TRGO2 ADC_CR2_EXTSEL_T8TRGO2
#define ADC3_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1
#define ADC3_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2
#define ADC3_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3
#define ADC3_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4
#define ADC3_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO
#define ADC3_EXTSEL_T8TRGO2 ADC_CR2_EXTSEL_T8TRGO2
#if defined(CONFIG_STM32L4_TIM1_ADC1)
# if CONFIG_STM32L4_ADC1_TIMTRIG == 0