SAMA5D4: Fix some memory remapping issues; updates to comments and README files

arch/arm/include/sama5/chip.h

@@ -133,8 +133,10 @@
  * - Some parts support a Video Decoder (SAMA5D43 and SAMA5D44)
  * - Includes an L2 data cache, NEON FPU, and TrustZone
  * - New XDMAC DMA controller
- * - There are few differences in the support peripherals (Gigbit Ethernet is not supported,
+ * - There are few differences in the support peripherals.  As examples:
- *   for example)
+ *   Gigbit Ethernet is not supported, for example; 10/100Base-T Ethernet
+ *   is different.  Additional instances of peripherals:  USART4, TWI3,
+ *   and SPI2.
  */
 
 #elif defined(CONFIG_ARCH_CHIP_ATSAMA5D41) || defined(CONFIG_ARCH_CHIP_ATSAMA5D42) || \

arch/arm/src/sama5/sam_dmac.h

@@ -66,6 +66,8 @@
 
 /* Configurable properties of the channel */
 
+#if defined(ATSAMA5D3)
+
 #  define DMACH_FLAG_BURST_LARGEST            0  /* Largest length AHB burst */
 #  define DMACH_FLAG_BURST_HALF               1  /* Half FIFO size */
 #  define DMACH_FLAG_BURST_SINGLE             2  /* Single AHB access */
@@ -78,6 +80,62 @@
 
 /* Peripheral endpoint characteristics */
 
+#  define DMACH_FLAG_PERIPHPID_SHIFT          (2)       /* Bits 0-6: Peripheral PID */
+#  define DMACH_FLAG_PERIPHPID_MASK           (0x7f << DMACH_FLAG_PERIPHPID_SHIFT)
+#  define DMACH_FLAG_PERIPHH2SEL              (1 << 7)  /* Bits 7: HW handshaking */
+#  define DMACH_FLAG_PERIPHISPERIPH           (1 << 8)  /* Bits 8: 0=memory; 1=peripheral */
+#  define DMACH_FLAG_PERIPHAHB_SHIFT          (9)       /* Bits 9-10: Peripheral ABH layer number */
+#  define DMACH_FLAG_PERIPHAHB_MASK           (3 << DMACH_FLAG_PERIPHAHB_SHIFT)
+#    define DMACH_FLAG_PERIPHAHB_AHB_IF0      (0 << DMACH_FLAG_PERIPHAHB_SHIFT) /* AHB-Lite Interface 0 */
+#    define DMACH_FLAG_PERIPHAHB_AHB_IF1      (1 << DMACH_FLAG_PERIPHAHB_SHIFT) /* AHB-Lite Interface 1 */
+#    define DMACH_FLAG_PERIPHAHB_AHB_IF2      (2 << DMACH_FLAG_PERIPHAHB_SHIFT) /* AHB-Lite Interface 2 */
+#  define DMACH_FLAG_PERIPHWIDTH_SHIFT        (11)      /* Bits 11-12: Peripheral width */
+#  define DMACH_FLAG_PERIPHWIDTH_MASK         (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT)
+#    define DMACH_FLAG_PERIPHWIDTH_8BITS      (0 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 8 bits */
+#    define DMACH_FLAG_PERIPHWIDTH_16BITS     (1 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 16 bits */
+#    define DMACH_FLAG_PERIPHWIDTH_32BITS     (2 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 32 bits */
+#    define DMACH_FLAG_PERIPHWIDTH_64BITS     (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 64 bits */
+#  define DMACH_FLAG_PERIPHINCREMENT          (1 << 13) /* Bit 13: Autoincrement peripheral address */
+#  define DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT    (14)      /* Bits 14-15: Peripheral chunk size */
+#  define DMACH_FLAG_PERIPHCHUNKSIZE_MASK     (3 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT)
+#    define DMACH_FLAG_PERIPHCHUNKSIZE_1      (0 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) /* Peripheral chunksize=1 */
+#    define DMACH_FLAG_PERIPHCHUNKSIZE_4      (1 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) /* Peripheral chunksize=4 */
+#    define DMACH_FLAG_PERIPHCHUNKSIZE_8      (3 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) /* Peripheral chunksize=8 */
+#    define DMACH_FLAG_PERIPHCHUNKSIZE_16     (4 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) /* Peripheral chunksize=16 */
+
+/* Memory endpoint characteristics */
+
+#  define DMACH_FLAG_MEMPID_SHIFT             (16)      /* Bits 16-22: Memory PID */
+#  define DMACH_FLAG_MEMPID_MASK              (0x75 << DMACH_FLAG_MEMPID_SHIFT)
+#  define DMACH_FLAG_MEMH2SEL                 (1 << 23) /* Bits 23: HW handshaking */
+#  define DMACH_FLAG_MEMISPERIPH              (1 << 24) /* Bits 24: 0=memory; 1=peripheral */
+#  define DMACH_FLAG_MEMAHB_SHIFT             (25)      /* Bits 25-26: Peripheral ABH layer number */
+#  define DMACH_FLAG_MEMAHB_MASK              (3 << DMACH_FLAG_MEMAHB_SHIFT)
+#    define DMACH_FLAG_MEMAHB_AHB_IF0         (0 << DMACH_FLAG_MEMAHB_SHIFT) /* AHB-Lite Interface 0 */
+#    define DMACH_FLAG_MEMAHB_AHB_IF1         (1 << DMACH_FLAG_MEMAHB_SHIFT) /* AHB-Lite Interface 1 */
+#    define DMACH_FLAG_MEMAHB_AHB_IF2         (2 << DMACH_FLAG_MEMAHB_SHIFT) /* AHB-Lite Interface 2 */
+#  define DMACH_FLAG_MEMWIDTH_SHIFT           (27)      /* Bits 27-28: Memory width */
+#  define DMACH_FLAG_MEMWIDTH_MASK            (3 << DMACH_FLAG_MEMWIDTH_SHIFT)
+#    define DMACH_FLAG_MEMWIDTH_8BITS         (0 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 8 bits */
+#    define DMACH_FLAG_MEMWIDTH_16BITS        (1 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 16 bits */
+#    define DMACH_FLAG_MEMWIDTH_32BITS        (2 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 32 bits */
+#    define DMACH_FLAG_MEMWIDTH_64BITS        (3 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 64 bits */
+#  define DMACH_FLAG_MEMINCREMENT             (1 << 29) /* Bit 29: Autoincrement memory address */
+#  define DMACH_FLAG_MEMCHUNKSIZE_SHIFT       (30)      /* Bit 30-31: Memory chunk size */
+#  define DMACH_FLAG_MEMCHUNKSIZE_MASK        (3 << DMACH_FLAG_MEMCHUNKSIZE_SHIFT)
+#    define DMACH_FLAG_MEMCHUNKSIZE_1         (0 << DMACH_FLAG_MEMCHUNKSIZE_SHIFT) /* Peripheral chunksize = 1 */
+#    define DMACH_FLAG_MEMCHUNKSIZE_4         (1 << DMACH_FLAG_MEMCHUNKSIZE_SHIFT) /* Peripheral chunksize = 4 */
+#    define DMACH_FLAG_MEMCHUNKSIZE_8         (3 << DMACH_FLAG_MEMCHUNKSIZE_SHIFT) /* Peripheral chunksize = 8 */
+#    define DMACH_FLAG_MEMCHUNKSIZE_16        (4 << DMACH_FLAG_MEMCHUNKSIZE_SHIFT) /* Peripheral chunksize = 16 */
+
+#elif defined(ATSAMA5D4)
+
+#  define DMACH_FLAG_FIFOCFG_LARGEST        (0) /* Not used */
+#  define DMACH_FLAG_FIFOCFG_HALF           (0) /* Not used */
+#  define DMACH_FLAG_FIFOCFG_SINGLE         (0) /* Not used */
+
+/* Peripheral endpoint characteristics */
+
 #  define DMACH_FLAG_PERIPHPID_SHIFT          (2)       /* Bits 2-7: Peripheral PID */
 #  define DMACH_FLAG_PERIPHPID_MASK           (63 << DMACH_FLAG_PERIPHPID_SHIFT)
 #  define DMACH_FLAG_PERIPHH2SEL              (1 << 8)  /* Bits 8: HW handshaking */
@@ -126,6 +184,8 @@
 #    define DMACH_FLAG_MEMCHUNKSIZE_8         (3 << DMACH_FLAG_MEMCHUNKSIZE_SHIFT) /* Peripheral chunksize = 8 */
 #    define DMACH_FLAG_MEMCHUNKSIZE_16        (4 << DMACH_FLAG_MEMCHUNKSIZE_SHIFT) /* Peripheral chunksize = 16 */
 
+#endif /* ATSAMA5D4 */
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/

arch/arm/src/sama5/sam_irq.c

@@ -54,6 +54,7 @@
 #  include "sam_pio.h"
 #endif
 
+#include "chip.h"
 #include "mmu.h"
 #include "cache.h"
 #include "sctlr.h"
@@ -377,11 +378,13 @@ void up_irqinitialize(void)
    * address 0x0000:0000 in that case anyway.
    */
 
+#ifdef ATSAMA5D3
   putreg32(MATRIX_MRCR_RCB0, SAM_MATRIX_MRCR);   /* Enable Cortex-A5 remap */
+#endif
 
 #if defined(CONFIG_SAMA5_BOOT_ISRAM)
   putreg32(AXIMX_REMAP_REMAP0, SAM_AXIMX_REMAP); /* Remap SRAM */
-#else /* elif defined(CONFIG_SAMA5_BOOT_CS0FLASH) */
+#elif defined(ATSAMA5D3) /* && defined(CONFIG_SAMA5_BOOT_CS0FLASH) */
   putreg32(AXIMX_REMAP_REMAP1, SAM_AXIMX_REMAP); /* Remap NOR FLASH on CS0 */
 #endif
 

configs/sama5d4-ek/README.txt

@@ -872,9 +872,11 @@ Buttons and LEDs
 Serial Console
 ==============
 
-  Two UARTs are available:
+  Two UART ports are available:
+
+  Virtual COM / DBGU Port (J24).  Either may be driven by USART3, depending
+  upon the setting of JP19 and JP20:
 
-  USART3 Virtual Com
   ------------------------------ ------------------- -------------------------
   SAMA5D4 PIO                    SIGNAL              USAGE
   ------------------------------ ------------------- -------------------------
@@ -882,8 +884,12 @@ Serial Console
   PE17/A17/TXD3/TCLK0            DBGU_TXD3_PE17      DBGU_TXD3 (See JP20)
   ------------------------------ ------------------- -------------------------
 
-  Connects to the SAM3U which will, in turn, provide the serial output on a
+  In one jumper position UART3 connects to the SAM3U which will, in turn,
-  virual COM port.  JP19 and JP20 can disconnect USART3 from the SAM3U.
+  provide the serial output over a USB virtual COM port.  In other other
+  jumper position, UART3 will connect the RS-232 port labelled DBGU (J24).
+
+  I personally prefer the RS-2323 port because my terminal software does not
+  lose the USB Virtual COM everytime I reset or power-cycle the board.
 
   USART4 TTL-Level
   ------------------------------ ------------------- -------------------------
@@ -900,9 +906,9 @@ Serial Console
   - VCC_3V3 is also available at Expansion Interface, J19B pins 21 and 22
   - GND is available J19A pin 11, J19B pin 31, and J19C pin 51
 
-  By default the DBGU/USART3 is used as the NuttX serial console in all
+  By default the RS-232 DBGU port on USART3 is used as the NuttX serial
-  configurations (unless otherwise noted).  USART4, however, is the more
+  console in all configurations (unless otherwise noted).  USART4, however,
-  convenient USART to use during board bring-up.
+  is the also available.
 
 Networking
 ==========