From d80d6b87740e08d18dd5d4b61352ca7c1d48dc19 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 19 Dec 2019 15:40:56 +0000 Subject: [PATCH] Merged in raiden00/nuttx_nrf52 (pull request #1098) nrf52 updates arch/arm/nrf52: add more options to Kconfig arch/arm/nrf52: cosmetics changes to some files arch/arm/nrf52: nfct, radio, twi, spi registers definitions arch/arm/nrf52: fix warnings in nrf52_gpio.c Approved-by: Gregory Nutt --- arch/arm/include/nrf52/chip.h | 1 + arch/arm/include/nrf52/nrf52_irq.h | 16 +- arch/arm/src/nrf52/Kconfig | 125 +++- arch/arm/src/nrf52/hardware/nrf52_clock.h | 53 +- arch/arm/src/nrf52/hardware/nrf52_memorymap.h | 167 ++--- arch/arm/src/nrf52/hardware/nrf52_nfc.h | 150 +++++ arch/arm/src/nrf52/hardware/nrf52_radio.h | 587 ++++++++++++++++++ arch/arm/src/nrf52/hardware/nrf52_spi.h | 253 ++++++++ arch/arm/src/nrf52/hardware/nrf52_twi.h | 201 ++++++ arch/arm/src/nrf52/hardware/nrf52_uarte.h | 306 +++++++-- arch/arm/src/nrf52/hardware/nrf52_wdt.h | 4 +- arch/arm/src/nrf52/nrf52_allocateheap.c | 2 + arch/arm/src/nrf52/nrf52_flash.c | 1 - arch/arm/src/nrf52/nrf52_gpio.c | 19 +- arch/arm/src/nrf52/nrf52_lowputc.c | 35 +- arch/arm/src/nrf52/nrf52_lowputc.h | 4 +- arch/arm/src/nrf52/nrf52_serial.c | 94 ++- arch/arm/src/nrf52/nrf52_wdt.c | 17 +- boards/arm/nrf52/nrf52840-dk/include/board.h | 8 + 19 files changed, 1832 insertions(+), 211 deletions(-) create mode 100644 arch/arm/src/nrf52/hardware/nrf52_nfc.h create mode 100644 arch/arm/src/nrf52/hardware/nrf52_radio.h create mode 100644 arch/arm/src/nrf52/hardware/nrf52_spi.h create mode 100644 arch/arm/src/nrf52/hardware/nrf52_twi.h diff --git a/arch/arm/include/nrf52/chip.h b/arch/arm/include/nrf52/chip.h index 43a2e8a4c9..d0f055f39b 100644 --- a/arch/arm/include/nrf52/chip.h +++ b/arch/arm/include/nrf52/chip.h @@ -47,6 +47,7 @@ *********************************************************************************** /* NVIC priority levels *************************************************************/ + /* Each priority field holds a priority value, 0-31. The lower the value, the greater * the priority of the corresponding interrupt. * diff --git a/arch/arm/include/nrf52/nrf52_irq.h b/arch/arm/include/nrf52/nrf52_irq.h index 641aa9bb51..3d3a23426b 100644 --- a/arch/arm/include/nrf52/nrf52_irq.h +++ b/arch/arm/include/nrf52/nrf52_irq.h @@ -87,15 +87,17 @@ #define NRF52_IRQ_FPU (NRF52_IRQ_EXTINT+38) /* FPU interrupt */ #if defined(CONFIG_ARCH_FAMILY_NRF52840) -#define NRF52_IRQ_USBD (NRF52_IRQ_EXTINT+39) /* USB device */ -#define NRF52_IRQ_UARTE1 (NRF52_IRQ_EXTINT+40) /* UARTE 1 */ -#define NRF52_IRQ_QSPI (NRF52_IRQ_EXTINT+41) /* Quad SPI */ -#define NRF52_IRQ_PWM3 (NRF52_IRQ_EXTINT+45) /* Pulse Width Modulation Unit 3 */ -#define NRF52_IRQ_SPIM3 (NRF52_IRQ_EXTINT+47) /* SPI Master 3 */ +# define NRF52_IRQ_USBD (NRF52_IRQ_EXTINT+39) /* USB device */ +# define NRF52_IRQ_UART1 (NRF52_IRQ_EXTINT+40) /* UART/UARTE 1 */ +# define NRF52_IRQ_QSPI (NRF52_IRQ_EXTINT+41) /* Quad SPI */ +# define NRF52_IRQ_PWM3 (NRF52_IRQ_EXTINT+45) /* Pulse Width Modulation Unit 3 */ +# define NRF52_IRQ_SPIM3 (NRF52_IRQ_EXTINT+47) /* SPI Master 3 */ +#endif -#define NRF52_IRQ_NEXTINT (48) +#if defined(CONFIG_ARCH_FAMILY_NRF52840) +# define NRF52_IRQ_NEXTINT (48) #else -#define NRF52_IRQ_NEXTINT (39) +# define NRF52_IRQ_NEXTINT (39) #endif #define NRF52_IRQ_NIRQS (NRF52_IRQ_EXTINT+NRF52_IRQ_NEXTINT) diff --git a/arch/arm/src/nrf52/Kconfig b/arch/arm/src/nrf52/Kconfig index d1fc2cd84d..b7024cde83 100644 --- a/arch/arm/src/nrf52/Kconfig +++ b/arch/arm/src/nrf52/Kconfig @@ -14,15 +14,25 @@ config ARCH_CHIP_NRF52832 bool "NRF52832" select ARCH_FAMILY_NRF52 select ARCH_FAMILY_NRF52832 - #select NRF52_HAVE_I2C_MASTER + +config ARCH_CHIP_NRF52833 + bool "NRF52832" + select ARCH_FAMILY_NRF52 + select ARCH_FAMILY_NRF52833 + select NRF52_HAVE_UART1 + select NRF52_HAVE_PORT1 + select NRF52_HAVE_SPI3_MASTER + select NRF52_HAVE_USBDEV config ARCH_CHIP_NRF52840 bool "NRF52840" select ARCH_FAMILY_NRF52 select ARCH_FAMILY_NRF52840 - #select NRF52_HAVE_I2C_MASTER select NRF52_HAVE_UART1 select NRF52_HAVE_PORT1 + select NRF52_HAVE_SPI3_MASTER + select NRF52_HAVE_QSPI + select NRF52_HAVE_USBDEV endchoice # NRF52 Chip Selection @@ -36,20 +46,16 @@ config ARCH_FAMILY_NRF52832 bool default n +config ARCH_FAMILY_NRF52833 + bool + default n + config ARCH_FAMILY_NRF52840 bool default n # Peripheral support -config NRF52_HAVE_I2C_MASTER - bool - default n - -config NRF52_HAVE_SPI_MASTER - bool - default n - config NRF52_HAVE_UART1 bool default n @@ -58,8 +64,28 @@ config NRF52_HAVE_PORT1 bool default n +config NRF52_HAVE_SPI3_MASTER + bool + default n + +config NRF52_HAVE_QSPI + bool + default n + +config NRF52_HAVE_USBDEV + bool + default n + # Peripheral Selection +config NRF52_I2C_MASTER + bool + default n + +config NRF52_SPI_MASTER + bool + default n + config NRF52_UART bool default n @@ -69,12 +95,28 @@ menu "NRF52 Peripheral Selection" config NRF52_I2C0_MASTER bool "I2C0 Master" default n - select NRF52_HAVE_I2C_MASTER + select NRF52_I2C_MASTER config NRF52_I2C1_MASTER bool "I2C1 Master" default n - select NRF52_HAVE_I2C_MASTER + select NRF52_I2C_MASTER + +config NRF52_SPI0_MASTER + bool "SPI0 Master" + default n + select NRF52_SPI_MASTER + +config NRF52_SPI1_MASTER + bool "SPI1 Master" + default n + select NRF52_SPI_MASTER + +config NRF52_SPI3_MASTER + bool "SPI3 Master" + default n + select NRF52_SPI_MASTER + depends on NRF52_HAVE_SPI3_MASTER config NRF52_UART0 bool "UART0" @@ -97,13 +139,70 @@ config NRF52_RNG config NRF52_QSPI bool "QSPI" default n - depends on ARCH_CHIP_NRF52840 + depends on NRF52_HAVE_QSPI config NRF52_WDT bool "Watchdog (WDT)" default n select WATCHDOG +config NRF52_RADIO + bool "RADIO" + default n + +config NRF52_NFCT + bool "NFCT" + default n + +config NRF52_SAADC + bool "SAADC" + default n + +config NRF52_TIMER0 + bool "TIMER0" + default n + +config NRF52_TIMER1 + bool "TIMER1" + default n + +config NRF52_TIMER2 + bool "TIMER2" + default n + +config NRF52_TIMER3 + bool "TIMER3" + default n + +config NRF52_TIMER4 + bool "TIMER4" + default n + +config NRF52_RTC0 + bool "RTC0" + default n + +config NRF52_RTC1 + bool "RTC1" + default n + +config NRF52_RTC2 + bool "RTC2" + default n + +config NRF52_I2S + bool "I2S" + default n + +config NRF52_USBDEV + bool "USB Device" + default n + depends on NRF52_HAVE_USBDEV + +config NRF52_COMP + bool "COMP" + default n + endmenu # NRF52 Peripheral Selection config NRF52_FLASH_PREFETCH diff --git a/arch/arm/src/nrf52/hardware/nrf52_clock.h b/arch/arm/src/nrf52/hardware/nrf52_clock.h index 7501481a14..dd80d0b6a5 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_clock.h +++ b/arch/arm/src/nrf52/hardware/nrf52_clock.h @@ -60,6 +60,10 @@ #define NRF52_CLOCK_EVENTS_LFCLKSTARTED_OFFSET 0x0104 /* LFCLK started */ #define NRF52_CLOCK_EVENTS_DONE_OFFSET 0x010c /* Calibration of LFCLK RC oscillator complete event */ #define NRF52_CLOCK_EVENTS_CTTO_OFFSET 0x0110 /* Calibration timer timeout */ +#ifdef CONFIG_ARCH_CHIP_NRF52840 +# define NRF52_CLOCK_EVENTS_CSTARTED_OFFSET 0x0128 /* Calibration timer has been started */ +# define NRF52_CLOCK_EVENTS_CTSTOPPED_OFFSET 0x012c /* Calibration timer has been stopped */ +#endif #define NRF52_CLOCK_INTENSET_OFFSET 0x0304 /* Enable interrupt */ #define NRF52_CLOCK_INTENCLR_OFFSET 0x0308 /* Disable interrupt */ #define NRF52_CLOCK_HFCLKRUN_OFFSET 0x0408 /* Status indicating that HFCLKSTART task has been triggered */ @@ -68,6 +72,9 @@ #define NRF52_CLOCK_LFCLKSTAT_OFFSET 0x0418 /* LFCLK status */ #define NRF52_CLOCK_LFCLKSRCCOPY_OFFSET 0x041c /* Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ #define NRF52_CLOCK_LFCLKSRC_OFFSET 0x0518 /* Clock source for the LFCLK */ +#ifdef CONFIG_ARCH_CHIP_NRF52840 +# define NRF52_CLOCK_HFXODEBOUNCE_OFFSET 0x0528 /* HFXO debounce time */ +#endif #define NRF52_CLOCK_CTIV_OFFSET 0x0538 /* Calibration timer interval */ #define NRF52_CLOCK_TRACECONFIG_OFFSET 0x055c /* Clocking options for the Trace Port debug interface */ @@ -84,6 +91,10 @@ #define NRF52_CLOCK_EVENTS_LFCLKSTARTED (NRF52_CLOCK_BASE + NRF52_CLOCK_EVENTS_LFCLKSTARTED_OFFSET) #define NRF52_CLOCK_EVENTS_DONE (NRF52_CLOCK_BASE + NRF52_CLOCK_EVENTS_DONE_OFFSET) #define NRF52_CLOCK_EVENTS_CTTO (NRF52_CLOCK_BASE + NRF52_CLOCK_EVENTS_CTTO_OFFSET) +#ifdef CONFIG_ARCH_CHIP_NRF52840 +# define NRF52_CLOCK_EVENTS_CSTARTED (NRF52_CLOCK_BASE + NRF52_CLOCK_EVENTS_CSTARTED_OFFSET) +# define NRF52_CLOCK_EVENTS_CSTOPPED (NRF52_CLOCK_BASE + NRF52_CLOCK_EVENTS_CSTOPPED_OFFSET) +#endif #define NRF52_CLOCK_INTENSET (NRF52_CLOCK_BASE + NRF52_CLOCK_INTENSET_OFFSET) #define NRF52_CLOCK_INTENCLR (NRF52_CLOCK_BASE + NRF52_CLOCK_INTENCLR_OFFSET) #define NRF52_CLOCK_HFCLKRUN (NRF52_CLOCK_BASE + NRF52_CLOCK_HFCLKRUN_OFFSET) @@ -91,10 +102,48 @@ #define NRF52_CLOCK_LFCLKRUN (NRF52_CLOCK_BASE + NRF52_CLOCK_LFCLKRUN_OFFSET) #define NRF52_CLOCK_LFCLKSTAT (NRF52_CLOCK_BASE + NRF52_CLOCK_LFCLKSTAT_OFFSET) #define NRF52_CLOCK_LFCLKSRCCOPY (NRF52_CLOCK_BASE + NRF52_CLOCK_LFCLKSRCCOPY_OFFSET) -#define NRF52_CLOCK_LFCLKSRC (NRF52_CLOCK_BASE + NRF52_CLOCK_LFCLKSRC_OFFSET ) +#define NRF52_CLOCK_LFCLKSRC (NRF52_CLOCK_BASE + NRF52_CLOCK_LFCLKSRC_OFFSET) +#ifdef CONFIG_ARCH_CHIP_NRF52840 +# define NRF52_CLOCK_HFXODEBOUNCE (NRF52_CLOCK_BASE + NRF52_CLOCK_HFXODEBOUNCE_OFFSET) +#endif #define NRF52_CLOCK_CTIV (NRF52_CLOCK_BASE + NRF52_CLOCK_CTIV_OFFSET) #define NRF52_CLOCK_TRACECONFIG (NRF52_CLOCK_BASE + NRF52_CLOCK_TRACECONFIG_OFFSET) /* Register Bitfield Definitions ****************************************************************/ -#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_LCD_H */ +/* HFCLKRUN Register */ + +#define CLOCK_HFCLKRUN_STATUS (1 << 0) /* Bit 0: HFCLSTART task triggered status */ + +/* HFCLKSTAT Register */ + +#define CLOCK_HFCLKSTAT_SRC_SHIFT (0) /* Bit 0: Source of HFCLK */ +#define CLOCK_HFCLKSTAT_SRC_MASK (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) +# define CLOCK_HFCLKSTAT_SRC_RC (0 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b0: 64 MHz internal oscillator (HFINT) */ +# define CLOCK_HFCLKSTAT_SRC_XTAL (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b1: 64 MHz crystal oscilator (HFXO) */ +#define CLOCK_HFCLKSTAT_STATE (1 << 16) /* Bit 16: HFCLK state */ + +/* LFCLKRUN Register */ + +#define CLOCK_LFCLKRUN_STATUS (1 << 0) /* Bit 0: LFCLKSTART task triggered status */ + +/* LFCLKSTAT Register */ + +#define CLOCK_LFCLKSTAT_SRC_SHIFT (0) /* Bits 0-1: Source of LFCLK */ +#define CLOCK_LFCLKSTAT_SRC_MASK (3 << CLOCK_LFCLKSTAT_SRC_SHIFT) +# define CLOCK_LFCLKSTAT_SRC_RC (0 << CLOCK_LFCLKSTAT_SRC_SHIFT) /* 0b0: RC oscillator (LFRC) */ +# define CLOCK_LFCLKSTAT_SRC_XTAL (1 << CLOCK_LFCLKSTAT_SRC_SHIFT) /* 0b1: crystal oscillator (LFXO) */ +# define CLOCK_LFCLKSTAT_SRC_SYNTH (2 << CLOCK_LFCLKSTAT_SRC_SHIFT) /* 0b2: synthesized from HFCLK (LFSYNT) */ +#define CLOCK_LFCLKSTAT_STATE (1 << 16) /* Bit 16: LFCLKSTAT state */ + +/* LFCLKSRC Register */ + +#define CLOCK_LFCLKSRC_SRC_SHIFT (0) /* Bits 0-1: LFRC clock soruce */ +#define CLOCK_LFCLKSRC_SRC_MASK (3 << CLOCK_LFCLKSRC_SRC_SHIFT) +# define CLOCK_LFCLKSRC_SRC_RC (0 << CLOCK_LFCLKSRC_SRC_SHIFT) +# define CLOCK_LFCLKSRC_SRC_RC (1 << CLOCK_LFCLKSRC_SRC_SHIFT) +# define CLOCK_LFCLKSRC_SRC_RC (2 << CLOCK_LFCLKSRC_SRC_SHIFT) +#define CLOCK_LFCLKSRC_BYPASS (1 << 16) /* Bit 16: Enable/disable bypass of LFCLK crystal oscillator */ +#define CLOCK_LFCLKSRC_EXTERNAL (1 << 17) /* Bit 17: Enable/disable external source for LFCLK */ + +#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_CLOCK_H */ diff --git a/arch/arm/src/nrf52/hardware/nrf52_memorymap.h b/arch/arm/src/nrf52/hardware/nrf52_memorymap.h index e32056c692..3673c1629f 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_memorymap.h +++ b/arch/arm/src/nrf52/hardware/nrf52_memorymap.h @@ -48,86 +48,103 @@ /* Memory Map */ -#define NRF52_FLASH_BASE 0x00000000 /* Flash memory Start Address */ -#define NRF52_SRAM_BASE 0x20000000 /* SRAM Start Address */ -#define NRF52_FICR_BASE 0x10000000 /* FICR */ -#define NRF52_UICR_BASE 0x10001000 /* UICR */ -#define NRF52_APB0_BASE 0x40000000 /* APB */ +#define NRF52_FLASH_BASE 0x00000000 /* Flash memory Start Address */ +#define NRF52_SRAM_BASE 0x20000000 /* SRAM Start Address */ +#define NRF52_FICR_BASE 0x10000000 /* FICR */ +#define NRF52_UICR_BASE 0x10001000 /* UICR */ +#define NRF52_APB0_BASE 0x40000000 /* APB */ +#define NRF52_AHB0_BASE 0x50000000 /* AHB */ -#define NRF52_CORTEXM4_BASE 0xe0000000 /* Cortex-M4 Private Peripheral Bus */ +#define NRF52_CORTEXM4_BASE 0xe0000000 /* Cortex-M4 Private Peripheral Bus */ /* APB Peripherals */ -#define NRF52_CLOCK_BASE 0x40000000 -#define NRF52_POWER_BASE 0x40000000 -#define NRF52_BPROT_BASE 0x40000000 -#define NRF52_RADIO_BASE 0x40001000 -#define NRF52_UARTE0_BASE 0x40002000 -#define NRF52_UART0_BASE 0x40002000 -#define NRF52_SPIM0_BASE 0x40003000 -#define NRF52_SPIS0_BASE 0x40003000 -#define NRF52_TWIM0_BASE 0x40003000 -#define NRF52_TWI0_BASE 0x40003000 -#define NRF52_SPI0_BASE 0x40003000 -#define NRF52_TWIS0_BASE 0x40003000 -#define NRF52_SPIM1_BASE 0x40004000 -#define NRF52_TWI1_BASE 0x40004000 -#define NRF52_SPIS1_BASE 0x40004000 -#define NRF52_TWIS1_BASE 0x40004000 -#define NRF52_TWIM1_BASE 0x40004000 -#define NRF52_SPI1_BASE 0x40004000 -#define NRF52_NFCT_BASE 0x40005000 -#define NRF52_GPIOTE_BASE 0x40006000 -#define NRF52_SAADC_BASE 0x40007000 -#define NRF52_TIMER0_BASE 0x40008000 -#define NRF52_TIMER1_BASE 0x40009000 -#define NRF52_TIMER2_BASE 0x4000a000 -#define NRF52_RTC0_BASE 0x4000b000 -#define NRF52_TEMP_BASE 0x4000c000 -#define NRF52_RNG_BASE 0x4000d000 -#define NRF52_ECB_BASE 0x4000e000 -#define NRF52_CCM_BASE 0x4000f000 -#define NRF52_AAR_BASE 0x4000f000 -#define NRF52_WDT_BASE 0x40010000 -#define NRF52_RTC1_BASE 0x40011000 -#define NRF52_QDEC_BASE 0x40012000 -#define NRF52_LPCOMP_BASE 0x40013000 -#define NRF52_COMP_BASE 0x40013000 -#define NRF52_SWI0_BASE 0x40014000 -#define NRF52_EGU0_BASE 0x40014000 -#define NRF52_EGU1_BASE 0x40015000 -#define NRF52_SWI1_BASE 0x40015000 -#define NRF52_SWI2_BASE 0x40016000 -#define NRF52_EGU2_BASE 0x40016000 -#define NRF52_SWI3_BASE 0x40017000 -#define NRF52_EGU3_BASE 0x40017000 -#define NRF52_EGU4_BASE 0x40018000 -#define NRF52_SWI4_BASE 0x40018000 -#define NRF52_SWI5_BASE 0x40019000 -#define NRF52_EGU5_BASE 0x40019000 -#define NRF52_TIMER3_BASE 0x4001a000 -#define NRF52_TIMER4_BASE 0x4001b000 -#define NRF52_PWM0_BASE 0x4001c000 -#define NRF52_PDM_BASE 0x4001d000 -#define NRF52_NVMC_BASE 0x4001e000 -#define NRF52_PPI_BASE 0x4001f000 -#define NRF52_MWU_BASE 0x40020000 -#define NRF52_PWM1_BASE 0x40021000 -#define NRF52_PWM2_BASE 0x40022000 -#define NRF52_SPI2_BASE 0x40023000 -#define NRF52_SPIS2_BASE 0x40023000 -#define NRF52_SPIM2_BASE 0x40023000 -#define NRF52_RTC2_BASE 0x40024000 -#define NRF52_I2S_BASE 0x40025000 -#define NRF52_FPU_BASE 0x40026000 +#define NRF52_CLOCK_BASE 0x40000000 +#define NRF52_POWER_BASE 0x40000000 +#ifdef CONFIG_ARCH_CHIP_NRF52832 +# define NRF52_BPROT_BASE 0x40000000 +#endif +#define NRF52_RADIO_BASE 0x40001000 +#define NRF52_UARTE0_BASE 0x40002000 +#define NRF52_UART0_BASE 0x40002000 +#define NRF52_SPI0_BASE 0x40003000 +#define NRF52_SPIM0_BASE 0x40003000 +#define NRF52_SPIS0_BASE 0x40003000 +#define NRF52_TWI0_BASE 0x40003000 +#define NRF52_TWIM0_BASE 0x40003000 +#define NRF52_TWIS0_BASE 0x40003000 +#define NRF52_SPI1_BASE 0x40004000 +#define NRF52_SPIM1_BASE 0x40004000 +#define NRF52_SPIS1_BASE 0x40004000 +#define NRF52_TWI1_BASE 0x40004000 +#define NRF52_TWIM1_BASE 0x40004000 +#define NRF52_TWIS1_BASE 0x40004000 +#define NRF52_NFCT_BASE 0x40005000 +#define NRF52_GPIOTE_BASE 0x40006000 +#define NRF52_SAADC_BASE 0x40007000 +#define NRF52_TIMER0_BASE 0x40008000 +#define NRF52_TIMER1_BASE 0x40009000 +#define NRF52_TIMER2_BASE 0x4000a000 +#define NRF52_RTC0_BASE 0x4000b000 +#define NRF52_TEMP_BASE 0x4000c000 +#define NRF52_RNG_BASE 0x4000d000 +#define NRF52_ECB_BASE 0x4000e000 +#define NRF52_CCM_BASE 0x4000f000 +#define NRF52_AAR_BASE 0x4000f000 +#define NRF52_WDT_BASE 0x40010000 +#define NRF52_RTC1_BASE 0x40011000 +#define NRF52_QDEC_BASE 0x40012000 +#define NRF52_LPCOMP_BASE 0x40013000 +#define NRF52_COMP_BASE 0x40013000 +#define NRF52_SWI0_BASE 0x40014000 +#define NRF52_EGU0_BASE 0x40014000 +#define NRF52_EGU1_BASE 0x40015000 +#define NRF52_SWI1_BASE 0x40015000 +#define NRF52_SWI2_BASE 0x40016000 +#define NRF52_EGU2_BASE 0x40016000 +#define NRF52_SWI3_BASE 0x40017000 +#define NRF52_EGU3_BASE 0x40017000 +#define NRF52_EGU4_BASE 0x40018000 +#define NRF52_SWI4_BASE 0x40018000 +#define NRF52_SWI5_BASE 0x40019000 +#define NRF52_EGU5_BASE 0x40019000 +#define NRF52_TIMER3_BASE 0x4001a000 +#define NRF52_TIMER4_BASE 0x4001b000 +#define NRF52_PWM0_BASE 0x4001c000 +#define NRF52_PDM_BASE 0x4001d000 +#ifdef CONFIG_ARCH_CHIP_NRF52840 +# define NRF52_ACL_BASE 0x4001e000 +#endif +#define NRF52_NVMC_BASE 0x4001e000 +#define NRF52_PPI_BASE 0x4001f000 +#define NRF52_MWU_BASE 0x40020000 +#define NRF52_PWM1_BASE 0x40021000 +#define NRF52_PWM2_BASE 0x40022000 +#define NRF52_SPI2_BASE 0x40023000 +#define NRF52_SPIS2_BASE 0x40023000 +#define NRF52_SPIM2_BASE 0x40023000 +#define NRF52_RTC2_BASE 0x40024000 +#define NRF52_I2S_BASE 0x40025000 +#define NRF52_FPU_BASE 0x40026000 +#ifdef CONFIG_ARCH_CHIP_NRF52840 +# define NRF52_USBD_BASE 0x40027000 +# define NRF52_UART1_BASE 0x40028000 +# define NRF52_UARTE1_BASE 0x40028000 +# define NRF52_QSPI_BASE 0x40029000 +# define NRF52_PWM3_BASE 0x4002d000 +# define NRF52_SPIM3_BASE 0x4002f000 +#endif -#define NRF52_USBD_BASE 0x40027000 -#define NRF52_UARTE1_BASE 0x40028000 -#define NRF52_QSPI_BASE 0x40029000 -#define NRF52_PWM3_BASE 0x4002d000 -#define NRF52_SPIM3_BASE 0x4002f000 +/* AHB Peripherals */ -#define NRF52_GPIO_P0_BASE 0x50000000 -#define NRF52_GPIO_P1_BASE 0x50003000 +#define NRF52_GPIO_P0_BASE 0x50000000 +#ifdef CONFIG_ARCH_CHIP_NRF52840 +# define NRF52_GPIO_P1_BASE 0x50003000 +#endif + +#ifdef CONFIG_ARCH_CHIP_NRF52840 +# define NRF52_CCHOSTRGF_BASE 0x5002a000 +# define NRF52_CRYPTOCELL_BASE 0x5002a000 +#endif #endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_MEMORYMAP_H */ diff --git a/arch/arm/src/nrf52/hardware/nrf52_nfc.h b/arch/arm/src/nrf52/hardware/nrf52_nfc.h new file mode 100644 index 0000000000..f074100682 --- /dev/null +++ b/arch/arm/src/nrf52/hardware/nrf52_nfc.h @@ -0,0 +1,150 @@ +/************************************************************************************************ + * arch/arm/src/nrf52/hardware/nrf52_nfc.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_NFC_H +#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_NFC_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include +#include "hardware/nrf52_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* Register offsets *****************************************************************************/ + +#define NRF52_NFC_TASKS_ACTIVATE_OFFSET 0x0000 /* Activate NFCT peripheral */ +#define NRF52_NFC_TASKS_DISABLE_OFFSET 0x0004 /* Disable NFCT peripheral */ +#define NRF52_NFC_TASKS_SENSE_OFFSET 0x0008 /* Enable NFC sense field mode */ +#define NRF52_NFC_TASKS_STARTTX_OFFSET 0x000c /* Start transmission of an outgoing frame */ +#define NRF52_NFC_TASKS_ENABLERXDATA_OFFSET 0x001c /* Initializes the EasyDMA for receive */ +#define NRF52_NFC_TASKS_GOIDLE_OFFSET 0x0024 /* Force state machine to IDLE state */ +#define NRF52_NFC_TASKS_GOSLEEP_OFFSET 0x0028 /* Force state machine to SLEEP_A state */ +#define NRF52_NFC_EVENTS_READY_OFFSET 0x0100 /* The NFCT peripheral is ready to receive and send frames */ +#define NRF52_NFC_EVENTS_FIELDDETECTED_OFFSET 0x0104 /* Remote NFC field detected */ +#define NRF52_NFC_EVENTS_FIELDLOST_OFFSET 0x0108 /* Remote NFC field lost */ +#define NRF52_NFC_EVENTS_TXFRAMESTART_OFFSET 0x010c /* Marks the start of the first symbol of a transmitted frame */ +#define NRF52_NFC_EVENTS_TXFRAMEEND_OFFSET 0x0110 /* Marks the end of the last transmitted on-air symbol of a frame */ +#define NRF52_NFC_EVENTS_RXFRAMESTART_OFFSET 0x0114 /* Marks the end of the first symbol of a received frame */ +#define NRF52_NFC_EVENTS_RXFRAMEEND_OFFSET 0x0118 /* Received data has been checked (CRC, parity) and transferred to RAM */ +#define NRF52_NFC_EVENTS_ERROR_OFFSET 0x011c /* NFC error reported */ +#define NRF52_NFC_EVENTS_RXERROR_OFFSET 0x0128 /* NFC RX frame error reported */ +#define NRF52_NFC_EVENTS_ENDRX_OFFSET 0x012c /* RX buffer in Data RAM full */ +#define NRF52_NFC_EVENTS_ENDTX_OFFSET 0x0130 /* Transmission of data in RAM has ended */ +#define NRF52_NFC_EVENTS_ACRSTARTED_OFFSET 0x0138 /* Auto collision resolution process has started */ +#define NRF52_NFC_EVENTS_COLLISION_OFFSET 0x0148 /* NFC auto collision resolution error reported */ +#define NRF52_NFC_EVENTS_SELECTED_OFFSET 0x014c /* NFC auto collision resolution successfully completed */ +#define NRF52_NFC_EVENTS_STARTED_OFFSET 0x0150 /* EasyDMA is ready to receive or send frames */ +#define NRF52_NFC_SHORTS_OFFSET 0x0200 /* Shortcuts between local events and tasks */ +#define NRF52_NFC_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */ +#define NRF52_NFC_INTENSET_OFFSET 0x0304 /* Enable interrupt */ +#define NRF52_NFC_INTENCLR_OFFSET 0x0308 /* Disable interrupt */ +#define NRF52_NFC_ERRORSTATUS_OFFSET 0x0404 /* NFC Error Status register */ +#define NRF52_NFC_FRAMESTATUSRX_OFFSET 0x040c /* Result of last incoming frame */ +#define NRF52_NFC_NFCTAGSTATE_OFFSET 0x0410 /* NFC Tag state register */ +#define NRF52_NFC_SLEEPSTATE_OFFSET 0x0420 /* Sleep state during automatic collision resolution */ +#define NRF52_NFC_FIELDPRESENT_OFFSET 0x043c /* Indicates the presence or not of a valid field */ +#define NRF52_NFC_FRAMEDELAYMIN_OFFSET 0x0504 /* Minimum frame delay */ +#define NRF52_NFC_FRAMEDELAYMAX_OFFSET 0x0508 /* Maximum frame delay */ +#define NRF52_NFC_FRAMEDELAYMODE_OFFSET 0x050c /* Configuration register for the Frame Delay Timer */ +#define NRF52_NFC_PACKETPTR_OFFSET 0x0510 /* Packet pointer for TXD and RXD data storage in Data RAM */ +#define NRF52_NFC_MAXLEN_OFFSET 0x0514 /* Size of the RAM buffer allocated to TXD and RXD data storage each */ +#define NRF52_NFC_TXDFRAMECONFIG_OFFSET 0x0518 /* Configuration of outgoing frames */ +#define NRF52_NFC_TXDAMOUNT_OFFSET 0x051c /* Size of outgoing frame */ +#define NRF52_NFC_RXDFRAMECONFIG_OFFSET 0x0520 /* Configuration of incoming frames */ +#define NRF52_NFC_RXDAMOUNT_OFFSET 0x0524 /* Size of last incoming frame */ +#define NRF52_NFC_NFCID1LAST_OFFSET 0x0590 /* Last NFCID part (4, 7 or 10 bytes ID) */ +#define NRF52_NFC_NFCID2LAST_OFFSET 0x0594 /* Second last NFCID part (7 or 10 bytes ID) */ +#define NRF52_NFC_NFCID3LAST_OFFSET 0x0598 /* Third last NFCID part (10 bytes ID) */ +#define NRF52_NFC_ACRCONFIG_OFFSET 0x059c /* Controls the auto collision resolution function */ +#define NRF52_NFC_SENSRES_OFFSET 0x05a0 /* NFC-A SENS_RES auto-response settings */ +#define NRF52_NFC_SELRES_OFFSET 0x05a4 /* NFC-A SEL_RES auto-response settings */ + +/* Register Addresses ***************************************************************************/ + +#define NRF52_NFC_TASKS_ACTIVATE (NRF52_NFCT_BASE + NRF52_NFC_TASKS_ACTIVATE_OFFSET) +#define NRF52_NFC_TASKS_DISABLE (NRF52_NFCT_BASE + NRF52_NFC_TASKS_DISABLE_OFFSET) +#define NRF52_NFC_TASKS_SENSE (NRF52_NFCT_BASE + NRF52_NFC_TASKS_SENSE_OFFSET) +#define NRF52_NFC_TASKS_STARTTX (NRF52_NFCT_BASE + NRF52_NFC_TASKS_STARTTX_OFFSET) +#define NRF52_NFC_TASKS_ENABLERXDATA (NRF52_NFCT_BASE + NRF52_NFC_TASKS_ENABLERXDATA_OFFSET) +#define NRF52_NFC_TASKS_GOIDLE (NRF52_NFCT_BASE + NRF52_NFC_TASKS_GOIDLE_OFFSET) +#define NRF52_NFC_TASKS_GOSLEEP (NRF52_NFCT_BASE + NRF52_NFC_TASKS_GOSLEEP_OFFSET) +#define NRF52_NFC_EVENTS_READY (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_READY_OFFSET) +#define NRF52_NFC_EVENTS_FIELDDETECTED (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_FIELDDETECTED_OFFSET) +#define NRF52_NFC_EVENTS_FIELDLOST (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_FIELDLOST_OFFSET) +#define NRF52_NFC_EVENTS_TXFRAMESTART (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_TXFRAMESTART_OFFSET) +#define NRF52_NFC_EVENTS_TXFRAMEEND (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_TXFRAMEEND_OFFSET) +#define NRF52_NFC_EVENTS_RXFRAMESTART (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_RXFRAMESTART_OFFSET) +#define NRF52_NFC_EVENTS_RXFRAMEEND (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_RXFRAMEEND_OFFSET) +#define NRF52_NFC_EVENTS_ERROR (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_ERROR_OFFSET) +#define NRF52_NFC_EVENTS_RXERROR (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_RXERROR_OFFSET) +#define NRF52_NFC_EVENTS_ENDRX (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_ENDRX_OFFSET) +#define NRF52_NFC_EVENTS_ENDTX (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_ENDTX_OFFSET) +#define NRF52_NFC_EVENTS_ACRSTARTED (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_ACRSTARTED_OFFSET) +#define NRF52_NFC_EVENTS_COLLISION (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_COLLISION_OFFSET) +#define NRF52_NFC_EVENTS_SELECTED (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_SELECTED_OFFSET) +#define NRF52_NFC_EVENTS_STARTED (NRF52_NFCT_BASE + NRF52_NFC_EVENTS_STARTED_OFFSET) +#define NRF52_NFC_SHORTS (NRF52_NFCT_BASE + NRF52_NFC_SHORTS_OFFSET) +#define NRF52_NFC_INTEN (NRF52_NFCT_BASE + NRF52_NFC_INTEN_OFFSET) +#define NRF52_NFC_INTENSET (NRF52_NFCT_BASE + NRF52_NFC_INTENSET_OFFSET) +#define NRF52_NFC_INTENCLR (NRF52_NFCT_BASE + NRF52_NFC_INTENCLR_OFFSET) +#define NRF52_NFC_ERRORSTATUS (NRF52_NFCT_BASE + NRF52_NFC_ERRORSTATUS_OFFSET) +#define NRF52_NFC_FRAMESTATUSRX (NRF52_NFCT_BASE + NRF52_NFC_FRAMESTATUSRX_OFFSET) +#define NRF52_NFC_NFCTAGSTATE (NRF52_NFCT_BASE + NRF52_NFC_NFCTAGSTATE_OFFSET) +#define NRF52_NFC_SLEEPSTATE (NRF52_NFCT_BASE + NRF52_NFC_SLEEPSTATE_OFFSET) +#define NRF52_NFC_FIELDPRESENT (NRF52_NFCT_BASE + NRF52_NFC_FIELDPRESENT_OFFSET) +#define NRF52_NFC_FRAMEDELAYMIN (NRF52_NFCT_BASE + NRF52_NFC_FRAMEDELAYMIN_OFFSET) +#define NRF52_NFC_FRAMEDELAYMAX (NRF52_NFCT_BASE + NRF52_NFC_FRAMEDELAYMAX_OFFSET) +#define NRF52_NFC_FRAMEDELAYMODE (NRF52_NFCT_BASE + NRF52_NFC_FRAMEDELAYMODE_OFFSET) +#define NRF52_NFC_PACKETPTR (NRF52_NFCT_BASE + NRF52_NFC_PACKETPTR_OFFSET) +#define NRF52_NFC_MAXLEN (NRF52_NFCT_BASE + NRF52_NFC_MAXLEN_OFFSET) +#define NRF52_NFC_TXDFRAMECONFIG (NRF52_NFCT_BASE + NRF52_NFC_TXDFRAMECONFIG_OFFSET) +#define NRF52_NFC_TXDAMOUNT (NRF52_NFCT_BASE + NRF52_NFC_TXDAMOUNT_OFFSET) +#define NRF52_NFC_RXDFRAMECONFIG (NRF52_NFCT_BASE + NRF52_NFC_RXDFRAMECONFIG_OFFSET) +#define NRF52_NFC_RXDAMOUNT (NRF52_NFCT_BASE + NRF52_NFC_RXDAMOUNT_OFFSET) +#define NRF52_NFC_NFCID1LAST (NRF52_NFCT_BASE + NRF52_NFC_NFCID1LAST_OFFSET) +#define NRF52_NFC_NFCID2LAST (NRF52_NFCT_BASE + NRF52_NFC_NFCID2LAST_OFFSET) +#define NRF52_NFC_NFCID3LAST (NRF52_NFCT_BASE + NRF52_NFC_NFCID3LAST_OFFSET) +#define NRF52_NFC_ACRCONFIG (NRF52_NFCT_BASE + NRF52_NFC_ACRCONFIG_OFFSET) +#define NRF52_NFC_SENSRES (NRF52_NFCT_BASE + NRF52_NFC_SENSRES_OFFSET) +#define NRF52_NFC_SELRES (NRF52_NFCT_BASE + NRF52_NFC_SELRESOFFSET) + +/* Register Bitfield Definitions ****************************************************************/ + +#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_NFC_H */ diff --git a/arch/arm/src/nrf52/hardware/nrf52_radio.h b/arch/arm/src/nrf52/hardware/nrf52_radio.h new file mode 100644 index 0000000000..7b279e8477 --- /dev/null +++ b/arch/arm/src/nrf52/hardware/nrf52_radio.h @@ -0,0 +1,587 @@ +/************************************************************************************************ + * arch/arm/src/nrf52/hardware/nrf52_radio.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_RADIO_H +#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_RADIO_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include +#include "hardware/nrf52_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* Register offsets *****************************************************************************/ + +#define NRF52_RADIO_TASKS_TXEN_OFFSET 0x0000 /* Enable RADIO in TX mode */ +#define NRF52_RADIO_TASKS_RXEN_OFFSET 0x0004 /* Enable RADIO in RX mode */ +#define NRF52_RADIO_TASKS_START_OFFSET 0x0008 /* Start RADIO */ +#define NRF52_RADIO_TASKS_STOP_OFFSET 0x000C /* Stop RADIO */ +#define NRF52_RADIO_TASKS_DISABLE_OFFSET 0x0010 /* Disable RADIO */ +#define NRF52_RADIO_TASKS_RSSISTART_OFFSET 0x0014 /* Start the RSSI and take one single sample of the receive signal strength */ +#define NRF52_RADIO_TASKS_RSSISTOP_OFFSET 0x0018 /* Stop the RSSI measurement */ +#define NRF52_RADIO_TASKS_BCSTART_OFFSET 0x001c /* Start the bit counter */ +#define NRF52_RADIO_TASKS_BCSTOP_OFFSET 0x0020 /* Stop the bit counter */ +#define NRF52_RADIO_TASKS_EDSTART_OFFSET 0x0024 /* Start the energy detect measurement used in IEEE 802.15.4 mode */ +#define NRF52_RADIO_TASKS_EDSTOP_OFFSET 0x0028 /* Stop the energy detect measurement */ +#define NRF52_RADIO_TASKS_CCASTART_OFFSET 0x002c /* Start the clear channel assessment used in IEEE 802.15.4 mode */ +#define NRF52_RADIO_TASKS_CCASTOP_OFFSET 0x0030 /* Stop the clear channel assessment */ +#define NRF52_RADIO_EVENTS_READY_OFFSET 0x0100 /* RADIO has ramped up and is ready to be started */ +#define NRF52_RADIO_EVENTS_ADDRESS_OFFSET 0x0104 /* Address sent or received */ +#define NRF52_RADIO_EVENTS_PAYLOAD_OFFSET 0x0108 /* Packet payload sent or received */ +#define NRF52_RADIO_EVENTS_END_OFFSET 0x010c /* Packet sent or received */ +#define NRF52_RADIO_EVENTS_DISABLED_OFFSET 0x0110 /* RADIO has been disabled */ +#define NRF52_RADIO_EVENTS_DEVMATCH_OFFSET 0x0114 /* A device address match occurred on the last received packet */ +#define NRF52_RADIO_EVENTS_DEVMISS_OFFSET 0x0118 /* No device address match occurred on the last received packet */ +#define NRF52_RADIO_EVENTS_RSSIEND_OFFSET 0x011c /* Sampling of receive signal strength complete */ +#define NRF52_RADIO_EVENTS_BCMATCH_OFFSET 0x0128 /* Bit counter reached bit count value */ +#define NRF52_RADIO_EVENTS_CRCOK_OFFSET 0x0130 /* Packet received with CRC ok */ +#define NRF52_RADIO_EVENTS_CRCERROR_OFFSET 0x0134 /* Packet received with CRC error */ +#define NRF52_RADIO_EVENTS_FRAMESTART_OFFSET 0x0138 /* IEEE 802.15.4 length field received */ +#define NRF52_RADIO_EVENTS_EDEND_OFFSET 0x013c /* Sampling of energy detection complete */ +#define NRF52_RADIO_EVENTS_EDSTOPPED_OFFSET 0x0140 /* The sampling of energy detection has stopped */ +#define NRF52_RADIO_EVENTS_CCAIDLE_OFFSET 0x0144 /* Wireless medium in idle - clear to send */ +#define NRF52_RADIO_EVENTS_CCABUSY_OFFSET 0x0148 /* Wireless medium busy - do not send */ +#define NRF52_RADIO_EVENTS_CCASTOPPED_OFFSET 0x014c /* The CCA has stopped */ +#define NRF52_RADIO_EVENTS_RATEBOOST_OFFSET 0x0150 /* Ble_LR CI field received */ +#define NRF52_RADIO_EVENTS_TXREADY_OFFSET 0x0154 /* RADIO has ramped up and is ready to be started TX path */ +#define NRF52_RADIO_EVENTS_RXREADY_OFFSET 0x0158 /* RADIO has ramped up and is ready to be started RX path */ +#define NRF52_RADIO_EVENTS_MHRMATCH_OFFSET 0x015c /* MAC header match found */ +#define NRF52_RADIO_EVENTS_PHYEND_OFFSET 0x016c /* Last bit is sent on air */ +#define NRF52_RADIO_SHORTS_OFFSET 0x0200 /* Shortcuts between local events and tasks */ +#define NRF52_RADIO_INTENSET_OFFSET 0x0304 /* Enable interrupt */ +#define NRF52_RADIO_INTENCLR_OFFSET 0x0308 /* Disable interrupt */ +#define NRF52_RADIO_CRCSTATUS_OFFSET 0x0400 /* CRC status */ +#define NRF52_RADIO_RXMATCH_OFFSET 0x0408 /* Received address */ +#define NRF52_RADIO_RXCRC_OFFSET 0x040c /* CRC field of previously received packet */ +#define NRF52_RADIO_DAI_OFFSET 0x0410 /* Device address match index */ +#define NRF52_RADIO_PDUSTAT_OFFSET 0x0414 /* Payload status */ +#define NRF52_RADIO_PACKETPTR_OFFSET 0x0504 /* Packet pointer */ +#define NRF52_RADIO_FREQUENCY_OFFSET 0x0508 /* Frequency */ +#define NRF52_RADIO_TXPOWER_OFFSET 0x050c /* Output power */ +#define NRF52_RADIO_MODE_OFFSET 0x0510 /* Data rate and modulation */ +#define NRF52_RADIO_PCNF0_OFFSET 0x0514 /* Packet configuration register 0 */ +#define NRF52_RADIO_PCNF1_OFFSET 0x0518 /* Packet configuration register 1 */ +#define NRF52_RADIO_BASE0_OFFSET 0x051c /* Base address 0 */ +#define NRF52_RADIO_BASE1_OFFSET 0x0520 /* Base address 1 */ +#define NRF52_RADIO_PREFIX0_OFFSET 0x0524 /* Prefixes bytes for logical addresses 0-3 */ +#define NRF52_RADIO_PREFIX1_OFFSET 0x0528 /* Prefixes bytes for logical addresses 4-7 */ +#define NRF52_RADIO_TXADDRESS_OFFSET 0x052c /* Transmit address select */ +#define NRF52_RADIO_RXADDRESS_OFFSET 0x0530 /* Receive address select */ +#define NRF52_RADIO_CRCCNF_OFFSET 0x0534 /* CRC configuration */ +#define NRF52_RADIO_CRCPOLY_OFFSET 0x0538 /* CRC polynomial */ +#define NRF52_RADIO_CRCINIT_OFFSET 0x053c /* CRC initial value */ +#define NRF52_RADIO_TIFS_OFFSET 0x0544 /* Interframe spacing in μs */ +#define NRF52_RADIO_RSSISAMPLE_OFFSET 0x0548 /* RSSI sample */ +#define NRF52_RADIO_STATE_OFFSET 0x0550 /* Current radio state */ +#define NRF52_RADIO_DATAWHITEIV_OFFSET 0x0554 /* Data whitening initial value */ +#define NRF52_RADIO_BCC_OFFSET 0x0560 /* Bit counter compare */ +#define NRF52_RADIO_DAB_OFFSET(p) (0x0600 + ((p) * 0x4)) /* Device address base segment */ +#define NRF52_RADIO_DAP_OFFSET(p) (0x0620 + ((p) * 0x4)) /* Device address prefix */ +#define NRF52_RADIO_DACNF_OFFSET 0x0640 /* Device address match configuration */ +#define NRF52_RADIO_MHRMATCHCONF_OFFSET 0x0644 /* Search pattern configuration */ +#define NRF52_RADIO_MHRMATCHMAS_OFFSET 0x0648 /* Pattern mask */ +#define NRF52_RADIO_MODECNF0_OFFSET 0x0650 /* Radio mode configuration register 0 */ +#define NRF52_RADIO_SFD_OFFSET 0x0660 /* IEEE 802.15.4 start of frame delimiter */ +#define NRF52_RADIO_EDCNT_OFFSET 0x0664 /* IEEE 802.15.4 energy detect loop count */ +#define NRF52_RADIO_EDSAMPLE_OFFSET 0x0668 /* IEEE 802.15.4 energy detect level */ +#define NRF52_RADIO_CCACTRL_OFFSET 0x066c /* IEEE 802.15.4 clear channel assessment control */ +#define NRF52_RADIO_POWER_OFFSET 0x0ffc /* Peripheral power control */ + +/* Register Addresses ***************************************************************************/ + +#define NRF52_RADIO_TASKS_TXEN (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_TXEN_OFFSET) +#define NRF52_RADIO_TASKS_RXEN (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_RXEN_OFFSET) +#define NRF52_RADIO_TASKS_START (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_START_OFFSET) +#define NRF52_RADIO_TASKS_STOP (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_STOP_OFFSET) +#define NRF52_RADIO_TASKS_DISABLE (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_DISABLE_OFFSET) +#define NRF52_RADIO_TASKS_RSSISTART (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_RSSISTART_OFFSET) +#define NRF52_RADIO_TASKS_RSSISTOP (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_RSSISTOP_OFFSET) +#define NRF52_RADIO_TASKS_BCSTART (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_BCSTART_OFFSET) +#define NRF52_RADIO_TASKS_BCSTOP (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_BCSTOP_OFFSET) +#define NRF52_RADIO_TASKS_EDSTART (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_EDSTART_OFFSET) +#define NRF52_RADIO_TASKS_EDSTOP (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_EDSTOP_OFFSET) +#define NRF52_RADIO_TASKS_CCASTART (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_CCASTART_OFFSET) +#define NRF52_RADIO_TASKS_CCASTOP (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_CCASTOP_OFFSET) +#define NRF52_RADIO_EVENTS_READY (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_READY_OFFSET) +#define NRF52_RADIO_EVENTS_ADDRESS (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_ADDRESS_OFFSET) +#define NRF52_RADIO_EVENTS_PAYLOAD (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_PAYLOAD_OFFSET) +#define NRF52_RADIO_EVENTS_END (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_END_OFFSET) +#define NRF52_RADIO_EVENTS_DISABLED (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_DISABLED_OFFSET) +#define NRF52_RADIO_EVENTS_DEVMATCH (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_DEVMATCH_OFFSET) +#define NRF52_RADIO_EVENTS_DEVMISS (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_DEVMISS_OFFSET) +#define NRF52_RADIO_EVENTS_RSSIEND (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_RSSIEND_OFFSET) +#define NRF52_RADIO_EVENTS_BCMATCH (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_BCMATCH_OFFSET) +#define NRF52_RADIO_EVENTS_CRCOK (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_CRCOK_OFFSET) +#define NRF52_RADIO_EVENTS_CRCERROR (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_CRCERROR_OFFSET) +#define NRF52_RADIO_EVENTS_FRAMESTART (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_FRAMESTART_OFFSET) +#define NRF52_RADIO_EVENTS_EDEND (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_EDEND_OFFSET) +#define NRF52_RADIO_EVENTS_EDSTOPPED (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_EDSTOPPED_OFFSET) +#define NRF52_RADIO_EVENTS_CCAIDLE (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_CCAIDLE_OFFSET) +#define NRF52_RADIO_EVENTS_CCABUSY (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_CCABUSY_OFFSET) +#define NRF52_RADIO_EVENTS_CCASTOPPED (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_CCASTOPPED_OFFSET) +#define NRF52_RADIO_EVENTS_RATEBOOST (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_RATEBOOST_OFFSET) +#define NRF52_RADIO_EVENTS_TXREADY (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_TXREADY_OFFSET) +#define NRF52_RADIO_EVENTS_RXREADY (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_RXREADY_OFFSET) +#define NRF52_RADIO_EVENTS_MHRMATCH (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_MHRMATCH_OFFSET) +#define NRF52_RADIO_EVENTS_PHYEND (NRF52_RADIO_BASE + NRF52_RADIO_EVENTS_PHYEND_OFFSET) +#define NRF52_RADIO_SHORTS (NRF52_RADIO_BASE + NRF52_RADIO_SHORTS_OFFSET) +#define NRF52_RADIO_INTENSET (NRF52_RADIO_BASE + NRF52_RADIO_INTENSET_OFFSET) +#define NRF52_RADIO_INTENCLR (NRF52_RADIO_BASE + NRF52_RADIO_INTENCLR_OFFSET) +#define NRF52_RADIO_CRCSTATUS (NRF52_RADIO_BASE + NRF52_RADIO_CRCSTATUS_OFFSET) +#define NRF52_RADIO_RXMATCH (NRF52_RADIO_BASE + NRF52_RADIO_RXMATCH_OFFSET) +#define NRF52_RADIO_RXCRC (NRF52_RADIO_BASE + NRF52_RADIO_RXCRC_OFFSET) +#define NRF52_RADIO_DAI (NRF52_RADIO_BASE + NRF52_RADIO_DAI_OFFSET) +#define NRF52_RADIO_PDUSTAT (NRF52_RADIO_BASE + NRF52_RADIO_PDUSTAT_OFFSET) +#define NRF52_RADIO_PACKETPTR (NRF52_RADIO_BASE + NRF52_RADIO_PACKETPTR_OFFSET) +#define NRF52_RADIO_FREQUENCY (NRF52_RADIO_BASE + NRF52_RADIO_FREQUENCY_OFFSET) +#define NRF52_RADIO_TXPOWER (NRF52_RADIO_BASE + NRF52_RADIO_TXPOWER_OFFSET) +#define NRF52_RADIO_MODE (NRF52_RADIO_BASE + NRF52_RADIO_MODE_OFFSET) +#define NRF52_RADIO_PCNF0 (NRF52_RADIO_BASE + NRF52_RADIO_PCNF0_OFFSET) +#define NRF52_RADIO_PCNF1 (NRF52_RADIO_BASE + NRF52_RADIO_PCNF1_OFFSET) +#define NRF52_RADIO_BASE0 (NRF52_RADIO_BASE + NRF52_RADIO_BASE0_OFFSET) +#define NRF52_RADIO_BASE1 (NRF52_RADIO_BASE + NRF52_RADIO_BASE1_OFFSET) +#define NRF52_RADIO_PREFIX0 (NRF52_RADIO_BASE + NRF52_RADIO_PREFIX0_OFFSET) +#define NRF52_RADIO_PREFIX1 (NRF52_RADIO_BASE + NRF52_RADIO_PREFIX1_OFFSET) +#define NRF52_RADIO_TXADDRESS (NRF52_RADIO_BASE + NRF52_RADIO_TXADDRESS_OFFSET) +#define NRF52_RADIO_RXADDRESS (NRF52_RADIO_BASE + NRF52_RADIO_RXADDRESS_OFFSET) +#define NRF52_RADIO_CRCCNF (NRF52_RADIO_BASE + NRF52_RADIO_CRCCNF_OFFSET) +#define NRF52_RADIO_CRCPOLY (NRF52_RADIO_BASE + NRF52_RADIO_CRCPOLY_OFFSET) +#define NRF52_RADIO_CRCINIT (NRF52_RADIO_BASE + NRF52_RADIO_CRCINIT_OFFSET) +#define NRF52_RADIO_TIFS (NRF52_RADIO_BASE + NRF52_RADIO_TIFS_OFFSET) +#define NRF52_RADIO_RSSISAMPLE (NRF52_RADIO_BASE + NRF52_RADIO_RSSISAMPLE_OFFSET) +#define NRF52_RADIO_STATE (NRF52_RADIO_BASE + NRF52_RADIO_STATE_OFFSET) +#define NRF52_RADIO_DATAWHITEIV (NRF52_RADIO_BASE + NRF52_RADIO_DATAWHITEIV_OFFSET) +#define NRF52_RADIO_BCC (NRF52_RADIO_BASE + NRF52_RADIO_BCC_OFFSET) +#define NRF52_RADIO_DAB(p) (NRF52_RADIO_BASE + NRF52_RADIO_DAB_OFFSET(p)) +#define NRF52_RADIO_DAP(p) (NRF52_RADIO_BASE + NRF52_RADIO_PAP_OFFSET(p)) +#define NRF52_RADIO_DACNF (NRF52_RADIO_BASE + NRF52_RADIO_DACNF_OFFSET) +#define NRF52_RADIO_MHRMATCHCONF (NRF52_RADIO_BASE + NRF52_RADIO_MHRMATCHCONF_OFFSET) +#define NRF52_RADIO_MHRMATCHMAS (NRF52_RADIO_BASE + NRF52_RADIO_MHRMATCHMAS_OFFSET) +#define NRF52_RADIO_MODECNF0 (NRF52_RADIO_BASE + NRF52_RADIO_MODECNF0_OFFSET) +#define NRF52_RADIO_SFD (NRF52_RADIO_BASE + NRF52_RADIO_SFD_OFFSET) +#define NRF52_RADIO_EDCNT (NRF52_RADIO_BASE + NRF52_RADIO_EDCNT_OFFSET) +#define NRF52_RADIO_EDSAMPLE (NRF52_RADIO_BASE + NRF52_RADIO_EDSAMPLE_OFFSET) +#define NRF52_RADIO_CCACTRL (NRF52_RADIO_BASE + NRF52_RADIO_CCACTRL_OFFSET) +#define NRF52_RADIO_POWER (NRF52_RADIO_BASE + NRF52_RADIO_POWER_OFFSET) + +/* Register Bitfield Definitions ****************************************************************/ + +/* TASKS_TXEN Register */ + +#define RADIO_TASKS_TXEN (1 << 0) /* Bit 0: Enable RADIO in TX mode */ + +/* TASKS_RXEN Register */ + +#define RADIO_TASKS_RXEN (1 << 0) /* Bit 0: Enable RADIO in RX mode */ + +/* TASKS_START Register */ + +#define RADIO_TASKS_START (1 << 0) /* Bit 0: Start RADIO */ + +/* TASKS_STOP Register */ + +#define RADIO_TASKS_STOP (1 << 0) /* Bit 0: Stop RADIO */ + +/* TASKS_DISABLE Register */ + +#define RADIO_TASKS_DISABLE (1 << 0) /* Bit 0: Disable RADIO */ + +/* TASKS_RSSISTART Register */ + +#define RADIO_TASKS_RSSISTART (1 << 0) /* Bit 0: Start the RSSI */ + +/* TASKS_RSSISTOP Register */ + +#define RADIO_TASKS_RSSISTOP (1 << 0) /* Bit 0: Stop the RSSI */ + +/* TASKS_BCSTART Register */ + +#define RADIO_TASKS_BCSTART (1 << 0) /* Bit 0: Start the bit counter */ + +/* TASKS_BCSTOP Register */ + +#define RADIO_TASKS_BCSTOP (1 << 0) /* Bit 0: Stop the bit counter */ + +/* TASKS_EDSTART Register */ + +#define RADIO_TASKS_EDSTART (1 << 0) /* Bit 0: Start the energy detect measurement (IEEE 802.15.4) */ + +/* TASKS_EDSTOP Register */ + +#define RADIO_TASKS_EDSTOP (1 << 0) /* Bit 0: Stop the energy detect measurement (IEEE 802.15.4) */ + +/* TASKS_CCASTART Register */ + +#define RADIO_TASKS_CCASTART (1 << 0) /* Bit 0: Start the channel assessment (IEEE 802.15.4) */ + +/* TASKS_CCASTOP Register */ + +#define RADIO_TASKS_CCASTOP (1 << 0) /* Bit 0: Stop the channel assessment (IEEE 802.15.4) */ + +/* EVENTS_READY Register */ + +#define RADIO_EVENTS_READY (1 << 0) /* Bit 0: RADIO has ramped up and is ready to be started */ + +/* EVENTS_ADDRESS Register */ + +#define RADIO_EVENTS_ADDRESS (1 << 0) /* Bit 0: Address sent or received */ + +/* EVENTS_PAYLOAD Register */ + +#define RADIO_EVENTS_PAYLOAD (1 << 0) /* Bit 0: Packet payload sent or received */ + +/* EVENTS_END Register */ + +#define RADIO_EVENTS_END (1 << 0) /* Bit 0: Packet sent or received */ + +/* EVENTS_DISABLED Register */ + +#define RADIO_EVENTS_DISABLED (1 << 0) /* Bit 0: RADIO has been disabled */ + +/* EVENTS_DEVMATCH Register */ + +#define RADIO_EVENTS_DEVMATCH (1 << 0) /* Bit 0: A device address match */ + +/* EVENTS_DEVMISS Register */ + +#define RADIO_EVENTS_DEVMISS (1 << 0) /* Bit 0: No device address match */ + +/* EVENTS_RSSIEND Register */ + +#define RADIO_EVENTS_RSSIEND (1 << 0) /* Bit 0: Sampling of receive signal strength complete */ + +/* EVENTS_BCMATCH Register */ + +#define RADIO_EVENTS_BCMATCH (1 << 0) /* Bit 0: Bit counter reached bit count value */ + +/* EVENTS_CRCOK Register */ + +#define RADIO_EVENTS_CRCOK (1 << 0) /* Bit 0: Packet received with CRC ok */ + +/* EVENTS_CRCERROR Register */ + +#define RADIO_EVENTS_CRCERROR (1 << 0) /* Bit 0: Packet received with CRC error */ + +/* EVENTS_FRAMESTART Register */ + +#define RADIO_EVENTS_FRAMESTART (1 << 0) /* Bit 0: IEEE 802.15.4 length field received*/ + +/* EVENTS_EDEND Register */ + +#define RADIO_EVENTS_EDEND (1 << 0) /* Bit 0: ampling of energy detection complete */ + +/* EVENTS_EDSTOPPED Register */ + +#define RADIO_EVENTS_EDSTOPPED (1 << 0) /* Bit 0: The sampling of energy detection has stopped */ + +/* EVENTS_CCAIDLE Register */ + +#define RADIO_EVENTS_CCAIDLE (1 << 0) /* Bit 0: Wireless medium in idle */ + +/* EVENTS_CCABUSY Register */ + +#define RADIO_EVENTS_CCABUSY (1 << 0) /* Bit 0: Wireless medium busy */ + +/* EVENTS_CCASTOPPED Register */ + +#define RADIO_EVENTS_CCASTOPPED (1 << 0) /* Bit 0: The CCA has stopped */ + +/* EVENTS_RATEBOOST Register */ + +#define RADIO_EVENTS_RATEBOOST (1 << 0) /* Bit 0: Ble_LR CI field received */ + +/* EVENTS_TXREADY Register */ + +#define RADIO_EVENTS_TXREADY (1 << 0) /* Bit 0: RADIO has ramped up and is ready to be started TX path */ + +/* EVENTS_RXREADY Register */ + +#define RADIO_EVENTS_RXREADY (1 << 0) /* Bit 0: RADIO has ramped up and is ready to be started RX path */ + +/* EVENTS_MHRMATCH Register */ + +#define RADIO_EVENTS_MHRMATCH (1 << 0) /* Bit 0: MAC header match found */ + +/* EVENTS_PHYEND Register */ + +#define RADIO_EVENTS_PHYEND (1 << 0) /* Bit 0: Last bit is sent on air */ + +/* SHORTS Register */ + +#define RADIO_SHORTS_READY_START (1 << 0) /* Bit 0: Shortcut between event READY and task START */ +#define RADIO_SHORTS_END_DISABLE (1 << 1) /* Bit 1: Shortcut between event END and task DISABLE */ +#define RADIO_SHORTS_DISABLED_TXEN (1 << 2) /* Bit 2: Shortcut between event DISABLED and task TXEN */ +#define RADIO_SHORTS_DISABLED_RXEN (1 << 3) /* Bit 3: Shortcut between event DISABLED and task RXEN */ +#define RADIO_SHORTS_ADDRESS_RSSISTART (1 << 4) /* Bit 4: Shortcut between event ADDRESS and task RSSISTART */ +#define RADIO_SHORTS_END_START (1 << 5) /* Bit 5: Shortcut between event END and task START */ +#define RADIO_SHORTS_ADDRESS_BCSTART (1 << 6) /* Bit 6: Shortcut between event ADDRESS and task BCSTART */ +#define RADIO_SHORTS_DISABLED_RSSISTOP (1 << 8) /* Bit 8: Shortcut between event DISABLED and task RSSISTOP */ +#define RADIO_SHORTS_RXREADY_CCASTART (1 << 11) /* Bit 11: Shortcut between event RXREADY and task CCASTART */ +#define RADIO_SHORTS_CCAIDLE_TXEN (1 << 12) /* Bit 12: Shortcut between event CCAIDLE and task TXEN */ +#define RADIO_SHORTS_CCABUSY_DISABLE (1 << 13) /* Bit 13: Shortcut between event CCABUSY and task DISABLE */ +#define RADIO_SHORTS_FRAMESTART_BCSTART (1 << 14) /* Bit 14: Shortcut between event FRAMESTART and task BCSTART */ +#define RADIO_SHORTS_READY_EDSTART (1 << 15) /* Bit 15: Shortcut between event READY and task EDSTART */ +#define RADIO_SHORTS_EDEND_DISABLE (1 << 16) /* Bit 16: Shortcut between event EDEND and task DISABLE */ +#define RADIO_SHORTS_CCAIDLE_STOP (1 << 17) /* Bit 17: Shortcut between event CCAIDLE and task STOP */ +#define RADIO_SHORTS_TXREADY_START (1 << 18) /* Bit 18: Shortcut between event TXREADY and task START */ +#define RADIO_SHORTS_RXREADY_START (1 << 19) /* Bit 19: Shortcut between event RXREADY and task START */ +#define RADIO_SHORTS_PHYEND_DISABLE (1 << 20) /* Bit 20: Shortcut between event PHYEND and task DISABLE */ +#define RADIO_SHORTS_PHYEND_START (1 << 21) /* Bit 21: Shortcut between event PHYEND and task START */ + +/* INTENSET/INTENCLR Register */ + +#define RADIO_INT_READY (1 << 0) /* Bit 0: Interrupt for event READY */ +#define RADIO_INT_ADDRESS (1 << 1) /* Bit 1: Interrupt for event ADDRESS */ +#define RADIO_INT_PAYLOAD (1 << 2) /* Bit 2: Interrupt for event PAYLOAD */ +#define RADIO_INT_END (1 << 3) /* Bit 3: Interrupt for event END */ +#define RADIO_INT_DISABLED (1 << 4) /* Bit 4: Interrupt for event DISABLED */ +#define RADIO_INT_DEVMATCH (1 << 5) /* Bit 5: Interrupt for event DEVMTCH */ +#define RADIO_INT_DEVMISS (1 << 6) /* Bit 6: Interrupt for event DEVMISS */ +#define RADIO_INT_RSSIEND (1 << 7) /* Bit 7: Interrupt for event RSSIEND */ +#define RADIO_INT_BCMATCH (1 << 10) /* Bit 10: Interrupt for event BCMATCH */ +#define RADIO_INT_CRCOK (1 << 12) /* Bit 12: Interrupt for event CRCOK */ +#define RADIO_INT_CRCERROR (1 << 13) /* Bit 13: Interrupt for event CRCERROR */ +#define RADIO_INT_FRAMESTART (1 << 14) /* Bit 14: Interrupt for event FRAMESTART */ +#define RADIO_INT_EDEND (1 << 15) /* Bit 15: Interrupt for event EDEND */ +#define RADIO_INT_EDSTOPPED (1 << 16) /* Bit 16: Interrupt for event EDSTOPPED */ +#define RADIO_INT_CCAIDLE (1 << 17) /* Bit 17: Interrupt for event CCAIDLE */ +#define RADIO_INT_CCABUSY (1 << 18) /* Bit 18: Interrupt for event CCABUSY */ +#define RADIO_INT_CCASTOPPED (1 << 19) /* Bit 19: Interrupt for event CCASTOPPED */ +#define RADIO_INT_RATEBOOST (1 << 20) /* Bit 20: Interrupt for event RATEBOOST */ +#define RADIO_INT_TXREADY (1 << 21) /* Bit 21: Interrupt for event TXREADY */ +#define RADIO_INT_RXREADY (1 << 22) /* Bit 22: Interrupt for event RXREADY */ +#define RADIO_INT_MHRMATCH (1 << 23) /* Bit 23: Interrupt for event MHRMATCH */ +#define RADIO_INT_PHYEND (1 << 27) /* Bit 27: Interrupt for event PHYEND */ + +/* CRCSTATUS Register */ + +#define RADIO_CRCSTATUS_OK (1 << 0) /* Bit 0: CRC status of packet received */ + +/* RXMATCH Register */ + +#define RADIO_RXMATCH_SHIFT (0) /* Bits 0-2: Received address */ +#define RADIO_RXMATCH_MASK (0x7 << RADIO_RXMATCH_SHIFT) + +/* RXCRC Register */ + +#define RADIO_RXCRC_SHIFT (0) /* Bits 0-23: CRC Field of previously received packet */ +#define RADIO_RXCRC_MASK (0x00ffffff << RADIO_RXCRC_SHIFT) + +/* DAI Register */ + +#define RADIO_DAI_SHIFT (0) /* Bits 0-2: Device address match index */ +#define RADIO_DAI_MASK (0x7 << RADIO_DAI_SHIFT) + +/* PDUSTAT Register */ + +#define RADIO_PDUSTAT_PDUSTAT (1 << 0) /* Bit 0: Status on payload length vs. PCNF1.MAXLEN */ +#define RADIO_PDUSTAT_CISTAT_SHIFT (1) /* Bits 1-2: Status on what rate packet is received with in Long Range */ +#define RADIO_PDUSTAT_CISTAT_MASK (0x3 << RADIO_PDUSTAT_CISTAT_SHIFT) +# define RADIO_PDUSTAT_CISTAT_LR125KBIT (0 << RADIO_PDUSTAT_CISTAT_SHIFT) /* 0: Frame is received at 125kbps */ +# define RADIO_PDUSTAT_CISTAT_LR500KBIT (1 << RADIO_PDUSTAT_CISTAT_SHIFT) /* 1: Frame is received at 500kbps */ + +/* FREQUENCY Register */ + +#define RADIO_FREQUENCY_SHIFT (0) /* Bits 0-6: Radio channel frequency*/ +#define RADIO_FREQUENCY_MASK (0x7f << RADIO_FREQUENCY_SHIFT) +#define RADIO_FREQUENCY_MAP_2400MHZ (0 << 8) /* Bit 8: Channel map between 2400 MHz - 2500 MHz*/ +#define RADIO_FREQUENCY_MAP_2360MHZ (1 << 8) /* Bit 8: Channel map between 2360 MHz - 2460 MHz*/ + +/* TXPOWER Register */ + +#define RADIO_TXPOWER_SHIFT (0) /* Bits 0-7: RADIO output power */ +#define RADIO_TXPOWER_MASK (0xff << RADIO_TXPOWER_SHIFT) + +/* MODE Register */ + +#define RADIO_MODE_SHIFT (0) /* Bits 0-3: Radio data rate and modulation setting (FSK) */ +#define RADIO_MODE_MASK (0xf << RADIO_MODE_SHIFT) +#define RADIO_MODE_NRF1MBIT (0x00 << RADIO_MODE_SHIFT) /* 0: 1 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_NRF2MBIT (0x01 << RADIO_MODE_SHIFT) /* 1: 2 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_BLE1MBIT (0x03 << RADIO_MODE_SHIFT) /* 3: 1 Mbit/s BLE */ +#define RADIO_MODE_BLE2MBIT (0x04 << RADIO_MODE_SHIFT) /* 4: 2 Mbit/s BLE */ +#define RADIO_MODE_BLELR125KBIT (0x05 << RADIO_MODE_SHIFT) /* 5: Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ +#define RADIO_MODE_BLELR500KBIT (0x06 << RADIO_MODE_SHIFT) /* 6: Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ +#define RADIO_MODE_IEEE802154 (0x0f << RADIO_MODE_SHIFT) /* 15: IEEE 802.15.4-2006 250 kbit/s */ + +/* PCNF0 Register */ + +#define RADIO_PCNF0_LFLEN_SHIFT (0) /* Bits 0-3: Length on air of LENGTH field in number of bits */ +#define RADIO_PCNF0_LFLEN_MASK (0xf << RADIO_PCNF0_LFLEN_SHIFT) +#define RADIO_PCNF0_S0LEN (1 << 8) /* Bit 8: Length on air of S0 field in number of bytes */ +#define RADIO_PCNF0_S1LEN_SHIFT (16) /* Bits 16-19: Length on air of S1 field in number of bits */ +#define RADIO_PCNF0_S1LEN_MASK (0xf << RADIO_PCNF0_S1LEN_SHIFT) +#define RADIO_PCNF0_S1INCL (1 << 20) /* Bit 20: Include or exclude S1 field in RAM */ +#define RADIO_PCNF0_CILEN_SHIFT (22) /* Bits 22-23: Length of code indicator - long range */ +#define RADIO_PCNF0_CILEN_MASK (0x3 << RADIO_PCNF0_CILEN_SHIFT) +#define RADIO_PCNF0_PLEN_SHIFT (24) /* Bits 24-25: Length of preamble on air */ +#define RADIO_PCNF0_PLEN_MASK (0x3 << RADIO_PCNF0_PLEN_SHIFT) +# define RADIO_PCNF0_PLEN_8BIT (0 << RADIO_PCNF0_PLEN_SHIFT) +# define RADIO_PCNF0_PLEN_16BIT (1 << RADIO_PCNF0_PLEN_SHIFT) +# define RADIO_PCNF0_PLEN_32BITZ (2 << RADIO_PCNF0_PLEN_SHIFT) +# define RADIO_PCNF0_PLEN_LONGRANGE (3 << RADIO_PCNF0_PLEN_SHIFT) +#define RADIO_PCNF0_CRCINC (1 << 26) /* Bit 26: Indicates if LENGTH field contains CRC */ +#define RADIO_PCNF0_TERMLEN_SHIFT (29) /* Bits 29-30: Length of TERM field in Long Range operation */ +#define RADIO_PCNF0_TERMLEN_MASK (0x3 << RADIO_PCNF0_TERMLEN_SHIFT) + +/* PCNF1 Register */ + +#define RADIO_PCNF1_MAXLEN_SHIFT (0) /* Bits 0-7: Maximum length of packet payload */ +#define RADIO_PCNF1_MAXLEN_MASK (0xff << RADIO_PCNF1_MAXLEN_SHIFT) +#define RADIO_PCNF1_STATLEN_SHIFT (8) /* Bits 8-15: Static length in number of bytes */ +#define RADIO_PCNF1_STATLEN_MASK (0xff << RADIO_PCNF1_STATLEN_SHIFT) +#define RADIO_PCNF1_BALEN_SHIFT (16) /* Bits 16-18: Base address length in number of bytes */ +#define RADIO_PCNF1_BALEN_MASK (0x7 << RADIO_PCNF1_BALEN_SHIFT) +#define RADIO_PCNF1_ENDIAN (1 << 24) /* Bit 24: On air endianness of packet */ +# define RADIO_PCNF1_ENDIAN_LITTLE (0 << 24) /* Least significant bit on air first */ +# define RADIO_PCNF1_ENDIAN_BITG (1 << 24) /* Most significant bit on air first */ +#define RADIO_PCNF1_WHITEEN (1 << 25) /* Bit 25: Enable or disable packet whitening */ + +/* TXADDRESS Register */ + +#define RADIO_TXADDRESS_SHIFT (0) /* Bits 0-2: Transmit address select */ +#define RADIO_TXADDRESS_MASK (0x7 << RADIO_TXADDRESS_SHIFT) + +/* RXADDRESSES Register */ + +#define RADIO_RXADDRESSES_ADDR(i) (1 << (i)) /* Bits 0-7: Enable or disable reception on logical addres i */ + +/* CRCCNF Register */ + +#define RADIO_CRCCNF_LEN_SHIFT (0) /* Bit 0-1: CRC length in number of bytes */ +#define RADIO_CRCCNF_LEN_MASK (0x3 << RADIO_CRCCNF_LEN_SHIFT) +# define RADIO_CRCCNF_LEN_DIS (0 << RADIO_CRCCNF_LEN_SHIFT) +# define RADIO_CRCCNF_LEN_1 (1 << RADIO_CRCCNF_LEN_SHIFTb) +# define RADIO_CRCCNF_LEN_2 (2 << RADIO_CRCCNF_LEN_SHIFT) +# define RADIO_CRCCNF_LEN_3 (3 << RADIO_CRCCNF_LEN_SHIFT) +#define RADIO_CRCCNF_SKIPADDR_SHIFT (8) /* Bit 8-9: Include or exclude packet address field out of CRC calculation */ +#define RADIO_CRCCNF_SKIPADDR_MASK (0x3 << RADIO_CRCCNF_SKIPADDR_SHIFT) +# define RADIO_CRCCNF_SKIPADDR_INCL (0x3 << RADIO_CRCCNF_SKIPADDR_SHIFT) +# define RADIO_CRCCNF_SKIPADDR_SKIP (0x3 << RADIO_CRCCNF_SKIPADDR_SHIFT) +# define RADIO_CRCCNF_SKIPADDR_IEEE (0x3 << RADIO_CRCCNF_SKIPADDR_SHIFT) + +/* CRCPOLY Register */ + +#define RADIO_CRCPOLY_SHIFT (0) /* Bits 0-23: CRC polynomial */ +#define RADIO_CRCPOLY_MASK (0x00ffffff << RADIO_CRCPOLY_SHIFT) + +/* CRCINIT Register */ + +#define RADIO_CRCINIT_SHIFT (0) /* Bits 0-23: CRC initial value */ +#define RADIO_CRCINIT_MASK (0x00ffffff << RADIO_CRCINIT_SHIFT) + +/* TIFS Register */ + +#define RADIO_TIFS_SHIFT (0) /* Bits 0-9: Interframe spacing in μs */ +#define RADIO_TIFS_MASK (0x3ff << RADIO_TIFS_SHIFT) + +/* RSSISAMPLE Register */ + +#define RADIO_RSSISAMPLE_SHIFT (0) /* Bits 0-6: RSSI sample */ +#define RADIO_RSSISAMPLE_MASK (0x7f << RADIO_RSSISAMPLE_SHIFT) + +/* STATE Register */ + +#define RADIO_STATE_SHIFT (0) /* Bits 0-2: Current radio state */ +#define RADIO_STATE_MASK (0xf << RADIO_STATE_STATE_SHIFT) +# define RADIO_STATE_DISABLED (0 << RADIO_STATE_STATE_SHIFT) +# define RADIO_STATE_RXRU (1 << RADIO_STATE_STATE_SHIFT) +# define RADIO_STATE_RXIDLE (2 << RADIO_STATE_STATE_SHIFT) +# define RADIO_STATE_RX (3 << RADIO_STATE_STATE_SHIFT) +# define RADIO_STATE_RXDISABLE (4 << RADIO_STATE_STATE_SHIFT) +# define RADIO_STATE_TXRU (9 << RADIO_STATE_STATE_SHIFT) +# define RADIO_STATE_TXIDLE 10 << RADIO_STATE_STATE_SHIFT) +# define RADIO_STATE_TX (11 << RADIO_STATE_STATE_SHIFT) +# define RADIO_STATE_TXDISABLE (12 << RADIO_STATE_STATE_SHIFT) + +/* DATAWHITEIV Register */ + +#define RADIO_DATAWHITEIV_SHIFT (0) /* Bits 0-6: Data whitening initial value */ +#define RADIO_DATAWHITEIV_MASK (0x3f << RADIO_DATAWHITEIV_SHIFT) + +/* DAP Register */ + +#define RADIO_DAP_SHIFT (0) /* Bits 0-15: Device address prefix n */ +#define RADIO_DAP_MASK (0xffff << RADIO_DAP_SHIFT) + +/* DANCF Register */ + +#define RADIO_DACNF_ENA(i) (1 << (i)) /* Bits 0-7: Enable device address matching using */ +#define RADIO_DACNF_TXADD(i) (1 << (i + 8)) /* Bits 8-15: TXADD for device address i */ + +/* MODECNF0 Register */ + +#define RADIO_MODECNF0_RU (1 << 0) /* Bit 0: Radio ramp-up time */ +#define RADIO_MODECNF0_DTX_SHIFT (8) /* Bits 8-9: Default TX value */ +#define RADIO_MODECNF0_DTX_MASK (0x3 << RADIO_MODECNF0_DTX_SHIFT) +# define RADIO_MODECNF0_DTX_B1 (0 << RADIO_MODECNF0_DTX_SHIFT) +# define RADIO_MODECNF0_DTX_B0 (1 << RADIO_MODECNF0_DTX_SHIFT) +# define RADIO_MODECNF0_DTX_CENTER (2 << RADIO_MODECNF0_DTX_SHIFT) + +/* SFD Register */ + +#define RADIO_SFD_SHIFT (0) /* Bits 0-7: IEEE 802.15.4 start of frame delimiter */ +#define RADIO_SFD_MASK (0xff << RADIO_SFD_SHIFT) + +/* EDCNT Register */ + +#define RADIO_EDCNT_SHIFT (0) /* Bits 0-20: IEEE 802.15.4 energy detect loop count */ +#define RADIO_EDCNT_MASK (0x1fffff << RADIO_EDCNT_SHIFT) + +/* EDSAMPLE Register */ + +#define RADIO_EDSAMPLE_SHIFT (0) /* Bits 0-7: IEEE 802.15.4 energy detect level */ +#define RADIO_EDSAMPLE_MASK (0xff << RADIO_EDSAMPLE_SHIFT) + +/* CCACTRL Register */ + +#define RADIO_CCACTRL_CCAMODE_SHIFT (0) /* Bits 0-3: CCA mode of operation */ +#define RADIO_CCACTRL_CCAMODE_MASK (0x7 << RADIO_CCACTRL_CCAMODE_SHIFT) +# define RADIO_CCACTRL_CCAMODE_ED (0 << RADIO_CCACTRL_CCAMODE_SHIFT) +# define RADIO_CCACTRL_CCAMODE_C (1 << RADIO_CCACTRL_CCAMODE_SHIFT) +# define RADIO_CCACTRL_CCAMODE_CANDED (2 << RADIO_CCACTRL_CCAMODE_SHIFT) +# define RADIO_CCACTRL_CCAMODE_CORED (3 << RADIO_CCACTRL_CCAMODE_SHIFT) +# define RADIO_CCACTRL_CCAMODE_EDTST1 (4 << RADIO_CCACTRL_CCAMODE_SHIFT) + +/* POWER Register */ + +#define RADIO_POWER_ENABLE (1 << 0) /* Bit 0: Peripheral power control */ + +#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_RADIO_H */ diff --git a/arch/arm/src/nrf52/hardware/nrf52_spi.h b/arch/arm/src/nrf52/hardware/nrf52_spi.h new file mode 100644 index 0000000000..7f56d98367 --- /dev/null +++ b/arch/arm/src/nrf52/hardware/nrf52_spi.h @@ -0,0 +1,253 @@ +/************************************************************************************************ + * arch/arm/src/nrf52/hardware/nrf52_spi.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_SPI_H +#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_SPI_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include +#include "hardware/nrf52_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* Register offsets for SPI master (SPIM) *******************************************************/ + +#define NRF52_SPIM_TASK_START_OFFSET (0x0010) /* Start SPI transaction */ +#define NRF52_SPIM_TASK_STOP_OFFSET (0x0014) /* Stop SPI transaction */ +#define NRF52_SPIM_TASK_SUSPEND_OFFSET (0x001c) /* Suspend SPI transaction */ +#define NRF52_SPIM_TASK_RESUME_OFFSET (0x0020) /* Resume SPI transaction */ +#define NRF52_SPIM_EVENTS_STOPPED_OFFSET (0x0104) /* SPI transaction has stopped */ +#define NRF52_SPIM_EVENTS_ENDRX_OFFSET (0x0110) /* End of RXD buffer reached */ +#define NRF52_SPIM_EVENTS_END_OFFSET (0x0118) /* End of RXD buffer and TXD buffer reached */ +#define NRF52_SPIM_EVENTS_ENDTX_OFFSET (0x0120) /* End of TXD buffer reached */ +#define NRF52_SPIM_EVENTS_STARTED_OFFSET (0x014c) /* Transaction started */ +#define NRF52_SPIM_SHORTS_OFFSET (0x0200) /* Shortcuts between local events and tasks */ +#define NRF52_SPIM_INTENSET_OFFSET (0x0304) /* Enable interrupt */ +#define NRF52_SPIM_INTENCLR_OFFSET (0x0308) /* Disable interrupt */ +#define NRF52_SPIM_STALLSTAT_OFFSET (0x0400) /* Stall status for EasyDMA RAM accesses */ +#define NRF52_SPIM_ENABLE_OFFSET (0x0500) /* Enable SPIM */ +#define NRF52_SPIM_PSELSCK_OFFSET (0x0508) /* Pin select for SCK */ +#define NRF52_SPIM_PSELMOSI_OFFSET (0x050c) /* Pin select for MOSI */ +#define NRF52_SPIM_PSELMISO_OFFSET (0x0510) /* Pin select for MISO */ +#define NRF52_SPIM_PSELCSN_OFFSET (0x0514) /* Pin select for CSN */ +#define NRF52_SPIM_FREQUENCY_OFFSET (0x0524) /* SPI frequency. */ +#define NRF52_SPIM_RXDPTR_OFFSET (0x0534) /* Data pointer */ +#define NRF52_SPIM_RXDMAXCNT_OFFSET (0x0538) /* Maximum number of bytes in receive buffer */ +#define NRF52_SPIM_RXDMAMOUNT_OFFSET (0x053c) /* Number of bytes transferred in the last transaction */ +#define NRF52_SPIM_RXDLIST_OFFSET (0x0540) /* RXD EasyDMA list type */ +#define NRF52_SPIM_TXDPTR_OFFSET (0x0544) /* Data pointer */ +#define NRF52_SPIM_TXDMAXCNT_OFFSET (0x0548) /* Number of bytes in transmit buffer */ +#define NRF52_SPIM_TXDAMOUNT_OFFSET (0x054c) /* Number of bytes transferred in the last transaction */ +#define NRF52_SPIM_TXDLIST_OFFSET (0x0550) /* TXD EasyDMA list type */ +#define NRF52_SPIM_CONFIG_OFFSET (0x0554) /* Configuration register */ +#define NRF52_SPIM_RXDELAY_OFFSET (0x0560) /* Sample delay for input serial data on MISO */ +#define NRF52_SPIM_CSNDUR_OFFSET (0x0564) /* IFTIMING.CSNDUR */ +#define NRF52_SPIM_CSNPOL_OFFSET (0x0568) /* Polarity of CSN output */ +#define NRF52_SPIM_PSELDCX_OFFSET (0x056c) /* Pin select for DCX signal */ +#define NRF52_SPIM_DCXCNT_OFFSET (0x0570) /* DCX configuration */ +#define NRF52_SPIM_ORC_OFFSET (0x05c0) /* ORC */ + +/* Register offsets for SPI slave (SPIS) *******************************************************/ + +#define NRF52_SPIS_SHORTS_OFFSET (0x0200) /* Shortcuts between local events and tasks */ +#define NRF52_SPIS_INTENSET_OFFSET (0x0304) /* Enable interrupt */ +#define NRF52_SPIS_INTENCLR_OFFSET (0x0308) /* Disable interrupt */ +#define NRF52_SPIS_SEMSTAT_OFFSET (0x0400) /* Semaphore status register */ +#define NRF52_SPIS_STATUS_OFFSET (0x0440) /* Status from last transaction */ +#define NRF52_SPIS_ENABLE_OFFSET (0x0500) /* Enable SPIS */ +#define NRF52_SPIS_PSELSCK_OFFSET (0x0508) /* Pin select for SCK */ +#define NRF52_SPIS_PSELMOSI_OFFSET (0x050c) /* Pin select for MOSI signal */ +#define NRF52_SPIS_PSELMISO_OFFSET (0x0510) /* Pin select for MISO signal */ +#define NRF52_SPIS_PSELCSN_OFFSET (0x0514) /* Pin select for CSN */ +#define NRF52_SPIS_RXDPTR_OFFSET (0x0534) /* Data pointer */ +#define NRF52_SPIS_RXDMAXCNT_OFFSET (0x0538) /* Maximum number of bytes in receive buffer */ +#define NRF52_SPIS_RXDMAMOUNT_OFFSET (0x053c) /* Number of bytes transferred in the last transaction */ +#define NRF52_SPIS_RXDLIST_OFFSET (0x0540) /* RXD EasyDMA list type */ +#define NRF52_SPIS_TXDPTR_OFFSET (0x0544) /* Data pointer */ +#define NRF52_SPIS_TXDMAXCNT_OFFSET (0x0548) /* Number of bytes in transmit buffer */ +#define NRF52_SPIS_TXDAMOUNT_OFFSET (0x054c) /* Number of bytes transferred in the last transaction */ +#define NRF52_SPIS_TXDLIST_OFFSET (0x0550) /* TXD EasyDMA list type */ +#define NRF52_SPIS_CONFIG_OFFSET (0x0554) /* Configuration register */ +#define NRF52_SPIS_DEF_OFFSET (0x055c) /* Default character */ +#define NRF52_SPIS_ORC_OFFSET (0x05c0) /* Over-read character */ + +/* Register Bitfield Definitions for SPIM *******************************************************/ + +/* TASKS_START Register */ + +#define SPIM_TASKS_START (1 << 0) /* Bit 0: Start SPI transaction */ + +/* TASKS_STOP Register */ + +#define SPIM_TASKS_STOP (1 << 0) /* Bit 0: Stop SPI transaction */ + +/* TASKS_SUSPEND Register */ + +#define SPIM_TASKS_SUSPEND (1 << 0) /* Bit 0: Suspend SPI transaction */ + +/* TASKS_RESUME Register */ + +#define SPIM_TASKS_RESUME (1 << 0) /* Bit 0: Resume SPI transaction */ + +/* EVENTS_STOPPED Register */ + +#define SPIM_EVENTS_STOPPED (1 << 0) /* Bit 0: SPI transaction has stopped */ + +/* EVENTS_ENDRX Register */ + +#define SPIM_EVENTS_ENDRX (1 << 0) /* Bit 0: End of RXD buffer reached */ + +/* EVENTS_END Register */ + +#define SPIM_EVENTS_END (1 << 0) /* Bit 0: End of RXD buffer and TXD buffer reached */ + +/* EVENTS_ENDTX Register */ + +#define SPIM_EVENTS_ENDTX (1 << 0) /* Bit 0: End of TXD buffer reached */ + +/* EVENTS_STARTED Register */ + +#define SPIM_EVENTS_STARTED (1 << 0) /* Bit 0: Transaction started */ + +/* SHORTS Register */ + +#define SPIM_SHORTS_ENDSTART (1 << 0) /* Bit 0: Shortcut between event END and task START */ + +/* INTENSET/INTENCLR Register */ + +#define SPIM_INT_STOPPED (1 << 1) /* Bit 1: Enable interrupt for STOPPED */ +#define SPIM_INT_ENDRX (1 << 4) /* Bit 4: Enable interrupt for ENDRX */ +#define SPIM_INT_END (1 << 6) /* Bit 6: Enable interrupt for END */ +#define SPIM_INT_ENDTX (1 << 8) /* Bit 8: Enable interrupt for ENDTX */ +#define SPIM_INT_STARTED (1 << 19) /* Bit 19: Enable interrupt for STARTED */ + +/* STALLLSTAT Register */ + +#define SPIM_STALLSTAT_TX (1 << 0) /* Bit 0: Stall status for EasyDMA RAM reads */ +#define SPIM_STALLSTAT_TX (1 << 1) /* Bit 1: Stall status for EasyDMA RAM writes */ + +/* ENABLE Register */ + +#define SPIM_ENABLE_DIS (0) /* Disable SPIM */ +#define SPIM_ENABLE_EN (0xf << 0) /* Enable SPIM */ + +/* PSELSCK Register */ + +#define SPIM_PSELSCK_PIN_SHIFT (0) /* Bits 0-4: SCK pin number */ +#define SPIM_PSELSCK_PIN_MASK (0xf << SPIM_PSELSCK_PIN_SHIFT) +#define SPIM_PSELSCK_PORT_SHIFT (5) /* Bit 5: SCK port number */ +#define SPIM_PSELSCK_PORT_MASK (0x1 << SPIM_PSELSCK_PORT_SHIFT) +#define SPIM_PSELSCK_CONNECTED (1 << 31) /* Bit 31: Connection */ + +/* PSELMOSI Register */ + +#define SPIM_PSELMOSI_PIN_SHIFT (0) /* Bits 0-4: MOSI pin number */ +#define SPIM_PSELMOSI_PIN_MASK (0xf << SPIM_PSELMOSI_PIN_SHIFT) +#define SPIM_PSELMOSI_PORT_SHIFT (5) /* Bit 5: MOSI port number */ +#define SPIM_PSELMOSI_PORT_MASK (0x1 << SPIM_PSELMOSI_PORT_SHIFT) +#define SPIM_PSELMOSI_CONNECTED (1 << 31) /* Bit 31: Connection */ + +/* PSELMISO Register */ + +#define SPIM_PSELMISO_PIN_SHIFT (0) /* Bits 0-4: MISO pin number */ +#define SPIM_PSELMISO_PIN_MASK (0xf << SPIM_PSELMISO_PIN_SHIFT) +#define SPIM_PSELMISO_PORT_SHIFT (5) /* Bit 5: MISO port number */ +#define SPIM_PSELMISO_PORT_MASK (0x1 << SPIM_PSELMISO_PORT_SHIFT) +#define SPIM_PSELMISO_CONNECTED (1 << 31) /* Bit 31: Connection */ + +/* PSELCSN Register */ + +#define SPIM_PSELCSN_PIN_SHIFT (0) /* Bits 0-4: CSN pin number */ +#define SPIM_PSELCSN_PIN_MASK (0xf << SPIM_PSELCSN_PIN_SHIFT) +#define SPIM_PSELCSN_PORT_SHIFT (5) /* Bit 5: CSN port number */ +#define SPIM_PSELCSN_PORT_MASK (0x1 << SPIM_PSELCSN_PORT_SHIFT) +#define SPIM_PSELCSN_CONNECTED (1 << 31) /* Bit 31: Connection */ + +/* FREQUENCY Register */ + +#define SPIM_FREQUENCY_125KBPS (0x02000000) /* 125 kbps */ +#define SPIM_FREQUENCY_250KBPS (0x04000000) /* 250 kbps */ +#define SPIM_FREQUENCY_500KBPS (0x08000000) /* 500 kbps */ +#define SPIM_FREQUENCY_1MBPS (0x10000000) /* 1 Mbps */ +#define SPIM_FREQUENCY_2MBPS (0x20000000) /* 2 Mbps */ +#define SPIM_FREQUENCY_4MBPS (0x40000000) /* 4 Mbps */ +#define SPIM_FREQUENCY_8MBPS (0x80000000) /* 8 Mbps */ +#define SPIM_FREQUENCY_16MBPS (0x0A000000) /* 16 Mbps */ +#define SPIM_FREQUENCY_32MBPS (0x14000000) /* 32 Mbps */ + +/* RXDMAXCNT Register */ + +#define SPIM_RXDMAXCNT_SHIFT (0) /* Bits 0-15: Maximum number of bytes in receive buffer */ +#define SPIM_RXDMAXCNT_MASK (0xffff << SPIM_RXDMAXCNT_SHIFT) + +/* RXDAMOUNT Register */ + +#define SPIM_RXDAMOUNT_SHIFT (0) /* Bits 0-15: Number of bytes transferred in the last transaction */ +#define SPIM_RXDAMOUNT_MASK (0xffff << SPIM_RXDAMOUNT_SHIFT) + +/* TXDMAXCNT Register */ + +#define SPIM_TXDMAXCNT_SHIFT (0) /* Bits 0-15: Maximum number of bytes in transmit buffer */ +#define SPIM_TXDMAXCNT_MASK (0xffff << SPIM_TXDMAXCNT_MASK) + +/* TXDAMOUNT Register */ + +#define SPIM_TXDAMOUNT_SHIFT (0) /* Bits 0-15: Number of bytes transferred in the last transaction */ +#define SPIM_TXDAMOUNT_MASK (0xffff << SPIM_TXDAMOUNT_SHIFT) + +/* CONFIG Register */ + +#define SPIM_CONFIG_ORDER (1 << 0) /* Bit 0: Bit order */ +#define SPIM_CONFIG_CPHA (1 << 1) /* Bit 1: Serial clock phase */ +#define SPIM_CONFIG_CPOL (1 << 2) /* Bit 2: Serial clock polarity */ + +/* PSELDCX Register */ + +#define SPIM_PSELDCX_PIN_SHIFT (0) /* Bits 0-4: DCX pin number */ +#define SPIM_PSELDCX_PIN_MASK (0xf << SPIM_PSELDCX_PIN_SHIFT) +#define SPIM_PSELDCX_PORT_SHIFT (5) /* Bit 5: SCK port number */ +#define SPIM_PSELDCX_PORT_MASK (0x1 << SPIM_PSELDCX_PORT_SHIFT) +#define SPIM_PSELDCX_CONNECTED (1 << 31) /* Bit 31: Connection */ + +/* Register Bitfield Definitions for SPIS *******************************************************/ + +/* TODO */ + +#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_SPI_H */ diff --git a/arch/arm/src/nrf52/hardware/nrf52_twi.h b/arch/arm/src/nrf52/hardware/nrf52_twi.h new file mode 100644 index 0000000000..c27e9b9140 --- /dev/null +++ b/arch/arm/src/nrf52/hardware/nrf52_twi.h @@ -0,0 +1,201 @@ +/************************************************************************************************ + * arch/arm/src/nrf52/hardware/nrf52_twi.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TWI_H +#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TWI_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include +#include "hardware/nrf52_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* Register offsets for TWI master (TWIM) *******************************************************/ + +#define NRF52_TWIM_TASKS_STARTRX_OFFSET 0x0000 /* Start TWIM receive sequence */ +#define NRF52_TWIM_TASKS_STARTTX_OFFSET 0x0008 /* Start TWIM transmit sequence */ +#define NRF52_TWIM_TASKS_STOP_OFFSET 0x0014 /* Stop TWIM transaction */ +#define NRF52_TWIM_TASKS_SUSPEND_OFFSET 0x001c /* Suspend TWIM transaction */ +#define NRF52_TWIM_TASKS_RESUME_OFFSET 0x0020 /* Resume TWIM transaction */ +#define NRF52_TWIM_EVENTS_STOPPED_OFFSET 0x0104 /* TWIM stopped */ +#define NRF52_TWIM_EVENTS_ERROR_OFFSET 0x0124 /* TWIM error */ +#define NRF52_TWIM_EVENTS_SUSPENDED_OFFSET 0x0148 /* Last byte has been sent out after the SUSPEND task has been issued */ +#define NRF52_TWIM_EVENTS_RXSTARTED_OFFSET 0x014c /* Receive sequence started */ +#define NRF52_TWIM_EVENTS_TXSTARTED_OFFSET 0x0150 /* Transmit sequence started */ +#define NRF52_TWIM_EVENTS_LASTRX_OFFSET 0x015c /* Byte boundary, starting to receive the last byte */ +#define NRF52_TWIM_EVENTS_LASTTX_OFFSET 0x0160 /* Byte boundary, starting to transmit the last byte */ +#define NRF52_TWIM_SHORTS_OFFSET 0x0200 /* Shortcuts between local events and tasks */ +#define NRF52_TWIM_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */ +#define NRF52_TWIM_INTENSET_OFFSET 0x0304 /* Enable interrupt */ +#define NRF52_TWIM_INTENCLR_OFFSET 0x0308 /* Disable interrupt */ +#define NRF52_TWIM_ERRORSRC_OFFSET 0x04c4 /* Error source */ +#define NRF52_TWIM_ENABLE_OFFSET 0x0500 /* Enable TWIMS */ +#define NRF52_TWIM_PSELSCL_OFFSET 0x0508 /* Pin select for SCL signal */ +#define NRF52_TWIM_PSELSDA_OFFSET 0x050c /* Pin select for SDA signal */ +#define NRF52_TWIM_FREQUENCY_OFFSET 0x0524 /* TWIM frequency */ +#define NRF52_TWIM_RXDPTR_OFFSET 0x0534 /* RXD Data pointer */ +#define NRF52_TWIM_RXDMAXCNT_OFFSET 0x0538 /* Maximum number of bytes in RXD buffer */ +#define NRF52_TWIM_RXDAMOUNT_OFFSET 0x053c /* Number of bytes transferred in the last RXD transaction */ +#define NRF52_TWIM_RXDLIST_OFFSET 0x0540 /* RX EasyDMA list type */ +#define NRF52_TWIM_TXDPTR_OFFSET 0x0544 /* TXD Data pointer */ +#define NRF52_TWIM_TXMAXCNT_OFFSET 0x0548 /* Maximum number of bytes in TXD buffer */ +#define NRF52_TWIM_TXAMOUNT_OFFSET 0x054c /* Number of bytes transferred in the last TXD transaction */ +#define NRF52_TWIM_TXLIST_OFFSET 0x0550 /* TX EasyDMA list type */ +#define NRF52_TWIM_ADDRESS_OFFSET 0x0588 /* TWIM address */ + +/* Register offsets for TWI slave (TWIS) ********************************************************/ + +#define NRF52_TWIS_TASKS_STOP_OFFSET 0x0014 /* Stop TWIS transaction */ +#define NRF52_TWIS_TASKS_SUSPEND_OFFSET 0x001c /* Suspend TWIS transaction */ +#define NRF52_TWIS_TASKS_RESUME_OFFSET 0x0020 /* Resume TWIS transaction */ +#define NRF52_TWIS_TASKS_PREPARERX_OFFSET 0x0030 /* Prepare the TWIS slave to respond to a write command */ +#define NRF52_TWIS_TASKS_PREPARETX_OFFSET 0x0034 /* Prepare the TWIS slave to respond to a read command */ +#define NRF52_TWIS_EVENTS_STOPPED_OFFSET 0x0104 /* TWIS stopped */ +#define NRF52_TWIS_EVENTS_ERROR_OFFSET 0x0124 /* TWIS error */ +#define NRF52_TWIS_EVENTS_RXSTARTED_OFFSET 0x014c /* Receive sequence started */ +#define NRF52_TWIS_EVENTS_TXSTARTED_OFFSET 0x0150 /* Transmit sequence started */ +#define NRF52_TWIS_EVENTS_WRITE_OFFSET 0x0164 /* Write command received */ +#define NRF52_TWIS_EVENTS_READ_OFFSET 0x0168 /* Read command received */ +#define NRF52_TWIS_SHORTS_OFFSET 0x0200 /* Shortcuts between local events and tasks */ +#define NRF52_TWIS_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */ +#define NRF52_TWIS_INTENSET_OFFSET 0x0304 /* Enable interrupt */ +#define NRF52_TWIS_INTENCLR_OFFSET 0x0308 /* Disable interrupt */ +#define NRF52_TWIS_ERRORSRC_OFFSET 0x04d0 /* Error source */ +#define NRF52_TWIS_MATCH_OFFSET 0x04d4 /* Status register indicating which address had a match */ +#define NRF52_TWIS_ENABLE_OFFSET 0x0500 /* Enable TWISS */ +#define NRF52_TWIS_PSELSCL_OFFSET 0x0508 /* Pin select for SCL signal */ +#define NRF52_TWIS_PSELSDA_OFFSET 0x050c /* Pin select for SDA signal */ +#define NRF52_TWIS_RXDPTR_OFFSET 0x0534 /* RXD Data pointer */ +#define NRF52_TWIS_RXDMAXCNT_OFFSET 0x0538 /* Maximum number of bytes in RXD buffer */ +#define NRF52_TWIS_RXDAMOUNT_OFFSET 0x053c /* Number of bytes transferred in the last RXD transaction */ +#define NRF52_TWIS_RXDLIST_OFFSET 0x0540 /* RX EasyDMA list type */ +#define NRF52_TWIS_TXDPTR_OFFSET 0x0544 /* TXD Data pointer */ +#define NRF52_TWIS_TXMAXCNT_OFFSET 0x0548 /* Maximum number of bytes in TXD buffer */ +#define NRF52_TWIS_TXAMOUNT_OFFSET 0x054c /* Number of bytes transferred in the last TXD transaction */ +#define NRF52_TWIS_TXLIST_OFFSET 0x0550 /* TX EasyDMA list type */ +#define NRF52_TWIS_ADDRESS0_OFFSET 0x0588 /* TWIS address 0 */ +#define NRF52_TWIS_ADDRESS1_OFFSET 0x058c /* TWIS address 1 */ +#define NRF52_TWIS_CONFIG_OFFSET 0x0594 /* Configuration register for the address match mechanism */ +#define NRF52_TWIS_ORC_OFFSET 0x05c0 /* Over-read character */ + +/* Register Bitfield Definitions for TWIM *******************************************************/ + +/* SHORTS Register */ + +#define TWIM_SHORTS_LASTTX_STARTRX (1 << 7) /* Bit 7: Shortcut between event LASTTX and task STARTRX */ +#define TWIM_SHORTS_LASTTX_SUSPEND (1 << 8) /* Bit 8: Shortcut between event LASTTX and task SUSPEND */ +#define TWIM_SHORTS_LASTTX_STOP (1 << 9) /* Bit 9: Shortcut between event LASTTX and task STOP */ +#define TWIM_SHORTS_LASTRX_STARTTX (1 << 10) /* Bit 10: Shortcut between event LASTRX and task STARTTX */ +#define TWIM_SHORTS_LASTRX_SUSPEND (1 << 11) /* Bit 11: Shortcut between event LASTRX and task SUSPEND */ +#define TWIM_SHORTS_LASTRX_STOP (1 << 12) /* Bit 12: Shortcut between event LASTRX and task STOP */ + +/* INTEN/INTENSET/INTENCLR Register */ + +#define TWIM_INT_STOPPED (1 << 1) /* Bit 1: Interrupt for event STOPPED */ +#define TWIM_INT_ERROR (1 << 9) /* Bit 9: Interrupt for event ERROR */ +#define TWIM_INT_SUSPENDED (1 << 18) /* Bit 18: Interrupt for event SUSPENDED */ +#define TWIM_INT_RXSTARTED (1 << 19) /* Bit 19: Interrupt for event RXSTARTED */ +#define TWIM_INT_TXSTARTED (1 << 20) /* Bit 20: Interrupt for event TXSTARTED */ +#define TWIM_INT_LASTRX (1 << 23) /* Bit 23: Interrupt for event LASTRX */ +#define TWIM_INT_LASTTX (1 << 24) /* Bit 24: Interrupt for event LASTTX */ + +/* ERRORSRC Register */ + +#define TWIM_ERRORSRC_OVERRUN (1 << 0) /* Bit 0: Overrun error */ +#define TWIM_ERRORSRC_ANACK (1 << 1) /* Bit 1: NACK received after sending the address */ +#define TWIM_ERRORSRC_DNACK (1 << 2) /* Bit 2: NACK received after sending a data byte */ + +/* ENABLE Register */ + +#define TWIM_ENABLE_DIS (0) /* Disable TWIM */ +#define TWIM_ENABLE_EN (0xf << 0) /* Disable TWIM */ + +/* PSELSCL Register */ + +#define TWIM_PSELSCL_PIN_SHIFT (0) /* Bits 0-4: SCL pin number */ +#define TWIM_PSELSCL_PIN_MASK (0xf << TWIM_PSELSCL_PIN_SHIFT) +#define TWIM_PSELSCL_PORT_SHIFT (5) /* Bit 5: SCL port number */ +#define TWIM_PSELSCL_PORT_MASK (0x1 << TWIM_PSELSCL_PORT_SHIFT) +#define TWIM_PSELSCL_CONNECTED (1 << 31) /* Bit 31: Connection */ + +/* PSELSDA Register */ + +#define TWIM_PSELSDA_PIN_SHIFT (0) /* Bits 0-4: SDA pin number */ +#define TWIM_PSELSDA_PIN_MASK (0xf << TWIM_PSELSDA_PIN_SHIFT) +#define TWIM_PSELSDA_PORT_SHIFT (5) /* Bit 5: SDA port number */ +#define TWIM_PSELSDA_PORT_MASK (0x1 << TWIM_PSELSDA_PORT_SHIFT) +#define TWIM_PSELSDA_CONNECTED (1 << 31) /* Bit 31: Connection */ + +/* FREQUENCY Register */ + +#define TWIM_FREQUENCY_100KBPS (0x01980000) /* 100 kbps */ +#define TWIM_FREQUENCY_250KBPS (0x04000000) /* 250 kbps */ +#define TWIM_FREQUENCY_400KBPS (0x64000000) /* 400 kbps */ + +/* RXDMAXCNT Register */ + +#define TWIM_RXDMAXCNT_SHIFT (0) /* Bits 0-15: Maximum number of bytes in receive buffer */ +#define TWIM_RXDMAXCNT_MASK (0xffff << TWIM_RXDMAXCNT_SHIFT) + +/* RXDAMOUNT Register */ + +#define TWIM_RXDAMOUNT_SHIFT (0) /* Bits 0-15: Number of bytes transferred in the last transaction */ +#define TWIM_RXDAMOUNT_MASK (0xffff << TWIM_RXDAMOUNT_SHIFT) + +/* TXDMAXCNT Register */ + +#define TWIM_TXDMAXCNT_SHIFT (0) /* Bits 0-15: Maximum number of bytes in transmit buffer */ +#define TWIM_TXDMAXCNT_MASK (0xffff << TWIM_TXDMAXCNT_SHIFT) + +/* TXDAMOUNT Register */ + +#define TWIM_TXDAMOUNT_SHIFT (0) /* Bits 0-15: Number of bytes transferred in the last transaction */ +#define TWIM_TXDAMOUNT_MASK (0xffff << TWIM_TXDAMOUNT_SHIFT) + +/* ADDRESS Register */ + +#define TWIM_ADDRESS_SHIFT (0) /* Bits 0-6: Address used in the TWI transfer */ +#define TWIM_ADDRESS_MASK (0x7f << TWIM_ADDRESS_SHIFT) + +/* Register Bitfield Definitions for TWIS *******************************************************/ + +/* TODO */ + +#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TWI_H */ diff --git a/arch/arm/src/nrf52/hardware/nrf52_uarte.h b/arch/arm/src/nrf52/hardware/nrf52_uarte.h index f40e01bae1..cb9c3c258a 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_uarte.h +++ b/arch/arm/src/nrf52/hardware/nrf52_uarte.h @@ -47,9 +47,7 @@ * Pre-processor Definitions *****************************************************************************************************/ -/* UARTE Register Offsets ****************************************************************************/ - -/* Registers for the UARTE function: */ +/* UART/UARTE Register Offsets ***********************************************************************/ #define NRF52_UARTE_TASKS_STARTRX_OFFSET 0x0000 /* Start UART receiver */ #define NRF52_UARTE_TASKS_STOPRX_OFFSET 0x0004 /* Stop UART receiver */ @@ -86,42 +84,6 @@ #define NRF52_UARTE_TXD_AMOUNT_OFFSET 0x054c /* Number of bytes transferred in the last transaction */ #define NRF52_UARTE_CONFIG_OFFSET 0x056c /* Configuration of parity and hardware flow control */ - -#define NRF52_UARTE_TASKS_STARTRX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_STARTRX_OFFSET) -#define NRF52_UARTE_TASKS_STOPRX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_STOPRX_OFFSET) -#define NRF52_UARTE_TASKS_STARTTX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_STARTTX_OFFSET) -#define NRF52_UARTE_TASKS_STOPTX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_STOPTX_OFFSET) -#define NRF52_UARTE_TASKS_FLUSHRX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_FLUSHRX_OFFSET) -#define NRF52_UARTE_EVENTS_CTS (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_CTS_OFFSET) -#define NRF52_UARTE_EVENTS_NCTS (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_NCTS_OFFSET) -#define NRF52_UARTE_EVENTS_RXDRDY (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_RXDRDY_OFFSET) -#define NRF52_UARTE_EVENTS_ENDRX (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_ENDRX_OFFSET) -#define NRF52_UARTE_EVENTS_TXDRDY (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_TXDRDY_OFFSET) -#define NRF52_UARTE_EVENTS_ENDTX (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_ENDTX_OFFSET) -#define NRF52_UARTE_EVENTS_ERROR (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_ERROR_OFFSET) -#define NRF52_UARTE_EVENTS_RXTO (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_RXTO_OFFSET) -#define NRF52_UARTE_EVENTS_RXSTARTED (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_RXSTARTED_OFFSET) -#define NRF52_UARTE_EVENTS_TXSTARTED (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_TXSTARTED_OFFSET) -#define NRF52_UARTE_EVENTS_TXSTOPPED (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_TXSTOPPED_OFFSET) -#define NRF52_UARTE_SHORTS (NRF52_UARTE0_BASE + NRF52_UARTE_SHORTS_OFFSET) -#define NRF52_UARTE_INTEN (NRF52_UARTE0_BASE + NRF52_UARTE_INTEN_OFFSET) -#define NRF52_UARTE_INTENSET (NRF52_UARTE0_BASE + NRF52_UARTE_INTENSET_OFFSET) -#define NRF52_UARTE_INTENCLR (NRF52_UARTE0_BASE + NRF52_UARTE_INTENCLR_OFFSET) -#define NRF52_UARTE_ERRORSRC (NRF52_UARTE0_BASE + NRF52_UARTE_ERRORSRC_OFFSET) -#define NRF52_UARTE_ENABLE (NRF52_UARTE0_BASE + NRF52_UARTE_ENABLE_OFFSET) -#define NRF52_UARTE_PSEL_RTS (NRF52_UARTE0_BASE + NRF52_UARTE_PSEL_RTS_OFFSET) -#define NRF52_UARTE_PSEL_TXD (NRF52_UARTE0_BASE + NRF52_UARTE_PSEL_TXD_OFFSET) -#define NRF52_UARTE_PSEL_CTS (NRF52_UARTE0_BASE + NRF52_UARTE_PSEL_CTS_OFFSET) -#define NRF52_UARTE_PSEL_RXD (NRF52_UARTE0_BASE + NRF52_UARTE_PSEL_RXD_OFFSET) -#define NRF52_UARTE_BAUDRATE (NRF52_UARTE0_BASE + NRF52_UARTE_BAUDRATE_OFFSET) -#define NRF52_UARTE_RXD_PTR (NRF52_UARTE0_BASE + NRF52_UARTE_RXD_PTR_OFFSET) -#define NRF52_UARTE_RXD_MAXCNT (NRF52_UARTE0_BASE + NRF52_UARTE_RXD_MAXCNT_OFFSET) -#define NRF52_UARTE_RXD_AMOUNT (NRF52_UARTE0_BASE + NRF52_UARTE_RXD_AMOUNT_OFFSET) -#define NRF52_UARTE_TXD_PTR (NRF52_UARTE0_BASE + NRF52_UARTE_TXD_PTR_OFFSET) -#define NRF52_UARTE_TXD_MAXCNT (NRF52_UARTE0_BASE + NRF52_UARTE_TXD_MAXCNT_OFFSET) -#define NRF52_UARTE_TXD_AMOUNT (NRF52_UARTE0_BASE + NRF52_UARTE_TXD_AMOUNT_OFFSET) -#define NRF52_UARTE_CONFIG (NRF52_UARTE0_BASE + NRF52_UARTE_CONFIG_OFFSET) - #define NRF52_UART_TASKS_STARTRX_OFFSET 0x0000 /* Start UART receiver */ #define NRF52_UART_TASKS_STOPRX_OFFSET 0x0004 /* Stop UART receiver */ #define NRF52_UART_TASKS_STARTTX_OFFSET 0x0008 /* Start UART transmitter */ @@ -147,42 +109,254 @@ #define NRF52_UART_BAUDRATE_OFFSET 0x0524 /* Baud rate */ #define NRF52_UART_CONFIG_OFFSET 0x056c /* Configuration of parity and hardware flow control */ -#define NRF52_UART_TASKS_STARTRX (NRF52_UART0_BASE + NRF52_UART_TASKS_STARTRX_OFFSET) -#define NRF52_UART_TASKS_STOPRX (NRF52_UART0_BASE + NRF52_UART_TASKS_STOPRX_OFFSET) -#define NRF52_UART_TASKS_STARTTX (NRF52_UART0_BASE + NRF52_UART_TASKS_STARTTX_OFFSET) -#define NRF52_UART_TASKS_STOPTX (NRF52_UART0_BASE + NRF52_UART_TASKS_STOPTX_OFFSET) -#define NRF52_UART_TASKS_SUSPEND (NRF52_UART0_BASE + NRF52_UART_TASKS_SUSPEND_OFFSET) -#define NRF52_UART_EVENTS_CTS (NRF52_UART0_BASE + NRF52_UART_EVENTS_CTS_OFFSET) -#define NRF52_UART_EVENTS_NCTS (NRF52_UART0_BASE + NRF52_UART_EVENTS_NCTS_OFFSET) -#define NRF52_UART_EVENTS_RXDRDY (NRF52_UART0_BASE + NRF52_UART_EVENTS_RXDRDY_OFFSET) -#define NRF52_UART_EVENTS_TXDRDY (NRF52_UART0_BASE + NRF52_UART_EVENTS_TXDRDY_OFFSET) -#define NRF52_UART_EVENTS_ERROR (NRF52_UART0_BASE + NRF52_UART_EVENTS_ERROR_OFFSET) -#define NRF52_UART_EVENTS_RXTO (NRF52_UART0_BASE + NRF52_UART_EVENTS_RXTO_OFFSET) -#define NRF52_UART_SHORTS (NRF52_UART0_BASE + NRF52_UART_SHORTS_OFFSET) -#define NRF52_UART_INTENSET (NRF52_UART0_BASE + NRF52_UART_INTENSET_OFFSET) -#define NRF52_UART_INTENCLR (NRF52_UART0_BASE + NRF52_UART_INTENCLR_OFFSET) -#define NRF52_UART_ERRORSRC (NRF52_UART0_BASE + NRF52_UART_ERRORSRC_OFFSET) -#define NRF52_UART_ENABLE (NRF52_UART0_BASE + NRF52_UART_ENABLE_OFFSET) -#define NRF52_UART_PSELRTS (NRF52_UART0_BASE + NRF52_UART_PSELRTS_OFFSET) -#define NRF52_UART_PSELTXD (NRF52_UART0_BASE + NRF52_UART_PSELTXD_OFFSET) -#define NRF52_UART_PSELCTS (NRF52_UART0_BASE + NRF52_UART_PSELCTS_OFFSET) -#define NRF52_UART_PSELRXD (NRF52_UART0_BASE + NRF52_UART_PSELRXD_OFFSET) -#define NRF52_UART_RXD (NRF52_UART0_BASE + NRF52_UART_RXD_OFFSET) -#define NRF52_UART_TXD (NRF52_UART0_BASE + NRF52_UART_TXD_OFFSET) -#define NRF52_UART_BAUDRATE (NRF52_UART0_BASE + NRF52_UART_BAUDRATE_OFFSET) -#define NRF52_UART_CONFIG (NRF52_UART0_BASE + NRF52_UART_CONFIG_OFFSET) +/* UART/UARTE Register Addresses *********************************************************************/ -/* UARTE Register Addresses **************************************************************************/ +#define NRF52_UARTE0_TASKS_STARTRX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_STARTRX_OFFSET) +#define NRF52_UARTE0_TASKS_STOPRX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_STOPRX_OFFSET) +#define NRF52_UARTE0_TASKS_STARTTX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_STARTTX_OFFSET) +#define NRF52_UARTE0_TASKS_STOPTX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_STOPTX_OFFSET) +#define NRF52_UARTE0_TASKS_FLUSHRX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_FLUSHRX_OFFSET) +#define NRF52_UARTE0_EVENTS_CTS (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_CTS_OFFSET) +#define NRF52_UARTE0_EVENTS_NCTS (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_NCTS_OFFSET) +#define NRF52_UARTE0_EVENTS_RXDRDY (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_RXDRDY_OFFSET) +#define NRF52_UARTE0_EVENTS_ENDRX (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_ENDRX_OFFSET) +#define NRF52_UARTE0_EVENTS_TXDRDY (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_TXDRDY_OFFSET) +#define NRF52_UARTE0_EVENTS_ENDTX (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_ENDTX_OFFSET) +#define NRF52_UARTE0_EVENTS_ERROR (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_ERROR_OFFSET) +#define NRF52_UARTE0_EVENTS_RXTO (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_RXTO_OFFSET) +#define NRF52_UARTE0_EVENTS_RXSTARTED (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_RXSTARTED_OFFSET) +#define NRF52_UARTE0_EVENTS_TXSTARTED (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_TXSTARTED_OFFSET) +#define NRF52_UARTE0_EVENTS_TXSTOPPED (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_TXSTOPPED_OFFSET) +#define NRF52_UARTE0_SHORTS (NRF52_UARTE0_BASE + NRF52_UARTE_SHORTS_OFFSET) +#define NRF52_UARTE0_INTEN (NRF52_UARTE0_BASE + NRF52_UARTE_INTEN_OFFSET) +#define NRF52_UARTE0_INTENSET (NRF52_UARTE0_BASE + NRF52_UARTE_INTENSET_OFFSET) +#define NRF52_UARTE0_INTENCLR (NRF52_UARTE0_BASE + NRF52_UARTE_INTENCLR_OFFSET) +#define NRF52_UARTE0_ERRORSRC (NRF52_UARTE0_BASE + NRF52_UARTE_ERRORSRC_OFFSET) +#define NRF52_UARTE0_ENABLE (NRF52_UARTE0_BASE + NRF52_UARTE_ENABLE_OFFSET) +#define NRF52_UARTE0_PSEL_RTS (NRF52_UARTE0_BASE + NRF52_UARTE_PSEL_RTS_OFFSET) +#define NRF52_UARTE0_PSEL_TXD (NRF52_UARTE0_BASE + NRF52_UARTE_PSEL_TXD_OFFSET) +#define NRF52_UARTE0_PSEL_CTS (NRF52_UARTE0_BASE + NRF52_UARTE_PSEL_CTS_OFFSET) +#define NRF52_UARTE0_PSEL_RXD (NRF52_UARTE0_BASE + NRF52_UARTE_PSEL_RXD_OFFSET) +#define NRF52_UARTE0_BAUDRATE (NRF52_UARTE0_BASE + NRF52_UARTE_BAUDRATE_OFFSET) +#define NRF52_UARTE0_RXD_PTR (NRF52_UARTE0_BASE + NRF52_UARTE_RXD_PTR_OFFSET) +#define NRF52_UARTE0_RXD_MAXCNT (NRF52_UARTE0_BASE + NRF52_UARTE_RXD_MAXCNT_OFFSET) +#define NRF52_UARTE0_RXD_AMOUNT (NRF52_UARTE0_BASE + NRF52_UARTE_RXD_AMOUNT_OFFSET) +#define NRF52_UARTE0_TXD_PTR (NRF52_UARTE0_BASE + NRF52_UARTE_TXD_PTR_OFFSET) +#define NRF52_UARTE0_TXD_MAXCNT (NRF52_UARTE0_BASE + NRF52_UARTE_TXD_MAXCNT_OFFSET) +#define NRF52_UARTE0_TXD_AMOUNT (NRF52_UARTE0_BASE + NRF52_UARTE_TXD_AMOUNT_OFFSET) +#define NRF52_UARTE0_CONFIG (NRF52_UARTE0_BASE + NRF52_UARTE_CONFIG_OFFSET) + +#define NRF52_UART0_TASKS_STARTRX (NRF52_UART0_BASE + NRF52_UART_TASKS_STARTRX_OFFSET) +#define NRF52_UART0_TASKS_STOPRX (NRF52_UART0_BASE + NRF52_UART_TASKS_STOPRX_OFFSET) +#define NRF52_UART0_TASKS_STARTTX (NRF52_UART0_BASE + NRF52_UART_TASKS_STARTTX_OFFSET) +#define NRF52_UART0_TASKS_STOPTX (NRF52_UART0_BASE + NRF52_UART_TASKS_STOPTX_OFFSET) +#define NRF52_UART0_TASKS_SUSPEND (NRF52_UART0_BASE + NRF52_UART_TASKS_SUSPEND_OFFSET) +#define NRF52_UART0_EVENTS_CTS (NRF52_UART0_BASE + NRF52_UART_EVENTS_CTS_OFFSET) +#define NRF52_UART0_EVENTS_NCTS (NRF52_UART0_BASE + NRF52_UART_EVENTS_NCTS_OFFSET) +#define NRF52_UART0_EVENTS_RXDRDY (NRF52_UART0_BASE + NRF52_UART_EVENTS_RXDRDY_OFFSET) +#define NRF52_UART0_EVENTS_TXDRDY (NRF52_UART0_BASE + NRF52_UART_EVENTS_TXDRDY_OFFSET) +#define NRF52_UART0_EVENTS_ERROR (NRF52_UART0_BASE + NRF52_UART_EVENTS_ERROR_OFFSET) +#define NRF52_UART0_EVENTS_RXTO (NRF52_UART0_BASE + NRF52_UART_EVENTS_RXTO_OFFSET) +#define NRF52_UART0_SHORTS (NRF52_UART0_BASE + NRF52_UART_SHORTS_OFFSET) +#define NRF52_UART0_INTENSET (NRF52_UART0_BASE + NRF52_UART_INTENSET_OFFSET) +#define NRF52_UART0_INTENCLR (NRF52_UART0_BASE + NRF52_UART_INTENCLR_OFFSET) +#define NRF52_UART0_ERRORSRC (NRF52_UART0_BASE + NRF52_UART_ERRORSRC_OFFSET) +#define NRF52_UART0_ENABLE (NRF52_UART0_BASE + NRF52_UART_ENABLE_OFFSET) +#define NRF52_UART0_PSELRTS (NRF52_UART0_BASE + NRF52_UART_PSELRTS_OFFSET) +#define NRF52_UART0_PSELTXD (NRF52_UART0_BASE + NRF52_UART_PSELTXD_OFFSET) +#define NRF52_UART0_PSELCTS (NRF52_UART0_BASE + NRF52_UART_PSELCTS_OFFSET) +#define NRF52_UART0_PSELRXD (NRF52_UART0_BASE + NRF52_UART_PSELRXD_OFFSET) +#define NRF52_UART0_RXD (NRF52_UART0_BASE + NRF52_UART_RXD_OFFSET) +#define NRF52_UART0_TXD (NRF52_UART0_BASE + NRF52_UART_TXD_OFFSET) +#define NRF52_UART0_BAUDRATE (NRF52_UART0_BASE + NRF52_UART_BAUDRATE_OFFSET) +#define NRF52_UART0_CONFIG (NRF52_UART0_BASE + NRF52_UART_CONFIG_OFFSET) + +#ifdef CONFIG_NRF52_UART1 +# define NRF52_UARTE1_TASKS_STARTRX (NRF52_UARTE1_BASE + NRF52_UARTE_TASKS_STARTRX_OFFSET) +# define NRF52_UARTE1_TASKS_STOPRX (NRF52_UARTE1_BASE + NRF52_UARTE_TASKS_STOPRX_OFFSET) +# define NRF52_UARTE1_TASKS_STARTTX (NRF52_UARTE1_BASE + NRF52_UARTE_TASKS_STARTTX_OFFSET) +# define NRF52_UARTE1_TASKS_STOPTX (NRF52_UARTE1_BASE + NRF52_UARTE_TASKS_STOPTX_OFFSET) +# define NRF52_UARTE1_TASKS_FLUSHRX (NRF52_UARTE1_BASE + NRF52_UARTE_TASKS_FLUSHRX_OFFSET) +# define NRF52_UARTE1_EVENTS_CTS (NRF52_UARTE1_BASE + NRF52_UARTE_EVENTS_CTS_OFFSET) +# define NRF52_UARTE1_EVENTS_NCTS (NRF52_UARTE1_BASE + NRF52_UARTE_EVENTS_NCTS_OFFSET) +# define NRF52_UARTE1_EVENTS_RXDRDY (NRF52_UARTE1_BASE + NRF52_UARTE_EVENTS_RXDRDY_OFFSET) +# define NRF52_UARTE1_EVENTS_ENDRX (NRF52_UARTE1_BASE + NRF52_UARTE_EVENTS_ENDRX_OFFSET) +# define NRF52_UARTE1_EVENTS_TXDRDY (NRF52_UARTE1_BASE + NRF52_UARTE_EVENTS_TXDRDY_OFFSET) +# define NRF52_UARTE1_EVENTS_ENDTX (NRF52_UARTE1_BASE + NRF52_UARTE_EVENTS_ENDTX_OFFSET) +# define NRF52_UARTE1_EVENTS_ERROR (NRF52_UARTE1_BASE + NRF52_UARTE_EVENTS_ERROR_OFFSET) +# define NRF52_UARTE1_EVENTS_RXTO (NRF52_UARTE1_BASE + NRF52_UARTE_EVENTS_RXTO_OFFSET) +# define NRF52_UARTE1_EVENTS_RXSTARTED (NRF52_UARTE1_BASE + NRF52_UARTE_EVENTS_RXSTARTED_OFFSET) +# define NRF52_UARTE1_EVENTS_TXSTARTED (NRF52_UARTE1_BASE + NRF52_UARTE_EVENTS_TXSTARTED_OFFSET) +# define NRF52_UARTE1_EVENTS_TXSTOPPED (NRF52_UARTE1_BASE + NRF52_UARTE_EVENTS_TXSTOPPED_OFFSET) +# define NRF52_UARTE1_SHORTS (NRF52_UARTE1_BASE + NRF52_UARTE_SHORTS_OFFSET) +# define NRF52_UARTE1_INTEN (NRF52_UARTE1_BASE + NRF52_UARTE_INTEN_OFFSET) +# define NRF52_UARTE1_INTENSET (NRF52_UARTE1_BASE + NRF52_UARTE_INTENSET_OFFSET) +# define NRF52_UARTE1_INTENCLR (NRF52_UARTE1_BASE + NRF52_UARTE_INTENCLR_OFFSET) +# define NRF52_UARTE1_ERRORSRC (NRF52_UARTE1_BASE + NRF52_UARTE_ERRORSRC_OFFSET) +# define NRF52_UARTE1_ENABLE (NRF52_UARTE1_BASE + NRF52_UARTE_ENABLE_OFFSET) +# define NRF52_UARTE1_PSEL_RTS (NRF52_UARTE1_BASE + NRF52_UARTE_PSEL_RTS_OFFSET) +# define NRF52_UARTE1_PSEL_TXD (NRF52_UARTE1_BASE + NRF52_UARTE_PSEL_TXD_OFFSET) +# define NRF52_UARTE1_PSEL_CTS (NRF52_UARTE1_BASE + NRF52_UARTE_PSEL_CTS_OFFSET) +# define NRF52_UARTE1_PSEL_RXD (NRF52_UARTE1_BASE + NRF52_UARTE_PSEL_RXD_OFFSET) +# define NRF52_UARTE1_BAUDRATE (NRF52_UARTE1_BASE + NRF52_UARTE_BAUDRATE_OFFSET) +# define NRF52_UARTE1_RXD_PTR (NRF52_UARTE1_BASE + NRF52_UARTE_RXD_PTR_OFFSET) +# define NRF52_UARTE1_RXD_MAXCNT (NRF52_UARTE1_BASE + NRF52_UARTE_RXD_MAXCNT_OFFSET) +# define NRF52_UARTE1_RXD_AMOUNT (NRF52_UARTE1_BASE + NRF52_UARTE_RXD_AMOUNT_OFFSET) +# define NRF52_UARTE1_TXD_PTR (NRF52_UARTE1_BASE + NRF52_UARTE_TXD_PTR_OFFSET) +# define NRF52_UARTE1_TXD_MAXCNT (NRF52_UARTE1_BASE + NRF52_UARTE_TXD_MAXCNT_OFFSET) +# define NRF52_UARTE1_TXD_AMOUNT (NRF52_UARTE1_BASE + NRF52_UARTE_TXD_AMOUNT_OFFSET) +# define NRF52_UARTE1_CONFIG (NRF52_UARTE1_BASE + NRF52_UARTE_CONFIG_OFFSET) + +# define NRF52_UART1_TASKS_STARTRX (NRF52_UART1_BASE + NRF52_UART_TASKS_STARTRX_OFFSET) +# define NRF52_UART1_TASKS_STOPRX (NRF52_UART1_BASE + NRF52_UART_TASKS_STOPRX_OFFSET) +# define NRF52_UART1_TASKS_STARTTX (NRF52_UART1_BASE + NRF52_UART_TASKS_STARTTX_OFFSET) +# define NRF52_UART1_TASKS_STOPTX (NRF52_UART1_BASE + NRF52_UART_TASKS_STOPTX_OFFSET) +# define NRF52_UART1_TASKS_SUSPEND (NRF52_UART1_BASE + NRF52_UART_TASKS_SUSPEND_OFFSET) +# define NRF52_UART1_EVENTS_CTS (NRF52_UART1_BASE + NRF52_UART_EVENTS_CTS_OFFSET) +# define NRF52_UART1_EVENTS_NCTS (NRF52_UART1_BASE + NRF52_UART_EVENTS_NCTS_OFFSET) +# define NRF52_UART1_EVENTS_RXDRDY (NRF52_UART1_BASE + NRF52_UART_EVENTS_RXDRDY_OFFSET) +# define NRF52_UART1_EVENTS_TXDRDY (NRF52_UART1_BASE + NRF52_UART_EVENTS_TXDRDY_OFFSET) +# define NRF52_UART1_EVENTS_ERROR (NRF52_UART1_BASE + NRF52_UART_EVENTS_ERROR_OFFSET) +# define NRF52_UART1_EVENTS_RXTO (NRF52_UART1_BASE + NRF52_UART_EVENTS_RXTO_OFFSET) +# define NRF52_UART1_SHORTS (NRF52_UART1_BASE + NRF52_UART_SHORTS_OFFSET) +# define NRF52_UART1_INTENSET (NRF52_UART1_BASE + NRF52_UART_INTENSET_OFFSET) +# define NRF52_UART1_INTENCLR (NRF52_UART1_BASE + NRF52_UART_INTENCLR_OFFSET) +# define NRF52_UART1_ERRORSRC (NRF52_UART1_BASE + NRF52_UART_ERRORSRC_OFFSET) +# define NRF52_UART1_ENABLE (NRF52_UART1_BASE + NRF52_UART_ENABLE_OFFSET) +# define NRF52_UART1_PSELRTS (NRF52_UART1_BASE + NRF52_UART_PSELRTS_OFFSET) +# define NRF52_UART1_PSELTXD (NRF52_UART1_BASE + NRF52_UART_PSELTXD_OFFSET) +# define NRF52_UART1_PSELCTS (NRF52_UART1_BASE + NRF52_UART_PSELCTS_OFFSET) +# define NRF52_UART1_PSELRXD (NRF52_UART1_BASE + NRF52_UART_PSELRXD_OFFSET) +# define NRF52_UART1_RXD (NRF52_UART1_BASE + NRF52_UART_RXD_OFFSET) +# define NRF52_UART1_TXD (NRF52_UART1_BASE + NRF52_UART_TXD_OFFSET) +# define NRF52_UART1_BAUDRATE (NRF52_UART1_BASE + NRF52_UART_BAUDRATE_OFFSET) +# define NRF52_UART1_CONFIG (NRF52_UART1_BASE + NRF52_UART_CONFIG_OFFSET) +#endif /* UART Register Bitfield Definitions ****************************************************************/ +/* PSELRTS Register */ + +#define UART_PSELRTS_PIN_SHIFT (0) /* Bits 0-4: Pin number*/ +#define UART_PSELRTS_PIN_MASK (0xf << UART_PSELRTS_PIN_SHIFT) +#define UART_PSELRTS_PORT_SHIFT (5) /* Bit 5: Port number */ +#define UART_PSELRTS_PORT_MASK (0x1 << UART_PSELRTS_PORT_SHIFT) +#define UART_PSELRTS_CONNECT (1 << 31) /* Bit 31: Connection */ + +/* PSELTXD Register */ + +#define UART_PSELTXD_PIN_SHIFT (0) /* Bits 0-4: Pin number*/ +#define UART_PSELTXD_PIN_MASK (0xf << UART_PSELTXD_PIN_SHIFT) +#define UART_PSELTXD_PORT_SHIFT (5) /* Bit 5: Port number */ +#define UART_PSELTXD_PORT_MASK (0x1 << UART_PSELTXD_PORT_SHIFT) +#define UART_PSELTXD_CONNECT (1 << 31) /* Bit 31: Connection */ + +/* PSELCTS Register */ + +#define UART_PSELCTS_PIN_SHIFT (0) /* Bits 0-4: Pin number*/ +#define UART_PSELCTS_PIN_MASK (0xf << UART_PSELCTS_PIN_SHIFT) +#define UART_PSELCTS_PORT_SHIFT (5) /* Bit 5: Port number */ +#define UART_PSELCTS_PORT_MASK (0x1 << UART_PSELCTS_PORT_SHIFT) +#define UART_PSELCTS_CONNECT (1 << 31) /* Bit 31: Connection */ + +/* PSELRXD Register */ + +#define UART_PSELRXD_PIN_SHIFT (0) /* Bits 0-4: Pin number*/ +#define UART_PSELRXD_PIN_MASK (0xf << UART_PSELRXD_PIN_SHIFT) +#define UART_PSELRXD_PORT_SHIFT (5) /* Bit 5: Port number */ +#define UART_PSELRXD_PORT_MASK (0x1 << UART_PSELRXD_PORT_SHIFT) +#define UART_PSELRXD_CONNECT (1 << 31) /* Bit 31: Connection */ + /* ENABLE Register */ #define NRF52_UART_ENABLE_DISABLE (0) #define NRF52_UART_ENABLE_ENABLE (4) -/* INTENSET Register */ +/* INTEN/INTENSET/INTENCLR Register */ -#define NRF52_UART_INTENSET_RXDRDY (1 << 2) +#define UART_INT_CTS (1 << 0) +#define UART_INT_NCTS (1 << 1) +#define UART_INT_RXDRDY (1 << 2) +#define UART_INT_ENDRX (1 << 4) +#define UART_INT_TXDRDY (1 << 7) +#define UART_INT_ENDTX (1 << 8) +#define UART_INT_ERROR (1 << 9) +#define UART_INT_RXTO (1 << 17) +#define UART_INT_RXSTARTED (1 << 19) +#define UART_INT_TXSTARTED (1 << 20) +#define UART_INT_TXSTOPPED (1 << 22) + +/* BAUDRATE Register */ + +#if defined(CONFIG_ARCH_CHIP_NRF52832) +# define UART_BAUDRATE_1200 (0x0004f000) +# define UART_BAUDRATE_2400 (0x0009d000) +# define UART_BAUDRATE_4800 (0x0013b000) +# define UART_BAUDRATE_9600 (0x00275000) +# define UART_BAUDRATE_14400 (0x003b0000) +# define UART_BAUDRATE_19200 (0x004ea000) +# define UART_BAUDRATE_28800 (0x0075f000) +# define UART_BAUDRATE_38400 (0x009d5000) +# define UART_BAUDRATE_57600 (0x00ebf000) +# define UART_BAUDRATE_76000 (0x013a9000) +# define UART_BAUDRATE_115200 (0x01d7e000) +# define UART_BAUDRATE_230400 (0x03afb000) +# define UART_BAUDRATE_250000 (0x04000000) +# define UART_BAUDRATE_460800 (0x075f7000) +# define UART_BAUDRATE_921600 (0x0ebed000) +# define UART_BAUDRATE_1000000 (0x10000000) +#elif defined(CONFIG_ARCH_CHIP_NRF52833) +# define UART_BAUDRATE_1200 (0x0004f000) +# define UART_BAUDRATE_2400 (0x0009d000) +# define UART_BAUDRATE_4800 (0x0013b000) +# define UART_BAUDRATE_9600 (0x00275000) +# define UART_BAUDRATE_14400 (0x003b0000) +# define UART_BAUDRATE_19200 (0x004ea000) +# define UART_BAUDRATE_28800 (0x0075f000) +# define UART_BAUDRATE_31250 (0x00800000) +# define UART_BAUDRATE_38400 (0x009d5000) +# define UART_BAUDRATE_56000 (0x00e50000) +# define UART_BAUDRATE_57600 (0x00ebf000) +# define UART_BAUDRATE_76000 (0x013a9000) +# define UART_BAUDRATE_115200 (0x01d7e000) +# define UART_BAUDRATE_230400 (0x03afb000) +# define UART_BAUDRATE_250000 (0x04000000) +# define UART_BAUDRATE_460800 (0x075f7000) +# define UART_BAUDRATE_921600 (0x0ebed000) +# define UART_BAUDRATE_1000000 (0x10000000) +#elif defined(CONFIG_ARCH_CHIP_NRF52840) +# define UART_BAUDRATE_1200 (0x0004f000) +# define UART_BAUDRATE_2400 (0x0009d000) +# define UART_BAUDRATE_4800 (0x0013b000) +# define UART_BAUDRATE_9600 (0x00275000) +# define UART_BAUDRATE_14400 (0x003af000) +# define UART_BAUDRATE_19200 (0x004ea000) +# define UART_BAUDRATE_28800 (0x0075c000) +# define UART_BAUDRATE_31250 (0x00800000) +# define UART_BAUDRATE_38400 (0x009d0000) +# define UART_BAUDRATE_56000 (0x00e50000) +# define UART_BAUDRATE_57600 (0x00eb0000) +# define UART_BAUDRATE_76000 (0x013a9000) +# define UART_BAUDRATE_115200 (0x01d60000) +# define UART_BAUDRATE_230400 (0x03b00000) +# define UART_BAUDRATE_250000 (0x04000000) +# define UART_BAUDRATE_460800 (0x07400000) +# define UART_BAUDRATE_921600 (0x0f000000) +# define UART_BAUDRATE_1000000 (0x10000000) +#endif + +/* CONFIG Register */ + +#define UART_CONFIG_HWFC (1 << 0) /* Bit 0: Hardware flow control */ +#define UART_CONFIG_PARITY_SHIFT (1) /* Bits 1-3: Parity */ +#define UART_CONFIG_PARITY (7 << UART_CONFIG_PARITY_SHIFT) + +#if defined(CONFIG_ARCH_CHIP_NRF52833) || defined(CONFIG_ARCH_CHIP_NRF52840) +# define UART_CONFIG_STOP (1 << 4) /* Bit 4: Stop bits */ +#endif + +#ifdef CONFIG_ARCH_CHIP_NRF52833 +# define UART_CONFIG_PARITYTYPE (1 << 8) /* Bit 8: Parity type */ +#endif #endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_UARTE_H */ diff --git a/arch/arm/src/nrf52/hardware/nrf52_wdt.h b/arch/arm/src/nrf52/hardware/nrf52_wdt.h index 2037c91b93..0ad0447aa1 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_wdt.h +++ b/arch/arm/src/nrf52/hardware/nrf52_wdt.h @@ -69,6 +69,8 @@ #define NRF52_WDT_RR6_OFFSET 0x0618 /* Reload request 6 */ #define NRF52_WDT_RR7_OFFSET 0x061c /* Reload request 7 */ +/* WDT Register Addresses **************************************************************************/ + #define NRF52_WDT_TASKS_START (NRF52_WDT_BASE + NRF52_WDT_TASKS_START_OFFSET) #define NRF52_WDT_EVENTS_TIMEOUT (NRF52_WDT_BASE + NRF52_WDT_EVENTS_TIMEOUT_OFFSET) #define NRF52_WDT_INTENSET (NRF52_WDT_BASE + NRF52_WDT_INTENSET_OFFSET) @@ -87,8 +89,6 @@ #define NRF52_WDT_RR6 (NRF52_WDT_BASE + NRF52_WDT_RR6_OFFSET) #define NRF52_WDT_RR7 (NRF52_WDT_BASE + NRF52_WDT_RR7_OFFSET) -/* WDT Register Addresses **************************************************************************/ - /* UART Register Bitfield Definitions **************************************************************/ /* ENABLE Register */ diff --git a/arch/arm/src/nrf52/nrf52_allocateheap.c b/arch/arm/src/nrf52/nrf52_allocateheap.c index 344d47fc3f..dedf174cdd 100644 --- a/arch/arm/src/nrf52/nrf52_allocateheap.c +++ b/arch/arm/src/nrf52/nrf52_allocateheap.c @@ -59,7 +59,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ + /* Terminology. In the flat build (CONFIG_BUILD_FLAT=y), there is only a * single heap access with the standard allocations (malloc/free). This * heap is referred to as the user heap. In the protected build diff --git a/arch/arm/src/nrf52/nrf52_flash.c b/arch/arm/src/nrf52/nrf52_flash.c index 73073d8d21..746d09f9ba 100644 --- a/arch/arm/src/nrf52/nrf52_flash.c +++ b/arch/arm/src/nrf52/nrf52_flash.c @@ -324,7 +324,6 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) return -EFAULT; } - /* Get flash ready and begin flashing */ for (addr += NRF52_FLASH_BASE; count; count -= 4, pword++, addr += 4) diff --git a/arch/arm/src/nrf52/nrf52_gpio.c b/arch/arm/src/nrf52/nrf52_gpio.c index 2704d6c58d..70c788488d 100644 --- a/arch/arm/src/nrf52/nrf52_gpio.c +++ b/arch/arm/src/nrf52/nrf52_gpio.c @@ -242,6 +242,13 @@ void nrf52_gpio_write(nrf52_pinset_t pinset, bool value) unsigned int port; uint32_t offset; + /* Get port and pin number */ + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + + /* Get register address */ + if (value) { offset = nrf52_gpio_regget(port, NRF52_GPIO_OUTSET_OFFSET); @@ -251,8 +258,7 @@ void nrf52_gpio_write(nrf52_pinset_t pinset, bool value) offset = nrf52_gpio_regget(port, NRF52_GPIO_OUTCLR_OFFSET); } - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + /* Put register value */ putreg32(1 << pin, offset); } @@ -272,10 +278,17 @@ bool nrf52_gpio_read(nrf52_pinset_t pinset) uint32_t regval; uint32_t offset; - offset = nrf52_gpio_regget(port, NRF52_GPIO_IN_OFFSET); + /* Get port and pin number */ port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Get register address */ + + offset = nrf52_gpio_regget(port, NRF52_GPIO_IN_OFFSET); + + /* Get register value */ + regval = getreg32(offset); return (regval >> pin) & 1UL; diff --git a/arch/arm/src/nrf52/nrf52_lowputc.c b/arch/arm/src/nrf52/nrf52_lowputc.c index 2491191bdb..ca44bcb04c 100644 --- a/arch/arm/src/nrf52/nrf52_lowputc.c +++ b/arch/arm/src/nrf52/nrf52_lowputc.c @@ -116,11 +116,11 @@ static const struct uart_config_s g_console_config = #ifdef HAVE_UART_DEVICE static void nrf52_setbaud(uintptr_t base, const struct uart_config_s *config) { - uint32_t br = 0x01d7e000; /* 268.444444 */ + uint32_t br = 0; if (config->baud == 115200) { - br = 0x01d7e000; + br = UART_BAUDRATE_115200; } putreg32(br, base + NRF52_UART_BAUDRATE_OFFSET); @@ -135,7 +135,7 @@ static void nrf52_setbaud(uintptr_t base, const struct uart_config_s *config) * Name: nrf52_lowsetup * * Description: - * Called at the very beginning of _start. Performs low level initialization + * Called at the very beginning of _start. Performs low level initialization * including setup of the console UART. This UART initialization is done * early so that the serial console is available for debugging very early in * the boot sequence. @@ -165,7 +165,9 @@ void nrf52_lowsetup(void) #ifdef HAVE_UART_DEVICE void nrf52_usart_configure(uintptr_t base, const struct uart_config_s *config) { - uint32_t pin; + uint32_t pin = 0; + uint32_t port = 0; + uint32_t regval = 0; putreg32(1, base + NRF52_UART_TASKS_STOPRX_OFFSET); putreg32(1, base + NRF52_UART_TASKS_STOPTX_OFFSET); @@ -175,17 +177,30 @@ void nrf52_usart_configure(uintptr_t base, const struct uart_config_s *config) nrf52_setbaud(base, config); - /* Config and select pins for uart */ + /* Config GPIO pins for uart */ nrf52_gpio_config(config->txpin); nrf52_gpio_config(config->rxpin); - pin = (config->txpin & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - putreg32(pin, base + NRF52_UART_PSELTXD_OFFSET); - pin = (config->rxpin & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - putreg32(pin, base + NRF52_UART_PSELRXD_OFFSET); + /* Setect TX pins for UART */ - /* Enable */ + pin = (config->txpin & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + port = (config->txpin & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + + regval = (pin << UART_PSELTXD_PIN_SHIFT); + regval |= (port << UART_PSELTXD_PORT_SHIFT); + putreg32(regval, base + NRF52_UART_PSELTXD_OFFSET); + + /* Setect RX pins for UART */ + + pin = (config->rxpin & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + port = (config->rxpin & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + + regval = (pin << UART_PSELRXD_PIN_SHIFT); + regval |= (port << UART_PSELRXD_PORT_SHIFT); + putreg32(regval, base + NRF52_UART_PSELRXD_OFFSET); + + /* Enable UART */ putreg32(NRF52_UART_ENABLE_ENABLE, base + NRF52_UART_ENABLE_OFFSET); } diff --git a/arch/arm/src/nrf52/nrf52_lowputc.h b/arch/arm/src/nrf52/nrf52_lowputc.h index dd0a57ce24..75034125fa 100644 --- a/arch/arm/src/nrf52/nrf52_lowputc.h +++ b/arch/arm/src/nrf52/nrf52_lowputc.h @@ -99,14 +99,14 @@ void nrf52_lowsetup(void); void nrf52_usart_configure(uintptr_t base, FAR const struct uart_config_s *config); #endif -/**************************************************************************** +/************************************************************************************ * Name: nrf52_usart_disable * * Description: * Disable a UART. it will be necessary to again call * nrf52_usart_configure() in order to use this UART channel again. * - ****************************************************************************/ + ************************************************************************************/ #ifdef HAVE_UART_DEVICE void nrf52_usart_disable(uintptr_t base); diff --git a/arch/arm/src/nrf52/nrf52_serial.c b/arch/arm/src/nrf52/nrf52_serial.c index 544424f4bb..a32b70360f 100644 --- a/arch/arm/src/nrf52/nrf52_serial.c +++ b/arch/arm/src/nrf52/nrf52_serial.c @@ -70,6 +70,14 @@ * Pre-processor Definitions ****************************************************************************/ +/* How many UARTs are supported */ + +#ifdef HAVE_UART1 +# define NRF52_NUART 2 +#else +# define NRF52_NUART 1 +#endif + /* Some sanity checks *******************************************************/ /* Is there at least one UART enabled and configured as a RS-232 device? */ @@ -89,6 +97,14 @@ * numbered UART. */ +#ifdef CONFIG_UART0_SERIAL_CONSOLE +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +#elif CONFIG_UART1_SERIAL_CONSOLE +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -208,8 +224,6 @@ static struct nrf52_dev_s g_uart1priv = .uartbase = NRF52_UART1_BASE, .irq = NRF52_IRQ_UART1, .rx_available = false, - .tx_gpio = BOARD_UART1_TX_PIN, - .rx_gpio = BOARD_UART1_RX_PIN, .config = { .baud = CONFIG_UART1_BAUD, @@ -244,13 +258,17 @@ static uart_dev_t g_uart1port = }; #endif -#ifdef CONFIG_UART0_SERIAL_CONSOLE -# define CONSOLE_DEV g_uart0port /* UART0 is console */ -# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ -#elif CONFIG_UART1_SERIAL_CONSOLE -# define CONSOLE_DEV g_uart1port /* UART1 is console */ -# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +/* This table lets us iterate over the configured UARTs */ + +static struct uart_dev_s * const g_uart_devs[NRF52_NUART] = +{ +#ifdef HAVE_UART0 + [0] = &g_uart0port, #endif +#ifdef HAVE_UART1 + [1] = &g_uart1port +#endif +}; /**************************************************************************** * Private Functions @@ -268,17 +286,19 @@ static uart_dev_t g_uart1port = static int nrf52_setup(struct uart_dev_s *dev) { #ifndef CONFIG_SUPPRESS_UART_CONFIG - /* struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv; */ + struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv; - /* Configure the UART as an RS-232 UART */ + /* TODO: Configure the UART as an RS-232 UART */ /* REVISIT: If nrf52_usart_configure() called 2nd time uart stops working. * Rx interrupt keeps firing. * configuring is done on __start + * + * UPDATE 19.12.2019: No problems described above were observed, + * but just in case we leave the above note for some time. */ - /* nrf52_usart_configure(priv->uartbase, &priv->config); */ - + nrf52_usart_configure(priv->uartbase, &priv->config); #endif /* TODO: configure UART if not selected as console */ @@ -317,9 +337,10 @@ static void nrf52_shutdown(struct uart_dev_s *dev) * the setup() method is called, however, the serial console may operate in * a non-interrupt driven mode during the boot phase. * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). + * The RX and TX interrupts are not enabled until the txint() and rxint() + * methods are called. * ****************************************************************************/ @@ -357,7 +378,7 @@ static void nrf52_detach(struct uart_dev_s *dev) /* Disable interrupts */ - putreg32(NRF52_UART_INTENSET_RXDRDY, priv->uartbase + NRF52_UART_INTENCLR_OFFSET); + putreg32(UART_INT_RXDRDY, priv->uartbase + NRF52_UART_INTENCLR_OFFSET); up_disable_irq(priv->irq); /* Detach from the interrupt(s) */ @@ -464,20 +485,18 @@ static void nrf52_rxint(struct uart_dev_s *dev, bool enable) if (enable) { #ifndef CONFIG_SUPPRESS_SERIAL_INTS - /* Receive an interrupt when their is anything in the Rx data register (or an Rx - * timeout occurs). + /* Receive an interrupt when their is anything in the Rx data register + * (or an Rx timeout occurs). */ - putreg32(NRF52_UART_INTENSET_RXDRDY, - priv->uartbase + NRF52_UART_INTENSET_OFFSET); + putreg32(UART_INT_RXDRDY, priv->uartbase + NRF52_UART_INTENSET_OFFSET); putreg32(1, priv->uartbase + NRF52_UART_TASKS_STARTRX_OFFSET); #endif } else { - putreg32(NRF52_UART_INTENSET_RXDRDY, - priv->uartbase + NRF52_UART_INTENCLR_OFFSET); + putreg32(UART_INT_RXDRDY, priv->uartbase + NRF52_UART_INTENCLR_OFFSET); putreg32(1, priv->uartbase + NRF52_UART_TASKS_STOPRX_OFFSET); } } @@ -636,6 +655,10 @@ void nrf52_earlyserialinit(void) void up_serialinit(void) { + unsigned minor = 0; + unsigned i = 0; + char devname[16]; + #ifdef HAVE_UART_CONSOLE /* Register the serial console */ @@ -643,6 +666,33 @@ void up_serialinit(void) #endif (void)uart_register("/dev/ttyS0", &TTYS0_DEV); + minor = 1; + + /* Register all remaining UARTs */ + + strcpy(devname, "/dev/ttySx"); + + for (i = 0; i < NRF52_NUART; i++) + { + /* Don't create a device for non-configured ports. */ + + if (g_uart_devs[i] == 0) + { + continue; + } + + /* Don't create a device for the console - we did that above */ + + if (g_uart_devs[i]->isconsole) + { + continue; + } + + /* Register USARTs as devices in increasing order */ + + devname[9] = '0' + minor++; + (void)uart_register(devname, g_uart_devs[i]); + } } /**************************************************************************** diff --git a/arch/arm/src/nrf52/nrf52_wdt.c b/arch/arm/src/nrf52/nrf52_wdt.c index 873f48a526..c34575d6ef 100644 --- a/arch/arm/src/nrf52/nrf52_wdt.c +++ b/arch/arm/src/nrf52/nrf52_wdt.c @@ -360,8 +360,8 @@ static int nrf52_keepalive(FAR struct watchdog_lowerhalf_s *lower) * Get the current watchdog timer status * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure. * status - The location to return the watchdog status information. * * Returned Values: @@ -420,8 +420,8 @@ static int nrf52_getstatus(FAR struct watchdog_lowerhalf_s *lower, * Set a new timeout value (and reset the watchdog timer) * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure. * timeout - The new timeout value in milliseconds. * * Returned Values: @@ -511,16 +511,17 @@ int nrf52_wdt_initialize(FAR const char *devpath, int16_t mode_sleep, nrf52_clock_init(); - /* Select the lower power external 32,768Hz (Low-Speed External, LSE) oscillator - * as RTC Clock Source and enable the Clock. + /* Select the lower power external 32,768Hz (Low-Speed External, LSE) + * oscillator as RTC Clock Source and enable the Clock. */ - nrf52_clock_lsclk_start(); + nrf52_clock_lsclk_start(); #endif /* Register the watchdog driver as /dev/watchdog0 */ - handle = watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv); + handle = watchdog_register(devpath, + (FAR struct watchdog_lowerhalf_s *)priv); return (handle != NULL) ? OK : -ENODEV; } diff --git a/boards/arm/nrf52/nrf52840-dk/include/board.h b/boards/arm/nrf52/nrf52840-dk/include/board.h index da3f18fa96..b207d04162 100644 --- a/boards/arm/nrf52/nrf52840-dk/include/board.h +++ b/boards/arm/nrf52/nrf52840-dk/include/board.h @@ -122,4 +122,12 @@ #define BOARD_UART0_RX_PIN (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN(8)) #define BOARD_UART0_TX_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN(6)) +/* UART1 + * UART1_RX - P1.1 + * UART1_TX - P1.2 + */ + +#define BOARD_UART1_RX_PIN (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN(1)) +#define BOARD_UART1_TX_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN(2)) + #endif /* __BOARDS_ARM_NRF52_NRF52840_DK_INCLUDE_BOARD_H */