Fixes for STM32F40xxx port
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4135 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -2217,14 +2217,13 @@
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* fs/fat/fs_fat32util.c: In fat_systime2fattime(void) should be
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clock_gettime() and not clock_gettime(). Also, there is a place where
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FAT date is used instead of FAT time. (Thanks to David Sidrane).
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* arch/arm/src/stm32: Add support for the STM3240xxx MCU family.
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* arch/arm/src/stm32 and arch/arm/include/stm32: Add support for the
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STM32F50xxx family of MCUs.
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STM32F40xxx family of MCUs.
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* configs/stm3240g-eval: Add framework for the STMicro STM3240G-EVAL
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board.
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* include/sys/types.h: wchar_t is a builtin type in C++ and its
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declaration can cause errors with certain C++ compilers.
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* sched/sig_timedwait.c: Fix signal handling with the returned info
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* sched/sig_timedwait.c: Fix signal handling when the returned info
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is NULL. Before this change, it would derefence a NULL pointer
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in this case.
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* graphics/nxfonts/nxfonts_sans17x22.h and nxfonts_sans20x26.h: Add
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@ -2234,4 +2233,6 @@
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* drivers/input/ads7843e.c and tsc2007.c: Fix some errors in the poll
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setup error checking that was cloned into both drivers.
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* sched/mq_notify.c: Set errno appropriately on failures. There are
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still severl message queue functions that do not set errno!
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still several message queue functions that do not set errno!
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* arch/arm/src/stm32: Fixes to several STM32F40xxx files (contributed by
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Mikhail Bychek).
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@ -183,7 +183,7 @@
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#define GPIO_MODER_ALT (2) /* Alternate mode */
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#define GPIO_MODER_ANALOG (3) /* Analog mode */
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#define GPIO_MODER_SHIFT(n) ((n) << 2)
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#define GPIO_MODER_SHIFT(n) ((n) << 1)
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#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n))
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#define GPIO_MODER0_SHIFT (0)
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@ -231,7 +231,7 @@
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#define GPIO_OSPEED_50MHz (2) /* 50 MHz Fast speed */
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#define GPIO_OSPEED_100MHz (3) /* 100 MHz High speed on 30 pF (80 MHz Output max speed on 15 pF) */
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#define GPIO_OSPEED_SHIFT(n) ((n) << 2)
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#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
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#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
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#define GPIO_OSPEED0_SHIFT (0)
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@ -273,7 +273,7 @@
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#define GPIO_PUPDR_PULLUP (1) /* Pull-up */
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#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */
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#define GPIO_PUPDR_SHIFT(n) ((n) << 2)
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#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
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#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n))
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#define GPIO_PUPDR0_SHIFT (0)
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@ -329,7 +329,7 @@
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/* GPIO alternate function low/high register */
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#define GPIO_AFR_SHIFT(n) ((n) << 4)
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#define GPIO_AFR_SHIFT(n) ((n) << 2)
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#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n))
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#define GPIO_AFRL0_SHIFT (0)
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@ -350,21 +350,21 @@
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#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT)
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#define GPIO_AFRH8_SHIFT (0)
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#define GPIO_AFRH8_MASK (15 << GPIO_AFRH0_SHIFT)
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#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT)
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#define GPIO_AFRH9_SHIFT (4)
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#define GPIO_AFRH9_MASK (15 << GPIO_AFRH1_SHIFT)
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#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT)
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#define GPIO_AFRH10_SHIFT (8)
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#define GPIO_AFRH10_MASK (15 << GPIO_AFRH2_SHIFT)
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#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT)
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#define GPIO_AFRH11_SHIFT (12)
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#define GPIO_AFRH11_MASK (15 << GPIO_AFRH3_SHIFT)
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#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT)
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#define GPIO_AFRH12_SHIFT (16)
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#define GPIO_AFRH12_MASK (15 << GPIO_AFRH4_SHIFT)
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#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT)
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#define GPIO_AFRH13_SHIFT (20)
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#define GPIO_AFRH13_MASK (15 << GPIO_AFRH5_SHIFT)
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#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT)
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#define GPIO_AFRH14_SHIFT (24)
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#define GPIO_AFRH14_MASK (15 << GPIO_AFRH6_SHIFT)
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#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT)
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#define GPIO_AFRH15_SHIFT (28)
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#define GPIO_AFRH15_MASK (15 << GPIO_AFRH7_SHIFT)
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#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_GPIO_H */
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@ -164,8 +164,8 @@
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#define STM32_GPIOH_BASE 0x40021C00 /* 0x40021C00-0x40021fff: GPIO Port H */
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#define STM32_GPIOI_BASE 0x40022000 /* 0x40022000-0x400223ff: GPIO Port I */
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#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */
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#define STM32_RCC_BASE 0x40023800 /* 0x40023800-0x40023bff: Reset and Clock control RCC */
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#define STM32_FLASHIF_BASE 0x40023c00 /* 0x40023c00-0x40023fff: Flash memory interface */
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#define STM32_RCC_BASE 0x40038000 /* 0x40023800-0x40023bff: Reset and Clock control RCC */
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#define STM32_BKPSRAM_BASE 0x40024000 /* 0x40024000-0x40024fff: Backup SRAM (BKPSRAM) */
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#define STM32_DMA1_BASE 0x40026000 /* 0x40026000-0x400263ff: DMA1 */
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#define STM32_DMA2_BASE 0x40026400 /* 0x40026400-0x400267ff: DMA2 */
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@ -118,7 +118,7 @@ static inline void rcc_enableahb1(void)
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* selected AHB1 peripherals.
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*/
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regval = getreg32(STM32_RCC_APB1ENR);
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regval = getreg32(STM32_RCC_AHB1ENR);
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/* Enable GPIOA, GPIOB, .... GPIOI*/
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@ -194,7 +194,7 @@ static inline void rcc_enableahb1(void)
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regval |= (RCC_AHB1ENR_OTGHSEN|RCC_AHB1ENR_OTGHSULPIEN);
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#endif
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putreg32(regval, STM32_RCC_APB1ENR); /* Enable peripherals */
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putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
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}
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/****************************************************************************
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