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arch/arm/src/tiva: Starting to work through alternate function pin configuration and GPIO interrupts for C13xx. Works a lot differently than the LM and Tiva parts.

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This commit is contained in:
Gregory Nutt 2018-12-05 15:17:22 -06:00
parent 051e37bce2
commit d830b323dd
16 changed files with 1364 additions and 662 deletions
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46
arch/arm/include/tiva/cc13x0_irq.h
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@ -53,9 +53,6 @@
/* External interrupts (vectors >= 16) */
#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external
* interrupt */
#define TIVA_IRQ_AON_GPIO_EDGE (16) /* Edge detect event from IOC */
#define TIVA_IRQ_I2C (17) /* Interrupt event from I2C */
#define TIVA_IRQ_RFC_CPE_1 (18) /* Combined Interrupt for CPE
@ -95,5 +92,48 @@
#define TIVA_IRQ_TRNG (49) /* TRNG Interrupt event */
#define NR_IRQS (50) /* Number of interrupt vectors */
#define TIVA_IRQ_NEXTINT (NR_IRQS - 16)
/* GPIO IRQs -- Up to 31 interrupts, one for each supported pin */
#if defined(CONFIG_TIVA_GPIOIRQS)
# define TIVA_IRQ_DIO_0 (NR_IRQS + 0)
# define TIVA_IRQ_DIO_1 (NR_IRQS + 1)
# define TIVA_IRQ_DIO_2 (NR_IRQS + 2)
# define TIVA_IRQ_DIO_3 (NR_IRQS + 3)
# define TIVA_IRQ_DIO_4 (NR_IRQS + 4)
# define TIVA_IRQ_DIO_5 (NR_IRQS + 5)
# define TIVA_IRQ_DIO_6 (NR_IRQS + 6)
# define TIVA_IRQ_DIO_7 (NR_IRQS + 7)
# define TIVA_IRQ_DIO_8 (NR_IRQS + 8)
# define TIVA_IRQ_DIO_9 (NR_IRQS + 9)
# define TIVA_IRQ_DIO_10 (NR_IRQS + 10)
# define TIVA_IRQ_DIO_11 (NR_IRQS + 11)
# define TIVA_IRQ_DIO_12 (NR_IRQS + 12)
# define TIVA_IRQ_DIO_13 (NR_IRQS + 13)
# define TIVA_IRQ_DIO_14 (NR_IRQS + 14)
# define TIVA_IRQ_DIO_15 (NR_IRQS + 15)
# define TIVA_IRQ_DIO_16 (NR_IRQS + 16)
# define TIVA_IRQ_DIO_17 (NR_IRQS + 17)
# define TIVA_IRQ_DIO_18 (NR_IRQS + 18)
# define TIVA_IRQ_DIO_19 (NR_IRQS + 19)
# define TIVA_IRQ_DIO_20 (NR_IRQS + 20)
# define TIVA_IRQ_DIO_21 (NR_IRQS + 21)
# define TIVA_IRQ_DIO_22 (NR_IRQS + 22)
# define TIVA_IRQ_DIO_23 (NR_IRQS + 23)
# define TIVA_IRQ_DIO_24 (NR_IRQS + 24)
# define TIVA_IRQ_DIO_25 (NR_IRQS + 25)
# define TIVA_IRQ_DIO_26 (NR_IRQS + 26)
# define TIVA_IRQ_DIO_27 (NR_IRQS + 27)
# define TIVA_IRQ_DIO_28 (NR_IRQS + 28)
# define TIVA_IRQ_DIO_29 (NR_IRQS + 29)
# define TIVA_IRQ_DIO_30 (NR_IRQS + 30)
# define TIVA_IRQ_DIO_31 (NR_IRQS + 31)
# define _NGPIOIRQS (NR_IRQS + 32)
#else
# define _NGPIOIRQS NR_IRQS
#endif
#define NR_GPIO_IRQS (_NGPIOTIRQS - NR_IRQS)
#endif /* __ARCH_ARM_INCLUDE_TIVA_CC13X0_IRQ_H */

54
arch/arm/include/tiva/cc13x2_cc26x2_v2_irq.h → arch/arm/include/tiva/cc13x2_cc26x2_irq.h
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@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/include/tiva/cc13x2_cc26x2_v1_irq.h
* arch/arm/include/tiva/cc13x2_cc26x2_irq.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_TIVA_CC13X2_CC26x2_V2_IRQ_H
#define __ARCH_ARM_INCLUDE_TIVA_CC13X2_CC26x2_V2_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_TIVA_CC13X2_CC26x2_IRQ_H
#define __ARCH_ARM_INCLUDE_TIVA_CC13X2_CC26x2_IRQ_H
/************************************************************************************
* Included Files
@ -53,9 +53,6 @@
/* External interrupts (vectors >= 16) */
#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external
* interrupt */
#define TIVA_IRQ_AON_GPIO_EDGE (16) /* Edge detect event from IOC */
#define TIVA_IRQ_I2C (17) /* Interrupt event from I2C */
#define TIVA_IRQ_RFC_CPE_1 (18) /* Combined Interrupt for CPE
@ -102,5 +99,48 @@
* monitor */
#define NR_IRQS (54) /* Number of interrupt vectors */
#define TIVA_IRQ_NEXTINT (NR_IRQS - 16)
#endif /* __ARCH_ARM_INCLUDE_TIVA_CC13X2_CC26x2_V2_IRQ_H */
/* GPIO IRQs -- Up to 31 interrupts, one for each supported pin */
#if defined(CONFIG_TIVA_GPIOIRQS)
# define TIVA_IRQ_DIO_0 (NR_IRQS + 0)
# define TIVA_IRQ_DIO_1 (NR_IRQS + 1)
# define TIVA_IRQ_DIO_2 (NR_IRQS + 2)
# define TIVA_IRQ_DIO_3 (NR_IRQS + 3)
# define TIVA_IRQ_DIO_4 (NR_IRQS + 4)
# define TIVA_IRQ_DIO_5 (NR_IRQS + 5)
# define TIVA_IRQ_DIO_6 (NR_IRQS + 6)
# define TIVA_IRQ_DIO_7 (NR_IRQS + 7)
# define TIVA_IRQ_DIO_8 (NR_IRQS + 8)
# define TIVA_IRQ_DIO_9 (NR_IRQS + 9)
# define TIVA_IRQ_DIO_10 (NR_IRQS + 10)
# define TIVA_IRQ_DIO_11 (NR_IRQS + 11)
# define TIVA_IRQ_DIO_12 (NR_IRQS + 12)
# define TIVA_IRQ_DIO_13 (NR_IRQS + 13)
# define TIVA_IRQ_DIO_14 (NR_IRQS + 14)
# define TIVA_IRQ_DIO_15 (NR_IRQS + 15)
# define TIVA_IRQ_DIO_16 (NR_IRQS + 16)
# define TIVA_IRQ_DIO_17 (NR_IRQS + 17)
# define TIVA_IRQ_DIO_18 (NR_IRQS + 18)
# define TIVA_IRQ_DIO_19 (NR_IRQS + 19)
# define TIVA_IRQ_DIO_20 (NR_IRQS + 20)
# define TIVA_IRQ_DIO_21 (NR_IRQS + 21)
# define TIVA_IRQ_DIO_22 (NR_IRQS + 22)
# define TIVA_IRQ_DIO_23 (NR_IRQS + 23)
# define TIVA_IRQ_DIO_24 (NR_IRQS + 24)
# define TIVA_IRQ_DIO_25 (NR_IRQS + 25)
# define TIVA_IRQ_DIO_26 (NR_IRQS + 26)
# define TIVA_IRQ_DIO_27 (NR_IRQS + 27)
# define TIVA_IRQ_DIO_28 (NR_IRQS + 28)
# define TIVA_IRQ_DIO_29 (NR_IRQS + 29)
# define TIVA_IRQ_DIO_30 (NR_IRQS + 30)
# define TIVA_IRQ_DIO_31 (NR_IRQS + 31)
# define _NGPIOIRQS (NR_IRQS + 32)
#else
# define _NGPIOIRQS NR_IRQS
#endif
#define NR_GPIO_IRQS (_NGPIOTIRQS - NR_IRQS)
#endif /* __ARCH_ARM_INCLUDE_TIVA_CC13X2_CC26x2_IRQ_H */

106
arch/arm/include/tiva/cc13x2_cc26x2_v1_irq.h
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@ -1,106 +0,0 @@
/************************************************************************************
* arch/arm/include/tiva/cc13x2_cc26x2_v1_irq.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_TIVA_CC13X2_CC26x2_V1_IRQ_H
#define __ARCH_ARM_INCLUDE_TIVA_CC13X2_CC26x2_V1_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/******************************************************************************
* Pre-processor Definitions
******************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* External interrupts (vectors >= 16) */
#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external
* interrupt */
#define TIVA_IRQ_AON_GPIO_EDGE (16) /* Edge detect event from IOC */
#define TIVA_IRQ_I2C (17) /* Interrupt event from I2C */
#define TIVA_IRQ_RFC_CPE_1 (18) /* Combined Interrupt for CPE
* Generated events */
#define TIVA_IRQ_PKA (19) /* PKA Interrupt event */
#define TIVA_IRQ_AON_RTC_COMB (20) /* Event from AON_RTC */
#define TIVA_IRQ_UART0_COMB (21) /* UART0 combined interrupt */
#define TIVA_IRQ_AUX_SWEV0 (22) /* AUX software event 0 */
#define TIVA_IRQ_SSI0_COMB (23) /* SSI0 combined interrupt */
#define TIVA_IRQ_SSI1_COMB (24) /* SSI1 combined interrupt */
#define TIVA_IRQ_RFC_CPE_0 (25) /* Combined Interrupt for CPE
* Generated events */
#define TIVA_IRQ_RFC_HW_COMB (26) /* Combined RFC hardware interrupt */
#define TIVA_IRQ_RFC_CMD_ACK (27) /* RFC Doorbell Command
* Acknowledgement Interrupt */
#define TIVA_IRQ_I2S (28) /* Interrupt event from I2S */
#define TIVA_IRQ_AUX_SWEV1 (29) /* AUX software event 1 */
#define TIVA_IRQ_WDT (30) /* Watchdog interrupt event */
#define TIVA_IRQ_GPT0A (31) /* GPT0A interrupt event */
#define TIVA_IRQ_GPT0B (32) /* GPT0B interrupt event */
#define TIVA_IRQ_GPT1A (33) /* GPT1A interrupt event */
#define TIVA_IRQ_GPT1B (34) /* GPT1B interrupt event */
#define TIVA_IRQ_GPT2A (35) /* GPT2A interrupt event */
#define TIVA_IRQ_GPT2B (36) /* GPT2B interrupt event */
#define TIVA_IRQ_GPT3A (37) /* GPT3A interrupt event */
#define TIVA_IRQ_GPT3B (38) /* GPT3B interrupt event */
#define TIVA_IRQ_CRYPTO_RESULT_AVAIL (39) /* CRYPTO result available interupt
* event */
#define TIVA_IRQ_DMA_DONE_COMB (40) /* Combined DMA done */
#define TIVA_IRQ_DMA_ERR (41) /* DMA bus error */
#define TIVA_IRQ_FLASH (42) /* FLASH controller error event */
#define TIVA_IRQ_SWEV0 (43) /* Software event 0 */
#define TIVA_IRQ_AUX_COMB (44) /* AUX combined event */
#define TIVA_IRQ_AON_PROG0 (45) /* AON programmable event 0 */
#define TIVA_IRQ_PROG0 (46) /* Programmable Interrupt 0 */
#define TIVA_IRQ_AUX_COMPA (47) /* AUX Compare A event */
#define TIVA_IRQ_AUX_ADC (48) /* AUX ADC interrupt event */
#define TIVA_IRQ_TRNG (49) /* TRNG Interrupt event */
#define TIVA_IRQ_OSC_COMB (50) /* Combined event from Oscillator
* control */
#define TIVA_IRQ_AUX_TIMER2_EV0 (51) /* AUX Timer2 event 0 */
#define TIVA_IRQ_UART1_COMB (52) /* UART1 combined interrupt */
#define TIVA_IRQ_BATMON_COMB (53) /* Combined event from battery
* monitor */
#define NR_IRQS (54) /* Number of interrupt vectors */
#endif /* __ARCH_ARM_INCLUDE_TIVA_CC13X2_CC26x2_V1_IRQ_H */

270
arch/arm/include/tiva/irq.h
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@ -175,7 +175,9 @@
#define TIVA_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define TIVA_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* Chip-specific Interrupts (vectors 16 and above) */
/* Chip-specific external Interrupts (vectors 16 and above) */
#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_LM3S)
# include <arch/tiva/lm3s_irq.h>
@ -185,274 +187,12 @@
# include <arch/tiva/tm4c_irq.h>
#elif defined(CONFIG_ARCH_CHIP_CC13X0)
# include <arch/tiva/cc13x0_irq.h>
#elif defined(CONFIG_ARCH_CHIP_CC13X2_V1)
# include <arch/tiva/cc13x2_cc26x2_v1_irq.h>
#elif defined(CONFIG_ARCH_CHIP_CC13X2_V2)
# include <arch/tiva/cc13x2_cc26x2_v2_irq.h>
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
# include <arch/tiva/cc13x2_cc26x2_irq.h>
#else
# error "Unsupported Stellaris IRQ file"
#endif
#define TIVA_IRQ_NEXTINT (NR_IRQS - 16)
/* GPIO IRQs -- Note that support for individual GPIO ports can
* be disabled in order to reduce the size of the implementation.
*/
#if defined(CONFIG_TIVA_GPIOA_IRQS)
# define TIVA_IRQ_GPIOA_0 (NR_IRQS + 0)
# define TIVA_IRQ_GPIOA_1 (NR_IRQS + 1)
# define TIVA_IRQ_GPIOA_2 (NR_IRQS + 2)
# define TIVA_IRQ_GPIOA_3 (NR_IRQS + 3)
# define TIVA_IRQ_GPIOA_4 (NR_IRQS + 4)
# define TIVA_IRQ_GPIOA_5 (NR_IRQS + 5)
# define TIVA_IRQ_GPIOA_6 (NR_IRQS + 6)
# define TIVA_IRQ_GPIOA_7 (NR_IRQS + 7)
# define _NGPIOAIRQS (NR_IRQS + 8)
#else
# define _NGPIOAIRQS NR_IRQS
#endif
#if defined(CONFIG_TIVA_GPIOB_IRQS)
# define TIVA_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
# define TIVA_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
# define TIVA_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
# define TIVA_IRQ_GPIOB_3 (_NGPIOAIRQS + 3)
# define TIVA_IRQ_GPIOB_4 (_NGPIOAIRQS + 4)
# define TIVA_IRQ_GPIOB_5 (_NGPIOAIRQS + 5)
# define TIVA_IRQ_GPIOB_6 (_NGPIOAIRQS + 6)
# define TIVA_IRQ_GPIOB_7 (_NGPIOAIRQS + 7)
# define _NGPIOBIRQS (_NGPIOAIRQS + 8)
#else
# define _NGPIOBIRQS _NGPIOAIRQS
#endif
#if defined(CONFIG_TIVA_GPIOC_IRQS)
# define TIVA_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
# define TIVA_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
# define TIVA_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
# define TIVA_IRQ_GPIOC_3 (_NGPIOBIRQS + 3)
# define TIVA_IRQ_GPIOC_4 (_NGPIOBIRQS + 4)
# define TIVA_IRQ_GPIOC_5 (_NGPIOBIRQS + 5)
# define TIVA_IRQ_GPIOC_6 (_NGPIOBIRQS + 6)
# define TIVA_IRQ_GPIOC_7 (_NGPIOBIRQS + 7)
# define _NGPIOCIRQS (_NGPIOBIRQS + 8)
#else
# define _NGPIOCIRQS _NGPIOBIRQS
#endif
#if defined(CONFIG_TIVA_GPIOD_IRQS)
# define TIVA_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
# define TIVA_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
# define TIVA_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
# define TIVA_IRQ_GPIOD_3 (_NGPIOCIRQS + 3)
# define TIVA_IRQ_GPIOD_4 (_NGPIOCIRQS + 4)
# define TIVA_IRQ_GPIOD_5 (_NGPIOCIRQS + 5)
# define TIVA_IRQ_GPIOD_6 (_NGPIOCIRQS + 6)
# define TIVA_IRQ_GPIOD_7 (_NGPIOCIRQS + 7)
# define _NGPIODIRQS (_NGPIOCIRQS + 8)
#else
# define _NGPIODIRQS _NGPIOCIRQS
#endif
#if defined(CONFIG_TIVA_GPIOE_IRQS)
# define TIVA_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
# define TIVA_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
# define TIVA_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
# define TIVA_IRQ_GPIOE_3 (_NGPIODIRQS + 3)
# define TIVA_IRQ_GPIOE_4 (_NGPIODIRQS + 4)
# define TIVA_IRQ_GPIOE_5 (_NGPIODIRQS + 5)
# define TIVA_IRQ_GPIOE_6 (_NGPIODIRQS + 6)
# define TIVA_IRQ_GPIOE_7 (_NGPIODIRQS + 7)
# define _NGPIOEIRQS (_NGPIODIRQS + 8)
#else
# define _NGPIOEIRQS _NGPIODIRQS
#endif
#if defined(CONFIG_TIVA_GPIOF_IRQS)
# define TIVA_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
# define TIVA_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
# define TIVA_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
# define TIVA_IRQ_GPIOF_3 (_NGPIOEIRQS + 3)
# define TIVA_IRQ_GPIOF_4 (_NGPIOEIRQS + 4)
# define TIVA_IRQ_GPIOF_5 (_NGPIOEIRQS + 5)
# define TIVA_IRQ_GPIOF_6 (_NGPIOEIRQS + 6)
# define TIVA_IRQ_GPIOF_7 (_NGPIOEIRQS + 7)
# define _NGPIOFIRQS (_NGPIOEIRQS + 8)
#else
# define _NGPIOFIRQS _NGPIOEIRQS
#endif
#if defined(CONFIG_TIVA_GPIOG_IRQS)
# define TIVA_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
# define TIVA_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
# define TIVA_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
# define TIVA_IRQ_GPIOG_3 (_NGPIOFIRQS + 3)
# define TIVA_IRQ_GPIOG_4 (_NGPIOFIRQS + 4)
# define TIVA_IRQ_GPIOG_5 (_NGPIOFIRQS + 5)
# define TIVA_IRQ_GPIOG_6 (_NGPIOFIRQS + 6)
# define TIVA_IRQ_GPIOG_7 (_NGPIOFIRQS + 7)
# define _NGPIOGIRQS (_NGPIOFIRQS + 8)
#else
# define _NGPIOGIRQS _NGPIOFIRQS
#endif
#if defined(CONFIG_TIVA_GPIOH_IRQS)
# define TIVA_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
# define TIVA_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
# define TIVA_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
# define TIVA_IRQ_GPIOH_3 (_NGPIOGIRQS + 3)
# define TIVA_IRQ_GPIOH_4 (_NGPIOGIRQS + 4)
# define TIVA_IRQ_GPIOH_5 (_NGPIOGIRQS + 5)
# define TIVA_IRQ_GPIOH_6 (_NGPIOGIRQS + 6)
# define TIVA_IRQ_GPIOH_7 (_NGPIOGIRQS + 7)
# define _NGPIOHIRQS (_NGPIOGIRQS + 8)
#else
# define _NGPIOHIRQS _NGPIOGIRQS
#endif
#if defined(CONFIG_TIVA_GPIOJ_IRQS)
# define TIVA_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0)
# define TIVA_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1)
# define TIVA_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2)
# define TIVA_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3)
# define TIVA_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4)
# define TIVA_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5)
# define TIVA_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6)
# define TIVA_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7)
# define _NGPIOJIRQS (_NGPIOHIRQS + 8)
#else
# define _NGPIOJIRQS _NGPIOHIRQS
#endif
#if defined(CONFIG_TIVA_GPIOK_IRQS)
# define TIVA_IRQ_GPIOK_0 (_NGPIOJIRQS + 0)
# define TIVA_IRQ_GPIOK_1 (_NGPIOJIRQS + 1)
# define TIVA_IRQ_GPIOK_2 (_NGPIOJIRQS + 2)
# define TIVA_IRQ_GPIOK_3 (_NGPIOJIRQS + 3)
# define TIVA_IRQ_GPIOK_4 (_NGPIOJIRQS + 4)
# define TIVA_IRQ_GPIOK_5 (_NGPIOJIRQS + 5)
# define TIVA_IRQ_GPIOK_6 (_NGPIOJIRQS + 6)
# define TIVA_IRQ_GPIOK_7 (_NGPIOJIRQS + 7)
# define _NGPIOKIRQS (_NGPIOJIRQS + 8)
#else
# define _NGPIOKIRQS _NGPIOJIRQS
#endif
#if defined(CONFIG_TIVA_GPIOL_IRQS)
# define TIVA_IRQ_GPIOL_0 (_NGPIOKIRQS + 0)
# define TIVA_IRQ_GPIOL_1 (_NGPIOKIRQS + 1)
# define TIVA_IRQ_GPIOL_2 (_NGPIOKIRQS + 2)
# define TIVA_IRQ_GPIOL_3 (_NGPIOKIRQS + 3)
# define TIVA_IRQ_GPIOL_4 (_NGPIOKIRQS + 4)
# define TIVA_IRQ_GPIOL_5 (_NGPIOKIRQS + 5)
# define TIVA_IRQ_GPIOL_6 (_NGPIOKIRQS + 6)
# define TIVA_IRQ_GPIOL_7 (_NGPIOKIRQS + 7)
# define _NGPIOLIRQS (_NGPIOKIRQS + 8)
#else
# define _NGPIOLIRQS _NGPIOKIRQS
#endif
#if defined(CONFIG_TIVA_GPIOM_IRQS)
# define TIVA_IRQ_GPIOM_0 (_NGPIOLIRQS + 0)
# define TIVA_IRQ_GPIOM_1 (_NGPIOLIRQS + 1)
# define TIVA_IRQ_GPIOM_2 (_NGPIOLIRQS + 2)
# define TIVA_IRQ_GPIOM_3 (_NGPIOLIRQS + 3)
# define TIVA_IRQ_GPIOM_4 (_NGPIOLIRQS + 4)
# define TIVA_IRQ_GPIOM_5 (_NGPIOLIRQS + 5)
# define TIVA_IRQ_GPIOM_6 (_NGPIOLIRQS + 6)
# define TIVA_IRQ_GPIOM_7 (_NGPIOLIRQS + 7)
# define _NGPIOMIRQS (_NGPIOLIRQS + 8)
#else
# define _NGPIOMIRQS _NGPIOLIRQS
#endif
#if defined(CONFIG_TIVA_GPION_IRQS)
# define TIVA_IRQ_GPION_0 (_NGPIOMIRQS + 0)
# define TIVA_IRQ_GPION_1 (_NGPIOMIRQS + 1)
# define TIVA_IRQ_GPION_2 (_NGPIOMIRQS + 2)
# define TIVA_IRQ_GPION_3 (_NGPIOMIRQS + 3)
# define TIVA_IRQ_GPION_4 (_NGPIOMIRQS + 4)
# define TIVA_IRQ_GPION_5 (_NGPIOMIRQS + 5)
# define TIVA_IRQ_GPION_6 (_NGPIOMIRQS + 6)
# define TIVA_IRQ_GPION_7 (_NGPIOMIRQS + 7)
# define _NGPIONIRQS (_NGPIOMIRQS + 8)
#else
# define _NGPIONIRQS _NGPIOMIRQS
#endif
#if defined(CONFIG_TIVA_GPIOP_IRQS)
# define TIVA_IRQ_GPIOP_0 (_NGPIONIRQS + 0)
# define TIVA_IRQ_GPIOP_1 (_NGPIONIRQS + 1)
# define TIVA_IRQ_GPIOP_2 (_NGPIONIRQS + 2)
# define TIVA_IRQ_GPIOP_3 (_NGPIONIRQS + 3)
# define TIVA_IRQ_GPIOP_4 (_NGPIONIRQS + 4)
# define TIVA_IRQ_GPIOP_5 (_NGPIONIRQS + 5)
# define TIVA_IRQ_GPIOP_6 (_NGPIONIRQS + 6)
# define TIVA_IRQ_GPIOP_7 (_NGPIONIRQS + 7)
# define _NGPIOPIRQS (_NGPIONIRQS + 8)
#else
# define _NGPIOPIRQS _NGPIONIRQS
#endif
#if defined(CONFIG_TIVA_GPIOQ_IRQS)
# define TIVA_IRQ_GPIOQ_0 (_NGPIOPIRQS + 0)
# define TIVA_IRQ_GPIOQ_1 (_NGPIOPIRQS + 1)
# define TIVA_IRQ_GPIOQ_2 (_NGPIOPIRQS + 2)
# define TIVA_IRQ_GPIOQ_3 (_NGPIOPIRQS + 3)
# define TIVA_IRQ_GPIOQ_4 (_NGPIOPIRQS + 4)
# define TIVA_IRQ_GPIOQ_5 (_NGPIOPIRQS + 5)
# define TIVA_IRQ_GPIOQ_6 (_NGPIOPIRQS + 6)
# define TIVA_IRQ_GPIOQ_7 (_NGPIOPIRQS + 7)
# define _NGPIOQIRQS (_NGPIOPIRQS + 8)
#else
# define _NGPIOQIRQS _NGPIOPIRQS
#endif
#if defined(CONFIG_TIVA_GPIOR_IRQS)
# define TIVA_IRQ_GPIOR_0 (_NGPIOQIRQS + 0)
# define TIVA_IRQ_GPIOR_1 (_NGPIOQIRQS + 1)
# define TIVA_IRQ_GPIOR_2 (_NGPIOQIRQS + 2)
# define TIVA_IRQ_GPIOR_3 (_NGPIOQIRQS + 3)
# define TIVA_IRQ_GPIOR_4 (_NGPIOQIRQS + 4)
# define TIVA_IRQ_GPIOR_5 (_NGPIOQIRQS + 5)
# define TIVA_IRQ_GPIOR_6 (_NGPIOQIRQS + 6)
# define TIVA_IRQ_GPIOR_7 (_NGPIOQIRQS + 7)
# define _NGPIORIRQS (_NGPIOQIRQS + 8)
#else
# define _NGPIORIRQS _NGPIOQIRQS
#endif
#if defined(CONFIG_TIVA_GPIOS_IRQS)
# define TIVA_IRQ_GPIOS_0 (_NGPIORIRQS + 0)
# define TIVA_IRQ_GPIOS_1 (_NGPIORIRQS + 1)
# define TIVA_IRQ_GPIOS_2 (_NGPIORIRQS + 2)
# define TIVA_IRQ_GPIOS_3 (_NGPIORIRQS + 3)
# define TIVA_IRQ_GPIOS_4 (_NGPIORIRQS + 4)
# define TIVA_IRQ_GPIOS_5 (_NGPIORIRQS + 5)
# define TIVA_IRQ_GPIOS_6 (_NGPIORIRQS + 6)
# define TIVA_IRQ_GPIOS_7 (_NGPIORIRQS + 7)
# define _NGPIOSIRQS (_NGPIORIRQS + 8)
#else
# define _NGPIOSIRQS _NGPIORIRQS
#endif
#if defined(CONFIG_TIVA_GPIOT_IRQS)
# define TIVA_IRQ_GPIOT_0 (_NGPIOSIRQS + 0)
# define TIVA_IRQ_GPIOT_1 (_NGPIOSIRQS + 1)
# define TIVA_IRQ_GPIOT_2 (_NGPIOSIRQS + 2)
# define TIVA_IRQ_GPIOT_3 (_NGPIOSIRQS + 3)
# define TIVA_IRQ_GPIOT_4 (_NGPIOSIRQS + 4)
# define TIVA_IRQ_GPIOT_5 (_NGPIOSIRQS + 5)
# define TIVA_IRQ_GPIOT_6 (_NGPIOSIRQS + 6)
# define TIVA_IRQ_GPIOT_7 (_NGPIOSIRQS + 7)
# define _NGPIOTIRQS (_NGPIOSIRQS + 8)
#else
# define _NGPIOTIRQS _NGPIOSIRQS
#endif
#define NR_GPIO_IRQS (_NGPIOTIRQS - NR_IRQS)
/************************************************************************************
* Public Types
************************************************************************************/

135
arch/arm/include/tiva/lm3s_irq.h
View File

@ -53,7 +53,6 @@
/* External interrupts (vectors >= 16) */
#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
@ -385,6 +384,140 @@
# error "IRQ Numbers not specified for this Stellaris chip"
#endif
#define TIVA_IRQ_NEXTINT (NR_IRQS - 16)
/* GPIO IRQs -- Note that support for individual GPIO ports can
* be disabled in order to reduce the size of the implementation.
*/
/* No supported architecture supports interrupts on ports G-N or R-T */
#undef CONFIG_TIVA_GPIOG_IRQS /* G-N */
#undef CONFIG_TIVA_GPIOH_IRQS
#undef CONFIG_TIVA_GPIOJ_IRQS
#undef CONFIG_TIVA_GPIOK_IRQS
#undef CONFIG_TIVA_GPIOL_IRQS
#undef CONFIG_TIVA_GPIOM_IRQS
#undef CONFIG_TIVA_GPION_IRQS
#undef CONFIG_TIVA_GPIOR_IRQS /* R-T */
#undef CONFIG_TIVA_GPIOS_IRQS
#undef CONFIG_TIVA_GPIOT_IRQS
#if defined(CONFIG_TIVA_GPIOA_IRQS)
# define TIVA_IRQ_GPIOA_0 (NR_IRQS + 0)
# define TIVA_IRQ_GPIOA_1 (NR_IRQS + 1)
# define TIVA_IRQ_GPIOA_2 (NR_IRQS + 2)
# define TIVA_IRQ_GPIOA_3 (NR_IRQS + 3)
# define TIVA_IRQ_GPIOA_4 (NR_IRQS + 4)
# define TIVA_IRQ_GPIOA_5 (NR_IRQS + 5)
# define TIVA_IRQ_GPIOA_6 (NR_IRQS + 6)
# define TIVA_IRQ_GPIOA_7 (NR_IRQS + 7)
# define _NGPIOBIRQS (NR_IRQS + 8)
#else
# define _NGPIOBIRQS NR_IRQS
#endif
#if defined(CONFIG_TIVA_GPIOB_IRQS)
# define TIVA_IRQ_GPIOB_0 (_NGPIOBIRQS + 0)
# define TIVA_IRQ_GPIOB_1 (_NGPIOBIRQS + 1)
# define TIVA_IRQ_GPIOB_2 (_NGPIOBIRQS + 2)
# define TIVA_IRQ_GPIOB_3 (_NGPIOBIRQS + 3)
# define TIVA_IRQ_GPIOB_4 (_NGPIOBIRQS + 4)
# define TIVA_IRQ_GPIOB_5 (_NGPIOBIRQS + 5)
# define TIVA_IRQ_GPIOB_6 (_NGPIOBIRQS + 6)
# define TIVA_IRQ_GPIOB_7 (_NGPIOBIRQS + 7)
# define _NGPIOCIRQS (_NGPIOBIRQS + 8)
#else
# define _NGPIOCIRQS _NGPIOBIRQS
#endif
#if defined(CONFIG_TIVA_GPIOC_IRQS)
# define TIVA_IRQ_GPIOC_0 (_NGPIOCIRQS + 0)
# define TIVA_IRQ_GPIOC_1 (_NGPIOCIRQS + 1)
# define TIVA_IRQ_GPIOC_2 (_NGPIOCIRQS + 2)
# define TIVA_IRQ_GPIOC_3 (_NGPIOCIRQS + 3)
# define TIVA_IRQ_GPIOC_4 (_NGPIOCIRQS + 4)
# define TIVA_IRQ_GPIOC_5 (_NGPIOCIRQS + 5)
# define TIVA_IRQ_GPIOC_6 (_NGPIOCIRQS + 6)
# define TIVA_IRQ_GPIOC_7 (_NGPIOCIRQS + 7)
# define _NGPIODIRQS (_NGPIOCIRQS + 8)
#else
# define _NGPIODIRQS _NGPIOCIRQS
#endif
#if defined(CONFIG_TIVA_GPIOD_IRQS)
# define TIVA_IRQ_GPIOD_0 (_NGPIODIRQS + 0)
# define TIVA_IRQ_GPIOD_1 (_NGPIODIRQS + 1)
# define TIVA_IRQ_GPIOD_2 (_NGPIODIRQS + 2)
# define TIVA_IRQ_GPIOD_3 (_NGPIODIRQS + 3)
# define TIVA_IRQ_GPIOD_4 (_NGPIODIRQS + 4)
# define TIVA_IRQ_GPIOD_5 (_NGPIODIRQS + 5)
# define TIVA_IRQ_GPIOD_6 (_NGPIODIRQS + 6)
# define TIVA_IRQ_GPIOD_7 (_NGPIODIRQS + 7)
# define _NGPIOEIRQS (_NGPIODIRQS + 8)
#else
# define _NGPIOEIRQS _NGPIODIRQS
#endif
#if defined(CONFIG_TIVA_GPIOE_IRQS)
# define TIVA_IRQ_GPIOE_0 (_NGPIOEIRQS + 0)
# define TIVA_IRQ_GPIOE_1 (_NGPIOEIRQS + 1)
# define TIVA_IRQ_GPIOE_2 (_NGPIOEIRQS + 2)
# define TIVA_IRQ_GPIOE_3 (_NGPIOEIRQS + 3)
# define TIVA_IRQ_GPIOE_4 (_NGPIOEIRQS + 4)
# define TIVA_IRQ_GPIOE_5 (_NGPIOEIRQS + 5)
# define TIVA_IRQ_GPIOE_6 (_NGPIOEIRQS + 6)
# define TIVA_IRQ_GPIOE_7 (_NGPIOEIRQS + 7)
# define _NGPIOFIRQS (_NGPIOEIRQS + 8)
#else
# define _NGPIOFIRQS _NGPIOEIRQS
#endif
#if defined(CONFIG_TIVA_GPIOF_IRQS)
# define TIVA_IRQ_GPIOF_0 (_NGPIOFIRQS + 0)
# define TIVA_IRQ_GPIOF_1 (_NGPIOFIRQS + 1)
# define TIVA_IRQ_GPIOF_2 (_NGPIOFIRQS + 2)
# define TIVA_IRQ_GPIOF_3 (_NGPIOFIRQS + 3)
# define TIVA_IRQ_GPIOF_4 (_NGPIOFIRQS + 4)
# define TIVA_IRQ_GPIOF_5 (_NGPIOFIRQS + 5)
# define TIVA_IRQ_GPIOF_6 (_NGPIOFIRQS + 6)
# define TIVA_IRQ_GPIOF_7 (_NGPIOFIRQS + 7)
# define _NGPIONIRQS (_NGPIOFIRQS + 8)
#else
# define _NGPIONIRQS _NGPIOMIRQS
#endif
#if defined(CONFIG_TIVA_GPIOP_IRQS)
# define TIVA_IRQ_GPIOP_0 (_NGPIONIRQS + 0)
# define TIVA_IRQ_GPIOP_1 (_NGPIONIRQS + 1)
# define TIVA_IRQ_GPIOP_2 (_NGPIONIRQS + 2)
# define TIVA_IRQ_GPIOP_3 (_NGPIONIRQS + 3)
# define TIVA_IRQ_GPIOP_4 (_NGPIONIRQS + 4)
# define TIVA_IRQ_GPIOP_5 (_NGPIONIRQS + 5)
# define TIVA_IRQ_GPIOP_6 (_NGPIONIRQS + 6)
# define TIVA_IRQ_GPIOP_7 (_NGPIONIRQS + 7)
# define _NGPIOPIRQS (_NGPIONIRQS + 8)
#else
# define _NGPIOPIRQS _NGPIONIRQS
#endif
#if defined(CONFIG_TIVA_GPIOQ_IRQS)
# define TIVA_IRQ_GPIOQ_0 (_NGPIOPIRQS + 0)
# define TIVA_IRQ_GPIOQ_1 (_NGPIOPIRQS + 1)
# define TIVA_IRQ_GPIOQ_2 (_NGPIOPIRQS + 2)
# define TIVA_IRQ_GPIOQ_3 (_NGPIOPIRQS + 3)
# define TIVA_IRQ_GPIOQ_4 (_NGPIOPIRQS + 4)
# define TIVA_IRQ_GPIOQ_5 (_NGPIOPIRQS + 5)
# define TIVA_IRQ_GPIOQ_6 (_NGPIOPIRQS + 6)
# define TIVA_IRQ_GPIOQ_7 (_NGPIOPIRQS + 7)
# define _NGPIOQIRQS (_NGPIOPIRQS + 8)
#else
# define _NGPIOQIRQS _NGPIOPIRQS
#endif
#define NR_GPIO_IRQS (_NGPIOTIRQS - NR_IRQS)
/************************************************************************************
* Public Types
************************************************************************************/

136
arch/arm/include/tiva/lm4f_irq.h
View File

@ -53,8 +53,6 @@
/* External interrupts (vectors >= 16) */
#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_LM4F120)
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
@ -217,6 +215,140 @@
# error "IRQ Numbers not known for this Tiva chip"
#endif
#define TIVA_IRQ_NEXTINT (NR_IRQS - 16)
/* GPIO IRQs -- Note that support for individual GPIO ports can
* be disabled in order to reduce the size of the implementation.
*/
/* No supported architecture supports interrupts on ports G-N or R-T */
#undef CONFIG_TIVA_GPIOG_IRQS /* G-N */
#undef CONFIG_TIVA_GPIOH_IRQS
#undef CONFIG_TIVA_GPIOJ_IRQS
#undef CONFIG_TIVA_GPIOK_IRQS
#undef CONFIG_TIVA_GPIOL_IRQS
#undef CONFIG_TIVA_GPIOM_IRQS
#undef CONFIG_TIVA_GPION_IRQS
#undef CONFIG_TIVA_GPIOR_IRQS /* R-T */
#undef CONFIG_TIVA_GPIOS_IRQS
#undef CONFIG_TIVA_GPIOT_IRQS
#if defined(CONFIG_TIVA_GPIOA_IRQS)
# define TIVA_IRQ_GPIOA_0 (NR_IRQS + 0)
# define TIVA_IRQ_GPIOA_1 (NR_IRQS + 1)
# define TIVA_IRQ_GPIOA_2 (NR_IRQS + 2)
# define TIVA_IRQ_GPIOA_3 (NR_IRQS + 3)
# define TIVA_IRQ_GPIOA_4 (NR_IRQS + 4)
# define TIVA_IRQ_GPIOA_5 (NR_IRQS + 5)
# define TIVA_IRQ_GPIOA_6 (NR_IRQS + 6)
# define TIVA_IRQ_GPIOA_7 (NR_IRQS + 7)
# define _NGPIOBIRQS (NR_IRQS + 8)
#else
# define _NGPIOBIRQS NR_IRQS
#endif
#if defined(CONFIG_TIVA_GPIOB_IRQS)
# define TIVA_IRQ_GPIOB_0 (_NGPIOBIRQS + 0)
# define TIVA_IRQ_GPIOB_1 (_NGPIOBIRQS + 1)
# define TIVA_IRQ_GPIOB_2 (_NGPIOBIRQS + 2)
# define TIVA_IRQ_GPIOB_3 (_NGPIOBIRQS + 3)
# define TIVA_IRQ_GPIOB_4 (_NGPIOBIRQS + 4)
# define TIVA_IRQ_GPIOB_5 (_NGPIOBIRQS + 5)
# define TIVA_IRQ_GPIOB_6 (_NGPIOBIRQS + 6)
# define TIVA_IRQ_GPIOB_7 (_NGPIOBIRQS + 7)
# define _NGPIOCIRQS (_NGPIOBIRQS + 8)
#else
# define _NGPIOCIRQS _NGPIOBIRQS
#endif
#if defined(CONFIG_TIVA_GPIOC_IRQS)
# define TIVA_IRQ_GPIOC_0 (_NGPIOCIRQS + 0)
# define TIVA_IRQ_GPIOC_1 (_NGPIOCIRQS + 1)
# define TIVA_IRQ_GPIOC_2 (_NGPIOCIRQS + 2)
# define TIVA_IRQ_GPIOC_3 (_NGPIOCIRQS + 3)
# define TIVA_IRQ_GPIOC_4 (_NGPIOCIRQS + 4)
# define TIVA_IRQ_GPIOC_5 (_NGPIOCIRQS + 5)
# define TIVA_IRQ_GPIOC_6 (_NGPIOCIRQS + 6)
# define TIVA_IRQ_GPIOC_7 (_NGPIOCIRQS + 7)
# define _NGPIODIRQS (_NGPIOCIRQS + 8)
#else
# define _NGPIODIRQS _NGPIOCIRQS
#endif
#if defined(CONFIG_TIVA_GPIOD_IRQS)
# define TIVA_IRQ_GPIOD_0 (_NGPIODIRQS + 0)
# define TIVA_IRQ_GPIOD_1 (_NGPIODIRQS + 1)
# define TIVA_IRQ_GPIOD_2 (_NGPIODIRQS + 2)
# define TIVA_IRQ_GPIOD_3 (_NGPIODIRQS + 3)
# define TIVA_IRQ_GPIOD_4 (_NGPIODIRQS + 4)
# define TIVA_IRQ_GPIOD_5 (_NGPIODIRQS + 5)
# define TIVA_IRQ_GPIOD_6 (_NGPIODIRQS + 6)
# define TIVA_IRQ_GPIOD_7 (_NGPIODIRQS + 7)
# define _NGPIOEIRQS (_NGPIODIRQS + 8)
#else
# define _NGPIOEIRQS _NGPIODIRQS
#endif
#if defined(CONFIG_TIVA_GPIOE_IRQS)
# define TIVA_IRQ_GPIOE_0 (_NGPIOEIRQS + 0)
# define TIVA_IRQ_GPIOE_1 (_NGPIOEIRQS + 1)
# define TIVA_IRQ_GPIOE_2 (_NGPIOEIRQS + 2)
# define TIVA_IRQ_GPIOE_3 (_NGPIOEIRQS + 3)
# define TIVA_IRQ_GPIOE_4 (_NGPIOEIRQS + 4)
# define TIVA_IRQ_GPIOE_5 (_NGPIOEIRQS + 5)
# define TIVA_IRQ_GPIOE_6 (_NGPIOEIRQS + 6)
# define TIVA_IRQ_GPIOE_7 (_NGPIOEIRQS + 7)
# define _NGPIOFIRQS (_NGPIOEIRQS + 8)
#else
# define _NGPIOFIRQS _NGPIOEIRQS
#endif
#if defined(CONFIG_TIVA_GPIOF_IRQS)
# define TIVA_IRQ_GPIOF_0 (_NGPIOFIRQS + 0)
# define TIVA_IRQ_GPIOF_1 (_NGPIOFIRQS + 1)
# define TIVA_IRQ_GPIOF_2 (_NGPIOFIRQS + 2)
# define TIVA_IRQ_GPIOF_3 (_NGPIOFIRQS + 3)
# define TIVA_IRQ_GPIOF_4 (_NGPIOFIRQS + 4)
# define TIVA_IRQ_GPIOF_5 (_NGPIOFIRQS + 5)
# define TIVA_IRQ_GPIOF_6 (_NGPIOFIRQS + 6)
# define TIVA_IRQ_GPIOF_7 (_NGPIOFIRQS + 7)
# define _NGPIONIRQS (_NGPIOFIRQS + 8)
#else
# define _NGPIONIRQS _NGPIOMIRQS
#endif
#if defined(CONFIG_TIVA_GPIOP_IRQS)
# define TIVA_IRQ_GPIOP_0 (_NGPIONIRQS + 0)
# define TIVA_IRQ_GPIOP_1 (_NGPIONIRQS + 1)
# define TIVA_IRQ_GPIOP_2 (_NGPIONIRQS + 2)
# define TIVA_IRQ_GPIOP_3 (_NGPIONIRQS + 3)
# define TIVA_IRQ_GPIOP_4 (_NGPIONIRQS + 4)
# define TIVA_IRQ_GPIOP_5 (_NGPIONIRQS + 5)
# define TIVA_IRQ_GPIOP_6 (_NGPIONIRQS + 6)
# define TIVA_IRQ_GPIOP_7 (_NGPIONIRQS + 7)
# define _NGPIOPIRQS (_NGPIONIRQS + 8)
#else
# define _NGPIOPIRQS _NGPIONIRQS
#endif
#if defined(CONFIG_TIVA_GPIOQ_IRQS)
# define TIVA_IRQ_GPIOQ_0 (_NGPIOPIRQS + 0)
# define TIVA_IRQ_GPIOQ_1 (_NGPIOPIRQS + 1)
# define TIVA_IRQ_GPIOQ_2 (_NGPIOPIRQS + 2)
# define TIVA_IRQ_GPIOQ_3 (_NGPIOPIRQS + 3)
# define TIVA_IRQ_GPIOQ_4 (_NGPIOPIRQS + 4)
# define TIVA_IRQ_GPIOQ_5 (_NGPIOPIRQS + 5)
# define TIVA_IRQ_GPIOQ_6 (_NGPIOPIRQS + 6)
# define TIVA_IRQ_GPIOQ_7 (_NGPIOPIRQS + 7)
# define _NGPIOQIRQS (_NGPIOPIRQS + 8)
#else
# define _NGPIOQIRQS _NGPIOPIRQS
#endif
#define NR_GPIO_IRQS (_NGPIOTIRQS - NR_IRQS)
/************************************************************************************
* Public Types
************************************************************************************/

166
arch/arm/include/tiva/tm4c_irq.h
View File

@ -53,8 +53,6 @@
/* External interrupts (vectors >= 16) */
#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
@ -632,6 +630,170 @@
# error "IRQ Numbers not known for this Tiva chip"
#endif
#define TIVA_IRQ_NEXTINT (NR_IRQS - 16)
/* GPIO IRQs -- Note that support for individual GPIO ports can
* be disabled in order to reduce the size of the implementation.
*/
/* The TM4C123GH6PMI supports ports A-F of which any can support interrupts */
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
# undef CONFIG_TIVA_GPIOP_IRQS /* P-Q */
# undef CONFIG_TIVA_GPIOQ_IRQS
/* The TM4C123GH6PGE supports interrupts only on port P */
#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE)
# undef CONFIG_TIVA_GPIOA_IRQS /* A-F */
# undef CONFIG_TIVA_GPIOB_IRQS
# undef CONFIG_TIVA_GPIOC_IRQS
# undef CONFIG_TIVA_GPIOD_IRQS
# undef CONFIG_TIVA_GPIOE_IRQS
# undef CONFIG_TIVA_GPIOF_IRQS
# undef CONFIG_TIVA_GPIOQ_IRQS /* Q */
/* The TM4C123GH6ZRB and the TM4C129x support interrupts only on ports P and Q. */
#else
# undef CONFIG_TIVA_GPIOA_IRQS /* A-F */
# undef CONFIG_TIVA_GPIOB_IRQS
# undef CONFIG_TIVA_GPIOC_IRQS
# undef CONFIG_TIVA_GPIOD_IRQS
# undef CONFIG_TIVA_GPIOE_IRQS
# undef CONFIG_TIVA_GPIOF_IRQS
#endif
/* No supported architecture supports interrupts on ports G-N or R-T */
#undef CONFIG_TIVA_GPIOG_IRQS /* G-N */
#undef CONFIG_TIVA_GPIOH_IRQS
#undef CONFIG_TIVA_GPIOJ_IRQS
#undef CONFIG_TIVA_GPIOK_IRQS
#undef CONFIG_TIVA_GPIOL_IRQS
#undef CONFIG_TIVA_GPIOM_IRQS
#undef CONFIG_TIVA_GPION_IRQS
#undef CONFIG_TIVA_GPIOR_IRQS /* R-T */
#undef CONFIG_TIVA_GPIOS_IRQS
#undef CONFIG_TIVA_GPIOT_IRQS
#if defined(CONFIG_TIVA_GPIOA_IRQS)
# define TIVA_IRQ_GPIOA_0 (NR_IRQS + 0)
# define TIVA_IRQ_GPIOA_1 (NR_IRQS + 1)
# define TIVA_IRQ_GPIOA_2 (NR_IRQS + 2)
# define TIVA_IRQ_GPIOA_3 (NR_IRQS + 3)
# define TIVA_IRQ_GPIOA_4 (NR_IRQS + 4)
# define TIVA_IRQ_GPIOA_5 (NR_IRQS + 5)
# define TIVA_IRQ_GPIOA_6 (NR_IRQS + 6)
# define TIVA_IRQ_GPIOA_7 (NR_IRQS + 7)
# define _NGPIOBIRQS (NR_IRQS + 8)
#else
# define _NGPIOBIRQS NR_IRQS
#endif
#if defined(CONFIG_TIVA_GPIOB_IRQS)
# define TIVA_IRQ_GPIOB_0 (_NGPIOBIRQS + 0)
# define TIVA_IRQ_GPIOB_1 (_NGPIOBIRQS + 1)
# define TIVA_IRQ_GPIOB_2 (_NGPIOBIRQS + 2)
# define TIVA_IRQ_GPIOB_3 (_NGPIOBIRQS + 3)
# define TIVA_IRQ_GPIOB_4 (_NGPIOBIRQS + 4)
# define TIVA_IRQ_GPIOB_5 (_NGPIOBIRQS + 5)
# define TIVA_IRQ_GPIOB_6 (_NGPIOBIRQS + 6)
# define TIVA_IRQ_GPIOB_7 (_NGPIOBIRQS + 7)
# define _NGPIOCIRQS (_NGPIOBIRQS + 8)
#else
# define _NGPIOCIRQS _NGPIOBIRQS
#endif
#if defined(CONFIG_TIVA_GPIOC_IRQS)
# define TIVA_IRQ_GPIOC_0 (_NGPIOCIRQS + 0)
# define TIVA_IRQ_GPIOC_1 (_NGPIOCIRQS + 1)
# define TIVA_IRQ_GPIOC_2 (_NGPIOCIRQS + 2)
# define TIVA_IRQ_GPIOC_3 (_NGPIOCIRQS + 3)
# define TIVA_IRQ_GPIOC_4 (_NGPIOCIRQS + 4)
# define TIVA_IRQ_GPIOC_5 (_NGPIOCIRQS + 5)
# define TIVA_IRQ_GPIOC_6 (_NGPIOCIRQS + 6)
# define TIVA_IRQ_GPIOC_7 (_NGPIOCIRQS + 7)
# define _NGPIODIRQS (_NGPIOCIRQS + 8)
#else
# define _NGPIODIRQS _NGPIOCIRQS
#endif
#if defined(CONFIG_TIVA_GPIOD_IRQS)
# define TIVA_IRQ_GPIOD_0 (_NGPIODIRQS + 0)
# define TIVA_IRQ_GPIOD_1 (_NGPIODIRQS + 1)
# define TIVA_IRQ_GPIOD_2 (_NGPIODIRQS + 2)
# define TIVA_IRQ_GPIOD_3 (_NGPIODIRQS + 3)
# define TIVA_IRQ_GPIOD_4 (_NGPIODIRQS + 4)
# define TIVA_IRQ_GPIOD_5 (_NGPIODIRQS + 5)
# define TIVA_IRQ_GPIOD_6 (_NGPIODIRQS + 6)
# define TIVA_IRQ_GPIOD_7 (_NGPIODIRQS + 7)
# define _NGPIOEIRQS (_NGPIODIRQS + 8)
#else
# define _NGPIOEIRQS _NGPIODIRQS
#endif
#if defined(CONFIG_TIVA_GPIOE_IRQS)
# define TIVA_IRQ_GPIOE_0 (_NGPIOEIRQS + 0)
# define TIVA_IRQ_GPIOE_1 (_NGPIOEIRQS + 1)
# define TIVA_IRQ_GPIOE_2 (_NGPIOEIRQS + 2)
# define TIVA_IRQ_GPIOE_3 (_NGPIOEIRQS + 3)
# define TIVA_IRQ_GPIOE_4 (_NGPIOEIRQS + 4)
# define TIVA_IRQ_GPIOE_5 (_NGPIOEIRQS + 5)
# define TIVA_IRQ_GPIOE_6 (_NGPIOEIRQS + 6)
# define TIVA_IRQ_GPIOE_7 (_NGPIOEIRQS + 7)
# define _NGPIOFIRQS (_NGPIOEIRQS + 8)
#else
# define _NGPIOFIRQS _NGPIOEIRQS
#endif
#if defined(CONFIG_TIVA_GPIOF_IRQS)
# define TIVA_IRQ_GPIOF_0 (_NGPIOFIRQS + 0)
# define TIVA_IRQ_GPIOF_1 (_NGPIOFIRQS + 1)
# define TIVA_IRQ_GPIOF_2 (_NGPIOFIRQS + 2)
# define TIVA_IRQ_GPIOF_3 (_NGPIOFIRQS + 3)
# define TIVA_IRQ_GPIOF_4 (_NGPIOFIRQS + 4)
# define TIVA_IRQ_GPIOF_5 (_NGPIOFIRQS + 5)
# define TIVA_IRQ_GPIOF_6 (_NGPIOFIRQS + 6)
# define TIVA_IRQ_GPIOF_7 (_NGPIOFIRQS + 7)
# define _NGPIONIRQS (_NGPIOFIRQS + 8)
#else
# define _NGPIONIRQS _NGPIOMIRQS
#endif
#if defined(CONFIG_TIVA_GPIOP_IRQS)
# define TIVA_IRQ_GPIOP_0 (_NGPIONIRQS + 0)
# define TIVA_IRQ_GPIOP_1 (_NGPIONIRQS + 1)
# define TIVA_IRQ_GPIOP_2 (_NGPIONIRQS + 2)
# define TIVA_IRQ_GPIOP_3 (_NGPIONIRQS + 3)
# define TIVA_IRQ_GPIOP_4 (_NGPIONIRQS + 4)
# define TIVA_IRQ_GPIOP_5 (_NGPIONIRQS + 5)
# define TIVA_IRQ_GPIOP_6 (_NGPIONIRQS + 6)
# define TIVA_IRQ_GPIOP_7 (_NGPIONIRQS + 7)
# define _NGPIOPIRQS (_NGPIONIRQS + 8)
#else
# define _NGPIOPIRQS _NGPIONIRQS
#endif
#if defined(CONFIG_TIVA_GPIOQ_IRQS)
# define TIVA_IRQ_GPIOQ_0 (_NGPIOPIRQS + 0)
# define TIVA_IRQ_GPIOQ_1 (_NGPIOPIRQS + 1)
# define TIVA_IRQ_GPIOQ_2 (_NGPIOPIRQS + 2)
# define TIVA_IRQ_GPIOQ_3 (_NGPIOPIRQS + 3)
# define TIVA_IRQ_GPIOQ_4 (_NGPIOPIRQS + 4)
# define TIVA_IRQ_GPIOQ_5 (_NGPIOPIRQS + 5)
# define TIVA_IRQ_GPIOQ_6 (_NGPIOPIRQS + 6)
# define TIVA_IRQ_GPIOQ_7 (_NGPIOPIRQS + 7)
# define _NGPIOQIRQS (_NGPIOPIRQS + 8)
#else
# define _NGPIOQIRQS _NGPIOPIRQS
#endif
#define NR_GPIO_IRQS (_NGPIOTIRQS - NR_IRQS)
/************************************************************************************
* Public Types
************************************************************************************/

12
arch/arm/src/tiva/Make.defs
View File

@ -83,19 +83,19 @@ CMN_CSRCS += up_allocateheap.c
endif
CHIP_ASRCS =
CHIP_CSRCS = tiva_allocateheap.c tiva_irq.c tiva_gpioirq.c tiva_lowputc.c
CHIP_CSRCS += tiva_serial.c tiva_ssi.c
CHIP_CSRCS = tiva_allocateheap.c tiva_irq.c tiva_lowputc.c tiva_serial.c
CHIP_CSRCS += tiva_ssi.c
ifeq ($(CONFIG_ARCH_CHIP_LM3S),y)
CHIP_CSRCS += tiva_start.c lm3s_gpio.c
CHIP_CSRCS += tiva_start.c lm3s_gpio.c tiva_gpioirq.c
else ifeq ($(CONFIG_ARCH_CHIP_LM4F),y)
CHIP_CSRCS += tiva_start.c lm4f_gpio.c
CHIP_CSRCS += tiva_start.c lm4f_gpio.c tiva_gpioirq.c
else ifeq ($(CONFIG_ARCH_CHIP_TM4C),y)
CHIP_CSRCS += tiva_start.c tm4c_gpio.c
else ifeq ($(CONFIG_ARCH_CHIP_CC13X0),y)
CHIP_CSRCS += cc13xx_start.c cc13c0_gpio.c
CHIP_CSRCS += cc13xx_start.c cc13xx_gpio.c cc13xx_gpioirq.c
else ifeq ($(CONFIG_ARCH_CHIP_CC13X2),y)
CHIP_CSRCS += cc13xx_start.c cc13x2_cc26x2_gpio.c
CHIP_CSRCS += cc13xx_start.c cc13xx_gpio.c cc13xx_gpioirq.c
endif
ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)

6
arch/arm/src/tiva/hardware/cc13x0/cc13x0_ioc.h
View File

@ -130,9 +130,9 @@
# define IOC_IOCFG_PORTID(n) ((uint32_t)(n) << IOC_IOCFG_PORTID_MASK) /* See PORT ID definitions */
#define IOC_IOCFG_IOSTR_SHIFT (8) /* Bits 8-9: I/O drive strength */
#define IOC_IOCFG_IOSTR_MASK (3 << IOC_IOCFG_IOSTR_SHIFT)
# define IOC_IOCFG_IOSTR_AUTO (3 << IOC_IOCFG_IOSTR_SHIFT) /* Automatic drive strength */
# define IOC_IOCFG_IOSTR_MIN (3 << IOC_IOCFG_IOSTR_SHIFT) /* Minimum drive strength */
# define IOC_IOCFG_IOSTR_MED (3 << IOC_IOCFG_IOSTR_SHIFT) /* Medium drive strength */
# define IOC_IOCFG_IOSTR_AUTO (0 << IOC_IOCFG_IOSTR_SHIFT) /* Automatic drive strength */
# define IOC_IOCFG_IOSTR_MIN (1 << IOC_IOCFG_IOSTR_SHIFT) /* Minimum drive strength */
# define IOC_IOCFG_IOSTR_MED (2 << IOC_IOCFG_IOSTR_SHIFT) /* Medium drive strength */
# define IOC_IOCFG_IOSTR_MAX (3 << IOC_IOCFG_IOSTR_SHIFT) /* Maximum drive strength */
#define IOC_IOCFG_IOCURR_SHIFT (10) /* Bits 10-11: I/O current mode */
#define IOC_IOCFG_IOCURR_MASK (3 << IOC_IOCFG_IOCURR_SHIFT)

8
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ioc.h
View File

@ -126,13 +126,13 @@
#define IOC_IOCFG_PORTID_MASK (0) /* Bits 0-5: Selects DIO usage */
#define IOC_IOCFG_PORTID_SHIFT (0x3f << IOC_IOCFG_PORTID_MASK)
# define IOC_IOCFG_PORTID(n) ((uint32_t)(n) << IOC_IOCFG_PORTID_MASK) /* See PORT ID definitions */
#define IOC_IOCFG_IOEV_MCU_WUEN (1 << 6) /* Bit 6: Input edte asserts MCU_WU event */
#define IOC_IOCFG_IOEV_MCU_WUEN (1 << 6) /* Bit 6: Input edge asserts MCU_WU event */
#define IOC_IOCFG_IOEV_RTCEN (1 << 7) /* Bit 7: Input edge asserts RTC event */
#define IOC_IOCFG_IOSTR_SHIFT (8) /* Bits 8-9: I/O drive strength */
#define IOC_IOCFG_IOSTR_MASK (3 << IOC_IOCFG_IOSTR_SHIFT)
# define IOC_IOCFG_IOSTR_AUTO (3 << IOC_IOCFG_IOSTR_SHIFT) /* Automatic drive strength */
# define IOC_IOCFG_IOSTR_MIN (3 << IOC_IOCFG_IOSTR_SHIFT) /* Minimum drive strength */
# define IOC_IOCFG_IOSTR_MED (3 << IOC_IOCFG_IOSTR_SHIFT) /* Medium drive strength */
# define IOC_IOCFG_IOSTR_AUTO (0 << IOC_IOCFG_IOSTR_SHIFT) /* Automatic drive strength */
# define IOC_IOCFG_IOSTR_MIN (1 << IOC_IOCFG_IOSTR_SHIFT) /* Minimum drive strength */
# define IOC_IOCFG_IOSTR_MED (2 << IOC_IOCFG_IOSTR_SHIFT) /* Medium drive strength */
# define IOC_IOCFG_IOSTR_MAX (3 << IOC_IOCFG_IOSTR_SHIFT) /* Maximum drive strength */
#define IOC_IOCFG_IOCURR_SHIFT (10) /* Bits 10-11: I/O current mode */
#define IOC_IOCFG_IOCURR_MASK (3 << IOC_IOCFG_IOCURR_SHIFT)

2
arch/arm/src/tiva/hardware/tiva_gpio.h
View File

@ -58,7 +58,7 @@
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_gpio.h"
#else
# error "Unsupported Tiva/Stellaris system control module"
# error "Unsupported Tiva/Stellaris system GPIO"
#endif
/************************************************************************************

6
arch/arm/src/tiva/hardware/tiva_pinmap.h
View File

@ -50,10 +50,8 @@
# include "hardware/lm/lm4f_pinmap.h"
#elif defined(CONFIG_ARCH_CHIP_TM4C)
# include "hardware/tm4c/tm4c_pinmap.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X0)
# include "hardware/cc13x0/cc13x0_pinmap.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_pinmap.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
/* There are no pin multiplex header files for these architectures */
#else
# error "Unsupported Tiva/Stellaris/SimpleLink PIN mapping"
#endif

241
arch/arm/src/tiva/lm/lm3s_gpio.h Normal file
View File

@ -0,0 +1,241 @@
/****************************************************************************
* arch/arm/src/tiva/lm/lm3s_gpio.h
*
* Copyright (C) 2009-2010, 2013-2015, 2017-2018 Gregory Nutt. All rights
* reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* With modifications from Calvin Maguranis <calvin.maguranis@trd2inc.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_LM_LM3S_H
#define __ARCH_ARM_SRC_TIVA_LM_LM3S_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* No supported architecture supports interrupts on ports G-N or R-T */
#undef CONFIG_TIVA_GPIOG_IRQS /* G-N */
#undef CONFIG_TIVA_GPIOH_IRQS
#undef CONFIG_TIVA_GPIOJ_IRQS
#undef CONFIG_TIVA_GPIOK_IRQS
#undef CONFIG_TIVA_GPIOL_IRQS
#undef CONFIG_TIVA_GPIOM_IRQS
#undef CONFIG_TIVA_GPION_IRQS
#undef CONFIG_TIVA_GPIOR_IRQS /* R-T */
#undef CONFIG_TIVA_GPIOS_IRQS
#undef CONFIG_TIVA_GPIOT_IRQS
/* Mark GPIO interrupts as disabled for non-existent GPIO ports. */
#if TIVA_NPORTS < 1
# undef CONFIG_TIVA_GPIOA_IRQS
#endif
#if TIVA_NPORTS < 2
# undef CONFIG_TIVA_GPIOB_IRQS
#endif
#if TIVA_NPORTS < 3
# undef CONFIG_TIVA_GPIOC_IRQS
#endif
#if TIVA_NPORTS < 4
# undef CONFIG_TIVA_GPIOD_IRQS
#endif
#if TIVA_NPORTS < 5
# undef CONFIG_TIVA_GPIOE_IRQS
#endif
#if TIVA_NPORTS < 6
# undef CONFIG_TIVA_GPIOF_IRQS
#endif
#if TIVA_NPORTS < 7
# undef CONFIG_TIVA_GPIOG_IRQS
#endif
#if TIVA_NPORTS < 8
# undef CONFIG_TIVA_GPIOH_IRQS
#endif
#if TIVA_NPORTS < 9
# undef CONFIG_TIVA_GPIOJ_IRQS
#endif
#if TIVA_NPORTS < 10
# undef CONFIG_TIVA_GPIOK_IRQS
#endif
#if TIVA_NPORTS < 11
# undef CONFIG_TIVA_GPIOL_IRQS
#endif
#if TIVA_NPORTS < 12
# undef CONFIG_TIVA_GPIOM_IRQS
#endif
#if TIVA_NPORTS < 13
# undef CONFIG_TIVA_GPION_IRQS
#endif
#if TIVA_NPORTS < 14
# undef CONFIG_TIVA_GPIOP_IRQS
#endif
#if TIVA_NPORTS < 15
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 16
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 17
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 18
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
/* Bit-encoded input to tiva_configgpio() *******************************************/
/* Encoding:
*
* FFFS SPPP III. .... .... ...V PPPP PBBB
*/
/* These bits set the primary function of the pin:
*
* FFF. .... .... .... .... .... .... ....
*/
#define GPIO_FUNC_SHIFT 29 /* Bit 31-29: GPIO function */
#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) /* (See table 9-1 in data sheet) */
# define GPIO_FUNC_INPUT (0 << GPIO_FUNC_SHIFT) /* Digital GPIO input */
# define GPIO_FUNC_OUTPUT (1 << GPIO_FUNC_SHIFT) /* Digital GPIO output */
# define GPIO_FUNC_ODINPUT (2 << GPIO_FUNC_SHIFT) /* Open-drain GPIO input */
# define GPIO_FUNC_ODOUTPUT (3 << GPIO_FUNC_SHIFT) /* Open-drain GPIO output */
# define GPIO_FUNC_PFODIO (4 << GPIO_FUNC_SHIFT) /* Open-drain input/output (I2C) */
# define GPIO_FUNC_PFINPUT (5 << GPIO_FUNC_SHIFT) /* Digital input (Timer, CCP) */
# define GPIO_FUNC_PFOUTPUT (5 << GPIO_FUNC_SHIFT) /* Digital output (Timer, PWM, Comparator) */
# define GPIO_FUNC_PFIO (5 << GPIO_FUNC_SHIFT) /* Digital input/output (SSI, UART) */
# define GPIO_FUNC_ANINPUT (6 << GPIO_FUNC_SHIFT) /* Analog input (ADC, Comparator) */
# define GPIO_FUNC_ANIO (6 << GPIO_FUNC_SHIFT) /* REVISIT: Analog input/output (USB) */
# define GPIO_FUNC_INTERRUPT (7 << GPIO_FUNC_SHIFT) /* Interrupt function */
# define GPIO_FUNC_MAX GPIO_FUNC_INTERRUPT
/* That primary may be modified by the following options
*
* ...S SPPP .... .... .... .... .... ....
*/
#define GPIO_STRENGTH_SHIFT 27 /* Bits 28-27: Pad drive strength */
#define GPIO_STRENGTH_MASK (3 << GPIO_STRENGTH_SHIFT)
# define GPIO_STRENGTH_2MA (0 << GPIO_STRENGTH_SHIFT) /* 2mA pad drive strength */
# define GPIO_STRENGTH_4MA (1 << GPIO_STRENGTH_SHIFT) /* 4mA pad drive strength */
# define GPIO_STRENGTH_8MA (2 << GPIO_STRENGTH_SHIFT) /* 8mA pad drive strength */
# define GPIO_STRENGTH_8MASC (3 << GPIO_STRENGTH_SHIFT) /* 8mA Pad drive with slew rate control */
# define GPIO_STRENGTH_MAX GPIO_STRENGTH_8MASC
#define GPIO_PADTYPE_SHIFT 24 /* Bits 26-24: Pad type */
#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT)
# define GPIO_PADTYPE_STD (0 << GPIO_PADTYPE_SHIFT) /* Push-pull */
# define GPIO_PADTYPE_STDWPU (1 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-up */
# define GPIO_PADTYPE_STDWPD (2 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-down */
# define GPIO_PADTYPE_OD (3 << GPIO_PADTYPE_SHIFT) /* Open-drain */
# define GPIO_PADTYPE_ODWPU (4 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-up */
# define GPIO_PADTYPE_ODWPD (5 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-down */
# define GPIO_PADTYPE_ANALOG (6 << GPIO_PADTYPE_SHIFT) /* Analog comparator */
/* If the pin is an interrupt, then the following options apply
*
* .... .... III. .... .... .... .... ....
*/
#define GPIO_INT_SHIFT 21 /* Bits 23-21: Interrupt type */
#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT)
# define GPIO_INT_FALLINGEDGE (0 << GPIO_INT_SHIFT) /* Interrupt on falling edge */
# define GPIO_INT_RISINGEDGE (1 << GPIO_INT_SHIFT) /* Interrupt on rising edge */
# define GPIO_INT_BOTHEDGES (2 << GPIO_INT_SHIFT) /* Interrupt on both edges */
# define GPIO_INT_LOWLEVEL (3 << GPIO_INT_SHIFT) /* Interrupt on low level */
# define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT) /* Interrupt on high level */
/* If the pin is an GPIO digital output, then this identifies the initial output value:
* .... .... .... .... .... ...V .... ....
*/
#define GPIO_VALUE_SHIFT 8 /* Bit 8: If output, inital value of output */
#define GPIO_VALUE_MASK (1 << GPIO_VALUE_SHIFT)
# define GPIO_VALUE_ZERO (0 << GPIO_VALUE_SHIFT) /* Initial value is zero */
# define GPIO_VALUE_ONE (1 << GPIO_VALUE_SHIFT) /* Initial value is one */
/* This identifies the GPIO port
* .... .... .... .... .... .... .PPP P...
*/
#define GPIO_PORT_SHIFT 3 /* Bit 3-7: Port number */
#define GPIO_PORT_MASK (31 << GPIO_PORT_SHIFT)
# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
# define GPIO_PORTJ (8 << GPIO_PORT_SHIFT) /* GPIOJ */
# define GPIO_PORTK (9 << GPIO_PORT_SHIFT) /* GPIOK */
# define GPIO_PORTL (10 << GPIO_PORT_SHIFT) /* GPIOL */
# define GPIO_PORTM (11 << GPIO_PORT_SHIFT) /* GPIOM */
# define GPIO_PORTN (12 << GPIO_PORT_SHIFT) /* GPION */
# define GPIO_PORTP (13 << GPIO_PORT_SHIFT) /* GPIOP */
# define GPIO_PORTQ (14 << GPIO_PORT_SHIFT) /* GPIOQ */
# define GPIO_PORTR (15 << GPIO_PORT_SHIFT) /* GPIOR */
# define GPIO_PORTS (16 << GPIO_PORT_SHIFT) /* GPIOS */
# define GPIO_PORTT (17 << GPIO_PORT_SHIFT) /* GPIOT */
/* This identifies the pin number in the port:
* .... .... .... .... .... .... .... .BBB
*/
#define GPIO_PIN_SHIFT 0 /* Bits 0-2: GPIO pin: 0-7 */
#define GPIO_PIN_MASK (7 << GPIO_PIN_SHIFT)
# define GPIO_PIN_0 (0 << GPIO_PIN_SHIFT)
# define GPIO_PIN_1 (1 << GPIO_PIN_SHIFT)
# define GPIO_PIN_2 (2 << GPIO_PIN_SHIFT)
# define GPIO_PIN_3 (3 << GPIO_PIN_SHIFT)
# define GPIO_PIN_4 (4 << GPIO_PIN_SHIFT)
# define GPIO_PIN_5 (5 << GPIO_PIN_SHIFT)
# define GPIO_PIN_6 (6 << GPIO_PIN_SHIFT)
# define GPIO_PIN_7 (7 << GPIO_PIN_SHIFT)
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_LM_LM3S_H */

269
arch/arm/src/tiva/lm/lmf4_gpio.h Normal file
View File

@ -0,0 +1,269 @@
/****************************************************************************
* arch/arm/src/tiva/lm/lm4f_gpio.h
*
* Copyright (C) 2009-2010, 2013-2015, 2017-2018 Gregory Nutt. All rights
* reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* With modifications from Calvin Maguranis <calvin.maguranis@trd2inc.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_LM_LM4F_H
#define __ARCH_ARM_SRC_TIVA_LM_LM4F_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* No supported architecture supports interrupts on ports G-N or R-T */
#undef CONFIG_TIVA_GPIOG_IRQS /* G-N */
#undef CONFIG_TIVA_GPIOH_IRQS
#undef CONFIG_TIVA_GPIOJ_IRQS
#undef CONFIG_TIVA_GPIOK_IRQS
#undef CONFIG_TIVA_GPIOL_IRQS
#undef CONFIG_TIVA_GPIOM_IRQS
#undef CONFIG_TIVA_GPION_IRQS
#undef CONFIG_TIVA_GPIOR_IRQS /* R-T */
#undef CONFIG_TIVA_GPIOS_IRQS
#undef CONFIG_TIVA_GPIOT_IRQS
/* Mark GPIO interrupts as disabled for non-existent GPIO ports. */
#if TIVA_NPORTS < 1
# undef CONFIG_TIVA_GPIOA_IRQS
#endif
#if TIVA_NPORTS < 2
# undef CONFIG_TIVA_GPIOB_IRQS
#endif
#if TIVA_NPORTS < 3
# undef CONFIG_TIVA_GPIOC_IRQS
#endif
#if TIVA_NPORTS < 4
# undef CONFIG_TIVA_GPIOD_IRQS
#endif
#if TIVA_NPORTS < 5
# undef CONFIG_TIVA_GPIOE_IRQS
#endif
#if TIVA_NPORTS < 6
# undef CONFIG_TIVA_GPIOF_IRQS
#endif
#if TIVA_NPORTS < 7
# undef CONFIG_TIVA_GPIOG_IRQS
#endif
#if TIVA_NPORTS < 8
# undef CONFIG_TIVA_GPIOH_IRQS
#endif
#if TIVA_NPORTS < 9
# undef CONFIG_TIVA_GPIOJ_IRQS
#endif
#if TIVA_NPORTS < 10
# undef CONFIG_TIVA_GPIOK_IRQS
#endif
#if TIVA_NPORTS < 11
# undef CONFIG_TIVA_GPIOL_IRQS
#endif
#if TIVA_NPORTS < 12
# undef CONFIG_TIVA_GPIOM_IRQS
#endif
#if TIVA_NPORTS < 13
# undef CONFIG_TIVA_GPION_IRQS
#endif
#if TIVA_NPORTS < 14
# undef CONFIG_TIVA_GPIOP_IRQS
#endif
#if TIVA_NPORTS < 15
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 16
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 17
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 18
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
/* Bit-encoded input to tiva_configgpio() *******************************************/
/* Encoding:
*
* FFFS SPPP III. AAAA .... ...V PPPP PBBB
*
* TODO: The LM4F alsso support configuration of pins to trigger ADC and/or uDMA.
* That configuration is not addressed in this this encoding.
*/
/* These bits set the primary function of the pin:
*
* FFF. .... .... .... .... .... .... ....
*/
#define GPIO_FUNC_SHIFT 29 /* Bit 31-29: GPIO function */
#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) /* (See table 9-1 in data sheet) */
# define GPIO_FUNC_INPUT (0 << GPIO_FUNC_SHIFT) /* Digital GPIO input */
# define GPIO_FUNC_OUTPUT (1 << GPIO_FUNC_SHIFT) /* Digital GPIO output */
# define GPIO_FUNC_ODINPUT (2 << GPIO_FUNC_SHIFT) /* Open-drain GPIO input */
# define GPIO_FUNC_ODOUTPUT (3 << GPIO_FUNC_SHIFT) /* Open-drain GPIO output */
# define GPIO_FUNC_PFODIO (4 << GPIO_FUNC_SHIFT) /* Open-drain input/output (I2C) */
# define GPIO_FUNC_PFINPUT (5 << GPIO_FUNC_SHIFT) /* Digital input (Timer, CCP) */
# define GPIO_FUNC_PFOUTPUT (5 << GPIO_FUNC_SHIFT) /* Digital output (Timer, PWM, Comparator) */
# define GPIO_FUNC_PFIO (5 << GPIO_FUNC_SHIFT) /* Digital input/output (SSI, UART) */
# define GPIO_FUNC_ANINPUT (6 << GPIO_FUNC_SHIFT) /* Analog input (ADC, Comparator) */
# define GPIO_FUNC_ANIO (6 << GPIO_FUNC_SHIFT) /* REVISIT: Analog input/output (USB) */
# define GPIO_FUNC_INTERRUPT (7 << GPIO_FUNC_SHIFT) /* Interrupt function */
# define GPIO_FUNC_MAX GPIO_FUNC_INTERRUPT
/* That primary may be modified by the following options
*
* ...S SPPP .... .... .... .... .... ....
*/
#define GPIO_STRENGTH_SHIFT 27 /* Bits 28-27: Pad drive strength */
#define GPIO_STRENGTH_MASK (3 << GPIO_STRENGTH_SHIFT)
# define GPIO_STRENGTH_2MA (0 << GPIO_STRENGTH_SHIFT) /* 2mA pad drive strength */
# define GPIO_STRENGTH_4MA (1 << GPIO_STRENGTH_SHIFT) /* 4mA pad drive strength */
# define GPIO_STRENGTH_8MA (2 << GPIO_STRENGTH_SHIFT) /* 8mA pad drive strength */
# define GPIO_STRENGTH_8MASC (3 << GPIO_STRENGTH_SHIFT) /* 8mA Pad drive with slew rate control */
# define GPIO_STRENGTH_MAX GPIO_STRENGTH_8MASC
#define GPIO_PADTYPE_SHIFT 24 /* Bits 26-24: Pad type */
#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT)
# define GPIO_PADTYPE_STD (0 << GPIO_PADTYPE_SHIFT) /* Push-pull */
# define GPIO_PADTYPE_STDWPU (1 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-up */
# define GPIO_PADTYPE_STDWPD (2 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-down */
# define GPIO_PADTYPE_OD (3 << GPIO_PADTYPE_SHIFT) /* Open-drain */
# define GPIO_PADTYPE_ODWPU (4 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-up */
# define GPIO_PADTYPE_ODWPD (5 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-down */
# define GPIO_PADTYPE_ANALOG (6 << GPIO_PADTYPE_SHIFT) /* Analog comparator */
/* If the pin is an interrupt, then the following options apply
*
* .... .... III. .... .... .... .... ....
*/
#define GPIO_INT_SHIFT 21 /* Bits 23-21: Interrupt type */
#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT)
# define GPIO_INT_FALLINGEDGE (0 << GPIO_INT_SHIFT) /* Interrupt on falling edge */
# define GPIO_INT_RISINGEDGE (1 << GPIO_INT_SHIFT) /* Interrupt on rising edge */
# define GPIO_INT_BOTHEDGES (2 << GPIO_INT_SHIFT) /* Interrupt on both edges */
# define GPIO_INT_LOWLEVEL (3 << GPIO_INT_SHIFT) /* Interrupt on low level */
# define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT) /* Interrupt on high level */
/* The LM4F supports up to 15 alternate functions per pin:
*
* .... .... .... AAAA .... .... .... ....
*/
#define GPIO_ALT_SHIFT 16 /* Bits 16-19: Alternate function */
#define GPIO_ALT_MASK (15 << GPIO_ALT_SHIFT)
# define GPIO_ALT(n) ((n) << GPIO_ALT_SHIFT)
# define GPIO_ALT_NONE (0 << GPIO_ALT_SHIFT)
# define GPIO_ALT_1 (1 << GPIO_ALT_SHIFT)
# define GPIO_ALT_2 (2 << GPIO_ALT_SHIFT)
# define GPIO_ALT_3 (3 << GPIO_ALT_SHIFT)
# define GPIO_ALT_4 (4 << GPIO_ALT_SHIFT)
# define GPIO_ALT_5 (5 << GPIO_ALT_SHIFT)
# define GPIO_ALT_6 (6 << GPIO_ALT_SHIFT)
# define GPIO_ALT_7 (7 << GPIO_ALT_SHIFT)
# define GPIO_ALT_8 (8 << GPIO_ALT_SHIFT)
# define GPIO_ALT_9 (9 << GPIO_ALT_SHIFT)
# define GPIO_ALT_10 (10 << GPIO_ALT_SHIFT)
# define GPIO_ALT_11 (11 << GPIO_ALT_SHIFT)
# define GPIO_ALT_12 (12 << GPIO_ALT_SHIFT)
# define GPIO_ALT_13 (13 << GPIO_ALT_SHIFT)
# define GPIO_ALT_14 (14 << GPIO_ALT_SHIFT)
# define GPIO_ALT_15 (15 << GPIO_ALT_SHIFT)
/* If the pin is an GPIO digital output, then this identifies the initial output value:
* .... .... .... .... .... ...V .... ....
*/
#define GPIO_VALUE_SHIFT 8 /* Bit 8: If output, inital value of output */
#define GPIO_VALUE_MASK (1 << GPIO_VALUE_SHIFT)
# define GPIO_VALUE_ZERO (0 << GPIO_VALUE_SHIFT) /* Initial value is zero */
# define GPIO_VALUE_ONE (1 << GPIO_VALUE_SHIFT) /* Initial value is one */
/* This identifies the GPIO port
* .... .... .... .... .... .... .PPP P...
*/
#define GPIO_PORT_SHIFT 3 /* Bit 3-7: Port number */
#define GPIO_PORT_MASK (31 << GPIO_PORT_SHIFT)
# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
# define GPIO_PORTJ (8 << GPIO_PORT_SHIFT) /* GPIOJ */
# define GPIO_PORTK (9 << GPIO_PORT_SHIFT) /* GPIOK */
# define GPIO_PORTL (10 << GPIO_PORT_SHIFT) /* GPIOL */
# define GPIO_PORTM (11 << GPIO_PORT_SHIFT) /* GPIOM */
# define GPIO_PORTN (12 << GPIO_PORT_SHIFT) /* GPION */
# define GPIO_PORTP (13 << GPIO_PORT_SHIFT) /* GPIOP */
# define GPIO_PORTQ (14 << GPIO_PORT_SHIFT) /* GPIOQ */
# define GPIO_PORTR (15 << GPIO_PORT_SHIFT) /* GPIOR */
# define GPIO_PORTS (16 << GPIO_PORT_SHIFT) /* GPIOS */
# define GPIO_PORTT (17 << GPIO_PORT_SHIFT) /* GPIOT */
/* This identifies the pin number in the port:
* .... .... .... .... .... .... .... .BBB
*/
#define GPIO_PIN_SHIFT 0 /* Bits 0-2: GPIO pin: 0-7 */
#define GPIO_PIN_MASK (7 << GPIO_PIN_SHIFT)
# define GPIO_PIN_0 (0 << GPIO_PIN_SHIFT)
# define GPIO_PIN_1 (1 << GPIO_PIN_SHIFT)
# define GPIO_PIN_2 (2 << GPIO_PIN_SHIFT)
# define GPIO_PIN_3 (3 << GPIO_PIN_SHIFT)
# define GPIO_PIN_4 (4 << GPIO_PIN_SHIFT)
# define GPIO_PIN_5 (5 << GPIO_PIN_SHIFT)
# define GPIO_PIN_6 (6 << GPIO_PIN_SHIFT)
# define GPIO_PIN_7 (7 << GPIO_PIN_SHIFT)
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_LM_LM4F_H */

270
arch/arm/src/tiva/tiva_gpio.h
View File

@ -58,266 +58,22 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#if defined(CONFIG_ARCH_CHIP_LM3S) || defined(CONFIG_ARCH_CHIP_LM4F)
/* I don't believe that any of these families support interrupts on port J. Many
* do not support interrupts on port H either.
*/
# undef CONFIG_TIVA_GPIOJ_IRQS
/* Include chip specific definitions */
#if defined(CONFIG_ARCH_CHIP_LM3S)
# include "lm/lm3s_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_LM4F)
# include "lm/lm4f_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_TM4C)
/* The TM4C123GH6PMI supports ports A-F of which any can support interrupts */
# if defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
# undef CONFIG_TIVA_GPIOP_IRQS /* P-Q */
# undef CONFIG_TIVA_GPIOQ_IRQS
/* The TM4C123GH6PGE supports interrupts only on port P */
# elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE)
# undef CONFIG_TIVA_GPIOA_IRQS /* A-F */
# undef CONFIG_TIVA_GPIOB_IRQS
# undef CONFIG_TIVA_GPIOC_IRQS
# undef CONFIG_TIVA_GPIOD_IRQS
# undef CONFIG_TIVA_GPIOE_IRQS
# undef CONFIG_TIVA_GPIOF_IRQS
# undef CONFIG_TIVA_GPIOQ_IRQS /* Q */
/* The TM4C123GH6ZRB and the TM4C129x support interrupts only on ports P and Q. */
# else
# undef CONFIG_TIVA_GPIOA_IRQS /* A-F */
# undef CONFIG_TIVA_GPIOB_IRQS
# undef CONFIG_TIVA_GPIOC_IRQS
# undef CONFIG_TIVA_GPIOD_IRQS
# undef CONFIG_TIVA_GPIOE_IRQS
# undef CONFIG_TIVA_GPIOF_IRQS
# endif
/* No supported architecture supports interrupts on ports G-N or R-T */
# undef CONFIG_TIVA_GPIOG_IRQS /* G-N */
# undef CONFIG_TIVA_GPIOH_IRQS
# undef CONFIG_TIVA_GPIOJ_IRQS
# undef CONFIG_TIVA_GPIOK_IRQS
# undef CONFIG_TIVA_GPIOL_IRQS
# undef CONFIG_TIVA_GPIOM_IRQS
# undef CONFIG_TIVA_GPION_IRQS
# undef CONFIG_TIVA_GPIOR_IRQS /* R-T */
# undef CONFIG_TIVA_GPIOS_IRQS
# undef CONFIG_TIVA_GPIOT_IRQS
# include "tm4c/tm4c_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X0)
# include "cc13x0/cc13x0_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
# include "cc13x2_cc26x2/cc13x2_cc26x2_gpio.h"
#else
# error "Unsupported Tiva/Stellaris system GPIO"
#endif
/* Mark GPIO interrupts as disabled for non-existent GPIO ports. */
#if TIVA_NPORTS < 1
# undef CONFIG_TIVA_GPIOA_IRQS
#endif
#if TIVA_NPORTS < 2
# undef CONFIG_TIVA_GPIOB_IRQS
#endif
#if TIVA_NPORTS < 3
# undef CONFIG_TIVA_GPIOC_IRQS
#endif
#if TIVA_NPORTS < 4
# undef CONFIG_TIVA_GPIOD_IRQS
#endif
#if TIVA_NPORTS < 5
# undef CONFIG_TIVA_GPIOE_IRQS
#endif
#if TIVA_NPORTS < 6
# undef CONFIG_TIVA_GPIOF_IRQS
#endif
#if TIVA_NPORTS < 7
# undef CONFIG_TIVA_GPIOG_IRQS
#endif
#if TIVA_NPORTS < 8
# undef CONFIG_TIVA_GPIOH_IRQS
#endif
#if TIVA_NPORTS < 9
# undef CONFIG_TIVA_GPIOJ_IRQS
#endif
#if TIVA_NPORTS < 10
# undef CONFIG_TIVA_GPIOK_IRQS
#endif
#if TIVA_NPORTS < 11
# undef CONFIG_TIVA_GPIOL_IRQS
#endif
#if TIVA_NPORTS < 12
# undef CONFIG_TIVA_GPIOM_IRQS
#endif
#if TIVA_NPORTS < 13
# undef CONFIG_TIVA_GPION_IRQS
#endif
#if TIVA_NPORTS < 14
# undef CONFIG_TIVA_GPIOP_IRQS
#endif
#if TIVA_NPORTS < 15
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 16
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 17
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 18
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
/* Bit-encoded input to tiva_configgpio() *******************************************/
/* Encoding:
*
* LM3S: FFFS SPPP III. .... .... ...V PPPP PBBB
* LM4F: FFFS SPPP III. AAAA .... ...V PPPP PBBB
* TM4C: FFFS SPPP III. AAAA .... ...V PPPP PBBB
*
* TODO: The LM4F/TM4C also support configuration of pins to trigger ADC and/or uDMA.
* That configuration is not addressed in this this encoding.
*/
/* These bits set the primary function of the pin:
*
* FFFn .... .... .... .... .... .... ....
*/
#define GPIO_FUNC_SHIFT 29 /* Bit 31-29: GPIO function */
#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) /* (See table 9-1 in data sheet) */
# define GPIO_FUNC_INPUT (0 << GPIO_FUNC_SHIFT) /* Digital GPIO input */
# define GPIO_FUNC_OUTPUT (1 << GPIO_FUNC_SHIFT) /* Digital GPIO output */
# define GPIO_FUNC_ODINPUT (2 << GPIO_FUNC_SHIFT) /* Open-drain GPIO input */
# define GPIO_FUNC_ODOUTPUT (3 << GPIO_FUNC_SHIFT) /* Open-drain GPIO output */
# define GPIO_FUNC_PFODIO (4 << GPIO_FUNC_SHIFT) /* Open-drain input/output (I2C) */
# define GPIO_FUNC_PFINPUT (5 << GPIO_FUNC_SHIFT) /* Digital input (Timer, CCP) */
# define GPIO_FUNC_PFOUTPUT (5 << GPIO_FUNC_SHIFT) /* Digital output (Timer, PWM, Comparator) */
# define GPIO_FUNC_PFIO (5 << GPIO_FUNC_SHIFT) /* Digital input/output (SSI, UART) */
# define GPIO_FUNC_ANINPUT (6 << GPIO_FUNC_SHIFT) /* Analog input (ADC, Comparator) */
# define GPIO_FUNC_ANIO (6 << GPIO_FUNC_SHIFT) /* REVISIT: Analog input/output (USB) */
# define GPIO_FUNC_INTERRUPT (7 << GPIO_FUNC_SHIFT) /* Interrupt function */
# define GPIO_FUNC_MAX GPIO_FUNC_INTERRUPT
/* That primary may be modified by the following options
*
* ...S SPPP .... .... .... .... .... ....
*/
#define GPIO_STRENGTH_SHIFT 27 /* Bits 28-27: Pad drive strength */
#define GPIO_STRENGTH_MASK (3 << GPIO_STRENGTH_SHIFT)
# define GPIO_STRENGTH_2MA (0 << GPIO_STRENGTH_SHIFT) /* 2mA pad drive strength */
# define GPIO_STRENGTH_4MA (1 << GPIO_STRENGTH_SHIFT) /* 4mA pad drive strength */
# define GPIO_STRENGTH_8MA (2 << GPIO_STRENGTH_SHIFT) /* 8mA pad drive strength */
# define GPIO_STRENGTH_8MASC (3 << GPIO_STRENGTH_SHIFT) /* 8mA Pad drive with slew rate control */
# define GPIO_STRENGTH_MAX GPIO_STRENGTH_8MASC
#define GPIO_PADTYPE_SHIFT 24 /* Bits 26-24: Pad type */
#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT)
# define GPIO_PADTYPE_STD (0 << GPIO_PADTYPE_SHIFT) /* Push-pull */
# define GPIO_PADTYPE_STDWPU (1 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-up */
# define GPIO_PADTYPE_STDWPD (2 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-down */
# define GPIO_PADTYPE_OD (3 << GPIO_PADTYPE_SHIFT) /* Open-drain */
# define GPIO_PADTYPE_ODWPU (4 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-up */
# define GPIO_PADTYPE_ODWPD (5 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-down */
# define GPIO_PADTYPE_ANALOG (6 << GPIO_PADTYPE_SHIFT) /* Analog comparator */
/* If the pin is an interrupt, then the following options apply
*
* .... .... III. .... .... .... .... ....
*/
#define GPIO_INT_SHIFT 21 /* Bits 23-21: Interrupt type */
#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT)
# define GPIO_INT_FALLINGEDGE (0 << GPIO_INT_SHIFT) /* Interrupt on falling edge */
# define GPIO_INT_RISINGEDGE (1 << GPIO_INT_SHIFT) /* Interrupt on rising edge */
# define GPIO_INT_BOTHEDGES (2 << GPIO_INT_SHIFT) /* Interrupt on both edges */
# define GPIO_INT_LOWLEVEL (3 << GPIO_INT_SHIFT) /* Interrupt on low level */
# define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT) /* Interrupt on high level */
/* The LM4F/TM4C supports up to 15 alternate functions per pin:
*
* LM4F: .... .... .... AAAA .... .... .... ....
* TM4C: .... .... .... AAAA .... .... .... ....
*/
#if defined(LM4F) || defined(TM4C)
# define GPIO_ALT_SHIFT 16 /* Bits 16-19: Alternate function */
# define GPIO_ALT_MASK (15 << GPIO_ALT_SHIFT)
# define GPIO_ALT(n) ((n) << GPIO_ALT_SHIFT)
# define GPIO_ALT_NONE (0 << GPIO_ALT_SHIFT)
# define GPIO_ALT_1 (1 << GPIO_ALT_SHIFT)
# define GPIO_ALT_2 (2 << GPIO_ALT_SHIFT)
# define GPIO_ALT_3 (3 << GPIO_ALT_SHIFT)
# define GPIO_ALT_4 (4 << GPIO_ALT_SHIFT)
# define GPIO_ALT_5 (5 << GPIO_ALT_SHIFT)
# define GPIO_ALT_6 (6 << GPIO_ALT_SHIFT)
# define GPIO_ALT_7 (7 << GPIO_ALT_SHIFT)
# define GPIO_ALT_8 (8 << GPIO_ALT_SHIFT)
# define GPIO_ALT_9 (9 << GPIO_ALT_SHIFT)
# define GPIO_ALT_10 (10 << GPIO_ALT_SHIFT)
# define GPIO_ALT_11 (11 << GPIO_ALT_SHIFT)
# define GPIO_ALT_12 (12 << GPIO_ALT_SHIFT)
# define GPIO_ALT_13 (13 << GPIO_ALT_SHIFT)
# define GPIO_ALT_14 (14 << GPIO_ALT_SHIFT)
# define GPIO_ALT_15 (15 << GPIO_ALT_SHIFT)
#endif
/* If the pin is an GPIO digital output, then this identifies the initial output value:
* .... .... .... .... .... ...V .... ....
*/
#define GPIO_VALUE_SHIFT 8 /* Bit 8: If output, inital value of output */
#define GPIO_VALUE_MASK (1 << GPIO_VALUE_SHIFT)
# define GPIO_VALUE_ZERO (0 << GPIO_VALUE_SHIFT) /* Initial value is zero */
# define GPIO_VALUE_ONE (1 << GPIO_VALUE_SHIFT) /* Initial value is one */
/* This identifies the GPIO port
* .... .... .... .... .... .... .PPP P...
*/
#define GPIO_PORT_SHIFT 3 /* Bit 3-7: Port number */
#define GPIO_PORT_MASK (31 << GPIO_PORT_SHIFT)
# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
# define GPIO_PORTJ (8 << GPIO_PORT_SHIFT) /* GPIOJ */
# define GPIO_PORTK (9 << GPIO_PORT_SHIFT) /* GPIOK */
# define GPIO_PORTL (10 << GPIO_PORT_SHIFT) /* GPIOL */
# define GPIO_PORTM (11 << GPIO_PORT_SHIFT) /* GPIOM */
# define GPIO_PORTN (12 << GPIO_PORT_SHIFT) /* GPION */
# define GPIO_PORTP (13 << GPIO_PORT_SHIFT) /* GPIOP */
# define GPIO_PORTQ (14 << GPIO_PORT_SHIFT) /* GPIOQ */
# define GPIO_PORTR (15 << GPIO_PORT_SHIFT) /* GPIOR */
# define GPIO_PORTS (16 << GPIO_PORT_SHIFT) /* GPIOS */
# define GPIO_PORTT (17 << GPIO_PORT_SHIFT) /* GPIOT */
/* This identifies the pin number in the port:
* .... .... .... .... .... .... .... .BBB
*/
#define GPIO_PIN_SHIFT 0 /* Bits 0-2: GPIO pin: 0-7 */
#define GPIO_PIN_MASK (7 << GPIO_PIN_SHIFT)
# define GPIO_PIN_0 (0 << GPIO_PIN_SHIFT)
# define GPIO_PIN_1 (1 << GPIO_PIN_SHIFT)
# define GPIO_PIN_2 (2 << GPIO_PIN_SHIFT)
# define GPIO_PIN_3 (3 << GPIO_PIN_SHIFT)
# define GPIO_PIN_4 (4 << GPIO_PIN_SHIFT)
# define GPIO_PIN_5 (5 << GPIO_PIN_SHIFT)
# define GPIO_PIN_6 (6 << GPIO_PIN_SHIFT)
# define GPIO_PIN_7 (7 << GPIO_PIN_SHIFT)
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
@ -329,8 +85,6 @@ extern "C"
{
#endif
uintptr_t tiva_gpiobaseaddress(unsigned int port);
/****************************************************************************
* Name: tiva_configgpio
*

299
arch/arm/src/tiva/tm4c/tm4c_gpio.h Normal file
View File

@ -0,0 +1,299 @@
/****************************************************************************
* arch/arm/src/tiva/tm4c/tm4c_gpio.h
*
* Copyright (C) 2009-2010, 2013-2015, 2017-2018 Gregory Nutt. All rights
* reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* With modifications from Calvin Maguranis <calvin.maguranis@trd2inc.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_TIVA_GPIO_H
#define __ARCH_ARM_SRC_TIVA_TIVA_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* The TM4C123GH6PMI supports ports A-F of which any can support interrupts */
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
# undef CONFIG_TIVA_GPIOP_IRQS /* P-Q */
# undef CONFIG_TIVA_GPIOQ_IRQS
/* The TM4C123GH6PGE supports interrupts only on port P */
#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE)
# undef CONFIG_TIVA_GPIOA_IRQS /* A-F */
# undef CONFIG_TIVA_GPIOB_IRQS
# undef CONFIG_TIVA_GPIOC_IRQS
# undef CONFIG_TIVA_GPIOD_IRQS
# undef CONFIG_TIVA_GPIOE_IRQS
# undef CONFIG_TIVA_GPIOF_IRQS
# undef CONFIG_TIVA_GPIOQ_IRQS /* Q */
/* The TM4C123GH6ZRB and the TM4C129x support interrupts only on ports P and Q. */
#else
# undef CONFIG_TIVA_GPIOA_IRQS /* A-F */
# undef CONFIG_TIVA_GPIOB_IRQS
# undef CONFIG_TIVA_GPIOC_IRQS
# undef CONFIG_TIVA_GPIOD_IRQS
# undef CONFIG_TIVA_GPIOE_IRQS
# undef CONFIG_TIVA_GPIOF_IRQS
#endif
/* No supported architecture supports interrupts on ports G-N or R-T */
#undef CONFIG_TIVA_GPIOG_IRQS /* G-N */
#undef CONFIG_TIVA_GPIOH_IRQS
#undef CONFIG_TIVA_GPIOJ_IRQS
#undef CONFIG_TIVA_GPIOK_IRQS
#undef CONFIG_TIVA_GPIOL_IRQS
#undef CONFIG_TIVA_GPIOM_IRQS
#undef CONFIG_TIVA_GPION_IRQS
#undef CONFIG_TIVA_GPIOR_IRQS /* R-T */
#undef CONFIG_TIVA_GPIOS_IRQS
#undef CONFIG_TIVA_GPIOT_IRQS
/* Mark GPIO interrupts as disabled for non-existent GPIO ports. */
#if TIVA_NPORTS < 1
# undef CONFIG_TIVA_GPIOA_IRQS
#endif
#if TIVA_NPORTS < 2
# undef CONFIG_TIVA_GPIOB_IRQS
#endif
#if TIVA_NPORTS < 3
# undef CONFIG_TIVA_GPIOC_IRQS
#endif
#if TIVA_NPORTS < 4
# undef CONFIG_TIVA_GPIOD_IRQS
#endif
#if TIVA_NPORTS < 5
# undef CONFIG_TIVA_GPIOE_IRQS
#endif
#if TIVA_NPORTS < 6
# undef CONFIG_TIVA_GPIOF_IRQS
#endif
#if TIVA_NPORTS < 7
# undef CONFIG_TIVA_GPIOG_IRQS
#endif
#if TIVA_NPORTS < 8
# undef CONFIG_TIVA_GPIOH_IRQS
#endif
#if TIVA_NPORTS < 9
# undef CONFIG_TIVA_GPIOJ_IRQS
#endif
#if TIVA_NPORTS < 10
# undef CONFIG_TIVA_GPIOK_IRQS
#endif
#if TIVA_NPORTS < 11
# undef CONFIG_TIVA_GPIOL_IRQS
#endif
#if TIVA_NPORTS < 12
# undef CONFIG_TIVA_GPIOM_IRQS
#endif
#if TIVA_NPORTS < 13
# undef CONFIG_TIVA_GPION_IRQS
#endif
#if TIVA_NPORTS < 14
# undef CONFIG_TIVA_GPIOP_IRQS
#endif
#if TIVA_NPORTS < 15
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 16
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 17
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 18
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
/* Bit-encoded input to tiva_configgpio() *******************************************/
/* Encoding:
*
* FFFS SPPP III. AAAA .... ...V PPPP PBBB
*
* TODO: The TM4C also supports configuration of pins to trigger ADC and/or uDMA.
* That configuration is not addressed in this this encoding.
*/
/* These bits set the primary function of the pin:
*
* FFF. .... .... .... .... .... .... ....
*/
#define GPIO_FUNC_SHIFT 29 /* Bit 31-29: GPIO function */
#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) /* (See table 9-1 in data sheet) */
# define GPIO_FUNC_INPUT (0 << GPIO_FUNC_SHIFT) /* Digital GPIO input */
# define GPIO_FUNC_OUTPUT (1 << GPIO_FUNC_SHIFT) /* Digital GPIO output */
# define GPIO_FUNC_ODINPUT (2 << GPIO_FUNC_SHIFT) /* Open-drain GPIO input */
# define GPIO_FUNC_ODOUTPUT (3 << GPIO_FUNC_SHIFT) /* Open-drain GPIO output */
# define GPIO_FUNC_PFODIO (4 << GPIO_FUNC_SHIFT) /* Open-drain input/output (I2C) */
# define GPIO_FUNC_PFINPUT (5 << GPIO_FUNC_SHIFT) /* Digital input (Timer, CCP) */
# define GPIO_FUNC_PFOUTPUT (5 << GPIO_FUNC_SHIFT) /* Digital output (Timer, PWM, Comparator) */
# define GPIO_FUNC_PFIO (5 << GPIO_FUNC_SHIFT) /* Digital input/output (SSI, UART) */
# define GPIO_FUNC_ANINPUT (6 << GPIO_FUNC_SHIFT) /* Analog input (ADC, Comparator) */
# define GPIO_FUNC_ANIO (6 << GPIO_FUNC_SHIFT) /* REVISIT: Analog input/output (USB) */
# define GPIO_FUNC_INTERRUPT (7 << GPIO_FUNC_SHIFT) /* Interrupt function */
# define GPIO_FUNC_MAX GPIO_FUNC_INTERRUPT
/* That primary may be modified by the following options
*
* ...S SPPP .... .... .... .... .... ....
*/
#define GPIO_STRENGTH_SHIFT 27 /* Bits 28-27: Pad drive strength */
#define GPIO_STRENGTH_MASK (3 << GPIO_STRENGTH_SHIFT)
# define GPIO_STRENGTH_2MA (0 << GPIO_STRENGTH_SHIFT) /* 2mA pad drive strength */
# define GPIO_STRENGTH_4MA (1 << GPIO_STRENGTH_SHIFT) /* 4mA pad drive strength */
# define GPIO_STRENGTH_8MA (2 << GPIO_STRENGTH_SHIFT) /* 8mA pad drive strength */
# define GPIO_STRENGTH_8MASC (3 << GPIO_STRENGTH_SHIFT) /* 8mA Pad drive with slew rate control */
# define GPIO_STRENGTH_MAX GPIO_STRENGTH_8MASC
#define GPIO_PADTYPE_SHIFT 24 /* Bits 26-24: Pad type */
#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT)
# define GPIO_PADTYPE_STD (0 << GPIO_PADTYPE_SHIFT) /* Push-pull */
# define GPIO_PADTYPE_STDWPU (1 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-up */
# define GPIO_PADTYPE_STDWPD (2 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-down */
# define GPIO_PADTYPE_OD (3 << GPIO_PADTYPE_SHIFT) /* Open-drain */
# define GPIO_PADTYPE_ODWPU (4 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-up */
# define GPIO_PADTYPE_ODWPD (5 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-down */
# define GPIO_PADTYPE_ANALOG (6 << GPIO_PADTYPE_SHIFT) /* Analog comparator */
/* If the pin is an interrupt, then the following options apply
*
* .... .... III. .... .... .... .... ....
*/
#define GPIO_INT_SHIFT 21 /* Bits 23-21: Interrupt type */
#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT)
# define GPIO_INT_FALLINGEDGE (0 << GPIO_INT_SHIFT) /* Interrupt on falling edge */
# define GPIO_INT_RISINGEDGE (1 << GPIO_INT_SHIFT) /* Interrupt on rising edge */
# define GPIO_INT_BOTHEDGES (2 << GPIO_INT_SHIFT) /* Interrupt on both edges */
# define GPIO_INT_LOWLEVEL (3 << GPIO_INT_SHIFT) /* Interrupt on low level */
# define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT) /* Interrupt on high level */
/* The TM4C supports up to 15 alternate functions per pin:
*
* .... .... .... AAAA .... .... .... ....
*/
#define GPIO_ALT_SHIFT 16 /* Bits 16-19: Alternate function */
#define GPIO_ALT_MASK (15 << GPIO_ALT_SHIFT)
# define GPIO_ALT(n) ((n) << GPIO_ALT_SHIFT)
# define GPIO_ALT_NONE (0 << GPIO_ALT_SHIFT)
# define GPIO_ALT_1 (1 << GPIO_ALT_SHIFT)
# define GPIO_ALT_2 (2 << GPIO_ALT_SHIFT)
# define GPIO_ALT_3 (3 << GPIO_ALT_SHIFT)
# define GPIO_ALT_4 (4 << GPIO_ALT_SHIFT)
# define GPIO_ALT_5 (5 << GPIO_ALT_SHIFT)
# define GPIO_ALT_6 (6 << GPIO_ALT_SHIFT)
# define GPIO_ALT_7 (7 << GPIO_ALT_SHIFT)
# define GPIO_ALT_8 (8 << GPIO_ALT_SHIFT)
# define GPIO_ALT_9 (9 << GPIO_ALT_SHIFT)
# define GPIO_ALT_10 (10 << GPIO_ALT_SHIFT)
# define GPIO_ALT_11 (11 << GPIO_ALT_SHIFT)
# define GPIO_ALT_12 (12 << GPIO_ALT_SHIFT)
# define GPIO_ALT_13 (13 << GPIO_ALT_SHIFT)
# define GPIO_ALT_14 (14 << GPIO_ALT_SHIFT)
# define GPIO_ALT_15 (15 << GPIO_ALT_SHIFT)
/* If the pin is an GPIO digital output, then this identifies the initial output value:
* .... .... .... .... .... ...V .... ....
*/
#define GPIO_VALUE_SHIFT 8 /* Bit 8: If output, inital value of output */
#define GPIO_VALUE_MASK (1 << GPIO_VALUE_SHIFT)
# define GPIO_VALUE_ZERO (0 << GPIO_VALUE_SHIFT) /* Initial value is zero */
# define GPIO_VALUE_ONE (1 << GPIO_VALUE_SHIFT) /* Initial value is one */
/* This identifies the GPIO port
* .... .... .... .... .... .... .PPP P...
*/
#define GPIO_PORT_SHIFT 3 /* Bit 3-7: Port number */
#define GPIO_PORT_MASK (31 << GPIO_PORT_SHIFT)
# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
# define GPIO_PORTJ (8 << GPIO_PORT_SHIFT) /* GPIOJ */
# define GPIO_PORTK (9 << GPIO_PORT_SHIFT) /* GPIOK */
# define GPIO_PORTL (10 << GPIO_PORT_SHIFT) /* GPIOL */
# define GPIO_PORTM (11 << GPIO_PORT_SHIFT) /* GPIOM */
# define GPIO_PORTN (12 << GPIO_PORT_SHIFT) /* GPION */
# define GPIO_PORTP (13 << GPIO_PORT_SHIFT) /* GPIOP */
# define GPIO_PORTQ (14 << GPIO_PORT_SHIFT) /* GPIOQ */
# define GPIO_PORTR (15 << GPIO_PORT_SHIFT) /* GPIOR */
# define GPIO_PORTS (16 << GPIO_PORT_SHIFT) /* GPIOS */
# define GPIO_PORTT (17 << GPIO_PORT_SHIFT) /* GPIOT */
/* This identifies the pin number in the port:
* .... .... .... .... .... .... .... .BBB
*/
#define GPIO_PIN_SHIFT 0 /* Bits 0-2: GPIO pin: 0-7 */
#define GPIO_PIN_MASK (7 << GPIO_PIN_SHIFT)
# define GPIO_PIN_0 (0 << GPIO_PIN_SHIFT)
# define GPIO_PIN_1 (1 << GPIO_PIN_SHIFT)
# define GPIO_PIN_2 (2 << GPIO_PIN_SHIFT)
# define GPIO_PIN_3 (3 << GPIO_PIN_SHIFT)
# define GPIO_PIN_4 (4 << GPIO_PIN_SHIFT)
# define GPIO_PIN_5 (5 << GPIO_PIN_SHIFT)
# define GPIO_PIN_6 (6 << GPIO_PIN_SHIFT)
# define GPIO_PIN_7 (7 << GPIO_PIN_SHIFT)
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_TIVA_GPIO_H */