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Gregory Nutt 2017-02-23 10:57:21 -06:00
parent 9937eed3f1
commit d83422a00d
5 changed files with 2419 additions and 111 deletions
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2
TODO
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@ -438,7 +438,7 @@ o pthreads (sched/pthreads)
serve as cancellation points. They are, however, simple wrappers around nanosleep
which is a true cancellation point.
NOTE 02: system() is actually implemented in apps/ as part of NSH. It cannot be
a cancellation point either.
a cancellation point.
NOTE 03: sigpause() is a user-space function in the C library and cannot serve as
cancellation points. It is, however, a simple wrapper around sigsuspend()
which is a true cancellation point.

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arch/arm/include/kinetis�kinetis_mcg.h Normal file
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@ -0,0 +1,620 @@
/************************************************************************************
* arch/arm/include/kinetis/kinetis_mcg.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_MCG_H
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_MCG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Note: It is envisioned that in the long term as a chip is added. The author of
* the new chip definitions will either find the exact configuration in an existing
* chip define and add the new chip to it Or add the MCG feature configuration
* #defines to the chip ifdef list below. In either case the author should mark
* it as "Verified to Document Number:" taken from the reference manual.
*
* To maintain backward compatibility to the version of NuttX prior to
* 2/5/2017, the catch all KINETIS_MCG_VERSION_UKN configuration is assigned
* to all the chips that did not have any conditional compilation based on
* NEW_MCG or KINETIS_K64. This is a "No worse" than the original code solution.
* N.B. Each original chip "if"definitions have been left intact so that the
* complete legacy definitions prior to 2/5/2017 may be filled in completely when
* vetted.
*/
/* MCG Configuration Parameters
*
* KINETIS_MCG_PLL_REF_MIN - OSCCLK/PLL_R minimum
* KINETIS_MCG_PLL_REF_MAX - OSCCLK/PLL_R maximum
* KINETIS_MCG_PLL_INTERNAL_DIVBY - The PLL clock is divided by n before VCO divider
* KINETIS_MCG_HAS_PLL_EXTRA_DIVBY - Is PLL clock divided by n before MCG PLL/FLL
* clock selection in the SIM module
* KINETIS_MCG_FFCLK_DIVBY - MCGFFCLK divided by n
* KINETIS_MCG_HAS_IRC_48M - Has 48MHz internal oscillator
* KINETIS_MCG_HAS_LOW_FREQ_IRC - Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]
* KINETIS_MCG_HAS_HIGH_FREQ_IRC - Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]
* KINETIS_MCG_HAS_PLL_INTERNAL_MODE - Has PEI mode or PBI mode
* KINETIS_MCG_HAS_RESET_IS_BLPI - Has Reset clock mode is BLPI
*
* MCG Register Configuration
*
* KINETIS_MCG_HAS_C1 - SoC has C1 Register
* KINETIS_MCG_HAS_C1_IREFS - SoC has C1[IREFS]
* KINETIS_MCG_HAS_C1_FRDIV - SoC has C1[FRDIV]
* KINETIS_MCG_C1_FRDIV_MAX - C1[FRDIV] maximum value 5=1024, 6=1280 7=1536
* KINETIS_MCG_HAS_C2 - SoC has C2 Register
* KINETIS_MCG_HAS_C2_HGO - SoC has C2[HGO]
* KINETIS_MCG_HAS_C2_RANGE - SoC has C2[RANG]
* KINETIS_MCG_HAS_C2_FCFTRIM - SoC has C2[FCFTRIM]
* KINETIS_MCG_HAS_C2_LOCRE0 - SoC has C2[LOCRE0]
* KINETIS_MCG_HAS_C3 - SoC has C3 Register
* KINETIS_MCG_HAS_C4 - SoC has C4 Register
* KINETIS_MCG_HAS_C5 - SoC has C5 Register
* KINETIS_MCG_HAS_C5_PRDIV - SoC has C5[PRDIV]
* KINETIS_MCG_C5_PRDIV_BASE - PRDIV base value corresponding to 0 in C5[PRDIV]
* KINETIS_MCG_C5_PRDIV_MAX - The Maximum value of C5[PRVDIV])
* KINETIS_MCG_C5_PRDIV_BITS - Has n bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV]
* KINETIS_MCG_HAS_C5_PLLREFSEL0 - SoC has C5[PLLREFSEL0]
* KINETIS_MCG_HAS_C6 - SoC has C6 Register
* KINETIS_MCG_HAS_C6_VDIV - SoC has C6[VDIV]
* KINETIS_MCG_C6_VDIV_BASE - VDIV base value corresponding to 0 in C6[VDIV]
* KINETIS_MCG_C6_VDIV_MAX - The Maximum value of C6[VDIV]
* KINETIS_MCG_HAS_C6_CME - SoC has C6[CME]
* KINETIS_MCG_HAS_C6_PLLS - SoC has C6[PLLS]
* KINETIS_MCG_HAS_C6_LOLIE0 - SoC has C6[LOLIE0]
* KINETIS_MCG_HAS_S - SoC has S Register
* KINETIS_MCG_HAS_S_PLLST - SoC has S[PLLST]
* KINETIS_MCG_HAS_S_LOCK0 - SoC has S[LOCK0]
* KINETIS_MCG_HAS_S_LOLS - SoC has S[LOLS]
* KINETIS_MCG_HAS_ATC - SoC has ATC Register
* KINETIS_MCG_HAS_ATCVH - SoC has ATCVH Register
* KINETIS_MCG_HAS_ATCVL - SoC has ATCVL Register
* KINETIS_MCG_HAS_SC - SoC has SC Register
* KINETIS_MCG_HAS_SC_ATMS - SoC has SC[ATMS]
* KINETIS_MCG_HAS_SC_ATMF - SoC has SC[ATMF]
* KINETIS_MCG_HAS_SC_ATME - SoC has SC[ATME]
* KINETIS_MCG_HAS_C7 - SoC has C7 Register
* KINETIS_MCG_HAS_C7_OSCSEL - SoC has C7[OSCSEL]
* KINETIS_MCG_C7_OSCSEL_BITS - C7[OSCSEL] is n bits wide
* KINETIS_MCG_HAS_C8 - SoC has C8 Register
* KINETIS_MCG_HAS_C8_LOCS1 - SoC has C8[LOCS1]
* KINETIS_MCG_HAS_C8_CME1 - SoC has C8[CME1]
* KINETIS_MCG_HAS_C8_LOLRE - SoC has C8[LOLRE]
* KINETIS_MCG_HAS_C8_LOCRE1 - SoC has C8[LOCRE1]
* KINETIS_MCG_HAS_C9 - SoC has C9 Register
* KINETIS_MCG_HAS_C9_EXT_PLL_LOCS - SoC has C9_EXT_PLL[LOCS]
* KINETIS_MCG_HAS_C9_PLL_LOCRE - SoC has C9_PLL[LOCRE]
* KINETIS_MCG_HAS_C9_PLL_CME - SoC has C9_PLL[CME]
* KINETIS_MCG_HAS_C10 - SoC has C10 Register
* KINETIS_MCG_HAS_C10_LOCS1 - SoC has C10[LOCS1]
* KINETIS_MCG_HAS_C11 - SoC has C11 Register
* KINETIS_MCG_HAS_C11_PLL1OSC1 - SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1],
* KINETIS_MCG_HAS_C11_PLLCS - SoC has C11[PLLCS]
* KINETIS_MCG_HAS_C11_PLLREFSEL1 - SoC has C11[PLLREFSEL1]
* KINETIS_MCG_HAS_C12 - SoC has C12 Register
* KINETIS_MCG_HAS_S2 - SoC has S2 Register
* KINETIS_MCG_HAS_S2_PLL1OSC1 - SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1]
* KINETIS_MCG_HAS_S2_PLLCST - SoC has S2[PLLCST]
*/
/* Describe the version of the MCG
*
* These defines are not related to any NXP reference but are merely
* a way to label the versions we are using
*/
#define KINETIS_MCG_VERSION_UKN -1 /* What was in nuttx prior to 2/5/2017 */
#define KINETIS_MCG_VERSION_01 1 /* The addition of MK60FN1M0VLQ12 Previously known as KINETIS_NEW_MCG
* Verified Document Number: K60P144M150SF3RM Rev. 3, November 2014 */
#define KINETIS_MCG_VERSION_04 4 /* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
#define KINETIS_MCG_VERSION_06 6 /* Verified to Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
/* MK20DX/DN---VLH5
*
* ------------- ------ --- ------- ------ ------- ------ ----- ----
* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
* FREQ CNT FLASH FLASH
* ------------- ------ --- ------- ------ ------- ------ ----- ----
* MK20DN32VLH5 50 MHz 64 LQFP 32 KB 32 KB — 8 KB 40
* MK20DX32VLH5 50 MHz 64 LQFP 64 KB 32 KB 2 KB 8 KB 40
* MK20DN64VLH5 50 MHz 64 LQFP 64 KB 64 KB — 16 KB 40
* MK20DX64VLH5 50 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40
* MK20DN128VLH5 50 MHz 64 LQFP 128 KB 128 KB — 16 KB 40
* MK20DX128VLH5 50 MHz 64 LQFP 160 KB 128 KB 2 KB 16 KB 40
*/
#if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DX32VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DN64VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DX64VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DN128VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DX128VLH5)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
/* MK20DX---VLH7
*
* ------------- ------ --- ------- ------ ------- ------ ----- ----
* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
* FREQ CNT FLASH FLASH
* ------------- ------ --- ------- ------ ------- ------ ----- ----
* MK20DX64VLH7 72 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40
* MK20DX128VLH7 72 MHz 64 LQFP 160 KB 128 KB 2 KB 32 KB 40
* MK20DX256VLH7 72 MHz 64 LQFP 288 KB 256 KB 2 KB 64 KB 40
* ------------- ------ --- ------- ------ ------- ------ ----- ----
*/
#elif defined(CONFIG_ARCH_CHIP_MK20DX64VLH7) || defined(CONFIG_ARCH_CHIP_MK20DX128VLH7) || \
defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \
defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \
defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \
defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \
defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \
defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12)
/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_01
/* MCG Configuration Parameters */
# define KINETIS_MCG_PLL_REF_MIN 8000000 /* OSCCLK/PLL_R minimum */
# define KINETIS_MCG_PLL_REF_MAX 16000000 /* OSCCLK/PLL_R maximum */
# define KINETIS_MCG_PLL_INTERNAL_DIVBY 2 /* The PLL clock is divided by 2 before VCO divider */
# define KINETIS_MCG_HAS_PLL_EXTRA_DIVBY 2 /* Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module */
# define KINETIS_MCG_FFCLK_DIVBY 2 /* MCGFFCLK divided by 2 */
# undef KINETIS_MCG_HAS_IRC_48M /* Has no 48MHz internal oscillator */
# undef KINETIS_MCG_HAS_LOW_FREQ_IRC /* Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2] */
# undef KINETIS_MCG_HAS_HIGH_FREQ_IRC /* Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN] */
# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
/* MCG Register Configuration */
# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
# define KINETIS_MCG_HAS_C1_FRDIV 1 /* SoC has C1[FRDIV] */
# define KINETIS_MCG_C1_FRDIV_MAX 7 /* C1[FRDIV] maximum value 5=1024, 6=1280 7=1536 */
# define KINETIS_MCG_HAS_C2 1 /* SoC has C2 Register */
# define KINETIS_MCG_HAS_C2_HGO 1 /* SoC has C2[HGO] */
# define KINETIS_MCG_HAS_C2_RANGE 1 /* SoC has C2[RANGE] */
# undef KINETIS_MCG_HAS_C2_FCFTRIM /* SoC has C2[FCFTRIM] */
# define KINETIS_MCG_HAS_C2_LOCRE0 1 /* SoC has C2[LOCRE0] */
# define KINETIS_MCG_HAS_C3 1 /* SoC has C3 Register */
# define KINETIS_MCG_HAS_C4 1 /* SoC has C4 Register */
# define KINETIS_MCG_HAS_C5 1 /* SoC has C5 Register */
# define KINETIS_MCG_HAS_C5_PRDIV 1 /* SoC has C5[PRDIV] */
# define KINETIS_MCG_C5_PRDIV_BASE 1 /* PRDIV base value corresponding to 0 in C5[PRDIV] */
# define KINETIS_MCG_C5_PRDIV_MAX 8 /* The Maximum value of C5[PRVDIV]) */
# define KINETIS_MCG_C5_PRDIV_BITS 3 /* Has 3 bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV] */
# define KINETIS_MCG_HAS_C5_PLLREFSEL0 1 /* SoC has C5[PLLREFSEL0] */
# define KINETIS_MCG_HAS_C6 1 /* SoC has C6 Register */
# define KINETIS_MCG_HAS_C6_VDIV 1 /* SoC has C6[VDIV] */
# define KINETIS_MCG_C6_VDIV_BASE 16 /* VDIV base value corresponding to 0 in C6[VDIV] */
# define KINETIS_MCG_C6_VDIV_MAX 47 /* The Maximum value of C6[VDIV] */
# define KINETIS_MCG_HAS_C6_CME 1 /* SoC has C6[CME] */
# define KINETIS_MCG_HAS_C6_PLLS 1 /* SoC has C6[PLLS] */
# define KINETIS_MCG_HAS_C6_LOLIE0 1 /* SoC has C6[LOLIE0] */
# define KINETIS_MCG_HAS_S 1 /* SoC has S Register */
# define KINETIS_MCG_HAS_S_PLLST 1 /* SoC has S[PLLST] */
# define KINETIS_MCG_HAS_S_LOCK0 1 /* SoC has S[LOCK0] */
# define KINETIS_MCG_HAS_S_LOLS 1 /* SoC has S[LOLS] */
# undef KINETIS_MCG_HAS_ATC /* SoC has ATC Register */
# define KINETIS_MCG_HAS_ATCVH 1 /* SoC has ATCVH Register */
# define KINETIS_MCG_HAS_ATCVL 1 /* SoC has ATCVL Register */
# define KINETIS_MCG_HAS_SC 1 /* SoC has SC Register */
# define KINETIS_MCG_HAS_SC_ATMS 1 /* SoC has SC[ATMS] */
# define KINETIS_MCG_HAS_SC_ATMF 1 /* SoC has SC[ATMF] */
# define KINETIS_MCG_HAS_SC_ATME 1 /* SoC has SC[ATME] */
# define KINETIS_MCG_HAS_C7 1 /* SoC has C7 Register */
# define KINETIS_MCG_HAS_C7_OSCSEL 1 /* SoC has C7[OSCSEL] */
# define KINETIS_MCG_C7_OSCSEL_BITS 1 /* C7[OSCSEL] is n bits wide */
# define KINETIS_MCG_HAS_C8 1 /* SoC has C8 Register */
# define KINETIS_MCG_HAS_C8_LOCS1 1 /* SoC has C8[LOCS1] */
# define KINETIS_MCG_HAS_C8_CME1 1 /* SoC has C8[CME1] */
# undef KINETIS_MCG_HAS_C8_LOLRE /* SoC has C8[LOLRE] */
# define KINETIS_MCG_HAS_C8_LOCRE1 1 /* SoC has C8[LOCRE1] */
# undef KINETIS_MCG_HAS_C9 1 /* SoC has C9 Register */
# undef KINETIS_MCG_HAS_C9_EXT_PLL_LOCS 1 /* SoC has C9_EXT_PLL[LOCS] */
# undef KINETIS_MCG_HAS_C9_PLL_LOCRE 1 /* SoC has C9_PLL[LOCRE] */
# undef KINETIS_MCG_HAS_C9_PLL_CME 1 /* SoC has C9_PLL[CME] */
# define KINETIS_MCG_HAS_C10 /* SoC has C10 Register */
# undef KINETIS_MCG_HAS_C10_LOCS1 /* SoC has C10[LOCS1] */
# define KINETIS_MCG_HAS_C11 /* SoC has C11 Register */
# define KINETIS_MCG_HAS_C11_PLL1OSC1 1 /* SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1] */
# define KINETIS_MCG_HAS_C11_PLLCS /* SoC has C11[PLLCS] */
# define KINETIS_MCG_HAS_C11_PLLREFSEL1 1 /* SoC has C11[PLLREFSEL1] */
# define KINETIS_MCG_HAS_C12 /* SoC has C12 Register */
# define KINETIS_MCG_HAS_S2 /* SoC has S2 Register */
# define KINETIS_MCG_HAS_S2_PLL1OSC1 1 /* SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1] */
# define KINETIS_MCG_HAS_S2_PLLCST /* SoC has S2[PLLCST] */
#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_04
/* MCG Configuration Parameters */
# define KINETIS_MCG_PLL_REF_MIN 2000000 /* OSCCLK/PLL_R minimum */
# define KINETIS_MCG_PLL_REF_MAX 4000000 /* OSCCLK/PLL_R maximum */
# define KINETIS_MCG_PLL_INTERNAL_DIVBY 1 /* The PLL clock is divided by 1 before VCO divider */
# define KINETIS_MCG_HAS_PLL_EXTRA_DIVBY 1 /* Is PLL clock divided by 1 before MCG PLL/FLL clock selection in the SIM module */
# define KINETIS_MCG_FFCLK_DIVBY 2 /* MCGFFCLK divided by 2 */
# define KINETIS_MCG_HAS_IRC_48M 1 /* Has 48MHz internal oscillator */
# undef KINETIS_MCG_HAS_LOW_FREQ_IRC /* Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2] */
# undef KINETIS_MCG_HAS_HIGH_FREQ_IRC /* Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN] */
# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
/* MCG Register Configuration */
# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
# define KINETIS_MCG_HAS_C1_FRDIV 1 /* SoC has C1[FRDIV] */
# define KINETIS_MCG_C1_FRDIV_MAX 7 /* C1[FRDIV] maximum value 5=1024, 6=1280 7=1536 */
# define KINETIS_MCG_HAS_C2 1 /* SoC has C2 Register */
# define KINETIS_MCG_HAS_C2_HGO 1 /* SoC has C2[HGO] */
# define KINETIS_MCG_HAS_C2_RANGE 1 /* SoC has C2[RANGE] */
# define KINETIS_MCG_HAS_C2_FCFTRIM 1 /* SoC has C2[FCFTRIM] */
# define KINETIS_MCG_HAS_C2_LOCRE0 1 /* SoC has C2[LOCRE0] */
# define KINETIS_MCG_HAS_C3 1 /* SoC has C3 Register */
# define KINETIS_MCG_HAS_C4 1 /* SoC has C4 Register */
# define KINETIS_MCG_HAS_C5 1 /* SoC has C5 Register */
# define KINETIS_MCG_HAS_C5_PRDIV 1 /* SoC has C5[PRDIV] */
# define KINETIS_MCG_C5_PRDIV_BASE 1 /* PRDIV base value corresponding to 0 in C5[PRDIV] */
# define KINETIS_MCG_C5_PRDIV_MAX 25 /* The Maximum value of C5[PRVDIV]) */
# define KINETIS_MCG_C5_PRDIV_BITS 5 /* Has 5 bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV] */
# undef KINETIS_MCG_HAS_C5_PLLREFSEL0 /* SoC has C5[PLLREFSEL0] */
# define KINETIS_MCG_HAS_C6 1 /* SoC has C6 Register */
# define KINETIS_MCG_HAS_C6_VDIV 1 /* SoC has C6[VDIV] */
# define KINETIS_MCG_C6_VDIV_BASE 24 /* VDIV base value corresponding to 0 in C6[VDIV] */
# define KINETIS_MCG_C6_VDIV_MAX 55 /* The Maximum value of C6[VDIV] */
# define KINETIS_MCG_HAS_C6_CME 1 /* SoC has C6[CME] */
# define KINETIS_MCG_HAS_C6_PLLS 1 /* SoC has C6[PLLS] */
# define KINETIS_MCG_HAS_C6_LOLIE0 1 /* SoC has C6[LOLIE0] */
# define KINETIS_MCG_HAS_S 1 /* SoC has S Register */
# define KINETIS_MCG_HAS_S_PLLST 1 /* SoC has S[PLLST] */
# define KINETIS_MCG_HAS_S_LOCK0 1 /* SoC has S[LOCK0] */
# define KINETIS_MCG_HAS_S_LOLS 1 /* SoC has S[LOLS] */
# undef KINETIS_MCG_HAS_ATC /* SoC has ATC Register */
# define KINETIS_MCG_HAS_ATCVH 1 /* SoC has ATCVH Register */
# define KINETIS_MCG_HAS_ATCVL 1 /* SoC has ATCVL Register */
# define KINETIS_MCG_HAS_SC 1 /* SoC has SC Register */
# define KINETIS_MCG_HAS_SC_ATMS 1 /* SoC has SC[ATMS] */
# define KINETIS_MCG_HAS_SC_ATMF 1 /* SoC has SC[ATMF] */
# define KINETIS_MCG_HAS_SC_ATME 1 /* SoC has SC[ATME] */
# define KINETIS_MCG_HAS_C7 1 /* SoC has C7 Register */
# define KINETIS_MCG_HAS_C7_OSCSEL 1 /* SoC has C7[OSCSEL] */
# define KINETIS_MCG_C7_OSCSEL_BITS 2 /* C7[OSCSEL] is n bits wide */
# define KINETIS_MCG_HAS_C8 1 /* SoC has C8 Register */
# define KINETIS_MCG_HAS_C8_LOCS1 1 /* SoC has C8[LOCS1] */
# define KINETIS_MCG_HAS_C8_CME1 1 /* SoC has C8[CME1] */
# define KINETIS_MCG_HAS_C8_LOLRE 1 /* SoC has C8[LOLRE] */
# define KINETIS_MCG_HAS_C8_LOCRE1 1 /* SoC has C8[LOCRE1] */
# undef KINETIS_MCG_HAS_C9 /* SoC has C9 Register */
# undef KINETIS_MCG_HAS_C9_EXT_PLL_LOCS /* SoC has C9_EXT_PLL[LOCS] */
# undef KINETIS_MCG_HAS_C9_PLL_LOCRE /* SoC has C9_PLL[LOCRE] */
# undef KINETIS_MCG_HAS_C9_PLL_CME /* SoC has C9_PLL[CME] */
# undef KINETIS_MCG_HAS_C10 /* SoC has C10 Register */
# undef KINETIS_MCG_HAS_C10_LOCS1 /* SoC has C10[LOCS1] */
# undef KINETIS_MCG_HAS_C11 /* SoC has C11 Register */
# undef KINETIS_MCG_HAS_C11_PLL1OSC1 /* SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1] */
# undef KINETIS_MCG_HAS_C11_PLLCS /* SoC has C11[PLLCS] */
# undef KINETIS_MCG_HAS_C11_PLLREFSEL1 /* SoC has C11[PLLREFSEL1] */
# undef KINETIS_MCG_HAS_C12 /* SoC has C12 Register */
# undef KINETIS_MCG_HAS_S2 /* SoC has S2 Register */
# undef KINETIS_MCG_HAS_S2_PLL1OSC1 /* SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1] */
# undef KINETIS_MCG_HAS_S2_PLLCST /* SoC has S2[PLLCST] */
/* MK66F N/X 1M0/2M0 V MD/LQ 18
*
* --------------- ------- --- ------- ------- ------ ------ ------ -----
* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
* FREQ CNT FLASH FLASH
* --------------- ------- --- ------- ------- ------ ------ ------ -----
* MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100
* MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100
* MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100
* MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100
*/
#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)
/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_06
/* MCG Configuration Parameters */
# define KINETIS_MCG_PLL_REF_MIN 8000000 /* OSCCLK/PLL_R minimum */
# define KINETIS_MCG_PLL_REF_MAX 16000000 /* OSCCLK/PLL_R maximum */
# define KINETIS_MCG_PLL_INTERNAL_DIVBY 2 /* The PLL clock is divided by 2 before VCO divider */
# define KINETIS_MCG_HAS_PLL_EXTRA_DIVBY 1 /* Is PLL clock divided by 1 before MCG PLL/FLL clock selection in the SIM module */
# define KINETIS_MCG_FFCLK_DIVBY 2 /* MCGFFCLK divided by 2 */
# define KINETIS_MCG_HAS_IRC_48M 1 /* Has 48MHz internal oscillator */
# undef KINETIS_MCG_HAS_LOW_FREQ_IRC /* Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2] */
# undef KINETIS_MCG_HAS_HIGH_FREQ_IRC /* Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN] */
# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
/* MCG Register Configuration */
# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
# define KINETIS_MCG_HAS_C1_FRDIV 1 /* SoC has C1[FRDIV] */
# define KINETIS_MCG_C1_FRDIV_MAX 7 /* C1[FRDIV] maximum value 5=1024, 6=1280 7=1536 */
# define KINETIS_MCG_HAS_C2 1 /* SoC has C2 Register */
# define KINETIS_MCG_HAS_C2_HGO 1 /* SoC has C2[HGO] */
# define KINETIS_MCG_HAS_C2_RANGE 1 /* SoC has C2[RANGE] */
# define KINETIS_MCG_HAS_C2_FCFTRIM 1 /* SoC has C2[FCFTRIM] */
# define KINETIS_MCG_HAS_C2_LOCRE0 1 /* SoC has C2[LOCRE0] */
# define KINETIS_MCG_HAS_C3 1 /* SoC has C3 Register */
# define KINETIS_MCG_HAS_C4 1 /* SoC has C4 Register */
# define KINETIS_MCG_HAS_C5 1 /* SoC has C5 Register */
# define KINETIS_MCG_HAS_C5_PRDIV 1 /* SoC has C5[PRDIV] */
# define KINETIS_MCG_C5_PRDIV_BASE 1 /* PRDIV base value corresponding to 0 in C5[PRDIV] */
# define KINETIS_MCG_C5_PRDIV_MAX 8 /* The Maximum value of C5[PRVDIV]) */
# define KINETIS_MCG_C5_PRDIV_BITS 3 /* Has 3 bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV] */
# undef KINETIS_MCG_HAS_C5_PLLREFSEL0 /* SoC has C5[PLLREFSEL0] */
# define KINETIS_MCG_HAS_C6 1 /* SoC has C6 Register */
# define KINETIS_MCG_HAS_C6_VDIV 1 /* SoC has C6[VDIV] */
# define KINETIS_MCG_C6_VDIV_BASE 16 /* VDIV base value corresponding to 0 in C6[VDIV] */
# define KINETIS_MCG_C6_VDIV_MAX 47 /* The Maximum value of C6[VDIV] */
# define KINETIS_MCG_HAS_C6_CME 1 /* SoC has C6[CME] */
# define KINETIS_MCG_HAS_C6_PLLS 1 /* SoC has C6[PLLS] */
# define KINETIS_MCG_HAS_C6_LOLIE0 1 /* SoC has C6[LOLIE0] */
# define KINETIS_MCG_HAS_S 1 /* SoC has S Register */
# define KINETIS_MCG_HAS_S_PLLST 1 /* SoC has S[PLLST] */
# define KINETIS_MCG_HAS_S_LOCK0 1 /* SoC has S[LOCK0] */
# define KINETIS_MCG_HAS_S_LOLS 1 /* SoC has S[LOLS] */
# undef KINETIS_MCG_HAS_ATC /* SoC has ATC Register */
# define KINETIS_MCG_HAS_ATCVH 1 /* SoC has ATCVH Register */
# define KINETIS_MCG_HAS_ATCVL 1 /* SoC has ATCVL Register */
# define KINETIS_MCG_HAS_SC 1 /* SoC has SC Register */
# define KINETIS_MCG_HAS_SC_ATMS 1 /* SoC has SC[ATMS] */
# define KINETIS_MCG_HAS_SC_ATMF 1 /* SoC has SC[ATMF] */
# define KINETIS_MCG_HAS_SC_ATME 1 /* SoC has SC[ATME] */
# define KINETIS_MCG_HAS_C7 1 /* SoC has C7 Register */
# define KINETIS_MCG_HAS_C7_OSCSEL 1 /* SoC has C7[OSCSEL] */
# define KINETIS_MCG_C7_OSCSEL_BITS 2 /* C7[OSCSEL] is n bits wide */
# define KINETIS_MCG_HAS_C8 1 /* SoC has C8 Register */
# define KINETIS_MCG_HAS_C8_LOCS1 1 /* SoC has C8[LOCS1] */
# define KINETIS_MCG_HAS_C8_CME1 1 /* SoC has C8[CME1] */
# define KINETIS_MCG_HAS_C8_LOLRE 1 /* SoC has C8[LOLRE] */
# define KINETIS_MCG_HAS_C8_LOCRE1 1 /* SoC has C8[LOCRE1] */
# define KINETIS_MCG_HAS_C9 1 /* SoC has C9 Register */
# define KINETIS_MCG_HAS_C9_EXT_PLL_LOCS 1 /* SoC has C9_EXT_PLL[LOCS] */
# define KINETIS_MCG_HAS_C9_PLL_LOCRE 1 /* SoC has C9_PLL[LOCRE] */
# define KINETIS_MCG_HAS_C9_PLL_CME 1 /* SoC has C9_PLL[CME] */
# undef KINETIS_MCG_HAS_C10 /* SoC has C10 Register */
# undef KINETIS_MCG_HAS_C10_LOCS1 /* SoC has C10[LOCS1] */
# define KINETIS_MCG_HAS_C11 /* SoC has C11 Register */
# undef KINETIS_MCG_HAS_C11_PLL1OSC1 /* SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1] */
# define KINETIS_MCG_HAS_C11_PLLCS /* SoC has C11[PLLCS] */
# undef KINETIS_MCG_HAS_C11_PLLREFSEL1 /* SoC has C11[PLLREFSEL1] */
# undef KINETIS_MCG_HAS_C12 /* SoC has C12 Register */
# define KINETIS_MCG_HAS_S2 /* SoC has S2 Register */
# undef KINETIS_MCG_HAS_S2_PLL1OSC1 /* SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1] */
# define KINETIS_MCG_HAS_S2_PLLCST /* SoC has S2[PLLCST] */
#else
# error "Unsupported Kinetis chip"
#endif
/* Use the catch all configuration for the MCG based on the implementations in nuttx prior 2/3/2017 */
#if KINETIS_MCG_VERSION == KINETIS_MCG_VERSION_UKN
/* MCG Configuration Parameters */
# define KINETIS_MCG_PLL_REF_MIN 2000000 /* OSCCLK/PLL_R minimum */
# define KINETIS_MCG_PLL_REF_MAX 4000000 /* OSCCLK/PLL_R maximum */
# define KINETIS_MCG_PLL_INTERNAL_DIVBY 1 /* The PLL clock is divided by 1 before VCO divider */
# define KINETIS_MCG_HAS_PLL_EXTRA_DIVBY 1 /* Is PLL clock divided by 1 before MCG PLL/FLL clock selection in the SIM module */
# define KINETIS_MCG_FFCLK_DIVBY 1 /* MCGFFCLK divided by 1 */
# undef KINETIS_MCG_HAS_IRC_48M /* Has 48MHz internal oscillator */
# undef KINETIS_MCG_HAS_LOW_FREQ_IRC /* Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2] */
# undef KINETIS_MCG_HAS_HIGH_FREQ_IRC /* Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN] */
# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
/* MCG Register Configuration */
# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
# define KINETIS_MCG_HAS_C1_FRDIV 1 /* SoC has C1[FRDIV] */
# define KINETIS_MCG_C1_FRDIV_MAX 5 /* C1[FRDIV] maximum value 5=1024, 6=1280 7=1536 */
# define KINETIS_MCG_HAS_C2 1 /* SoC has C2 Register */
# define KINETIS_MCG_HAS_C2_HGO 1 /* SoC has C2[HGO] */
# define KINETIS_MCG_HAS_C2_RANGE 1 /* SoC has C2[RANGE] */
# undef KINETIS_MCG_HAS_C2_FCFTRIM /* SoC has C2[FCFTRIM] */
# undef KINETIS_MCG_HAS_C2_LOCRE0 /* SoC has C2[LOCRE0] */
# define KINETIS_MCG_HAS_C3 1 /* SoC has C3 Register */
# define KINETIS_MCG_HAS_C4 1 /* SoC has C4 Register */
# define KINETIS_MCG_HAS_C5 1 /* SoC has C5 Register */
# define KINETIS_MCG_HAS_C5_PRDIV 1 /* SoC has C5[PRDIV] */
# define KINETIS_MCG_C5_PRDIV_BASE 1 /* PRDIV base value corresponding to 0 in C5[PRDIV] */
# define KINETIS_MCG_C5_PRDIV_MAX 25 /* The Maximum value of C5[PRVDIV]) */
# define KINETIS_MCG_C5_PRDIV_BITS 5 /* Has 5 bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV] */
# undef KINETIS_MCG_HAS_C5_PLLREFSEL0 /* SoC has C5[PLLREFSEL0] */
# define KINETIS_MCG_HAS_C6 1 /* SoC has C6 Register */
# define KINETIS_MCG_HAS_C6_VDIV 1 /* SoC has C6[VDIV] */
# define KINETIS_MCG_C6_VDIV_BASE 24 /* VDIV base value corresponding to 0 in C6[VDIV] */
# define KINETIS_MCG_C6_VDIV_MAX 55 /* The Maximum value of C6[VDIV] */
# define KINETIS_MCG_HAS_C6_CME 1 /* SoC has C6[CME] */
# define KINETIS_MCG_HAS_C6_PLLS 1 /* SoC has C6[PLLS] */
# define KINETIS_MCG_HAS_C6_LOLIE0 1 /* SoC has C6[LOLIE0] */
# define KINETIS_MCG_HAS_S 1 /* SoC has S Register */
# define KINETIS_MCG_HAS_S_PLLST 1 /* SoC has S[PLLST] */
# define KINETIS_MCG_HAS_S_LOCK0 1 /* SoC has S[LOCK0] */
# define KINETIS_MCG_HAS_S_LOLS 1 /* SoC has S[LOLS] */
# define KINETIS_MCG_HAS_ATC 1 /* SoC has ATC Register */
# define KINETIS_MCG_HAS_ATCVH 1 /* SoC has ATCVH Register */
# define KINETIS_MCG_HAS_ATCVL 1 /* SoC has ATCVL Register */
# undef KINETIS_MCG_HAS_SC /* SoC has SC Register */
# undef KINETIS_MCG_HAS_SC_ATMS /* SoC has SC[ATMS] */
# undef KINETIS_MCG_HAS_SC_ATMF /* SoC has SC[ATMF] */
# undef KINETIS_MCG_HAS_SC_ATME /* SoC has SC[ATME] */
# undef KINETIS_MCG_HAS_C7 /* SoC has C7 Register */
# undef KINETIS_MCG_HAS_C7_OSCSEL /* SoC has C7[OSCSEL] */
# undef KINETIS_MCG_C7_OSCSEL_BITS /* C7[OSCSEL] is n bits wide */
# undef KINETIS_MCG_HAS_C8 /* SoC has C8 Register */
# undef KINETIS_MCG_HAS_C8_LOCS1 /* SoC has C8[LOCS1] */
# undef KINETIS_MCG_HAS_C8_CME1 /* SoC has C8[CME1] */
# undef KINETIS_MCG_HAS_C8_LOLRE /* SoC has C8[LOLRE] */
# undef KINETIS_MCG_HAS_C8_LOCRE1 /* SoC has C8[LOCRE1] */
# undef KINETIS_MCG_HAS_C9 /* SoC has C9 Register */
# undef KINETIS_MCG_HAS_C9_EXT_PLL_LOCS /* SoC has C9_EXT_PLL[LOCS] */
# undef KINETIS_MCG_HAS_C9_PLL_LOCRE /* SoC has C9_PLL[LOCRE] */
# undef KINETIS_MCG_HAS_C9_PLL_CME /* SoC has C9_PLL[CME] */
# undef KINETIS_MCG_HAS_C10 /* SoC has C10 Register */
# undef KINETIS_MCG_HAS_C10_LOCS1 /* SoC has C10[LOCS1] */
# undef KINETIS_MCG_HAS_C11 /* SoC has C11 Register */
# undef KINETIS_MCG_HAS_C11_PLL1OSC1 /* SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1] */
# undef KINETIS_MCG_HAS_C11_PLLCS /* SoC has C11[PLLCS] */
# undef KINETIS_MCG_HAS_C11_PLLREFSEL1 /* SoC has C11[PLLREFSEL1] */
# undef KINETIS_MCG_HAS_C12 /* SoC has C12 Register */
# undef KINETIS_MCG_HAS_S2 /* SoC has S2 Register */
# undef KINETIS_MCG_HAS_S2_PLL1OSC1 /* SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1] */
# undef KINETIS_MCG_HAS_S2_PLLCST /* SoC has S2[PLLCST] */
#endif
#if !defined(KINETIS_MCG_VERSION)
# error "No KINETIS_MCG_VERSION defined!"
#endif
#if defined(KINETIS_MCG_HAS_C5_PRDIV)
# define KINETIS_MCG_C5_PRDIV_MASK ((1 << (KINETIS_MCG_C5_PRDIV_BITS))-1)
#endif
#if defined(KINETIS_MCG_HAS_C7_OSCSEL)
# define KINETIS_MCG_C7_OSCSEL_MASK ((1 << (KINETIS_MCG_C7_OSCSEL_BITS))-1)
#endif
#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_MCG_H */

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arch/arm/include/kinetis�kinetis_pmc.h Normal file
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@ -0,0 +1,324 @@
/************************************************************************************
* arch/arm/include/kinetis/kinetis_pmc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Note: It is envisioned that in the long term as a chip is added. The author of
* the new chip definitions will either find the exact configuration in an existing
* chip define and add the new chip to it Or add the PMC feature configuration
* #defines to the chip ifdef list below. In either case the author should mark
* it as "Verified to Document Number:" taken from the reference manual.
*
* To maintain backward compatibility to the version of NuttX prior to
* 2/22/2017, the catch all KINETIS_PMC_VERSION_UKN configuration is assigned
* to all the chips that did not have any conditional compilation based on
* KINETIS_K64 or KINETIS_K66. This is a "No worse" than the original code solution.
* N.B. Each original chip "if"definitions have been left intact so that the
* complete legacy definitions prior to 2/22/2017 may be filled in completely when
* vetted.
*/
/* PMC Register Configuration
*
* KINETIS_PMC_HAS_REGSC - SoC has REGSC Register
* KINETIS_PMC_HAS_REGSC_ACKISO - SoC has REGSC[ACKISO]
* KINETIS_PMC_HAS_REGSC_VLPRS - SoC has REGSC[VLPRS]
* KINETIS_PMC_HAS_REGSC_VLPO - SoC has REGSC[VLPO]
* KINETIS_PMC_HAS_REGSC_REGFPM - SoC has REGSC[REGFPM]
* KINETIS_PMC_HAS_REGSC_BGEN - SoC has REGSC[BGEN]
* KINETIS_PMC_HAS_REGSC_TRAMPO - SoC has REGSC[TRAMPO]
* KINETIS_PMC_HAS_REGSC_REGONS - SoC has REGSC[REGONS]
*/
/* Describe the version of the PMC
*
* These defines are not related to any NXP reference but are merely
* a way to label the versions we are using
*/
#define KINETIS_PMC_VERSION_UKN -1 /* What was in nuttx prior to 2/22/2017 */
#define KINETIS_PMC_VERSION_01 1 /* Verified Document Number: K60P144M150SF3RM Rev. 3, November 2014 */
#define KINETIS_PMC_VERSION_04 4 /* Verified to Document Numbers:
* K20P64M72SF1RM Rev. 1.1, Dec 2012
* K64P144M120SF5RM Rev. 2, January 2014
* K66P144M180SF5RMV2 Rev. 2, May 2015 */
/* MK20DX/DN---VLH5
*
* ------------- ------ --- ------- ------ ------- ------ ----- ----
* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
* FREQ CNT FLASH FLASH
* ------------- ------ --- ------- ------ ------- ------ ----- ----
* MK20DN32VLH5 50 MHz 64 LQFP 32 KB 32 KB — 8 KB 40
* MK20DX32VLH5 50 MHz 64 LQFP 64 KB 32 KB 2 KB 8 KB 40
* MK20DN64VLH5 50 MHz 64 LQFP 64 KB 64 KB — 16 KB 40
* MK20DX64VLH5 50 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40
* MK20DN128VLH5 50 MHz 64 LQFP 128 KB 128 KB — 16 KB 40
* MK20DX128VLH5 50 MHz 64 LQFP 160 KB 128 KB 2 KB 16 KB 40
*/
#if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DX32VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DN64VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DX64VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DN128VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DX128VLH5)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
/* MK20DX---VLH7
*
* ------------- ------ --- ------- ------ ------- ------ ----- ----
* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
* FREQ CNT FLASH FLASH
* ------------- ------ --- ------- ------ ------- ------ ----- ----
* MK20DX64VLH7 72 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40
* MK20DX128VLH7 72 MHz 64 LQFP 160 KB 128 KB 2 KB 32 KB 40
* MK20DX256VLH7 72 MHz 64 LQFP 288 KB 256 KB 2 KB 64 KB 40
* ------------- ------ --- ------- ------ ------- ------ ----- ----
*/
#elif defined(CONFIG_ARCH_CHIP_MK20DX64VLH7) || defined(CONFIG_ARCH_CHIP_MK20DX128VLH7) || \
defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
/* Verified to Document Number: K20P64M72SF1RM Rev. 1.1, Dec 2012 */
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \
defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \
defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \
defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \
defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \
defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12)
/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_01
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# undef KINETIS_PMC_HAS_REGSC_BGEN /* SoC has REGSC[BGEN] */
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
/* MK66F N/X 1M0/2M0 V MD/LQ 18
*
* --------------- ------- --- ------- ------- ------ ------ ------ -----
* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
* FREQ CNT FLASH FLASH
* --------------- ------- --- ------- ------- ------ ------ ------ -----
* MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100
* MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100
* MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100
* MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100
*/
#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)
/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
#else
# error "Unsupported Kinetis chip"
#endif
/* Use the catch all configuration for the PMC based on the implementations in nuttx prior 2/3/2017 */
#if KINETIS_PMC_VERSION == KINETIS_PMC_VERSION_UKN
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# undef KINETIS_PMC_HAS_REGSC_ACKISO /* SoC has REGSC[ACKISO] */
# define KINETIS_PMC_HAS_REGSC_VLPRS 1 /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# undef KINETIS_PMC_HAS_REGSC_BGEN /* SoC has REGSC[BGEN] */
# define KINETIS_PMC_HAS_REGSC_TRAMPO 1 /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
#endif
#if !defined(KINETIS_PMC_VERSION)
# error "No KINETIS_PMC_VERSION defined!"
#endif
#if defined(KINETIS_PMC_HAS_C5_PRDIV)
# define KINETIS_PMC_C5_PRDIV_MASK ((1 << (KINETIS_PMC_C5_PRDIV_BITS))-1)
#endif
#if defined(KINETIS_PMC_HAS_C7_OSCSEL)
# define KINETIS_PMC_C7_OSCSEL_MASK ((1 << (KINETIS_PMC_C7_OSCSEL_BITS))-1)
#endif
#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H */

1322
arch/arm/include/kinetis�kinetis_sim.h Normal file
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262
configs/stm32f103-minimum/README.txt
View File

@ -4,70 +4,86 @@ README
This README discusses issues unique to NuttX configurations for the
STM32F103C8T6 Minimum System Development Board for ARM Microcontroller.
This board is available from several vendors on the net, and may
be sold under different names or no name at all. It is based on a
STM32F103C8T6 and has a DIP-40 form-factor.
Contents
========
There are two versions of very similar boards: One is red and one is
blue. See http://www.stm32duino.com/viewtopic.php?f=28&t=117
- STM32F103C8T6 Minimum System Development Boards:
- LEDs
- UARTs
- Timer Inputs/Outputs
- Using 128KiB of Flash instead of 64KiB
- Quadrature Encoder
- STM32F103 Minimum - specific Configuration Options
- Configurations
The Red Board:
STM32F103C8T6 Minimum System Development Boards:
================================================
Good things about the red board:
This STM32F103C8T6 minimum system development board is available from
several vendors on the net, and may be sold under different names or
no name at all. It is based on a STM32F103C8T6 and has a DIP-40 form-
factor.
- 1.5k pull up resistor on the PA12 pin (USB D+) which you can
programatically drag down for automated USB reset.
- large power capacitors and LDO power.
There are two versions of very similar boards: One is red and one is
blue. See http://www.stm32duino.com/viewtopic.php?f=28&t=117
Problems with the red board:
The Red Board:
- Silk screen is barely readable, the text is chopped off on some of
the pins
- USB connector only has two anchor points and it is directly soldered
on the surface
- Small reset button with hardly any resistance
Good things about the red board:
The Blue Board:
- 1.5k pull up resistor on the PA12 pin (USB D+) which you can
programatically drag down for automated USB reset.
- large power capacitors and LDO power.
Good things about the blue board:
Problems with the red board:
- Four soldered anchor point on the USB connector. What you can't tell
from this picture is that there is a notch in the pcb board and the USB
connector sits down inside it some. This provides some lateral stability
that takes some of the stress off the solder points.
- It has nice clear readable silkscreen printing.
- It also a larger reset button.
- Silk screen is barely readable, the text is chopped off on some of
the pins
- USB connector only has two anchor points and it is directly soldered
on the surface
- Small reset button with hardly any resistance
Problems with the blue board:
The Blue Board:
- Probably won't work as a USB device if it has a 10k pull-up on PA12. You
have to check the pull up on PA12 (USB D+). If it has a 10k pull-up
resistor, you will need to replace it with a 1.5k one to use the native
USB.
- Puny voltage regulator probably 100mA.
Good things about the blue board:
A schematic for the blue board is available here:
http://www.stm32duino.com/download/file.php?id=276
- Four soldered anchor point on the USB connector. What you can't tell
from this picture is that there is a notch in the pcb board and the USB
connector sits down inside it some. This provides some lateral stability
that takes some of the stress off the solder points.
- It has nice clear readable silkscreen printing.
- It also a larger reset button.
Both Boards:
Problems with the blue board:
Nice features common to both:
- Probably won't work as a USB device if it has a 10k pull-up on PA12. You
have to check the pull up on PA12 (USB D+). If it has a 10k pull-up
resistor, you will need to replace it with a 1.5k one to use the native
USB.
- Puny voltage regulator probably 100mA.
- SWD pins broken out and easily connected (VCC, GND, SWDIO, SWCLK)
- USB 5V is broken out with easy access.
- User LED on PC13
- Power LED
- You can probably use more flash (128k) than officially documented for
the chip (stm32f103c8t6 64k), I was able to load 115k of flash on mine
and it seemed to work.
A schematic for the blue board is available here:
http://www.stm32duino.com/download/file.php?id=276
Problems with both boards:
Both Boards:
- No preloaded bootloader * to me this isn't really a problem as the
entire 64k of flash is available for use
- No user button
Nice features common to both:
This is the board pinout based on its form-factor for the Blue board:
- SWD pins broken out and easily connected (VCC, GND, SWDIO, SWCLK)
- USB 5V is broken out with easy access.
- User LED on PC13
- Power LED
- You can probably use more flash (128k) than officially documented for
the chip (stm32f103c8t6 64k), I was able to load 115k of flash on mine
and it seemed to work.
Problems with both boards:
- No preloaded bootloader * to me this isn't really a problem as the
entire 64k of flash is available for use
- No user button
This is the board pinout based on its form-factor for the Blue board:
USB
___
@ -94,25 +110,15 @@ This is the board pinout based on its form-factor for the Blue board:
|3.3V VB|
|_____________|
Contents
========
- LEDs
- UARTs
- Timer Inputs/Outputs
- Using 128KiB of Flash instead of 64KiB
- STM32F103 Minimum - specific Configuration Options
- Configurations
LEDs
====
The STM32F103 Minimum board has only one software controllable LED.
This LED can be used by the board port when CONFIG_ARCH_LEDS option is
enabled.
The STM32F103 Minimum board has only one software controllable LED.
This LED can be used by the board port when CONFIG_ARCH_LEDS option is
enabled.
If enabled the LED is simply turned on when the board boots
succesfully, and is blinking on panic / assertion failed.
If enabled the LED is simply turned on when the board boots
succesfully, and is blinking on panic / assertion failed.
UARTs
=====
@ -139,7 +145,7 @@ UARTs
Default USART/UART Configuration
--------------------------------
USART1 (RX & TX only) is available through pins PA9 (TX) and PA10 (RX).
USART1 (RX & TX only) is available through pins PA9 (TX) and PA10 (RX).
Timer Inputs/Outputs
====================
@ -171,69 +177,101 @@ Timer Inputs/Outputs
Using 128KiB of Flash instead of 64KiB
======================================
Some people figured out that the STM32F103C8T6 has 128KiB of internal memory
instead of 64KiB as documented in the datasheet and reported by its internal
register.
Some people figured out that the STM32F103C8T6 has 128KiB of internal memory
instead of 64KiB as documented in the datasheet and reported by its internal
register.
In order to enable 128KiB you need modify the linker script to reflect this
new size. Open the configs/stm32f103-minimum/scripts/ld.script and replace:
In order to enable 128KiB you need modify the linker script to reflect this
new size. Open the configs/stm32f103-minimum/scripts/ld.script and replace:
flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K
flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K
with
with
flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
Enable many NuttX features (ie. many filesystems and applications) to get a
large binary image with more than 64K.
Enable many NuttX features (ie. many filesystems and applications) to get a
large binary image with more than 64K.
We will use OpenOCD to write the firmware in the STM32F103C8T6 Flash. Use a
up to dated OpenOCD version (ie. openocd-0.9).
We will use OpenOCD to write the firmware in the STM32F103C8T6 Flash. Use a
up to dated OpenOCD version (ie. openocd-0.9).
You will need to create a copy of original openocd/scripts/target/stm32f1x.cfg
to openocd/scripts/target/stm32f103c8t6.cfg and edit the later file replacing:
You will need to create a copy of original openocd/scripts/target/stm32f1x.cfg
to openocd/scripts/target/stm32f103c8t6.cfg and edit the later file replacing:
flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
with
with
flash bank $_FLASHNAME stm32f1x 0x08000000 0x20000 0 0 $_TARGETNAME
flash bank $_FLASHNAME stm32f1x 0x08000000 0x20000 0 0 $_TARGETNAME
We will use OpenOCD with STLink-V2 programmer, but it will work with other
programmers (JLink, Versaloon, or some based on FTDI FT232, etc).
We will use OpenOCD with STLink-V2 programmer, but it will work with other
programmers (JLink, Versaloon, or some based on FTDI FT232, etc).
Open a terminal and execute:
Open a terminal and execute:
$ sudo openocd -f interface/stlink-v2.cfg -f target/stm32f103c8t6.cfg
$ sudo openocd -f interface/stlink-v2.cfg -f target/stm32f103c8t6.cfg
Now in other terminal execute:
Now in other terminal execute:
$ telnet localhost 4444
$ telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> reset halt
stm32f1x.cpu: target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x080003ac msp: 0x20000d78
> reset halt
stm32f1x.cpu: target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x080003ac msp: 0x20000d78
> flash write_image erase nuttx.bin 0x08000000
auto erase enabled
device id = 0x20036410
ignoring flash probed value, using configured bank size
flash size = 128kbytes
stm32f1x.cpu: target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x2000003a msp: 0x20000d78
wrote 92160 bytes from file nuttx.bin in 4.942194s (18.211 KiB/s)
> flash write_image erase nuttx.bin 0x08000000
auto erase enabled
device id = 0x20036410
ignoring flash probed value, using configured bank size
flash size = 128kbytes
stm32f1x.cpu: target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x2000003a msp: 0x20000d78
wrote 92160 bytes from file nuttx.bin in 4.942194s (18.211 KiB/s)
> reset run
> exit
> reset run
> exit
Now NuttX should start normally.
Now NuttX should start normally.
Quadrature Encoder:
===================
The nsh configuration has been used to test the Quadrture Encoder
(QEncoder, QE) with the following modifications to the configuration
file:
- These setting enable support for the common QEncode upper half driver:
CONFIG_SENSORS=y
CONFIG_QENCODER=y
- This is a board setting that selected timer 4 for use with the
quadrature encode:
CONFIG_STM32F103MINIMUM_QETIMER=4
- These settings enable the STM32 Quadrature encoder on timer 4:
CONFIG_STM32_TIM4_CAP=y
CONFIG_STM32_TIM4_QE=y
CONFIG_STM32_TIM4_QECLKOUT=2800000
CONFIG_STM32_QENCODER_FILTER=y
CONFIG_STM32_QENCODER_SAMPLE_EVENT_6=y
CONFIG_STM32_QENCODER_SAMPLE_FDTS_4=y
- These settings enable the test case at apps/examples/qencoder:
CONFIG_EXAMPLES_QENCODER=y
CONFIG_EXAMPLES_QENCODER_DELAY=100
CONFIG_EXAMPLES_QENCODER_DEVPATH="/dev/qe0"
STM32F103 Minimum - specific Configuration Options
==================================================
@ -406,21 +444,25 @@ STM32F103 Minimum - specific Configuration Options
Configurations
==============
Each STM32F103 Minimum configuration is maintained in a sub-directory and
can be selected as follow:
Instantiating Configurations
----------------------------
Each STM32F103 Minimum configuration is maintained in a sub-directory and
can be selected as follow:
cd tools
./configure.sh STM32F103 Minimum/<subdir>
cd -
. ./setenv.sh
If this is a Windows native build, then configure.bat should be used
instead of configure.sh:
If this is a Windows native build, then configure.bat should be used
instead of configure.sh:
configure.bat STM32F103-Minimum\<subdir>
Where <subdir> is one of the following:
Where <subdir> is one of the following:
Configuration Directories
-------------------------
nsh:
---
Configures the NuttShell (nsh) located at apps/examples/nsh. This