diff --git a/arch/arm/src/tms570/chip.h b/arch/arm/src/tms570/chip.h index ddd76b33c0..11c62adf00 100644 --- a/arch/arm/src/tms570/chip.h +++ b/arch/arm/src/tms570/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tms570/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TMS570_CHIP_H #define __ARCH_ARM_SRC_TMS570_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/tms570_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Cache line sizes (in bytes) */ diff --git a/arch/arm/src/tms570/hardware/tms570_esm.h b/arch/arm/src/tms570/hardware/tms570_esm.h index 989f1c84c9..121ad249e2 100644 --- a/arch/arm/src/tms570/hardware/tms570_esm.h +++ b/arch/arm/src/tms570/hardware/tms570_esm.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570_esm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ /* References: * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, @@ -27,22 +27,22 @@ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_ESM_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_ESM_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tms570_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ #define ESM_GROUP1 0 #define ESM_GROUP2 1 #define ESM_GROUP3 2 -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define TMS570_ESM_EEPAPR1_OFFSET 0x0000 /* ESM Enable ERROR Pin Action/Response Register 1 */ #define TMS570_ESM_DEPAPR1_OFFSET 0x0004 /* ESM Disable ERROR Pin Action/Response Register 1 */ @@ -50,7 +50,9 @@ #define TMS570_ESM_IECR1_OFFSET 0x000c /* ESM Interrupt Enable Clear/Status Register 1 */ #define TMS570_ESM_ILSR1_OFFSET 0x0010 /* Interrupt Level Set/Status Register 1 */ #define TMS570_ESM_ILCR1_OFFSET 0x0014 /* Interrupt Level Clear/Status Register 1 */ + #define TMS570_ESM_SRA_OFFSET(n) (0x0018 + ((n) << 2)) /* n=0, 1, 2 */ + # define TMS570_ESM_SR1_OFFSET 0x0018 /* ESM Status Register for group 1 */ # define TMS570_ESM_SR2_OFFSET 0x001c /* ESM Status Register for group 2 */ # define TMS570_ESM_SR3_OFFSET 0x0020 /* ESM Status Register for group 3 */ @@ -68,13 +70,15 @@ #define TMS570_ESM_ILSR4_OFFSET 0x0050 /* Interrupt Level Set/Status Register 4 */ #define TMS570_ESM_ILCR4_OFFSET 0x0054 /* Interrupt Level Clear/Status Register 4 */ #define TMS570_ESM_SR4_OFFSET 0x0058 /* ESM Status Register 4 */ + #define TMS570_ESM_SRB_OFFSET(n) (0x0058 + (((n)-4) << 2)) /* n=4, 5, 6 */ + # define TMS570_ESM_SR4_OFFSET 0x0058 /* ESM Status Register for group 4 */ # define TMS570_ESM_SR5_OFFSET 0x005c /* ESM Status Register for group 5 */ # define TMS570_ESM_SR6_OFFSET 0x0060 /* ESM Status Register for group 6 */ #define TMS570_ESM_SSR5_OFFSET 0x0064 /* ESM Status Shadow Register 5 */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define TMS570_ESM_EEPAPR1 (TMS570_ESM_BASE+TMS570_ESM_EEPAPR1_OFFSET) #define TMS570_ESM_DEPAPR1 (TMS570_ESM_BASE+TMS570_ESM_DEPAPR1_OFFSET) @@ -106,7 +110,7 @@ # define TMS570_ESM_SR6 (TMS570_ESM_BASE+TMS570_ESM_SR6_OFFSET) #define TMS570_ESM_SSR5 (TMS570_ESM_BASE+TMS570_ESM_SSR5_OFFSET) -/* Register Bit-Field Definitions *******************************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* ESM Enable ERROR Pin Action/Response Register 1 */ diff --git a/arch/arm/src/tms570/hardware/tms570_flash.h b/arch/arm/src/tms570/hardware/tms570_flash.h index 1a0354b167..f0068896bb 100644 --- a/arch/arm/src/tms570/hardware/tms570_flash.h +++ b/arch/arm/src/tms570/hardware/tms570_flash.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570_flash.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ /* References: * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, @@ -27,18 +27,18 @@ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_FLASH_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_FLASH_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tms570_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define TMS570_FLASH_FRDCNTL_OFFSET 0x000 /* Flash Option Control Register */ #define TMS570_FLASH_FEDACTRL1_OFFSET 0x008 /* Flash Error Detection and Correction Control Register 1 */ @@ -83,7 +83,7 @@ #define TMS570_FLASH_EEUNCERRADD_OFFSET 0x320 /* EEPROM Emulation Un-Correctable Error Address Register */ #define TMS570_FLASH_FCFGBANK_OFFSET 0x400 /* Flash Bank Configuration Register */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define TMS570_FLASH_FRDCNTL (TMS570_FWRAP_BASE+TMS570_FLASH_FRDCNTL_OFFSET) #define TMS570_FLASH_FEDACTRL1 (TMS570_FWRAP_BASE+TMS570_FLASH_FEDACTRL1_OFFSET) @@ -128,7 +128,7 @@ #define TMS570_FLASH_EEUNCERRADD (TMS570_FWRAP_BASE+TMS570_FLASH_EEUNCERRADD_OFFSET) #define TMS570_FLASH_FCFGBANK (TMS570_FWRAP_BASE+TMS570_FLASH_FCFGBANK_OFFSET) -/* Register Bit-Field Definitions *******************************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* Flash Option Control Register */ @@ -140,30 +140,43 @@ /* Flash Error Detection and Correction Control Register 1 */ #define FLASH_FEDACTRL1_ + /* Flash Error Detection and Correction Control Register 2 */ #define FLASH_FEDACTRL2_ + /* Flash Correctable Error Count Register */ #define FLASH_FCORERRCNT_ + /* Flash Correctable Error Address Register */ #define FLASH_FCORERRADD_ + /* Flash Correctable Error Position Register */ #define FLASH_FCORERRPOS_ + /* Flash Error Detection and Correction Status Register */ #define FLASH_FEDACSTATUS_ + /* Flash Un-Correctable Error Address Register */ #define FLASH_FUNCERRADD_ + /* Flash Error Detection and Correction Sector Disable Register */ #define FLASH_FEDACSDIS_ + /* Flash Primary Address Tag Register */ #define FLASH_FPRIMADDTAG_ + /* Flash Duplicate Address Tag Register */ #define FLASH_FDUPDDTAG_ + /* Flash Bank Protection Register */ #define FLASH_FBPROT_ + /* Flash Bank Sector Enable Register */ #define FLASH_FBSE_ + /* Flash Bank Busy Register */ #define FLASH_FBBUSY_ + /* Flash Bank Access Control Register */ #define FLASH_FBAC_ @@ -187,32 +200,46 @@ /* Flash Bank/Pump Ready Register */ #define FLASH_FBPRDY_ + /* Flash Pump Access Control Register 1 */ #define FLASH_FPAC1_ + /* Flash Pump Access Control Register 2 */ #define FLASH_FPAC2_ + /* Flash Module Access Control Register */ #define FLASH_FMAC_ + /* Flash Module Status Register */ #define FLASH_FMSTAT_ + /* EEPROM Emulation Data MSW Register */ #define FLASH_FEMUDMSW_ + /* EEPROM Emulation Data LSW Register */ #define FLASH_FEMUDLSW_ + /* EEPROM Emulation ECC Register */ #define FLASH_FEMUECC_ + /* EEPROM Emulation Address Register */ #define FLASH_FEMUADDR_ + /* Diagnostic Control Register */ #define FLASH_FDIAGCTRL_ + /* Uncorrected Raw Data High Register */ #define FLASH_FRAWDATAH_ + /* Uncorrected Raw Data Low Register */ #define FLASH_FRAWDATAL_ + /* Uncorrected Raw ECC Register */ #define FLASH_FRAWECC_ + /* Parity Override Register */ #define FLASH_FPAROVR_ + /* Flash Error Detection and Correction Sector Disable Register 2 */ #define FLASH_FEDACSDIS2_ @@ -238,18 +265,25 @@ /* EEPROM Emulation Error Detection and Correction Control Register 1 */ #define FLASH_EECTRL1_ + /* EEPROM Emulation Error Detection and Correction Control Register 2 */ #define FLASH_EECTRL2_ + /* EEPROM Emulation Correctable Error Count Register */ #define FLASH_EECORERRCNT_ + /* EEPROM Emulation Correctable Error Address Register */ #define FLASH_EECORERRADD_ + /* EEPROM Emulation Correctable Error Bit Position Register */ #define FLASH_EECORERRPOS_ + /* EEPROM Emulation Error Status Register */ #define FLASH_EESTATUS_ + /* EEPROM Emulation Un-Correctable Error Address Register */ #define FLASH_EEUNCERRADD_ + /* Flash Bank Configuration Register */ #define FLASH_FCFGBANK_ diff --git a/arch/arm/src/tms570/hardware/tms570_gio.h b/arch/arm/src/tms570/hardware/tms570_gio.h index 8ab93d7046..16dc41ee32 100644 --- a/arch/arm/src/tms570/hardware/tms570_gio.h +++ b/arch/arm/src/tms570/hardware/tms570_gio.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570_gio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ /* References: * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, @@ -27,16 +27,16 @@ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_GIO_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_GIO_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tms570_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ #define TMS570_GIOA 0 #define TMS570_GIOB 1 @@ -50,7 +50,7 @@ #define TMS570_NPORTS 8 #define TMS570_NIRQPORTS 4 -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define TMS570_GIO_GCR0_OFFSET 0x0000 /* GIO Global Control Register */ #define TMS570_GIO_INTDET_OFFSET 0x0008 /* GIO Interrupt Detect Register */ @@ -147,7 +147,7 @@ #define TMS570_GIOH_PULDIS_OFFSET 0x012c /* GIOH Pull Disable Register */ #define TMS570_GIOH_PSL_OFFSET 0x0130 /* GIOH Pull Select Register */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define TMS570_GIO_GCR0 (TMS570_GIO_BASE+TMS570_GIO_GCR0_OFFSET) #define TMS570_GIO_INTDET (TMS570_GIO_BASE+TMS570_GIO_INTDET_OFFSET) @@ -244,7 +244,7 @@ #define TMS570_GIOH_PULDIS (TMS570_GIO_BASE+TMS570_GIOH_PULDIS_OFFSET) #define TMS570_GIOH_PSL (TMS570_GIO_BASE+TMS570_GIOH_PSL_OFFSET) -/* Register Bit-Field Definitions *******************************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* GIO Global Control Register */ @@ -420,9 +420,14 @@ # define GIO_OFF_GIOD6 (0x1f) /* GIOD6 interrupt pending */ # define GIO_OFF_GIOD7 (0x20) /* GIOD7 interrupt pending */ -/* GIO Data Direction Register, GIO Data Input Register, GIO Data Output Register, - * GIO Data Set Register, GIO Data Clear Register, GIO Open Drain Register, - * GIO Pull Disable Register, and GIO Pull Select Register +/* GIO Data Direction Register, + * GIO Data Input Register, + * GIO Data Output Register, + * GIO Data Set Register, + * GIO Data Clear Register, + * GIO Open Drain Register, + * GIO Pull Disable Register, + * and GIO Pull Select Register */ #define GIO_PIN(n) (1 << (n)) /* Bit n: Corresponds to pin n */ diff --git a/arch/arm/src/tms570/hardware/tms570_iomm.h b/arch/arm/src/tms570/hardware/tms570_iomm.h index 80c8bf4355..04f3ffe48d 100644 --- a/arch/arm/src/tms570/hardware/tms570_iomm.h +++ b/arch/arm/src/tms570/hardware/tms570_iomm.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570_iomm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ /* References: * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, @@ -27,18 +27,18 @@ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_IOMM_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_IOMM_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tms570_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define TMS570_IOMM_REVISION_OFFSET 0x0000 /* Revision Register */ #define TMS570_IOMM_BOOT_OFFSET 0x0020 /* Boot Mode Register */ @@ -85,7 +85,7 @@ # define TMS570_IOMM_PINMMR29_OFFSET 0x0184 /* Pin Multiplexing Control Register 29 */ # define TMS570_IOMM_PINMMR30_OFFSET 0x0188 /* Pin Multiplexing Control Register 30 */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define TMS570_IOMM_REVISION (TMS570_IOMM_BASE+TMS570_IOMM_REVISION_OFFSET) #define TMS570_IOMM_BOOT (TMS570_IOMM_BASE+TMS570_IOMM_BOOT_OFFSET) @@ -132,10 +132,11 @@ # define TMS570_IOMM_PINMMR29 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR29_OFFSET) # define TMS570_IOMM_PINMMR30 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR30_OFFSET) -/* Register Bit-Field Definitions *******************************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* Revision Register */ #define IOMM_REVISION_ + /* Boot Mode Register */ #define IOMM_BOOT_ @@ -151,21 +152,28 @@ /* Error Raw Status / Set Register */ #define IOMM_ERRRAWSTATUS_ + /* Error Enabled Status / Clear Register */ #define IOMM_ERRSTATUS_ + /* Error Signaling Enable Register */ #define IOMM_ERRENABLE_ + /* Error Signaling Enable Clear Register */ #define IOMM_ERRENABLECLR_ + /* Fault Address Register */ #define IOMM_FAULTADDRESS_ + /* Fault Status Register */ #define IOMM_FAULTSTATUS_ + /* Fault Clear Register */ #define IOMM_FAULTCLR_ -/* Pin Multiplexing Control Register n, n=0..30. Each 8-bit field controls the functionality of - * one pin/ball. There are then a maximum of 31*4 = 124 pin/ball configurations supported. +/* Pin Multiplexing Control Register n, n=0..30. + * Each 8-bit field controls the functionality of one pin/ball. + * There are then a maximum of 31*4 = 124 pin/ball configurations supported. */ #define IOMM_PINMMR_REGNDX(n) ((n) >> 2) diff --git a/arch/arm/src/tms570/hardware/tms570_memorymap.h b/arch/arm/src/tms570/hardware/tms570_memorymap.h index 9078198046..cf67a2adb4 100644 --- a/arch/arm/src/tms570/hardware/tms570_memorymap.h +++ b/arch/arm/src/tms570/hardware/tms570_memorymap.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_MEMORYMAP_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_MEMORYMAP_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include diff --git a/arch/arm/src/tms570/hardware/tms570_pbist.h b/arch/arm/src/tms570/hardware/tms570_pbist.h index c5c25273fc..8bd949848c 100644 --- a/arch/arm/src/tms570/hardware/tms570_pbist.h +++ b/arch/arm/src/tms570/hardware/tms570_pbist.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570_pbist.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ /* References: * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, @@ -27,16 +27,17 @@ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PBIST_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PBIST_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tms570_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ + /* PBIST RAM Groups */ #define PBIST_PBIST_ROM_GROUP 1 /* ROM */ @@ -57,13 +58,13 @@ #define PBIST_DCAN1_RAM_RGS 3 /* Dual-port */ #define PBIST_DCAN2_RAM_RGS 4 /* Dual-port */ #define PBIST_ESRAM1_RAM_RGS 6 /* Single-port */ -#define PBIST_MIBSPI1_RAM_RGS 7 /* Dual-port */ +#define PBIST_MIBSPI1_RAM_RGS 7 /* Dual-port */ #define PBIST_VIM_RAM_RGS 8 /* Dual-port */ #define PBIST_MIBADC_RAM_RGS 9 /* Dual-port */ #define PBIST_N2HET_RAM_RGS 11 /* Dual-port */ #define PBIST_HET_TU_RAM_RGS 12 /* Dual-port */ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define TMS570_PBIST_RAMT_OFFSET 0x0160 /* RAM Configuration Register */ #define TMS570_PBIST_DLR_OFFSET 0x0164 /* Datalogger Register */ @@ -84,7 +85,7 @@ #define TMS570_PBIST_RINFOL_OFFSET 0x01c8 /* RAM Info Mask Lower Register */ #define TMS570_PBIST_RINFOU_OFFSET 0x01cc /* RAM Info Mask Upper Register */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define TMS570_PBIST_RAMT (TMS570_PBIST_BASE+TMS570_PBIST_RAMT_OFFSET) #define TMS570_PBIST_DLR (TMS570_PBIST_BASE+TMS570_PBIST_DLR_OFFSET) @@ -105,7 +106,7 @@ #define TMS570_PBIST_RINFOL (TMS570_PBIST_BASE+TMS570_PBIST_RINFOL_OFFSET) #define TMS570_PBIST_RINFOU (TMS570_PBIST_BASE+TMS570_PBIST_RINFOU_OFFSET) -/* Register Bit-Field Definitions *******************************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* RAM Configuration Register */ diff --git a/arch/arm/src/tms570/hardware/tms570_pcr.h b/arch/arm/src/tms570/hardware/tms570_pcr.h index c72c34f2bf..8b3870c17b 100644 --- a/arch/arm/src/tms570/hardware/tms570_pcr.h +++ b/arch/arm/src/tms570/hardware/tms570_pcr.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570_pcr.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ /* References: * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, @@ -27,18 +27,18 @@ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PCR_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PCR_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tms570_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define TMS570_PCR_PMPROTSET0_OFFSET 0x0000 /* Peripheral Memory Protection Set Register 0 */ #define TMS570_PCR_PMPROTSET1_OFFSET 0x0004 /* Peripheral Memory Protection Set Register 1 */ @@ -65,7 +65,7 @@ #define TMS570_PCR_PSPWRDWNCLR2_OFFSET 0x00a8 /* Peripheral Power-Down Clear Register 2 */ #define TMS570_PCR_PSPWRDWNCLR3_OFFSET 0x00ac /* Peripheral Power-Down Clear Register 3 */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define TMS570_PCR_PMPROTSET0 (TMS570_PCR_BASE+TMS570_PCR_PMPROTSET0_OFFSET) #define TMS570_PCR_PMPROTSET1 (TMS570_PCR_BASE+TMS570_PCR_PMPROTSET1_OFFSET) @@ -92,7 +92,7 @@ #define TMS570_PCR_PSPWRDWNCLR2 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNCLR2_OFFSET) #define TMS570_PCR_PSPWRDWNCLR3 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNCLR3_OFFSET) -/* Register Bit-Field Definitions *******************************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* Peripheral Memory Protection Set Register 0 */ #define PCR_PMPROTSET0_ @@ -142,7 +142,9 @@ /* Peripheral Memory Power-Down Clear Register 1 */ #define PCR_PCSPWRDWNCLR1_ -/* Peripheral Power-Down Set Register 0 and Peripheral Power-Down Clear Register 0 */ +/* Peripheral Power-Down Set Register 0 and + * Peripheral Power-Down Clear Register 0 + */ #define PCR_PSPWERDWN0_PS0_SHIFT (0) /* Bits 0-3: Quadrants for PS0 */ #define PCR_PSPWERDWN0_PS0_MASK (15 << PCR_PSPWERDWN0_PS0_SHIFT) @@ -201,7 +203,9 @@ # define PCR_PSPWERDWN0_PS7_Q4 (8 << PCR_PSPWERDWN0_PS7_SHIFT) # define PCR_PSPWERDWN0_PS7_QALL (15 << PCR_PSPWERDWN0_PS7_SHIFT) -/* Peripheral Power-Down Set Register 1 and Peripheral Power-Down Clear Register 1 */ +/* Peripheral Power-Down Set Register 1 + * and Peripheral Power-Down Clear Register 1 + */ #define PCR_PSPWERDWN1_PS8_SHIFT (0) /* Bits 0-3: Quadrants for PS8 */ #define PCR_PSPWERDWN1_PS8_MASK (15 << PCR_PSPWERDWN1_PS8_SHIFT) @@ -260,7 +264,9 @@ # define PCR_PSPWERDWN1_PS15_Q4 (8 << PCR_PSPWERDWN1_PS15_SHIFT) # define PCR_PSPWERDWN1_PS15_QALL (15 << PCR_PSPWERDWN1_PS15_SHIFT) -/* Peripheral Power-Down Set Register 2 and Peripheral Power-Down Clear Register 2*/ +/* Peripheral Power-Down Set Register 2 + * and Peripheral Power-Down Clear Register 2 + */ #define PCR_PSPWERDWN2_PS16_SHIFT (0) /* Bits 0-3: Quadrants for PS16 */ #define PCR_PSPWERDWN2_PS16_MASK (15 << PCR_PSPWERDWN2_PS16_SHIFT) @@ -319,7 +325,9 @@ # define PCR_PSPWERDWN2_PS23_Q4 (8 << PCR_PSPWERDWN2_PS23_SHIFT) # define PCR_PSPWERDWN2_PS23_QALL (15 << PCR_PSPWERDWN2_PS23_SHIFT) -/* Peripheral Power-Down Set Register 3 and Peripheral Power-Down Clear Register 3 */ +/* Peripheral Power-Down Set Register 3 + * and Peripheral Power-Down Clear Register 3 + */ #define PCR_PSPWERDWN3_PS24_SHIFT (0) /* Bits 0-3: Quadrants for PS24 */ #define PCR_PSPWERDWN3_PS24_MASK (15 << PCR_PSPWERDWN3_PS24_SHIFT) diff --git a/arch/arm/src/tms570/hardware/tms570_pinmux.h b/arch/arm/src/tms570/hardware/tms570_pinmux.h index ae6936c505..fb2e228046 100644 --- a/arch/arm/src/tms570/hardware/tms570_pinmux.h +++ b/arch/arm/src/tms570/hardware/tms570_pinmux.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570_pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PINMUX_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PINMUX_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include @@ -47,11 +47,13 @@ # error "Unrecognized Hercules chip" #endif -/**************************************************************************************************** +/**************************************************************************** * Pulbic Type Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Each chip-specific pinmux header file defines initializers for a type like: */ +/* Each chip-specific pinmux header file defines initializers for a type + * like: + */ struct tms570_pinmux_s { diff --git a/arch/arm/src/tms570/hardware/tms570_rti.h b/arch/arm/src/tms570/hardware/tms570_rti.h index 55af575071..40df27600f 100644 --- a/arch/arm/src/tms570/hardware/tms570_rti.h +++ b/arch/arm/src/tms570/hardware/tms570_rti.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570_rti.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ /* References: * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, @@ -27,18 +27,18 @@ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_RTI_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_RTI_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tms570_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define TMS570_RTI_GCTRL_OFFSET 0x0000 /* RTI Global Control Register */ /* 0x0004 RTITBCTRL Reserved. Do NOT use. */ @@ -80,7 +80,7 @@ #define TMS570_RTI_COMP2CLR_OFFSET 0x00b8 /* RTI Compare 2 Clear Register */ #define TMS570_RTI_COMP3CLR_OFFSET 0x00bc /* RTI Compare 3 Clear Register */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define TMS570_RTI_GCTRL (TMS570_RTIDWWD_BASE+TMS570_RTI_GCTRL_OFFSET) #define TMS570_RTI_CAPCTRL (TMS570_RTIDWWD_BASE+TMS570_RTI_CAPCTRL_OFFSET) @@ -119,7 +119,7 @@ #define TMS570_RTI_COMP2CLR (TMS570_RTIDWWD_BASE+TMS570_RTI_COMP2CLR_OFFSET) #define TMS570_RTI_COMP3CLR (TMS570_RTIDWWD_BASE+TMS570_RTI_COMP3CLR_OFFSET) -/* Register Bit-Field Definitions *******************************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* RTI Global Control Register */ @@ -140,15 +140,21 @@ #define RTI_COMPCTRL_COMPSEL3 (1 << 12) /* Bit 12: Compare select 3 */ /* RTI Free Running Counter 0/1 Register (32-bit counter value) */ + /* RTI Up Counter 0/1 Register (32-bit counter value) */ + /* RTI Compare Up Counter 0/1 Register (32-bit counter value) */ + /* RTI Capture Free Running Counter 0/1 Register (32-bit counter value) */ + /* RTI Capture Up Counter 0/1 Register (32-bit counter value) */ + /* RTI Compare 0/1/2/3 Register Section (32-bit counter value) */ + /* RTI Update Compare 0/1/2/3 Register (32-bit counter value) */ -/* RTI Set Interrupt Enable Register, RTI Clear Interrupt Enable Register, and - * RTI Interrupt Flag Register +/* RTI Set Interrupt Enable Register, RTI Clear Interrupt Enable Register, + * and RTI Interrupt Flag Register */ #define RTI_INT0 (1 << 0) /* Bit 0: Compare interrupt 0 */ @@ -162,26 +168,37 @@ /* Digital Watchdog Control Register */ #define RTI_DWDCTRL_ + /* Digital Watchdog Preload Register */ #define RTI_DWDPRLD_ + /* Watchdog Status Register */ #define RTI_WDSTATUS_ + /* RTI Watchdog Key Register */ #define RTI_WDKEY_ + /* RTI Digital Watchdog Down Counter Register */ #define RTI_DWDCNTR_ + /* Digital Windowed Watchdog Reaction Control Register Section */ #define RTI_WWDRXNCTRL_ + /* Digital Windowed Watchdog Window Size Control Register */ #define RTI_WWDSIZECTRL_ + /* RTI Compare Interrupt Clear Enable Register */ #define RTI_INTCLRENABLE_ + /* RTI Compare 0 Clear Register */ #define RTI_COMP0CLR_ + /* RTI Compare 1 Clear Register */ #define RTI_COMP1CLR_ + /* RTI Compare 2 Clear Register */ #define RTI_COMP2CLR_ + /* RTI Compare 3 Clear Register */ #define RTI_COMP3CLR_ diff --git a/arch/arm/src/tms570/hardware/tms570_sci.h b/arch/arm/src/tms570/hardware/tms570_sci.h index 4e2d3af988..5117cc1442 100644 --- a/arch/arm/src/tms570/hardware/tms570_sci.h +++ b/arch/arm/src/tms570/hardware/tms570_sci.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570_sci.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ /* References: * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, @@ -27,18 +27,18 @@ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SCI_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SCI_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tms570_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define TMS570_SCI_GCR0_OFFSET 0x0000 /* SCI Global Control Register 0 */ #define TMS570_SCI_GCR1_OFFSET 0x0004 /* SCI Global Control Register 1 */ @@ -86,7 +86,7 @@ #define TMS570_SCI_PD_OFFSET TMS570_SCI_PIO7_OFFSET /* Pin Pullup/Pulldown Disable Register */ #define TMS570_SCI_PSL_OFFSET TMS570_SCI_PIO8_OFFSET /* Pin Pullup/Pulldown Selection Register */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define TMS570_SCI1_GCR0 (TMS570_SCI1_BASE+TMS570_SCI_GCR0_OFFSET) #define TMS570_SCI1_GCR1 (TMS570_SCI1_BASE+TMS570_SCI_GCR1_OFFSET) @@ -178,7 +178,7 @@ # define TMS570_SCI1_PSL TMS570_SCI_PIO8 /* Pin Pullup/Pulldown Selection Register */ #endif -/* Register Bit-Field Definitions *******************************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* SCI Global Control Register 0 */ @@ -214,7 +214,7 @@ /* SCI Set Interrupt Register, * SCI Clear Interrupt Register, - ( SCI Set Interrupt Level Register, and + * SCI Set Interrupt Level Register, and * SCI Clear Interrupt Level Register */ @@ -309,8 +309,10 @@ /* Receiver Emulation Data Buffer */ #define SCI_ED_ + /* Receiver Data Buffer */ #define SCI_RD_ + /* Transmit Data Buffer */ #define SCI_TD_ @@ -330,20 +332,28 @@ /* LIN Compare Register */ #define LIN_COMPARE_ + /* LIN Receive Buffer 0 Register */ #define LIN_RD0_ + /* LIN Receive Buffer 1 Register */ #define LIN_RD1_ + /* LIN Mask Register */ #define LIN_MASK_ + /* LIN Identification Register */ #define LIN_ID_ + /* LIN Transmit Buffer 0 */ #define LIN_TD0_ + /* LIN Transmit Buffer 1 */ #define LIN_TD1_ + /* Maximum Baud Rate Selection Register */ #define SCI_MBRS_ + /* Input/Output Error Enable Register */ #define SCI_IODFTCTRL_ diff --git a/arch/arm/src/tms570/hardware/tms570_sys.h b/arch/arm/src/tms570/hardware/tms570_sys.h index e8e47e5640..c46cc24f96 100644 --- a/arch/arm/src/tms570/hardware/tms570_sys.h +++ b/arch/arm/src/tms570/hardware/tms570_sys.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570_sys.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ /* References: * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, @@ -27,16 +27,16 @@ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tms570_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ /* The LPO trim value may be programmed into the TI OTP: */ @@ -45,7 +45,7 @@ # define TMS570_TITCM_LPOTRIM_SHIFT (16) /* Bits 16-31: LPO trim value */ # define TMS570_TITCM_LPOTRIM_MASK (0xffff << TMS570_TITCM_LPOTRIM_SHIFT) -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define TMS570_SYS_PC1_OFFSET 0x0000 /* SYS Pin Control Register 1 */ #define TMS570_SYS_PC2_OFFSET 0x0004 /* SYS Pin Control Register 2 */ @@ -102,7 +102,7 @@ #define TMS570_SYS_SSIVEC_OFFSET 0x00f4 /* Software Interrupt Vector Register */ #define TMS570_SYS_SSIF_OFFSET 0x00f8 /* System Software Interrupt Flag Register */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define TMS570_SYS_PC1 (TMS570_SYS_BASE+TMS570_SYS_PC1_OFFSET) #define TMS570_SYS_PC2 (TMS570_SYS_BASE+TMS570_SYS_PC2_OFFSET) @@ -159,7 +159,7 @@ #define TMS570_SYS_SSIVEC (TMS570_SYS_BASE+TMS570_SYS_SSIVEC_OFFSET) #define TMS570_SYS_SSIF (TMS570_SYS_BASE+TMS570_SYS_SSIF_OFFSET) -/* Register Bit-Field Definitions *******************************************************************/ +/* Register Bit-Field Definitions *******************************************/ #define SYS_GLBSTAT_OSC_ERR_MASK (0x01) #define SYS_GLBSTAT_OSC_ERR_CLR (0x0301) @@ -200,8 +200,8 @@ #define SYS_PC9_ECPCLKPS (1 << 0) /* Bit 0: ECLK pull up/pull down select */ -/* Clock Source Disable Register, Clock Source Disable Set Register, and Clock Source - * Disable Clear Register +/* Clock Source Disable Register, Clock Source Disable Set Register, + * and Clock Source Disable Clear Register */ #define SYS_CSDIS_CLKSR0OFF (1 << 0) /* Bit 0: Clock source 0 */ @@ -221,8 +221,8 @@ #define SYS_CSDIS_CLKSRC_PLL2 SYS_CSDIS_CLKSR6OFF /* PLL2 */ #define SYS_CSDIS_CLKSRC_EXTCLKIN2 SYS_CSDIS_CLKSR7OFF /* EXTCLKIN2 */ -/* Clock Domain Disable Register, Clock Domain Disable Set Register, and Clock Domain - * Disable Clear Register. +/* Clock Domain Disable Register, Clock Domain Disable Set Register, + * and Clock Domain Disable Clear Register. */ #define SYS_CDDIS_GCLKOFF (1 << 0) /* Bit 0: GCLK domain off */ @@ -464,6 +464,7 @@ #define SYS_PLLCTL1_MASKSLIP_MASK (3 << SYS_PLLCTL1_MASKSLIP_SHIFT) # define SYS_PLLCTL1_MASKSLIP_DISABLE (0 << SYS_PLLCTL1_MASKSLIP_SHIFT) /* All values but 2 disable */ # define SYS_PLLCTL1_MASKSLIP_ENABLE (1 << SYS_PLLCTL1_MASKSLIP_SHIFT) + #define SYS_PLLCTL1_ROS (1 << 31) /* Bit 31: Reset on PLL Slip */ /* PLL Control Register 2 */ @@ -488,22 +489,24 @@ /* Die Identification Register, Lower Word */ #define SYS_DIEIDL_ + /* Die Identification Register, Upper Word */ #define SYS_DIEIDH_ + /* LPO/Clock Monitor Control Register */ #define SYS_LPOMONCTL_LFTRIM_SHIFT (0) /* Bits 0-4: Low frequency oscillator trim value */ #define SYS_LPOMONCTL_LFTRIM_MASK (31 << SYS_LPOMONCTL_LFTRIM_SHIFT) -# define SYS_LPOMONCTL_20p67 (0 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 20.67% */ -# define SYS_LPOMONCTL_25p76 (1 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 25.76% */ -# define SYS_LPOMONCTL_30p84 (2 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 30.84% */ -# define SYS_LPOMONCTL_35p90 (3 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 35.90% */ -# define SYS_LPOMONCTL_40p93 (4 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 40.93% */ -# define SYS_LPOMONCTL_45p95 (5 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 45.95% */ -# define SYS_LPOMONCTL_50p97 (6 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 50.97% */ -# define SYS_LPOMONCTL_55p91 (7 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 55.91% */ -# define SYS_LPOMONCTL_60p86 (8 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 60.86% */ -# define SYS_LPOMONCTL_65p78 (9 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 65.78% */ +# define SYS_LPOMONCTL_20p67 (0 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 20.67% */ +# define SYS_LPOMONCTL_25p76 (1 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 25.76% */ +# define SYS_LPOMONCTL_30p84 (2 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 30.84% */ +# define SYS_LPOMONCTL_35p90 (3 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 35.90% */ +# define SYS_LPOMONCTL_40p93 (4 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 40.93% */ +# define SYS_LPOMONCTL_45p95 (5 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 45.95% */ +# define SYS_LPOMONCTL_50p97 (6 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 50.97% */ +# define SYS_LPOMONCTL_55p91 (7 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 55.91% */ +# define SYS_LPOMONCTL_60p86 (8 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 60.86% */ +# define SYS_LPOMONCTL_65p78 (9 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 65.78% */ # define SYS_LPOMONCTL_70p75 (10 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 70.75% */ # define SYS_LPOMONCTL_75p63 (11 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 75.63% */ # define SYS_LPOMONCTL_80p61 (12 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 80.61% */ @@ -526,18 +529,19 @@ # define SYS_LPOMONCTL_161p38 (29 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 161.38% */ # define SYS_LPOMONCTL_165p90 (30 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 165.90% */ # define SYS_LPOMONCTL_170p42 (31 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 170.42% */ + #define SYS_LPOMONCTL_HFTRIM_SHIFT (8) /* Bits 8-12: High frequency oscillator trim value */ #define SYS_LPOMONCTL_HFTRIM_MASK (31 << SYS_LPOMONCTL_HFTRIM_SHIFT) -# define SYS_LPOMONCTL_HFTRIM_29p52 (0 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 29.52% */ -# define SYS_LPOMONCTL_HFTRIM_34p24 (1 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 34.24% */ -# define SYS_LPOMONCTL_HFTRIM_38p85 (2 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 38.85% */ -# define SYS_LPOMONCTL_HFTRIM_43p45 (3 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 43.45% */ -# define SYS_LPOMONCTL_HFTRIM_47p99 (4 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 47.99% */ -# define SYS_LPOMONCTL_HFTRIM_52p55 (5 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 52.55% */ -# define SYS_LPOMONCTL_HFTRIM_57p02 (6 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 57.02% */ -# define SYS_LPOMONCTL_HFTRIM_61p46 (7 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 61.46% */ -# define SYS_LPOMONCTL_HFTRIM_65p92 (8 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 65.92% */ -# define SYS_LPOMONCTL_HFTRIM_70p17 (9 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 70.17% */ +# define SYS_LPOMONCTL_HFTRIM_29p52 (0 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 29.52% */ +# define SYS_LPOMONCTL_HFTRIM_34p24 (1 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 34.24% */ +# define SYS_LPOMONCTL_HFTRIM_38p85 (2 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 38.85% */ +# define SYS_LPOMONCTL_HFTRIM_43p45 (3 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 43.45% */ +# define SYS_LPOMONCTL_HFTRIM_47p99 (4 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 47.99% */ +# define SYS_LPOMONCTL_HFTRIM_52p55 (5 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 52.55% */ +# define SYS_LPOMONCTL_HFTRIM_57p02 (6 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 57.02% */ +# define SYS_LPOMONCTL_HFTRIM_61p46 (7 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 61.46% */ +# define SYS_LPOMONCTL_HFTRIM_65p92 (8 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 65.92% */ +# define SYS_LPOMONCTL_HFTRIM_70p17 (9 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 70.17% */ # define SYS_LPOMONCTL_HFTRIM_74p55 (10 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 74.55% */ # define SYS_LPOMONCTL_HFTRIM_78p92 (11 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 78.92% */ # define SYS_LPOMONCTL_HFTRIM_83p17 (12 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 83.17% */ @@ -560,33 +564,46 @@ # define SYS_LPOMONCTL_HFTRIM_151p80 (29 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 151.80% */ # define SYS_LPOMONCTL_HFTRIM_155p50 (30 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 155.50% */ # define SYS_LPOMONCTL_HFTRIM_159p35 (31 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 159.35% */ + #define SYS_LPOMONCTL_OSCFRQCONFIGCNT (1 << 16) /* Bit 16: Configures the counter based on OSC frequency. */ #define SYS_LPOMONCTL_BIASENABLE (1 << 24) /* Bit 24: Bias enable. */ /* Clock Test Register */ #define SYS_CLKTEST_ + /* DFT Control Register */ #define SYS_DFTCTRLREG_ + /* DFT Control Register 2 */ #define SYS_DFTCTRLREG2_ + /* General Purpose Register */ #define SYS_GPREG1_ + /* Imprecise Fault Status Register */ #define SYS_IMPFASTS_ + /* Imprecise Fault Write Address Register */ #define SYS_IMPFTADD_ + /* System Software Interrupt Request 1 Register */ #define SYS_SSIR1_ + /* System Software Interrupt Request 2 Register */ #define SYS_SSIR2_ + /* System Software Interrupt Request 3 Register */ #define SYS_SSIR3_ + /* System Software Interrupt Request 4 Register */ #define SYS_SSIR4_ + /* RAM Control Register */ #define SYS_RAMGCR_ + /* Bus Matrix Module Control Register 1 */ #define SYS_BMMCR1_ + /* CPU Reset Control Register */ #define SYS_CPURSTCR_ @@ -612,13 +629,16 @@ # define SYS_ECPCNTL_ECPINSEL_LOW (0 << SYS_ECPCNTL_ECPINSEL_SHIFT) /* Tied Low */ # define SYS_ECPCNTL_ECPINSEL_HCLK (1 << SYS_ECPCNTL_ECPINSEL_SHIFT) /* HCLK */ # define SYS_ECPCNTL_ECPINSEL_EXTCLK (2 << SYS_ECPCNTL_ECPINSEL_SHIFT) /* External clock */ + #define SYS_ECPCNTL_ECPCOS (1 << 23) /* Bit 23: ECP continue on suspend */ #define SYS_ECPCNTL_ECPSSEL (1 << 24) /* Bit 24: Select VCLK os OSCIN as for ECLK */ /* DEV Parity Control Register 1 */ #define SYS_DEVCR1_ + /* System Exception Control Register */ #define SYS_ECR_ + /* System Exception Status Register */ #define SYS_ESR_MPMODE (1 << 0) /* Bit 0: Current memory protection unit (MPU) mode */ @@ -634,12 +654,16 @@ /* System Test Abort Status Register */ #define SYS_TASR_ + /* Global Status Register */ #define SYS_GLBSTAT_ + /* Device Identification Register */ #define SYS_DEVID_ + /* Software Interrupt Vector Register */ #define SYS_SSIVEC_ + /* System Software Interrupt Flag Register */ #define SYS_SSIF_ diff --git a/arch/arm/src/tms570/hardware/tms570_sys2.h b/arch/arm/src/tms570/hardware/tms570_sys2.h index ef8271952c..d6297e3afe 100644 --- a/arch/arm/src/tms570/hardware/tms570_sys2.h +++ b/arch/arm/src/tms570/hardware/tms570_sys2.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570_sys2.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ /* References: * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, @@ -27,18 +27,18 @@ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS2_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS2_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tms570_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define TMS570_SYS2_STCCLKDIV_OFFSET 0x0008 /* CPU Logic BIST Clock Divider */ #define TMS570_SYS2_CLKSLIP_OFFSET 0x0070 /* Clock Slip Register */ @@ -50,7 +50,7 @@ #define TMS570_SYS2_CLK2CNTRL_OFFSET 0x003c #define TMS570_SYS2_VCLKACON1_OFFSET 0x0040 -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define TMS570_SYS2_STCCLKDIV (TMS570_SYS2_BASE+TMS570_SYS2_STCCLKDIV_OFFSET) #define TMS570_SYS2_CLKSLIP (TMS570_SYS2_BASE+TMS570_SYS2_CLKSLIP_OFFSET) @@ -62,21 +62,34 @@ #define TMS570_SYS2_CLK2CNTRL (TMS570_SYS2_BASE+TMS570_SYS2_CLK2CNTRL_OFFSET) #define TMS570_SYS2_VCLKACON1 (TMS570_SYS2_BASE+TMS570_SYS2_VCLKACON1_OFFSET) -/* Register Bit-Field Definitions *******************************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* CPU Logic BIST Clock Divider */ + #define SYS2_STCCLKDIV_ + /* Clock Slip Register */ + #define SYS2_CLKSLIP_ + /* EFUSE Controller Control Register */ + #define SYS2_EFC_CTLREG_ + /* Die Identification Register Lower Word */ + #define SYS2_DIEDL_REG0_ + /* Die Identification Register Upper Word */ + #define SYS2_DIEDH_REG1_ + /* Die Identification Register Lower Word */ + #define SYS2_DIEDL_REG2_ + /* Die Identification Register Upper Word */ + #define SYS2_DIEDH_REG3_ #if defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT) diff --git a/arch/arm/src/tms570/hardware/tms570_vim.h b/arch/arm/src/tms570/hardware/tms570_vim.h index 813dc4a038..0ba05b2ce7 100644 --- a/arch/arm/src/tms570/hardware/tms570_vim.h +++ b/arch/arm/src/tms570/hardware/tms570_vim.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570_vim.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ /* References: * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, @@ -27,21 +27,21 @@ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_VIM_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_VIM_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tms570_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ #define VIM_REGNDX(ch) ((ch) >> 5) #define VIM_REGBIT(ch) ((ch) & 31) -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ /* Register Offsets relative to the VIM Parity Frame */ @@ -87,7 +87,7 @@ #define TMS570_VIM_CHANCTRL_INDEX(n) ((n) >> 2) #define TMS570_VIM_CHANCTRL_OFFSET(n) (0x0080 << (TMS570_VIM_CHANCTRL_INDEX(n) << 2)) -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ /* VIM Parity Frame Registers */ @@ -132,14 +132,17 @@ #define TMS570_VIM_CHANCTRL(n) (TMS570_VIM_BASE+TMS570_VIM_CHANCTRL_OFFSET(n)) -/* Register Bit-Field Definitions *******************************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* Interrupt Vector Table Parity Flag Register */ #define VIM_PARFLG_ + /* Interrupt Vector Table Parity Control Register */ #define VIM_PARCTL_ + /* Address Parity Error Register */ #define VIM_ADDERR_ + /* Fall-Back Address Parity Error Register */ #define VIM_FBPARERR_ @@ -153,44 +156,64 @@ /* FIQ/IRQ Program Control Register 0 */ #define VIM_FIRQPR0_ + /* FIQ/IRQ Program Control Register 1 */ #define VIM_FIRQPR1_ + /* FIQ/IRQ Program Control Register 2 */ #define VIM_FIRQPR2_ + /* Pending Interrupt Read Location Register 0 */ #define VIM_INTREQ0_ + /* Pending Interrupt Read Location Register 1 */ #define VIM_INTREQ1_ + /* Pending Interrupt Read Location Register 2 */ #define VIM_INTREQ2_ + /* Interrupt Enable Set Register 0 */ #define VIM_REQENASET0_ + /* Interrupt Enable Set Register 1 */ #define VIM_REQENASET1_ + /* Interrupt Enable Set Register 2 */ #define VIM_REQENASET2_ + /* Interrupt Enable Clear Register 0 */ #define VIM_REQENACLR0_ + /* Interrupt Enable Clear Register 1 */ #define VIM_REQENACLR1_ + /* Interrupt Enable Clear Register 2 */ #define VIM_REQENACLR2_ + /* Wake-up Enable Set Register 0 */ #define VIM_WAKEENASET0_ + /* Wake-up Enable Set Register 1 */ #define VIM_WAKEENASET1_ + /* Wake-up Enable Set Register 2 */ #define VIM_WAKEENASET2_ + /* Wake-up Enable Clear Register 0 */ #define VIM_WAKEENACLR0_ + /* Wake-up Enable Clear Register 1 */ #define VIM_WAKEENACLR1_ + /* Wake-up Enable Clear Register 2 */ #define VIM_WAKEENACLR2_ + /* IRQ Interrupt Vector Register */ #define VIM_IRQVECREG_ + /* FIQ Interrupt Vector Register */ #define VIM_FIQVECREG_ + /* Capture Event Register */ #define VIM_CAPEVT_ diff --git a/arch/arm/src/tms570/hardware/tms570ls04x03x_memorymap.h b/arch/arm/src/tms570/hardware/tms570ls04x03x_memorymap.h index d02b4f3415..de0ab1be7f 100644 --- a/arch/arm/src/tms570/hardware/tms570ls04x03x_memorymap.h +++ b/arch/arm/src/tms570/hardware/tms570ls04x03x_memorymap.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570ls04x03x_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_MEMORYMAP_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_MEMORYMAP_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ /* Memory Map Overview */ diff --git a/arch/arm/src/tms570/hardware/tms570ls04x03x_pinmux.h b/arch/arm/src/tms570/hardware/tms570ls04x03x_pinmux.h index da53821669..76e7541c8c 100644 --- a/arch/arm/src/tms570/hardware/tms570ls04x03x_pinmux.h +++ b/arch/arm/src/tms570/hardware/tms570ls04x03x_pinmux.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tms570/hardware/tms570ls04x03x_pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -17,7 +17,7 @@ * under the License. * * - ****************************************************************************************************/ + ****************************************************************************/ /* References: * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, @@ -28,16 +28,16 @@ #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_PINMUX_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_PINMUX_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tms570_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ /* DEFAULT SELECTION ALTERNATE SELECTION ALTERNATE SELECTION BIT * FUNCTION BIT FUNCTION 1 BIT FUNCTION 2 BIT diff --git a/arch/arm/src/tms570/tms570_boot.h b/arch/arm/src/tms570/tms570_boot.h index 3dd90a6e23..96cd3f03e3 100644 --- a/arch/arm/src/tms570/tms570_boot.h +++ b/arch/arm/src/tms570/tms570_boot.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tms570/tms570_boot.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TMS570_TMS570_BOOT_H #define __ARCH_ARM_SRC_TMS570_TMS570_BOOT_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -46,48 +46,51 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: tms570_lowsetup * * Description: - * Called at the very beginning of _start. Performs low level initialization - * including setup of the console SCI. This SCI done early so that the serial - * console is available for debugging very early in the boot sequence. + * Called at the very beginning of _start. + * Performs low level initialization including setup of the console SCI. + * This SCI done early so that the serial console is available for + * debugging very early in the boot sequence. * - ************************************************************************************/ + ****************************************************************************/ void tms570_lowsetup(void); -/************************************************************************************ +/**************************************************************************** * Name: tms570_boardinitialize * * Description: - * All TMS570 architectures must provide the following entry point. This function - * is called near the beginning of _start. This function is called after clocking - * has been configured but before caches have been enabled and before any devices - * have been initialized. .data/.bss memory may or may not have been initialized + * All TMS570 architectures must provide the following entry point. This + * function is called near the beginning of _start. This function is + * called after clocking has been configured but before caches have been + * enabled and before any devices have been initialized. + * .data/.bss memory may or may not have been initialized * (see the "special precautions" below). * * This function must perform low level initialization including * * - Initialization of board-specific memory resources (e.g., SDRAM) * - Configuration of board specific resources (GIOs, LEDs, etc). - * - Setup of the console SCI. This SCI done early so that the serial console - * is available for debugging very early in the boot sequence. + * - Setup of the console SCI. This SCI done early so that the serial + * console is available for debugging very early in the boot sequence. * - * Special precautions must be taken if .data/.bss lie in SRAM. in that case, - * the boot logic cannot initialize .data or .bss. The function must then: + * Special precautions must be taken if .data/.bss lie in SRAM. in that + * case, the boot logic cannot initialize .data or .bss. + * The function must then: * - * - Take precautions to assume that logic does not access any global data that - * might lie in SDRAM. + * - Take precautions to assume that logic does not access any global data + * that might lie in SDRAM. * - Call the function arm_data_initialize() as soon as SDRAM has been * properly configured for use. * - ************************************************************************************/ + ****************************************************************************/ void tms570_board_initialize(void); diff --git a/arch/arm/src/tms570/tms570_clockconfig.h b/arch/arm/src/tms570/tms570_clockconfig.h index 481211fcd3..95c4b74a4d 100644 --- a/arch/arm/src/tms570/tms570_clockconfig.h +++ b/arch/arm/src/tms570/tms570_clockconfig.h @@ -50,9 +50,10 @@ extern "C" * Name: tms570_clockconfig * * Description: - * Called to initialize TMS570 clocking. This does whatever setup is needed to - * put the SoC in a usable state. This includes, but is not limited to, the - * initialization of clocking using the settings in the board.h header file. + * Called to initialize TMS570 clocking. + * This does whatever setup is needed to put the SoC in a usable state. + * This includes, but is not limited to, theinitialization of clocking + * using the settings in the board.h header file. * ****************************************************************************/ diff --git a/arch/arm/src/tms570/tms570_gio.c b/arch/arm/src/tms570/tms570_gio.c index 6ef6f5f27f..a1b0599700 100644 --- a/arch/arm/src/tms570/tms570_gio.c +++ b/arch/arm/src/tms570/tms570_gio.c @@ -89,7 +89,9 @@ int tms570_gio_initialize(void) putreg32(GIO_GCR0_RESET, TMS570_GIO_GCR0); - /* Disable all pin interrupts on the pin. Make sure they are all level 0. */ + /* Disable all pin interrupts on the pin. + * Make sure they are all level 0. + */ putreg32(0xffffffff, TMS570_GIO_ENACLR); putreg32(0xffffffff, TMS570_GIO_LVLCLR); @@ -129,6 +131,7 @@ int tms570_configgio(gio_pinset_t cfgset) putreg32(GIO_LVLCLR_PORT_PIN(port, pin), TMS570_GIO_LVLCLR); /* Setup settings common to both input and output pins */ + /* Enable/disable the pull-up/down as requested */ switch (cfgset & GIO_CFG_MASK) @@ -266,13 +269,14 @@ bool tms570_gioread(gio_pinset_t pinset) return (regval & pinmask) != 0; } -/************************************************************************************ +/**************************************************************************** * Function: tms570_dumpgio * * Description: - * Dump all GIO registers associated with the base address of the provided pinset. + * Dump all GIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int tms570_dumpgio(uint32_t pinset, const char *msg) @@ -305,10 +309,13 @@ int tms570_dumpgio(uint32_t pinset, const char *msg) /* Port specific registers */ _info(" DIR: %08x DIN: %08x DOUT: %08x PDR: %08x\n", - getreg32(base + TMS570_GIO_DIR_OFFSET), getreg32(base + TMS570_GIO_DIN_OFFSET), - getreg32(base + TMS570_GIO_DOUT_OFFSET), getreg32(base + TMS570_GIO_PDR_OFFSET)); + getreg32(base + TMS570_GIO_DIR_OFFSET), + getreg32(base + TMS570_GIO_DIN_OFFSET), + getreg32(base + TMS570_GIO_DOUT_OFFSET), + getreg32(base + TMS570_GIO_PDR_OFFSET)); _info(" PULDIS: %08x PSL: %08x\n", - getreg32(base + TMS570_GIO_PULDIS_OFFSET), getreg32(base + TMS570_GIO_PSL_OFFSET)); + getreg32(base + TMS570_GIO_PULDIS_OFFSET), + getreg32(base + TMS570_GIO_PSL_OFFSET)); leave_critical_section(flags); return OK; diff --git a/arch/arm/src/tms570/tms570_gio.h b/arch/arm/src/tms570/tms570_gio.h index 0b3bcfbcdd..c25d584ddc 100644 --- a/arch/arm/src/tms570/tms570_gio.h +++ b/arch/arm/src/tms570/tms570_gio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tms570/tms570_gio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TMS570_TMS570_GIO_H #define __ARCH_ARM_SRC_TMS570_TMS570_GIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -33,11 +33,11 @@ #include "hardware/tms570_gio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Bit-encoded input to tms570_configgio() ********************************************/ +/* Bit-encoded input to tms570_configgio() **********************************/ /* 32-bit Encoding: * @@ -85,7 +85,8 @@ #define GIO_OPENDRAIN (1 << 9) /* Bit 9: Open drain mode */ -/* If the pin is an GIO output, then this identifies the initial output value: +/* If the pin is an GIO output, then this identifies the initial output + * value: * * .... .... .... .... .... ...V .... .... */ @@ -125,9 +126,9 @@ # define GIO_PIN6 (6 << GIO_PIN_SHIFT) # define GIO_PIN7 (7 << GIO_PIN_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -135,9 +136,9 @@ typedef uint16_t gio_pinset_t; -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -148,9 +149,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: tms570_gio_base @@ -205,9 +206,9 @@ static inline int tms570_gio_pinmask(gio_pinset_t cfgset) return 1 << ((cfgset & GIO_PIN_MASK) >> GIO_PIN_SHIFT); } -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: tms570_gio_initialize @@ -219,13 +220,14 @@ static inline int tms570_gio_pinmask(gio_pinset_t cfgset) int tms570_gio_initialize(void); -/************************************************************************************ +/**************************************************************************** * Name: tms570_gioirq_initialize * * Description: - * Initialize logic to support a second level of interrupt decoding for GIO pins. + * Initialize logic to support a second level of interrupt decoding for GIO + * pins. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_TMS570_GIO_IRQ void tms570_gioirq_initialize(void); @@ -233,43 +235,43 @@ void tms570_gioirq_initialize(void); # define tms570_gioirq_initialize() #endif -/************************************************************************************ +/**************************************************************************** * Name: tms570_configgio * * Description: * Configure a GIO pin based on bit-encoded description of the pin. * - ************************************************************************************/ + ****************************************************************************/ int tms570_configgio(gio_pinset_t cfgset); -/************************************************************************************ +/**************************************************************************** * Name: tms570_giowrite * * Description: * Write one or zero to the selected GIO pin * - ************************************************************************************/ + ****************************************************************************/ void tms570_giowrite(gio_pinset_t pinset, bool value); -/************************************************************************************ +/**************************************************************************** * Name: tms570_gioread * * Description: * Read one or zero from the selected GIO pin * - ************************************************************************************/ + ****************************************************************************/ bool tms570_gioread(gio_pinset_t pinset); -/************************************************************************************ +/**************************************************************************** * Name: tms570_gioirq * * Description: * Configure an interrupt for the specified GIO pin. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_TMS570_GIO_IRQ void tms570_gioirq(gio_pinset_t pinset); @@ -277,13 +279,13 @@ void tms570_gioirq(gio_pinset_t pinset); # define tms570_gioirq(pinset) #endif -/************************************************************************************ +/**************************************************************************** * Name: tms570_gioirqenable * * Description: * Enable the interrupt for specified GIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_TMS570_GIO_IRQ void tms570_gioirqenable(int irq); @@ -291,13 +293,13 @@ void tms570_gioirqenable(int irq); # define tms570_gioirqenable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Name: tms570_gioirqdisable * * Description: * Disable the interrupt for specified GIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_TMS570_GIO_IRQ void tms570_gioirqdisable(int irq); @@ -305,13 +307,14 @@ void tms570_gioirqdisable(int irq); # define tms570_gioirqdisable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Function: tms570_dumpgio * * Description: - * Dump all GIO registers associated with the base address of the provided pinset. + * Dump all GIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int tms570_dumpgio(uint32_t pinset, const char *msg); diff --git a/arch/arm/src/tms570/tms570_gioirq.c b/arch/arm/src/tms570/tms570_gioirq.c index 9398caddd9..4b86fbdee9 100644 --- a/arch/arm/src/tms570/tms570_gioirq.c +++ b/arch/arm/src/tms570/tms570_gioirq.c @@ -91,7 +91,9 @@ static int tms3570_gio_interrupt(int irq, void *context, FAR void *arg) void tms570_gioirq_initialize(void) { - /* Disable all pin interrupts on the pin. Make sure they are all level 0. */ + /* Disable all pin interrupts on the pin. + * Make sure they are all level 0. + */ putreg32(0xffffffff, TMS570_GIO_ENACLR); putreg32(0xffffffff, TMS570_GIO_LVLCLR); @@ -102,13 +104,13 @@ void tms570_gioirq_initialize(void) up_enable_irq(TMS570_REQ_GIO_0); } -/************************************************************************************ +/**************************************************************************** * Name: tms570_gioirq * * Description: * Configure an interrupt for the specified GIO pin. * - ************************************************************************************/ + ****************************************************************************/ void tms570_gioirq(gio_pinset_t pinset) { @@ -117,13 +119,15 @@ void tms570_gioirq(gio_pinset_t pinset) irqstate_t flags; uint32_t regval; - /* Start with the pin interrupts disabled. Make sure that level 0 is selected. */ + /* Start with the pin interrupts disabled. + * Make sure that level 0 is selected. + */ putreg32(GIO_ENACLR_PORT_PIN(port, pin), TMS570_GIO_ENACLR); putreg32(GIO_LVLCLR_PORT_PIN(port, pin), TMS570_GIO_LVLCLR); - /* Make sure that the pin is configured as an input and that interrupts can e - * supported on this port. + /* Make sure that the pin is configured as an input and that interrupts can + * e supported on this port. */ if ((pinset & GIO_MODE_MASK) == GIO_INPUT && port < TMS570_NIRQPORTS) @@ -182,13 +186,13 @@ void tms570_gioirq(gio_pinset_t pinset) } } -/************************************************************************************ +/**************************************************************************** * Name: tms570_gioirqenable * * Description: * Enable the interrupt for specified GIO IRQ * - ************************************************************************************/ + ****************************************************************************/ void tms570_gioirqenable(int irq) { @@ -210,13 +214,13 @@ void tms570_gioirqenable(int irq) } } -/************************************************************************************ +/**************************************************************************** * Name: tms570_gioirqdisable * * Description: * Disable the interrupt for specified GIO IRQ * - ************************************************************************************/ + ****************************************************************************/ void tms570_gioirqdisable(int irq) { diff --git a/arch/arm/src/tms570/tms570_lowputc.h b/arch/arm/src/tms570/tms570_lowputc.h index e5e7e5cc8b..292b011fbf 100644 --- a/arch/arm/src/tms570/tms570_lowputc.h +++ b/arch/arm/src/tms570/tms570_lowputc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tms570/tms570_lowputc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TMS570_TMS570_LOWPUTC_H #define __ARCH_ARM_SRC_TMS570_TMS570_LOWPUTC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -35,13 +35,13 @@ #include "arm_internal.h" #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* This structure describes the configuration of an SCI UART */ @@ -53,15 +53,15 @@ struct sci_config_s bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ }; -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -72,31 +72,33 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: tms570_lowsetup * * Description: - * Called at the very beginning of _start. Performs low level initialization - * including setup of the console SCI. This SCI done early so that the serial - * console is available for debugging very early in the boot sequence. + * Called at the very beginning of _start. + * Performs low level initialization including setup of the console SCI. + * This SCI done early so that the serial console is available for + * debugging very early in the boot sequence. * - ************************************************************************************/ + ****************************************************************************/ void tms570_lowsetup(void); -/************************************************************************************ +/**************************************************************************** * Name: tms570_sci_configure * * Description: * Configure an SCI for non-interrupt driven operation * - ************************************************************************************/ + ****************************************************************************/ -int tms570_sci_configure(uint32_t base, FAR const struct sci_config_s *config); +int tms570_sci_configure(uint32_t base, + FAR const struct sci_config_s *config); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/tms570/tms570_timerisr.c b/arch/arm/src/tms570/tms570_timerisr.c index b6fb1f90f3..8ecfe2bfd9 100644 --- a/arch/arm/src/tms570/tms570_timerisr.c +++ b/arch/arm/src/tms570/tms570_timerisr.c @@ -38,6 +38,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* The input clock to the RTI is the RTICLK. The RTI source is always VCLK * which may be divided down by 2. The correct RTICLK frequency must be * provided by board.h file as BOARD_RTICLK_FREQUENCY.