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arch: arm: tms570: fix nxstyle errors

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Fix nxstyle errors to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea 2021-03-24 09:38:16 +01:00 committed by Xiang Xiao
parent 0308842cf2
commit d83628af1d
23 changed files with 434 additions and 264 deletions
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12
arch/arm/src/tms570/chip.h
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@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/arm/src/tms570/chip.h * arch/arm/src/tms570/chip.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_TMS570_CHIP_H #ifndef __ARCH_ARM_SRC_TMS570_CHIP_H
#define __ARCH_ARM_SRC_TMS570_CHIP_H #define __ARCH_ARM_SRC_TMS570_CHIP_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <arch/tms570/chip.h> #include <arch/tms570/chip.h>
#include "hardware/tms570_memorymap.h" #include "hardware/tms570_memorymap.h"
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Cache line sizes (in bytes) */ /* Cache line sizes (in bytes) */

22
arch/arm/src/tms570/hardware/tms570_esm.h
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@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570_esm.h * arch/arm/src/tms570/hardware/tms570_esm.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
****************************************************************************************************/ ****************************************************************************/
/* References: /* References:
* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller,
@ -27,22 +27,22 @@
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_ESM_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_ESM_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_ESM_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_ESM_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "hardware/tms570_memorymap.h" #include "hardware/tms570_memorymap.h"
/**************************************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************************************/ ****************************************************************************/
#define ESM_GROUP1 0 #define ESM_GROUP1 0
#define ESM_GROUP2 1 #define ESM_GROUP2 1
#define ESM_GROUP3 2 #define ESM_GROUP3 2
/* Register Offsets *********************************************************************************/ /* Register Offsets *********************************************************/
#define TMS570_ESM_EEPAPR1_OFFSET 0x0000 /* ESM Enable ERROR Pin Action/Response Register 1 */ #define TMS570_ESM_EEPAPR1_OFFSET 0x0000 /* ESM Enable ERROR Pin Action/Response Register 1 */
#define TMS570_ESM_DEPAPR1_OFFSET 0x0004 /* ESM Disable ERROR Pin Action/Response Register 1 */ #define TMS570_ESM_DEPAPR1_OFFSET 0x0004 /* ESM Disable ERROR Pin Action/Response Register 1 */
@ -50,7 +50,9 @@
#define TMS570_ESM_IECR1_OFFSET 0x000c /* ESM Interrupt Enable Clear/Status Register 1 */ #define TMS570_ESM_IECR1_OFFSET 0x000c /* ESM Interrupt Enable Clear/Status Register 1 */
#define TMS570_ESM_ILSR1_OFFSET 0x0010 /* Interrupt Level Set/Status Register 1 */ #define TMS570_ESM_ILSR1_OFFSET 0x0010 /* Interrupt Level Set/Status Register 1 */
#define TMS570_ESM_ILCR1_OFFSET 0x0014 /* Interrupt Level Clear/Status Register 1 */ #define TMS570_ESM_ILCR1_OFFSET 0x0014 /* Interrupt Level Clear/Status Register 1 */
#define TMS570_ESM_SRA_OFFSET(n) (0x0018 + ((n) << 2)) /* n=0, 1, 2 */ #define TMS570_ESM_SRA_OFFSET(n) (0x0018 + ((n) << 2)) /* n=0, 1, 2 */
# define TMS570_ESM_SR1_OFFSET 0x0018 /* ESM Status Register for group 1 */ # define TMS570_ESM_SR1_OFFSET 0x0018 /* ESM Status Register for group 1 */
# define TMS570_ESM_SR2_OFFSET 0x001c /* ESM Status Register for group 2 */ # define TMS570_ESM_SR2_OFFSET 0x001c /* ESM Status Register for group 2 */
# define TMS570_ESM_SR3_OFFSET 0x0020 /* ESM Status Register for group 3 */ # define TMS570_ESM_SR3_OFFSET 0x0020 /* ESM Status Register for group 3 */
@ -68,13 +70,15 @@
#define TMS570_ESM_ILSR4_OFFSET 0x0050 /* Interrupt Level Set/Status Register 4 */ #define TMS570_ESM_ILSR4_OFFSET 0x0050 /* Interrupt Level Set/Status Register 4 */
#define TMS570_ESM_ILCR4_OFFSET 0x0054 /* Interrupt Level Clear/Status Register 4 */ #define TMS570_ESM_ILCR4_OFFSET 0x0054 /* Interrupt Level Clear/Status Register 4 */
#define TMS570_ESM_SR4_OFFSET 0x0058 /* ESM Status Register 4 */ #define TMS570_ESM_SR4_OFFSET 0x0058 /* ESM Status Register 4 */
#define TMS570_ESM_SRB_OFFSET(n) (0x0058 + (((n)-4) << 2)) /* n=4, 5, 6 */ #define TMS570_ESM_SRB_OFFSET(n) (0x0058 + (((n)-4) << 2)) /* n=4, 5, 6 */
# define TMS570_ESM_SR4_OFFSET 0x0058 /* ESM Status Register for group 4 */ # define TMS570_ESM_SR4_OFFSET 0x0058 /* ESM Status Register for group 4 */
# define TMS570_ESM_SR5_OFFSET 0x005c /* ESM Status Register for group 5 */ # define TMS570_ESM_SR5_OFFSET 0x005c /* ESM Status Register for group 5 */
# define TMS570_ESM_SR6_OFFSET 0x0060 /* ESM Status Register for group 6 */ # define TMS570_ESM_SR6_OFFSET 0x0060 /* ESM Status Register for group 6 */
#define TMS570_ESM_SSR5_OFFSET 0x0064 /* ESM Status Shadow Register 5 */ #define TMS570_ESM_SSR5_OFFSET 0x0064 /* ESM Status Shadow Register 5 */
/* Register Addresses *******************************************************************************/ /* Register Addresses *******************************************************/
#define TMS570_ESM_EEPAPR1 (TMS570_ESM_BASE+TMS570_ESM_EEPAPR1_OFFSET) #define TMS570_ESM_EEPAPR1 (TMS570_ESM_BASE+TMS570_ESM_EEPAPR1_OFFSET)
#define TMS570_ESM_DEPAPR1 (TMS570_ESM_BASE+TMS570_ESM_DEPAPR1_OFFSET) #define TMS570_ESM_DEPAPR1 (TMS570_ESM_BASE+TMS570_ESM_DEPAPR1_OFFSET)
@ -106,7 +110,7 @@
# define TMS570_ESM_SR6 (TMS570_ESM_BASE+TMS570_ESM_SR6_OFFSET) # define TMS570_ESM_SR6 (TMS570_ESM_BASE+TMS570_ESM_SR6_OFFSET)
#define TMS570_ESM_SSR5 (TMS570_ESM_BASE+TMS570_ESM_SSR5_OFFSET) #define TMS570_ESM_SSR5 (TMS570_ESM_BASE+TMS570_ESM_SSR5_OFFSET)
/* Register Bit-Field Definitions *******************************************************************/ /* Register Bit-Field Definitions *******************************************/
/* ESM Enable ERROR Pin Action/Response Register 1 */ /* ESM Enable ERROR Pin Action/Response Register 1 */

52
arch/arm/src/tms570/hardware/tms570_flash.h
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@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570_flash.h * arch/arm/src/tms570/hardware/tms570_flash.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
****************************************************************************************************/ ****************************************************************************/
/* References: /* References:
* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller,
@ -27,18 +27,18 @@
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_FLASH_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_FLASH_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_FLASH_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_FLASH_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "hardware/tms570_memorymap.h" #include "hardware/tms570_memorymap.h"
/**************************************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************************************/ ****************************************************************************/
/* Register Offsets *********************************************************************************/ /* Register Offsets *********************************************************/
#define TMS570_FLASH_FRDCNTL_OFFSET 0x000 /* Flash Option Control Register */ #define TMS570_FLASH_FRDCNTL_OFFSET 0x000 /* Flash Option Control Register */
#define TMS570_FLASH_FEDACTRL1_OFFSET 0x008 /* Flash Error Detection and Correction Control Register 1 */ #define TMS570_FLASH_FEDACTRL1_OFFSET 0x008 /* Flash Error Detection and Correction Control Register 1 */
@ -83,7 +83,7 @@
#define TMS570_FLASH_EEUNCERRADD_OFFSET 0x320 /* EEPROM Emulation Un-Correctable Error Address Register */ #define TMS570_FLASH_EEUNCERRADD_OFFSET 0x320 /* EEPROM Emulation Un-Correctable Error Address Register */
#define TMS570_FLASH_FCFGBANK_OFFSET 0x400 /* Flash Bank Configuration Register */ #define TMS570_FLASH_FCFGBANK_OFFSET 0x400 /* Flash Bank Configuration Register */
/* Register Addresses *******************************************************************************/ /* Register Addresses *******************************************************/
#define TMS570_FLASH_FRDCNTL (TMS570_FWRAP_BASE+TMS570_FLASH_FRDCNTL_OFFSET) #define TMS570_FLASH_FRDCNTL (TMS570_FWRAP_BASE+TMS570_FLASH_FRDCNTL_OFFSET)
#define TMS570_FLASH_FEDACTRL1 (TMS570_FWRAP_BASE+TMS570_FLASH_FEDACTRL1_OFFSET) #define TMS570_FLASH_FEDACTRL1 (TMS570_FWRAP_BASE+TMS570_FLASH_FEDACTRL1_OFFSET)
@ -128,7 +128,7 @@
#define TMS570_FLASH_EEUNCERRADD (TMS570_FWRAP_BASE+TMS570_FLASH_EEUNCERRADD_OFFSET) #define TMS570_FLASH_EEUNCERRADD (TMS570_FWRAP_BASE+TMS570_FLASH_EEUNCERRADD_OFFSET)
#define TMS570_FLASH_FCFGBANK (TMS570_FWRAP_BASE+TMS570_FLASH_FCFGBANK_OFFSET) #define TMS570_FLASH_FCFGBANK (TMS570_FWRAP_BASE+TMS570_FLASH_FCFGBANK_OFFSET)
/* Register Bit-Field Definitions *******************************************************************/ /* Register Bit-Field Definitions *******************************************/
/* Flash Option Control Register */ /* Flash Option Control Register */
@ -140,30 +140,43 @@
/* Flash Error Detection and Correction Control Register 1 */ /* Flash Error Detection and Correction Control Register 1 */
#define FLASH_FEDACTRL1_ #define FLASH_FEDACTRL1_
/* Flash Error Detection and Correction Control Register 2 */ /* Flash Error Detection and Correction Control Register 2 */
#define FLASH_FEDACTRL2_ #define FLASH_FEDACTRL2_
/* Flash Correctable Error Count Register */ /* Flash Correctable Error Count Register */
#define FLASH_FCORERRCNT_ #define FLASH_FCORERRCNT_
/* Flash Correctable Error Address Register */ /* Flash Correctable Error Address Register */
#define FLASH_FCORERRADD_ #define FLASH_FCORERRADD_
/* Flash Correctable Error Position Register */ /* Flash Correctable Error Position Register */
#define FLASH_FCORERRPOS_ #define FLASH_FCORERRPOS_
/* Flash Error Detection and Correction Status Register */ /* Flash Error Detection and Correction Status Register */
#define FLASH_FEDACSTATUS_ #define FLASH_FEDACSTATUS_
/* Flash Un-Correctable Error Address Register */ /* Flash Un-Correctable Error Address Register */
#define FLASH_FUNCERRADD_ #define FLASH_FUNCERRADD_
/* Flash Error Detection and Correction Sector Disable Register */ /* Flash Error Detection and Correction Sector Disable Register */
#define FLASH_FEDACSDIS_ #define FLASH_FEDACSDIS_
/* Flash Primary Address Tag Register */ /* Flash Primary Address Tag Register */
#define FLASH_FPRIMADDTAG_ #define FLASH_FPRIMADDTAG_
/* Flash Duplicate Address Tag Register */ /* Flash Duplicate Address Tag Register */
#define FLASH_FDUPDDTAG_ #define FLASH_FDUPDDTAG_
/* Flash Bank Protection Register */ /* Flash Bank Protection Register */
#define FLASH_FBPROT_ #define FLASH_FBPROT_
/* Flash Bank Sector Enable Register */ /* Flash Bank Sector Enable Register */
#define FLASH_FBSE_ #define FLASH_FBSE_
/* Flash Bank Busy Register */ /* Flash Bank Busy Register */
#define FLASH_FBBUSY_ #define FLASH_FBBUSY_
/* Flash Bank Access Control Register */ /* Flash Bank Access Control Register */
#define FLASH_FBAC_ #define FLASH_FBAC_
@ -187,32 +200,46 @@
/* Flash Bank/Pump Ready Register */ /* Flash Bank/Pump Ready Register */
#define FLASH_FBPRDY_ #define FLASH_FBPRDY_
/* Flash Pump Access Control Register 1 */ /* Flash Pump Access Control Register 1 */
#define FLASH_FPAC1_ #define FLASH_FPAC1_
/* Flash Pump Access Control Register 2 */ /* Flash Pump Access Control Register 2 */
#define FLASH_FPAC2_ #define FLASH_FPAC2_
/* Flash Module Access Control Register */ /* Flash Module Access Control Register */
#define FLASH_FMAC_ #define FLASH_FMAC_
/* Flash Module Status Register */ /* Flash Module Status Register */
#define FLASH_FMSTAT_ #define FLASH_FMSTAT_
/* EEPROM Emulation Data MSW Register */ /* EEPROM Emulation Data MSW Register */
#define FLASH_FEMUDMSW_ #define FLASH_FEMUDMSW_
/* EEPROM Emulation Data LSW Register */ /* EEPROM Emulation Data LSW Register */
#define FLASH_FEMUDLSW_ #define FLASH_FEMUDLSW_
/* EEPROM Emulation ECC Register */ /* EEPROM Emulation ECC Register */
#define FLASH_FEMUECC_ #define FLASH_FEMUECC_
/* EEPROM Emulation Address Register */ /* EEPROM Emulation Address Register */
#define FLASH_FEMUADDR_ #define FLASH_FEMUADDR_
/* Diagnostic Control Register */ /* Diagnostic Control Register */
#define FLASH_FDIAGCTRL_ #define FLASH_FDIAGCTRL_
/* Uncorrected Raw Data High Register */ /* Uncorrected Raw Data High Register */
#define FLASH_FRAWDATAH_ #define FLASH_FRAWDATAH_
/* Uncorrected Raw Data Low Register */ /* Uncorrected Raw Data Low Register */
#define FLASH_FRAWDATAL_ #define FLASH_FRAWDATAL_
/* Uncorrected Raw ECC Register */ /* Uncorrected Raw ECC Register */
#define FLASH_FRAWECC_ #define FLASH_FRAWECC_
/* Parity Override Register */ /* Parity Override Register */
#define FLASH_FPAROVR_ #define FLASH_FPAROVR_
/* Flash Error Detection and Correction Sector Disable Register 2 */ /* Flash Error Detection and Correction Sector Disable Register 2 */
#define FLASH_FEDACSDIS2_ #define FLASH_FEDACSDIS2_
@ -238,18 +265,25 @@
/* EEPROM Emulation Error Detection and Correction Control Register 1 */ /* EEPROM Emulation Error Detection and Correction Control Register 1 */
#define FLASH_EECTRL1_ #define FLASH_EECTRL1_
/* EEPROM Emulation Error Detection and Correction Control Register 2 */ /* EEPROM Emulation Error Detection and Correction Control Register 2 */
#define FLASH_EECTRL2_ #define FLASH_EECTRL2_
/* EEPROM Emulation Correctable Error Count Register */ /* EEPROM Emulation Correctable Error Count Register */
#define FLASH_EECORERRCNT_ #define FLASH_EECORERRCNT_
/* EEPROM Emulation Correctable Error Address Register */ /* EEPROM Emulation Correctable Error Address Register */
#define FLASH_EECORERRADD_ #define FLASH_EECORERRADD_
/* EEPROM Emulation Correctable Error Bit Position Register */ /* EEPROM Emulation Correctable Error Bit Position Register */
#define FLASH_EECORERRPOS_ #define FLASH_EECORERRPOS_
/* EEPROM Emulation Error Status Register */ /* EEPROM Emulation Error Status Register */
#define FLASH_EESTATUS_ #define FLASH_EESTATUS_
/* EEPROM Emulation Un-Correctable Error Address Register */ /* EEPROM Emulation Un-Correctable Error Address Register */
#define FLASH_EEUNCERRADD_ #define FLASH_EEUNCERRADD_
/* Flash Bank Configuration Register */ /* Flash Bank Configuration Register */
#define FLASH_FCFGBANK_ #define FLASH_FCFGBANK_

29
arch/arm/src/tms570/hardware/tms570_gio.h
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@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570_gio.h * arch/arm/src/tms570/hardware/tms570_gio.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
****************************************************************************************************/ ****************************************************************************/
/* References: /* References:
* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller,
@ -27,16 +27,16 @@
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_GIO_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_GIO_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_GIO_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_GIO_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "hardware/tms570_memorymap.h" #include "hardware/tms570_memorymap.h"
/**************************************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************************************/ ****************************************************************************/
#define TMS570_GIOA 0 #define TMS570_GIOA 0
#define TMS570_GIOB 1 #define TMS570_GIOB 1
@ -50,7 +50,7 @@
#define TMS570_NPORTS 8 #define TMS570_NPORTS 8
#define TMS570_NIRQPORTS 4 #define TMS570_NIRQPORTS 4
/* Register Offsets *********************************************************************************/ /* Register Offsets *********************************************************/
#define TMS570_GIO_GCR0_OFFSET 0x0000 /* GIO Global Control Register */ #define TMS570_GIO_GCR0_OFFSET 0x0000 /* GIO Global Control Register */
#define TMS570_GIO_INTDET_OFFSET 0x0008 /* GIO Interrupt Detect Register */ #define TMS570_GIO_INTDET_OFFSET 0x0008 /* GIO Interrupt Detect Register */
@ -147,7 +147,7 @@
#define TMS570_GIOH_PULDIS_OFFSET 0x012c /* GIOH Pull Disable Register */ #define TMS570_GIOH_PULDIS_OFFSET 0x012c /* GIOH Pull Disable Register */
#define TMS570_GIOH_PSL_OFFSET 0x0130 /* GIOH Pull Select Register */ #define TMS570_GIOH_PSL_OFFSET 0x0130 /* GIOH Pull Select Register */
/* Register Addresses *******************************************************************************/ /* Register Addresses *******************************************************/
#define TMS570_GIO_GCR0 (TMS570_GIO_BASE+TMS570_GIO_GCR0_OFFSET) #define TMS570_GIO_GCR0 (TMS570_GIO_BASE+TMS570_GIO_GCR0_OFFSET)
#define TMS570_GIO_INTDET (TMS570_GIO_BASE+TMS570_GIO_INTDET_OFFSET) #define TMS570_GIO_INTDET (TMS570_GIO_BASE+TMS570_GIO_INTDET_OFFSET)
@ -244,7 +244,7 @@
#define TMS570_GIOH_PULDIS (TMS570_GIO_BASE+TMS570_GIOH_PULDIS_OFFSET) #define TMS570_GIOH_PULDIS (TMS570_GIO_BASE+TMS570_GIOH_PULDIS_OFFSET)
#define TMS570_GIOH_PSL (TMS570_GIO_BASE+TMS570_GIOH_PSL_OFFSET) #define TMS570_GIOH_PSL (TMS570_GIO_BASE+TMS570_GIOH_PSL_OFFSET)
/* Register Bit-Field Definitions *******************************************************************/ /* Register Bit-Field Definitions *******************************************/
/* GIO Global Control Register */ /* GIO Global Control Register */
@ -420,9 +420,14 @@
# define GIO_OFF_GIOD6 (0x1f) /* GIOD6 interrupt pending */ # define GIO_OFF_GIOD6 (0x1f) /* GIOD6 interrupt pending */
# define GIO_OFF_GIOD7 (0x20) /* GIOD7 interrupt pending */ # define GIO_OFF_GIOD7 (0x20) /* GIOD7 interrupt pending */
/* GIO Data Direction Register, GIO Data Input Register, GIO Data Output Register, /* GIO Data Direction Register,
* GIO Data Set Register, GIO Data Clear Register, GIO Open Drain Register, * GIO Data Input Register,
* GIO Pull Disable Register, and GIO Pull Select Register * GIO Data Output Register,
* GIO Data Set Register,
* GIO Data Clear Register,
* GIO Open Drain Register,
* GIO Pull Disable Register,
* and GIO Pull Select Register
*/ */
#define GIO_PIN(n) (1 << (n)) /* Bit n: Corresponds to pin n */ #define GIO_PIN(n) (1 << (n)) /* Bit n: Corresponds to pin n */

30
arch/arm/src/tms570/hardware/tms570_iomm.h
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@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570_iomm.h * arch/arm/src/tms570/hardware/tms570_iomm.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
****************************************************************************************************/ ****************************************************************************/
/* References: /* References:
* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller,
@ -27,18 +27,18 @@
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_IOMM_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_IOMM_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_IOMM_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_IOMM_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "hardware/tms570_memorymap.h" #include "hardware/tms570_memorymap.h"
/**************************************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************************************/ ****************************************************************************/
/* Register Offsets *********************************************************************************/ /* Register Offsets *********************************************************/
#define TMS570_IOMM_REVISION_OFFSET 0x0000 /* Revision Register */ #define TMS570_IOMM_REVISION_OFFSET 0x0000 /* Revision Register */
#define TMS570_IOMM_BOOT_OFFSET 0x0020 /* Boot Mode Register */ #define TMS570_IOMM_BOOT_OFFSET 0x0020 /* Boot Mode Register */
@ -85,7 +85,7 @@
# define TMS570_IOMM_PINMMR29_OFFSET 0x0184 /* Pin Multiplexing Control Register 29 */ # define TMS570_IOMM_PINMMR29_OFFSET 0x0184 /* Pin Multiplexing Control Register 29 */
# define TMS570_IOMM_PINMMR30_OFFSET 0x0188 /* Pin Multiplexing Control Register 30 */ # define TMS570_IOMM_PINMMR30_OFFSET 0x0188 /* Pin Multiplexing Control Register 30 */
/* Register Addresses *******************************************************************************/ /* Register Addresses *******************************************************/
#define TMS570_IOMM_REVISION (TMS570_IOMM_BASE+TMS570_IOMM_REVISION_OFFSET) #define TMS570_IOMM_REVISION (TMS570_IOMM_BASE+TMS570_IOMM_REVISION_OFFSET)
#define TMS570_IOMM_BOOT (TMS570_IOMM_BASE+TMS570_IOMM_BOOT_OFFSET) #define TMS570_IOMM_BOOT (TMS570_IOMM_BASE+TMS570_IOMM_BOOT_OFFSET)
@ -132,10 +132,11 @@
# define TMS570_IOMM_PINMMR29 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR29_OFFSET) # define TMS570_IOMM_PINMMR29 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR29_OFFSET)
# define TMS570_IOMM_PINMMR30 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR30_OFFSET) # define TMS570_IOMM_PINMMR30 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR30_OFFSET)
/* Register Bit-Field Definitions *******************************************************************/ /* Register Bit-Field Definitions *******************************************/
/* Revision Register */ /* Revision Register */
#define IOMM_REVISION_ #define IOMM_REVISION_
/* Boot Mode Register */ /* Boot Mode Register */
#define IOMM_BOOT_ #define IOMM_BOOT_
@ -151,21 +152,28 @@
/* Error Raw Status / Set Register */ /* Error Raw Status / Set Register */
#define IOMM_ERRRAWSTATUS_ #define IOMM_ERRRAWSTATUS_
/* Error Enabled Status / Clear Register */ /* Error Enabled Status / Clear Register */
#define IOMM_ERRSTATUS_ #define IOMM_ERRSTATUS_
/* Error Signaling Enable Register */ /* Error Signaling Enable Register */
#define IOMM_ERRENABLE_ #define IOMM_ERRENABLE_
/* Error Signaling Enable Clear Register */ /* Error Signaling Enable Clear Register */
#define IOMM_ERRENABLECLR_ #define IOMM_ERRENABLECLR_
/* Fault Address Register */ /* Fault Address Register */
#define IOMM_FAULTADDRESS_ #define IOMM_FAULTADDRESS_
/* Fault Status Register */ /* Fault Status Register */
#define IOMM_FAULTSTATUS_ #define IOMM_FAULTSTATUS_
/* Fault Clear Register */ /* Fault Clear Register */
#define IOMM_FAULTCLR_ #define IOMM_FAULTCLR_
/* Pin Multiplexing Control Register n, n=0..30. Each 8-bit field controls the functionality of /* Pin Multiplexing Control Register n, n=0..30.
* one pin/ball. There are then a maximum of 31*4 = 124 pin/ball configurations supported. * Each 8-bit field controls the functionality of one pin/ball.
* There are then a maximum of 31*4 = 124 pin/ball configurations supported.
*/ */
#define IOMM_PINMMR_REGNDX(n) ((n) >> 2) #define IOMM_PINMMR_REGNDX(n) ((n) >> 2)

8
arch/arm/src/tms570/hardware/tms570_memorymap.h
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@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570_memorymap.h * arch/arm/src/tms570/hardware/tms570_memorymap.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
****************************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_MEMORYMAP_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_MEMORYMAP_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_MEMORYMAP_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_MEMORYMAP_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>

21
arch/arm/src/tms570/hardware/tms570_pbist.h
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@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570_pbist.h * arch/arm/src/tms570/hardware/tms570_pbist.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
****************************************************************************************************/ ****************************************************************************/
/* References: /* References:
* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller,
@ -27,16 +27,17 @@
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PBIST_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PBIST_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PBIST_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PBIST_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "hardware/tms570_memorymap.h" #include "hardware/tms570_memorymap.h"
/**************************************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************************************/ ****************************************************************************/
/* PBIST RAM Groups */ /* PBIST RAM Groups */
#define PBIST_PBIST_ROM_GROUP 1 /* ROM */ #define PBIST_PBIST_ROM_GROUP 1 /* ROM */
@ -57,13 +58,13 @@
#define PBIST_DCAN1_RAM_RGS 3 /* Dual-port */ #define PBIST_DCAN1_RAM_RGS 3 /* Dual-port */
#define PBIST_DCAN2_RAM_RGS 4 /* Dual-port */ #define PBIST_DCAN2_RAM_RGS 4 /* Dual-port */
#define PBIST_ESRAM1_RAM_RGS 6 /* Single-port */ #define PBIST_ESRAM1_RAM_RGS 6 /* Single-port */
#define PBIST_MIBSPI1_RAM_RGS 7 /* Dual-port */ #define PBIST_MIBSPI1_RAM_RGS 7 /* Dual-port */
#define PBIST_VIM_RAM_RGS 8 /* Dual-port */ #define PBIST_VIM_RAM_RGS 8 /* Dual-port */
#define PBIST_MIBADC_RAM_RGS 9 /* Dual-port */ #define PBIST_MIBADC_RAM_RGS 9 /* Dual-port */
#define PBIST_N2HET_RAM_RGS 11 /* Dual-port */ #define PBIST_N2HET_RAM_RGS 11 /* Dual-port */
#define PBIST_HET_TU_RAM_RGS 12 /* Dual-port */ #define PBIST_HET_TU_RAM_RGS 12 /* Dual-port */
/* Register Offsets *********************************************************************************/ /* Register Offsets *********************************************************/
#define TMS570_PBIST_RAMT_OFFSET 0x0160 /* RAM Configuration Register */ #define TMS570_PBIST_RAMT_OFFSET 0x0160 /* RAM Configuration Register */
#define TMS570_PBIST_DLR_OFFSET 0x0164 /* Datalogger Register */ #define TMS570_PBIST_DLR_OFFSET 0x0164 /* Datalogger Register */
@ -84,7 +85,7 @@
#define TMS570_PBIST_RINFOL_OFFSET 0x01c8 /* RAM Info Mask Lower Register */ #define TMS570_PBIST_RINFOL_OFFSET 0x01c8 /* RAM Info Mask Lower Register */
#define TMS570_PBIST_RINFOU_OFFSET 0x01cc /* RAM Info Mask Upper Register */ #define TMS570_PBIST_RINFOU_OFFSET 0x01cc /* RAM Info Mask Upper Register */
/* Register Addresses *******************************************************************************/ /* Register Addresses *******************************************************/
#define TMS570_PBIST_RAMT (TMS570_PBIST_BASE+TMS570_PBIST_RAMT_OFFSET) #define TMS570_PBIST_RAMT (TMS570_PBIST_BASE+TMS570_PBIST_RAMT_OFFSET)
#define TMS570_PBIST_DLR (TMS570_PBIST_BASE+TMS570_PBIST_DLR_OFFSET) #define TMS570_PBIST_DLR (TMS570_PBIST_BASE+TMS570_PBIST_DLR_OFFSET)
@ -105,7 +106,7 @@
#define TMS570_PBIST_RINFOL (TMS570_PBIST_BASE+TMS570_PBIST_RINFOL_OFFSET) #define TMS570_PBIST_RINFOL (TMS570_PBIST_BASE+TMS570_PBIST_RINFOL_OFFSET)
#define TMS570_PBIST_RINFOU (TMS570_PBIST_BASE+TMS570_PBIST_RINFOU_OFFSET) #define TMS570_PBIST_RINFOU (TMS570_PBIST_BASE+TMS570_PBIST_RINFOU_OFFSET)
/* Register Bit-Field Definitions *******************************************************************/ /* Register Bit-Field Definitions *******************************************/
/* RAM Configuration Register */ /* RAM Configuration Register */

34
arch/arm/src/tms570/hardware/tms570_pcr.h
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@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570_pcr.h * arch/arm/src/tms570/hardware/tms570_pcr.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
****************************************************************************************************/ ****************************************************************************/
/* References: /* References:
* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller,
@ -27,18 +27,18 @@
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PCR_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PCR_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PCR_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PCR_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "hardware/tms570_memorymap.h" #include "hardware/tms570_memorymap.h"
/**************************************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************************************/ ****************************************************************************/
/* Register Offsets *********************************************************************************/ /* Register Offsets *********************************************************/
#define TMS570_PCR_PMPROTSET0_OFFSET 0x0000 /* Peripheral Memory Protection Set Register 0 */ #define TMS570_PCR_PMPROTSET0_OFFSET 0x0000 /* Peripheral Memory Protection Set Register 0 */
#define TMS570_PCR_PMPROTSET1_OFFSET 0x0004 /* Peripheral Memory Protection Set Register 1 */ #define TMS570_PCR_PMPROTSET1_OFFSET 0x0004 /* Peripheral Memory Protection Set Register 1 */
@ -65,7 +65,7 @@
#define TMS570_PCR_PSPWRDWNCLR2_OFFSET 0x00a8 /* Peripheral Power-Down Clear Register 2 */ #define TMS570_PCR_PSPWRDWNCLR2_OFFSET 0x00a8 /* Peripheral Power-Down Clear Register 2 */
#define TMS570_PCR_PSPWRDWNCLR3_OFFSET 0x00ac /* Peripheral Power-Down Clear Register 3 */ #define TMS570_PCR_PSPWRDWNCLR3_OFFSET 0x00ac /* Peripheral Power-Down Clear Register 3 */
/* Register Addresses *******************************************************************************/ /* Register Addresses *******************************************************/
#define TMS570_PCR_PMPROTSET0 (TMS570_PCR_BASE+TMS570_PCR_PMPROTSET0_OFFSET) #define TMS570_PCR_PMPROTSET0 (TMS570_PCR_BASE+TMS570_PCR_PMPROTSET0_OFFSET)
#define TMS570_PCR_PMPROTSET1 (TMS570_PCR_BASE+TMS570_PCR_PMPROTSET1_OFFSET) #define TMS570_PCR_PMPROTSET1 (TMS570_PCR_BASE+TMS570_PCR_PMPROTSET1_OFFSET)
@ -92,7 +92,7 @@
#define TMS570_PCR_PSPWRDWNCLR2 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNCLR2_OFFSET) #define TMS570_PCR_PSPWRDWNCLR2 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNCLR2_OFFSET)
#define TMS570_PCR_PSPWRDWNCLR3 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNCLR3_OFFSET) #define TMS570_PCR_PSPWRDWNCLR3 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNCLR3_OFFSET)
/* Register Bit-Field Definitions *******************************************************************/ /* Register Bit-Field Definitions *******************************************/
/* Peripheral Memory Protection Set Register 0 */ /* Peripheral Memory Protection Set Register 0 */
#define PCR_PMPROTSET0_ #define PCR_PMPROTSET0_
@ -142,7 +142,9 @@
/* Peripheral Memory Power-Down Clear Register 1 */ /* Peripheral Memory Power-Down Clear Register 1 */
#define PCR_PCSPWRDWNCLR1_ #define PCR_PCSPWRDWNCLR1_
/* Peripheral Power-Down Set Register 0 and Peripheral Power-Down Clear Register 0 */ /* Peripheral Power-Down Set Register 0 and
* Peripheral Power-Down Clear Register 0
*/
#define PCR_PSPWERDWN0_PS0_SHIFT (0) /* Bits 0-3: Quadrants for PS0 */ #define PCR_PSPWERDWN0_PS0_SHIFT (0) /* Bits 0-3: Quadrants for PS0 */
#define PCR_PSPWERDWN0_PS0_MASK (15 << PCR_PSPWERDWN0_PS0_SHIFT) #define PCR_PSPWERDWN0_PS0_MASK (15 << PCR_PSPWERDWN0_PS0_SHIFT)
@ -201,7 +203,9 @@
# define PCR_PSPWERDWN0_PS7_Q4 (8 << PCR_PSPWERDWN0_PS7_SHIFT) # define PCR_PSPWERDWN0_PS7_Q4 (8 << PCR_PSPWERDWN0_PS7_SHIFT)
# define PCR_PSPWERDWN0_PS7_QALL (15 << PCR_PSPWERDWN0_PS7_SHIFT) # define PCR_PSPWERDWN0_PS7_QALL (15 << PCR_PSPWERDWN0_PS7_SHIFT)
/* Peripheral Power-Down Set Register 1 and Peripheral Power-Down Clear Register 1 */ /* Peripheral Power-Down Set Register 1
* and Peripheral Power-Down Clear Register 1
*/
#define PCR_PSPWERDWN1_PS8_SHIFT (0) /* Bits 0-3: Quadrants for PS8 */ #define PCR_PSPWERDWN1_PS8_SHIFT (0) /* Bits 0-3: Quadrants for PS8 */
#define PCR_PSPWERDWN1_PS8_MASK (15 << PCR_PSPWERDWN1_PS8_SHIFT) #define PCR_PSPWERDWN1_PS8_MASK (15 << PCR_PSPWERDWN1_PS8_SHIFT)
@ -260,7 +264,9 @@
# define PCR_PSPWERDWN1_PS15_Q4 (8 << PCR_PSPWERDWN1_PS15_SHIFT) # define PCR_PSPWERDWN1_PS15_Q4 (8 << PCR_PSPWERDWN1_PS15_SHIFT)
# define PCR_PSPWERDWN1_PS15_QALL (15 << PCR_PSPWERDWN1_PS15_SHIFT) # define PCR_PSPWERDWN1_PS15_QALL (15 << PCR_PSPWERDWN1_PS15_SHIFT)
/* Peripheral Power-Down Set Register 2 and Peripheral Power-Down Clear Register 2*/ /* Peripheral Power-Down Set Register 2
* and Peripheral Power-Down Clear Register 2
*/
#define PCR_PSPWERDWN2_PS16_SHIFT (0) /* Bits 0-3: Quadrants for PS16 */ #define PCR_PSPWERDWN2_PS16_SHIFT (0) /* Bits 0-3: Quadrants for PS16 */
#define PCR_PSPWERDWN2_PS16_MASK (15 << PCR_PSPWERDWN2_PS16_SHIFT) #define PCR_PSPWERDWN2_PS16_MASK (15 << PCR_PSPWERDWN2_PS16_SHIFT)
@ -319,7 +325,9 @@
# define PCR_PSPWERDWN2_PS23_Q4 (8 << PCR_PSPWERDWN2_PS23_SHIFT) # define PCR_PSPWERDWN2_PS23_Q4 (8 << PCR_PSPWERDWN2_PS23_SHIFT)
# define PCR_PSPWERDWN2_PS23_QALL (15 << PCR_PSPWERDWN2_PS23_SHIFT) # define PCR_PSPWERDWN2_PS23_QALL (15 << PCR_PSPWERDWN2_PS23_SHIFT)
/* Peripheral Power-Down Set Register 3 and Peripheral Power-Down Clear Register 3 */ /* Peripheral Power-Down Set Register 3
* and Peripheral Power-Down Clear Register 3
*/
#define PCR_PSPWERDWN3_PS24_SHIFT (0) /* Bits 0-3: Quadrants for PS24 */ #define PCR_PSPWERDWN3_PS24_SHIFT (0) /* Bits 0-3: Quadrants for PS24 */
#define PCR_PSPWERDWN3_PS24_MASK (15 << PCR_PSPWERDWN3_PS24_SHIFT) #define PCR_PSPWERDWN3_PS24_MASK (15 << PCR_PSPWERDWN3_PS24_SHIFT)

16
arch/arm/src/tms570/hardware/tms570_pinmux.h
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@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570_pinmux.h * arch/arm/src/tms570/hardware/tms570_pinmux.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
****************************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PINMUX_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PINMUX_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PINMUX_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PINMUX_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
@ -47,11 +47,13 @@
# error "Unrecognized Hercules chip" # error "Unrecognized Hercules chip"
#endif #endif
/**************************************************************************************************** /****************************************************************************
* Pulbic Type Definitions * Pulbic Type Definitions
****************************************************************************************************/ ****************************************************************************/
/* Each chip-specific pinmux header file defines initializers for a type like: */ /* Each chip-specific pinmux header file defines initializers for a type
* like:
*/
struct tms570_pinmux_s struct tms570_pinmux_s
{ {

39
arch/arm/src/tms570/hardware/tms570_rti.h
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@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570_rti.h * arch/arm/src/tms570/hardware/tms570_rti.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
****************************************************************************************************/ ****************************************************************************/
/* References: /* References:
* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller,
@ -27,18 +27,18 @@
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_RTI_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_RTI_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_RTI_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_RTI_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "hardware/tms570_memorymap.h" #include "hardware/tms570_memorymap.h"
/**************************************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************************************/ ****************************************************************************/
/* Register Offsets *********************************************************************************/ /* Register Offsets *********************************************************/
#define TMS570_RTI_GCTRL_OFFSET 0x0000 /* RTI Global Control Register */ #define TMS570_RTI_GCTRL_OFFSET 0x0000 /* RTI Global Control Register */
/* 0x0004 RTITBCTRL Reserved. Do NOT use. */ /* 0x0004 RTITBCTRL Reserved. Do NOT use. */
@ -80,7 +80,7 @@
#define TMS570_RTI_COMP2CLR_OFFSET 0x00b8 /* RTI Compare 2 Clear Register */ #define TMS570_RTI_COMP2CLR_OFFSET 0x00b8 /* RTI Compare 2 Clear Register */
#define TMS570_RTI_COMP3CLR_OFFSET 0x00bc /* RTI Compare 3 Clear Register */ #define TMS570_RTI_COMP3CLR_OFFSET 0x00bc /* RTI Compare 3 Clear Register */
/* Register Addresses *******************************************************************************/ /* Register Addresses *******************************************************/
#define TMS570_RTI_GCTRL (TMS570_RTIDWWD_BASE+TMS570_RTI_GCTRL_OFFSET) #define TMS570_RTI_GCTRL (TMS570_RTIDWWD_BASE+TMS570_RTI_GCTRL_OFFSET)
#define TMS570_RTI_CAPCTRL (TMS570_RTIDWWD_BASE+TMS570_RTI_CAPCTRL_OFFSET) #define TMS570_RTI_CAPCTRL (TMS570_RTIDWWD_BASE+TMS570_RTI_CAPCTRL_OFFSET)
@ -119,7 +119,7 @@
#define TMS570_RTI_COMP2CLR (TMS570_RTIDWWD_BASE+TMS570_RTI_COMP2CLR_OFFSET) #define TMS570_RTI_COMP2CLR (TMS570_RTIDWWD_BASE+TMS570_RTI_COMP2CLR_OFFSET)
#define TMS570_RTI_COMP3CLR (TMS570_RTIDWWD_BASE+TMS570_RTI_COMP3CLR_OFFSET) #define TMS570_RTI_COMP3CLR (TMS570_RTIDWWD_BASE+TMS570_RTI_COMP3CLR_OFFSET)
/* Register Bit-Field Definitions *******************************************************************/ /* Register Bit-Field Definitions *******************************************/
/* RTI Global Control Register */ /* RTI Global Control Register */
@ -140,15 +140,21 @@
#define RTI_COMPCTRL_COMPSEL3 (1 << 12) /* Bit 12: Compare select 3 */ #define RTI_COMPCTRL_COMPSEL3 (1 << 12) /* Bit 12: Compare select 3 */
/* RTI Free Running Counter 0/1 Register (32-bit counter value) */ /* RTI Free Running Counter 0/1 Register (32-bit counter value) */
/* RTI Up Counter 0/1 Register (32-bit counter value) */ /* RTI Up Counter 0/1 Register (32-bit counter value) */
/* RTI Compare Up Counter 0/1 Register (32-bit counter value) */ /* RTI Compare Up Counter 0/1 Register (32-bit counter value) */
/* RTI Capture Free Running Counter 0/1 Register (32-bit counter value) */ /* RTI Capture Free Running Counter 0/1 Register (32-bit counter value) */
/* RTI Capture Up Counter 0/1 Register (32-bit counter value) */ /* RTI Capture Up Counter 0/1 Register (32-bit counter value) */
/* RTI Compare 0/1/2/3 Register Section (32-bit counter value) */ /* RTI Compare 0/1/2/3 Register Section (32-bit counter value) */
/* RTI Update Compare 0/1/2/3 Register (32-bit counter value) */ /* RTI Update Compare 0/1/2/3 Register (32-bit counter value) */
/* RTI Set Interrupt Enable Register, RTI Clear Interrupt Enable Register, and /* RTI Set Interrupt Enable Register, RTI Clear Interrupt Enable Register,
* RTI Interrupt Flag Register * and RTI Interrupt Flag Register
*/ */
#define RTI_INT0 (1 << 0) /* Bit 0: Compare interrupt 0 */ #define RTI_INT0 (1 << 0) /* Bit 0: Compare interrupt 0 */
@ -162,26 +168,37 @@
/* Digital Watchdog Control Register */ /* Digital Watchdog Control Register */
#define RTI_DWDCTRL_ #define RTI_DWDCTRL_
/* Digital Watchdog Preload Register */ /* Digital Watchdog Preload Register */
#define RTI_DWDPRLD_ #define RTI_DWDPRLD_
/* Watchdog Status Register */ /* Watchdog Status Register */
#define RTI_WDSTATUS_ #define RTI_WDSTATUS_
/* RTI Watchdog Key Register */ /* RTI Watchdog Key Register */
#define RTI_WDKEY_ #define RTI_WDKEY_
/* RTI Digital Watchdog Down Counter Register */ /* RTI Digital Watchdog Down Counter Register */
#define RTI_DWDCNTR_ #define RTI_DWDCNTR_
/* Digital Windowed Watchdog Reaction Control Register Section */ /* Digital Windowed Watchdog Reaction Control Register Section */
#define RTI_WWDRXNCTRL_ #define RTI_WWDRXNCTRL_
/* Digital Windowed Watchdog Window Size Control Register */ /* Digital Windowed Watchdog Window Size Control Register */
#define RTI_WWDSIZECTRL_ #define RTI_WWDSIZECTRL_
/* RTI Compare Interrupt Clear Enable Register */ /* RTI Compare Interrupt Clear Enable Register */
#define RTI_INTCLRENABLE_ #define RTI_INTCLRENABLE_
/* RTI Compare 0 Clear Register */ /* RTI Compare 0 Clear Register */
#define RTI_COMP0CLR_ #define RTI_COMP0CLR_
/* RTI Compare 1 Clear Register */ /* RTI Compare 1 Clear Register */
#define RTI_COMP1CLR_ #define RTI_COMP1CLR_
/* RTI Compare 2 Clear Register */ /* RTI Compare 2 Clear Register */
#define RTI_COMP2CLR_ #define RTI_COMP2CLR_
/* RTI Compare 3 Clear Register */ /* RTI Compare 3 Clear Register */
#define RTI_COMP3CLR_ #define RTI_COMP3CLR_

30
arch/arm/src/tms570/hardware/tms570_sci.h
View File

@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570_sci.h * arch/arm/src/tms570/hardware/tms570_sci.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
****************************************************************************************************/ ****************************************************************************/
/* References: /* References:
* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller,
@ -27,18 +27,18 @@
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SCI_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SCI_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SCI_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SCI_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "hardware/tms570_memorymap.h" #include "hardware/tms570_memorymap.h"
/**************************************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************************************/ ****************************************************************************/
/* Register Offsets *********************************************************************************/ /* Register Offsets *********************************************************/
#define TMS570_SCI_GCR0_OFFSET 0x0000 /* SCI Global Control Register 0 */ #define TMS570_SCI_GCR0_OFFSET 0x0000 /* SCI Global Control Register 0 */
#define TMS570_SCI_GCR1_OFFSET 0x0004 /* SCI Global Control Register 1 */ #define TMS570_SCI_GCR1_OFFSET 0x0004 /* SCI Global Control Register 1 */
@ -86,7 +86,7 @@
#define TMS570_SCI_PD_OFFSET TMS570_SCI_PIO7_OFFSET /* Pin Pullup/Pulldown Disable Register */ #define TMS570_SCI_PD_OFFSET TMS570_SCI_PIO7_OFFSET /* Pin Pullup/Pulldown Disable Register */
#define TMS570_SCI_PSL_OFFSET TMS570_SCI_PIO8_OFFSET /* Pin Pullup/Pulldown Selection Register */ #define TMS570_SCI_PSL_OFFSET TMS570_SCI_PIO8_OFFSET /* Pin Pullup/Pulldown Selection Register */
/* Register Addresses *******************************************************************************/ /* Register Addresses *******************************************************/
#define TMS570_SCI1_GCR0 (TMS570_SCI1_BASE+TMS570_SCI_GCR0_OFFSET) #define TMS570_SCI1_GCR0 (TMS570_SCI1_BASE+TMS570_SCI_GCR0_OFFSET)
#define TMS570_SCI1_GCR1 (TMS570_SCI1_BASE+TMS570_SCI_GCR1_OFFSET) #define TMS570_SCI1_GCR1 (TMS570_SCI1_BASE+TMS570_SCI_GCR1_OFFSET)
@ -178,7 +178,7 @@
# define TMS570_SCI1_PSL TMS570_SCI_PIO8 /* Pin Pullup/Pulldown Selection Register */ # define TMS570_SCI1_PSL TMS570_SCI_PIO8 /* Pin Pullup/Pulldown Selection Register */
#endif #endif
/* Register Bit-Field Definitions *******************************************************************/ /* Register Bit-Field Definitions *******************************************/
/* SCI Global Control Register 0 */ /* SCI Global Control Register 0 */
@ -214,7 +214,7 @@
/* SCI Set Interrupt Register, /* SCI Set Interrupt Register,
* SCI Clear Interrupt Register, * SCI Clear Interrupt Register,
( SCI Set Interrupt Level Register, and * SCI Set Interrupt Level Register, and
* SCI Clear Interrupt Level Register * SCI Clear Interrupt Level Register
*/ */
@ -309,8 +309,10 @@
/* Receiver Emulation Data Buffer */ /* Receiver Emulation Data Buffer */
#define SCI_ED_ #define SCI_ED_
/* Receiver Data Buffer */ /* Receiver Data Buffer */
#define SCI_RD_ #define SCI_RD_
/* Transmit Data Buffer */ /* Transmit Data Buffer */
#define SCI_TD_ #define SCI_TD_
@ -330,20 +332,28 @@
/* LIN Compare Register */ /* LIN Compare Register */
#define LIN_COMPARE_ #define LIN_COMPARE_
/* LIN Receive Buffer 0 Register */ /* LIN Receive Buffer 0 Register */
#define LIN_RD0_ #define LIN_RD0_
/* LIN Receive Buffer 1 Register */ /* LIN Receive Buffer 1 Register */
#define LIN_RD1_ #define LIN_RD1_
/* LIN Mask Register */ /* LIN Mask Register */
#define LIN_MASK_ #define LIN_MASK_
/* LIN Identification Register */ /* LIN Identification Register */
#define LIN_ID_ #define LIN_ID_
/* LIN Transmit Buffer 0 */ /* LIN Transmit Buffer 0 */
#define LIN_TD0_ #define LIN_TD0_
/* LIN Transmit Buffer 1 */ /* LIN Transmit Buffer 1 */
#define LIN_TD1_ #define LIN_TD1_
/* Maximum Baud Rate Selection Register */ /* Maximum Baud Rate Selection Register */
#define SCI_MBRS_ #define SCI_MBRS_
/* Input/Output Error Enable Register */ /* Input/Output Error Enable Register */
#define SCI_IODFTCTRL_ #define SCI_IODFTCTRL_

90
arch/arm/src/tms570/hardware/tms570_sys.h
View File

@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570_sys.h * arch/arm/src/tms570/hardware/tms570_sys.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
****************************************************************************************************/ ****************************************************************************/
/* References: /* References:
* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller,
@ -27,16 +27,16 @@
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "hardware/tms570_memorymap.h" #include "hardware/tms570_memorymap.h"
/**************************************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************************************/ ****************************************************************************/
/* The LPO trim value may be programmed into the TI OTP: */ /* The LPO trim value may be programmed into the TI OTP: */
@ -45,7 +45,7 @@
# define TMS570_TITCM_LPOTRIM_SHIFT (16) /* Bits 16-31: LPO trim value */ # define TMS570_TITCM_LPOTRIM_SHIFT (16) /* Bits 16-31: LPO trim value */
# define TMS570_TITCM_LPOTRIM_MASK (0xffff << TMS570_TITCM_LPOTRIM_SHIFT) # define TMS570_TITCM_LPOTRIM_MASK (0xffff << TMS570_TITCM_LPOTRIM_SHIFT)
/* Register Offsets *********************************************************************************/ /* Register Offsets *********************************************************/
#define TMS570_SYS_PC1_OFFSET 0x0000 /* SYS Pin Control Register 1 */ #define TMS570_SYS_PC1_OFFSET 0x0000 /* SYS Pin Control Register 1 */
#define TMS570_SYS_PC2_OFFSET 0x0004 /* SYS Pin Control Register 2 */ #define TMS570_SYS_PC2_OFFSET 0x0004 /* SYS Pin Control Register 2 */
@ -102,7 +102,7 @@
#define TMS570_SYS_SSIVEC_OFFSET 0x00f4 /* Software Interrupt Vector Register */ #define TMS570_SYS_SSIVEC_OFFSET 0x00f4 /* Software Interrupt Vector Register */
#define TMS570_SYS_SSIF_OFFSET 0x00f8 /* System Software Interrupt Flag Register */ #define TMS570_SYS_SSIF_OFFSET 0x00f8 /* System Software Interrupt Flag Register */
/* Register Addresses *******************************************************************************/ /* Register Addresses *******************************************************/
#define TMS570_SYS_PC1 (TMS570_SYS_BASE+TMS570_SYS_PC1_OFFSET) #define TMS570_SYS_PC1 (TMS570_SYS_BASE+TMS570_SYS_PC1_OFFSET)
#define TMS570_SYS_PC2 (TMS570_SYS_BASE+TMS570_SYS_PC2_OFFSET) #define TMS570_SYS_PC2 (TMS570_SYS_BASE+TMS570_SYS_PC2_OFFSET)
@ -159,7 +159,7 @@
#define TMS570_SYS_SSIVEC (TMS570_SYS_BASE+TMS570_SYS_SSIVEC_OFFSET) #define TMS570_SYS_SSIVEC (TMS570_SYS_BASE+TMS570_SYS_SSIVEC_OFFSET)
#define TMS570_SYS_SSIF (TMS570_SYS_BASE+TMS570_SYS_SSIF_OFFSET) #define TMS570_SYS_SSIF (TMS570_SYS_BASE+TMS570_SYS_SSIF_OFFSET)
/* Register Bit-Field Definitions *******************************************************************/ /* Register Bit-Field Definitions *******************************************/
#define SYS_GLBSTAT_OSC_ERR_MASK (0x01) #define SYS_GLBSTAT_OSC_ERR_MASK (0x01)
#define SYS_GLBSTAT_OSC_ERR_CLR (0x0301) #define SYS_GLBSTAT_OSC_ERR_CLR (0x0301)
@ -200,8 +200,8 @@
#define SYS_PC9_ECPCLKPS (1 << 0) /* Bit 0: ECLK pull up/pull down select */ #define SYS_PC9_ECPCLKPS (1 << 0) /* Bit 0: ECLK pull up/pull down select */
/* Clock Source Disable Register, Clock Source Disable Set Register, and Clock Source /* Clock Source Disable Register, Clock Source Disable Set Register,
* Disable Clear Register * and Clock Source Disable Clear Register
*/ */
#define SYS_CSDIS_CLKSR0OFF (1 << 0) /* Bit 0: Clock source 0 */ #define SYS_CSDIS_CLKSR0OFF (1 << 0) /* Bit 0: Clock source 0 */
@ -221,8 +221,8 @@
#define SYS_CSDIS_CLKSRC_PLL2 SYS_CSDIS_CLKSR6OFF /* PLL2 */ #define SYS_CSDIS_CLKSRC_PLL2 SYS_CSDIS_CLKSR6OFF /* PLL2 */
#define SYS_CSDIS_CLKSRC_EXTCLKIN2 SYS_CSDIS_CLKSR7OFF /* EXTCLKIN2 */ #define SYS_CSDIS_CLKSRC_EXTCLKIN2 SYS_CSDIS_CLKSR7OFF /* EXTCLKIN2 */
/* Clock Domain Disable Register, Clock Domain Disable Set Register, and Clock Domain /* Clock Domain Disable Register, Clock Domain Disable Set Register,
* Disable Clear Register. * and Clock Domain Disable Clear Register.
*/ */
#define SYS_CDDIS_GCLKOFF (1 << 0) /* Bit 0: GCLK domain off */ #define SYS_CDDIS_GCLKOFF (1 << 0) /* Bit 0: GCLK domain off */
@ -464,6 +464,7 @@
#define SYS_PLLCTL1_MASKSLIP_MASK (3 << SYS_PLLCTL1_MASKSLIP_SHIFT) #define SYS_PLLCTL1_MASKSLIP_MASK (3 << SYS_PLLCTL1_MASKSLIP_SHIFT)
# define SYS_PLLCTL1_MASKSLIP_DISABLE (0 << SYS_PLLCTL1_MASKSLIP_SHIFT) /* All values but 2 disable */ # define SYS_PLLCTL1_MASKSLIP_DISABLE (0 << SYS_PLLCTL1_MASKSLIP_SHIFT) /* All values but 2 disable */
# define SYS_PLLCTL1_MASKSLIP_ENABLE (1 << SYS_PLLCTL1_MASKSLIP_SHIFT) # define SYS_PLLCTL1_MASKSLIP_ENABLE (1 << SYS_PLLCTL1_MASKSLIP_SHIFT)
#define SYS_PLLCTL1_ROS (1 << 31) /* Bit 31: Reset on PLL Slip */ #define SYS_PLLCTL1_ROS (1 << 31) /* Bit 31: Reset on PLL Slip */
/* PLL Control Register 2 */ /* PLL Control Register 2 */
@ -488,22 +489,24 @@
/* Die Identification Register, Lower Word */ /* Die Identification Register, Lower Word */
#define SYS_DIEIDL_ #define SYS_DIEIDL_
/* Die Identification Register, Upper Word */ /* Die Identification Register, Upper Word */
#define SYS_DIEIDH_ #define SYS_DIEIDH_
/* LPO/Clock Monitor Control Register */ /* LPO/Clock Monitor Control Register */
#define SYS_LPOMONCTL_LFTRIM_SHIFT (0) /* Bits 0-4: Low frequency oscillator trim value */ #define SYS_LPOMONCTL_LFTRIM_SHIFT (0) /* Bits 0-4: Low frequency oscillator trim value */
#define SYS_LPOMONCTL_LFTRIM_MASK (31 << SYS_LPOMONCTL_LFTRIM_SHIFT) #define SYS_LPOMONCTL_LFTRIM_MASK (31 << SYS_LPOMONCTL_LFTRIM_SHIFT)
# define SYS_LPOMONCTL_20p67 (0 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 20.67% */ # define SYS_LPOMONCTL_20p67 (0 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 20.67% */
# define SYS_LPOMONCTL_25p76 (1 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 25.76% */ # define SYS_LPOMONCTL_25p76 (1 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 25.76% */
# define SYS_LPOMONCTL_30p84 (2 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 30.84% */ # define SYS_LPOMONCTL_30p84 (2 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 30.84% */
# define SYS_LPOMONCTL_35p90 (3 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 35.90% */ # define SYS_LPOMONCTL_35p90 (3 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 35.90% */
# define SYS_LPOMONCTL_40p93 (4 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 40.93% */ # define SYS_LPOMONCTL_40p93 (4 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 40.93% */
# define SYS_LPOMONCTL_45p95 (5 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 45.95% */ # define SYS_LPOMONCTL_45p95 (5 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 45.95% */
# define SYS_LPOMONCTL_50p97 (6 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 50.97% */ # define SYS_LPOMONCTL_50p97 (6 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 50.97% */
# define SYS_LPOMONCTL_55p91 (7 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 55.91% */ # define SYS_LPOMONCTL_55p91 (7 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 55.91% */
# define SYS_LPOMONCTL_60p86 (8 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 60.86% */ # define SYS_LPOMONCTL_60p86 (8 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 60.86% */
# define SYS_LPOMONCTL_65p78 (9 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 65.78% */ # define SYS_LPOMONCTL_65p78 (9 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 65.78% */
# define SYS_LPOMONCTL_70p75 (10 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 70.75% */ # define SYS_LPOMONCTL_70p75 (10 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 70.75% */
# define SYS_LPOMONCTL_75p63 (11 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 75.63% */ # define SYS_LPOMONCTL_75p63 (11 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 75.63% */
# define SYS_LPOMONCTL_80p61 (12 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 80.61% */ # define SYS_LPOMONCTL_80p61 (12 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 80.61% */
@ -526,18 +529,19 @@
# define SYS_LPOMONCTL_161p38 (29 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 161.38% */ # define SYS_LPOMONCTL_161p38 (29 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 161.38% */
# define SYS_LPOMONCTL_165p90 (30 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 165.90% */ # define SYS_LPOMONCTL_165p90 (30 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 165.90% */
# define SYS_LPOMONCTL_170p42 (31 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 170.42% */ # define SYS_LPOMONCTL_170p42 (31 << SYS_LPOMONCTL_LFTRIM_SHIFT) /* 170.42% */
#define SYS_LPOMONCTL_HFTRIM_SHIFT (8) /* Bits 8-12: High frequency oscillator trim value */ #define SYS_LPOMONCTL_HFTRIM_SHIFT (8) /* Bits 8-12: High frequency oscillator trim value */
#define SYS_LPOMONCTL_HFTRIM_MASK (31 << SYS_LPOMONCTL_HFTRIM_SHIFT) #define SYS_LPOMONCTL_HFTRIM_MASK (31 << SYS_LPOMONCTL_HFTRIM_SHIFT)
# define SYS_LPOMONCTL_HFTRIM_29p52 (0 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 29.52% */ # define SYS_LPOMONCTL_HFTRIM_29p52 (0 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 29.52% */
# define SYS_LPOMONCTL_HFTRIM_34p24 (1 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 34.24% */ # define SYS_LPOMONCTL_HFTRIM_34p24 (1 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 34.24% */
# define SYS_LPOMONCTL_HFTRIM_38p85 (2 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 38.85% */ # define SYS_LPOMONCTL_HFTRIM_38p85 (2 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 38.85% */
# define SYS_LPOMONCTL_HFTRIM_43p45 (3 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 43.45% */ # define SYS_LPOMONCTL_HFTRIM_43p45 (3 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 43.45% */
# define SYS_LPOMONCTL_HFTRIM_47p99 (4 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 47.99% */ # define SYS_LPOMONCTL_HFTRIM_47p99 (4 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 47.99% */
# define SYS_LPOMONCTL_HFTRIM_52p55 (5 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 52.55% */ # define SYS_LPOMONCTL_HFTRIM_52p55 (5 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 52.55% */
# define SYS_LPOMONCTL_HFTRIM_57p02 (6 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 57.02% */ # define SYS_LPOMONCTL_HFTRIM_57p02 (6 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 57.02% */
# define SYS_LPOMONCTL_HFTRIM_61p46 (7 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 61.46% */ # define SYS_LPOMONCTL_HFTRIM_61p46 (7 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 61.46% */
# define SYS_LPOMONCTL_HFTRIM_65p92 (8 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 65.92% */ # define SYS_LPOMONCTL_HFTRIM_65p92 (8 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 65.92% */
# define SYS_LPOMONCTL_HFTRIM_70p17 (9 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 70.17% */ # define SYS_LPOMONCTL_HFTRIM_70p17 (9 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 70.17% */
# define SYS_LPOMONCTL_HFTRIM_74p55 (10 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 74.55% */ # define SYS_LPOMONCTL_HFTRIM_74p55 (10 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 74.55% */
# define SYS_LPOMONCTL_HFTRIM_78p92 (11 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 78.92% */ # define SYS_LPOMONCTL_HFTRIM_78p92 (11 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 78.92% */
# define SYS_LPOMONCTL_HFTRIM_83p17 (12 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 83.17% */ # define SYS_LPOMONCTL_HFTRIM_83p17 (12 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 83.17% */
@ -560,33 +564,46 @@
# define SYS_LPOMONCTL_HFTRIM_151p80 (29 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 151.80% */ # define SYS_LPOMONCTL_HFTRIM_151p80 (29 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 151.80% */
# define SYS_LPOMONCTL_HFTRIM_155p50 (30 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 155.50% */ # define SYS_LPOMONCTL_HFTRIM_155p50 (30 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 155.50% */
# define SYS_LPOMONCTL_HFTRIM_159p35 (31 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 159.35% */ # define SYS_LPOMONCTL_HFTRIM_159p35 (31 << SYS_LPOMONCTL_HFTRIM_SHIFT) /* 159.35% */
#define SYS_LPOMONCTL_OSCFRQCONFIGCNT (1 << 16) /* Bit 16: Configures the counter based on OSC frequency. */ #define SYS_LPOMONCTL_OSCFRQCONFIGCNT (1 << 16) /* Bit 16: Configures the counter based on OSC frequency. */
#define SYS_LPOMONCTL_BIASENABLE (1 << 24) /* Bit 24: Bias enable. */ #define SYS_LPOMONCTL_BIASENABLE (1 << 24) /* Bit 24: Bias enable. */
/* Clock Test Register */ /* Clock Test Register */
#define SYS_CLKTEST_ #define SYS_CLKTEST_
/* DFT Control Register */ /* DFT Control Register */
#define SYS_DFTCTRLREG_ #define SYS_DFTCTRLREG_
/* DFT Control Register 2 */ /* DFT Control Register 2 */
#define SYS_DFTCTRLREG2_ #define SYS_DFTCTRLREG2_
/* General Purpose Register */ /* General Purpose Register */
#define SYS_GPREG1_ #define SYS_GPREG1_
/* Imprecise Fault Status Register */ /* Imprecise Fault Status Register */
#define SYS_IMPFASTS_ #define SYS_IMPFASTS_
/* Imprecise Fault Write Address Register */ /* Imprecise Fault Write Address Register */
#define SYS_IMPFTADD_ #define SYS_IMPFTADD_
/* System Software Interrupt Request 1 Register */ /* System Software Interrupt Request 1 Register */
#define SYS_SSIR1_ #define SYS_SSIR1_
/* System Software Interrupt Request 2 Register */ /* System Software Interrupt Request 2 Register */
#define SYS_SSIR2_ #define SYS_SSIR2_
/* System Software Interrupt Request 3 Register */ /* System Software Interrupt Request 3 Register */
#define SYS_SSIR3_ #define SYS_SSIR3_
/* System Software Interrupt Request 4 Register */ /* System Software Interrupt Request 4 Register */
#define SYS_SSIR4_ #define SYS_SSIR4_
/* RAM Control Register */ /* RAM Control Register */
#define SYS_RAMGCR_ #define SYS_RAMGCR_
/* Bus Matrix Module Control Register 1 */ /* Bus Matrix Module Control Register 1 */
#define SYS_BMMCR1_ #define SYS_BMMCR1_
/* CPU Reset Control Register */ /* CPU Reset Control Register */
#define SYS_CPURSTCR_ #define SYS_CPURSTCR_
@ -612,13 +629,16 @@
# define SYS_ECPCNTL_ECPINSEL_LOW (0 << SYS_ECPCNTL_ECPINSEL_SHIFT) /* Tied Low */ # define SYS_ECPCNTL_ECPINSEL_LOW (0 << SYS_ECPCNTL_ECPINSEL_SHIFT) /* Tied Low */
# define SYS_ECPCNTL_ECPINSEL_HCLK (1 << SYS_ECPCNTL_ECPINSEL_SHIFT) /* HCLK */ # define SYS_ECPCNTL_ECPINSEL_HCLK (1 << SYS_ECPCNTL_ECPINSEL_SHIFT) /* HCLK */
# define SYS_ECPCNTL_ECPINSEL_EXTCLK (2 << SYS_ECPCNTL_ECPINSEL_SHIFT) /* External clock */ # define SYS_ECPCNTL_ECPINSEL_EXTCLK (2 << SYS_ECPCNTL_ECPINSEL_SHIFT) /* External clock */
#define SYS_ECPCNTL_ECPCOS (1 << 23) /* Bit 23: ECP continue on suspend */ #define SYS_ECPCNTL_ECPCOS (1 << 23) /* Bit 23: ECP continue on suspend */
#define SYS_ECPCNTL_ECPSSEL (1 << 24) /* Bit 24: Select VCLK os OSCIN as for ECLK */ #define SYS_ECPCNTL_ECPSSEL (1 << 24) /* Bit 24: Select VCLK os OSCIN as for ECLK */
/* DEV Parity Control Register 1 */ /* DEV Parity Control Register 1 */
#define SYS_DEVCR1_ #define SYS_DEVCR1_
/* System Exception Control Register */ /* System Exception Control Register */
#define SYS_ECR_ #define SYS_ECR_
/* System Exception Status Register */ /* System Exception Status Register */
#define SYS_ESR_MPMODE (1 << 0) /* Bit 0: Current memory protection unit (MPU) mode */ #define SYS_ESR_MPMODE (1 << 0) /* Bit 0: Current memory protection unit (MPU) mode */
@ -634,12 +654,16 @@
/* System Test Abort Status Register */ /* System Test Abort Status Register */
#define SYS_TASR_ #define SYS_TASR_
/* Global Status Register */ /* Global Status Register */
#define SYS_GLBSTAT_ #define SYS_GLBSTAT_
/* Device Identification Register */ /* Device Identification Register */
#define SYS_DEVID_ #define SYS_DEVID_
/* Software Interrupt Vector Register */ /* Software Interrupt Vector Register */
#define SYS_SSIVEC_ #define SYS_SSIVEC_
/* System Software Interrupt Flag Register */ /* System Software Interrupt Flag Register */
#define SYS_SSIF_ #define SYS_SSIF_

31
arch/arm/src/tms570/hardware/tms570_sys2.h
View File

@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570_sys2.h * arch/arm/src/tms570/hardware/tms570_sys2.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
****************************************************************************************************/ ****************************************************************************/
/* References: /* References:
* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller,
@ -27,18 +27,18 @@
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS2_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS2_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS2_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS2_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "hardware/tms570_memorymap.h" #include "hardware/tms570_memorymap.h"
/**************************************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************************************/ ****************************************************************************/
/* Register Offsets *********************************************************************************/ /* Register Offsets *********************************************************/
#define TMS570_SYS2_STCCLKDIV_OFFSET 0x0008 /* CPU Logic BIST Clock Divider */ #define TMS570_SYS2_STCCLKDIV_OFFSET 0x0008 /* CPU Logic BIST Clock Divider */
#define TMS570_SYS2_CLKSLIP_OFFSET 0x0070 /* Clock Slip Register */ #define TMS570_SYS2_CLKSLIP_OFFSET 0x0070 /* Clock Slip Register */
@ -50,7 +50,7 @@
#define TMS570_SYS2_CLK2CNTRL_OFFSET 0x003c #define TMS570_SYS2_CLK2CNTRL_OFFSET 0x003c
#define TMS570_SYS2_VCLKACON1_OFFSET 0x0040 #define TMS570_SYS2_VCLKACON1_OFFSET 0x0040
/* Register Addresses *******************************************************************************/ /* Register Addresses *******************************************************/
#define TMS570_SYS2_STCCLKDIV (TMS570_SYS2_BASE+TMS570_SYS2_STCCLKDIV_OFFSET) #define TMS570_SYS2_STCCLKDIV (TMS570_SYS2_BASE+TMS570_SYS2_STCCLKDIV_OFFSET)
#define TMS570_SYS2_CLKSLIP (TMS570_SYS2_BASE+TMS570_SYS2_CLKSLIP_OFFSET) #define TMS570_SYS2_CLKSLIP (TMS570_SYS2_BASE+TMS570_SYS2_CLKSLIP_OFFSET)
@ -62,21 +62,34 @@
#define TMS570_SYS2_CLK2CNTRL (TMS570_SYS2_BASE+TMS570_SYS2_CLK2CNTRL_OFFSET) #define TMS570_SYS2_CLK2CNTRL (TMS570_SYS2_BASE+TMS570_SYS2_CLK2CNTRL_OFFSET)
#define TMS570_SYS2_VCLKACON1 (TMS570_SYS2_BASE+TMS570_SYS2_VCLKACON1_OFFSET) #define TMS570_SYS2_VCLKACON1 (TMS570_SYS2_BASE+TMS570_SYS2_VCLKACON1_OFFSET)
/* Register Bit-Field Definitions *******************************************************************/ /* Register Bit-Field Definitions *******************************************/
/* CPU Logic BIST Clock Divider */ /* CPU Logic BIST Clock Divider */
#define SYS2_STCCLKDIV_ #define SYS2_STCCLKDIV_
/* Clock Slip Register */ /* Clock Slip Register */
#define SYS2_CLKSLIP_ #define SYS2_CLKSLIP_
/* EFUSE Controller Control Register */ /* EFUSE Controller Control Register */
#define SYS2_EFC_CTLREG_ #define SYS2_EFC_CTLREG_
/* Die Identification Register Lower Word */ /* Die Identification Register Lower Word */
#define SYS2_DIEDL_REG0_ #define SYS2_DIEDL_REG0_
/* Die Identification Register Upper Word */ /* Die Identification Register Upper Word */
#define SYS2_DIEDH_REG1_ #define SYS2_DIEDH_REG1_
/* Die Identification Register Lower Word */ /* Die Identification Register Lower Word */
#define SYS2_DIEDL_REG2_ #define SYS2_DIEDL_REG2_
/* Die Identification Register Upper Word */ /* Die Identification Register Upper Word */
#define SYS2_DIEDH_REG3_ #define SYS2_DIEDH_REG3_
#if defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT) #if defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT)

41
arch/arm/src/tms570/hardware/tms570_vim.h
View File

@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570_vim.h * arch/arm/src/tms570/hardware/tms570_vim.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
****************************************************************************************************/ ****************************************************************************/
/* References: /* References:
* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller,
@ -27,21 +27,21 @@
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_VIM_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_VIM_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_VIM_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_VIM_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "hardware/tms570_memorymap.h" #include "hardware/tms570_memorymap.h"
/**************************************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************************************/ ****************************************************************************/
#define VIM_REGNDX(ch) ((ch) >> 5) #define VIM_REGNDX(ch) ((ch) >> 5)
#define VIM_REGBIT(ch) ((ch) & 31) #define VIM_REGBIT(ch) ((ch) & 31)
/* Register Offsets *********************************************************************************/ /* Register Offsets *********************************************************/
/* Register Offsets relative to the VIM Parity Frame */ /* Register Offsets relative to the VIM Parity Frame */
@ -87,7 +87,7 @@
#define TMS570_VIM_CHANCTRL_INDEX(n) ((n) >> 2) #define TMS570_VIM_CHANCTRL_INDEX(n) ((n) >> 2)
#define TMS570_VIM_CHANCTRL_OFFSET(n) (0x0080 << (TMS570_VIM_CHANCTRL_INDEX(n) << 2)) #define TMS570_VIM_CHANCTRL_OFFSET(n) (0x0080 << (TMS570_VIM_CHANCTRL_INDEX(n) << 2))
/* Register Addresses *******************************************************************************/ /* Register Addresses *******************************************************/
/* VIM Parity Frame Registers */ /* VIM Parity Frame Registers */
@ -132,14 +132,17 @@
#define TMS570_VIM_CHANCTRL(n) (TMS570_VIM_BASE+TMS570_VIM_CHANCTRL_OFFSET(n)) #define TMS570_VIM_CHANCTRL(n) (TMS570_VIM_BASE+TMS570_VIM_CHANCTRL_OFFSET(n))
/* Register Bit-Field Definitions *******************************************************************/ /* Register Bit-Field Definitions *******************************************/
/* Interrupt Vector Table Parity Flag Register */ /* Interrupt Vector Table Parity Flag Register */
#define VIM_PARFLG_ #define VIM_PARFLG_
/* Interrupt Vector Table Parity Control Register */ /* Interrupt Vector Table Parity Control Register */
#define VIM_PARCTL_ #define VIM_PARCTL_
/* Address Parity Error Register */ /* Address Parity Error Register */
#define VIM_ADDERR_ #define VIM_ADDERR_
/* Fall-Back Address Parity Error Register */ /* Fall-Back Address Parity Error Register */
#define VIM_FBPARERR_ #define VIM_FBPARERR_
@ -153,44 +156,64 @@
/* FIQ/IRQ Program Control Register 0 */ /* FIQ/IRQ Program Control Register 0 */
#define VIM_FIRQPR0_ #define VIM_FIRQPR0_
/* FIQ/IRQ Program Control Register 1 */ /* FIQ/IRQ Program Control Register 1 */
#define VIM_FIRQPR1_ #define VIM_FIRQPR1_
/* FIQ/IRQ Program Control Register 2 */ /* FIQ/IRQ Program Control Register 2 */
#define VIM_FIRQPR2_ #define VIM_FIRQPR2_
/* Pending Interrupt Read Location Register 0 */ /* Pending Interrupt Read Location Register 0 */
#define VIM_INTREQ0_ #define VIM_INTREQ0_
/* Pending Interrupt Read Location Register 1 */ /* Pending Interrupt Read Location Register 1 */
#define VIM_INTREQ1_ #define VIM_INTREQ1_
/* Pending Interrupt Read Location Register 2 */ /* Pending Interrupt Read Location Register 2 */
#define VIM_INTREQ2_ #define VIM_INTREQ2_
/* Interrupt Enable Set Register 0 */ /* Interrupt Enable Set Register 0 */
#define VIM_REQENASET0_ #define VIM_REQENASET0_
/* Interrupt Enable Set Register 1 */ /* Interrupt Enable Set Register 1 */
#define VIM_REQENASET1_ #define VIM_REQENASET1_
/* Interrupt Enable Set Register 2 */ /* Interrupt Enable Set Register 2 */
#define VIM_REQENASET2_ #define VIM_REQENASET2_
/* Interrupt Enable Clear Register 0 */ /* Interrupt Enable Clear Register 0 */
#define VIM_REQENACLR0_ #define VIM_REQENACLR0_
/* Interrupt Enable Clear Register 1 */ /* Interrupt Enable Clear Register 1 */
#define VIM_REQENACLR1_ #define VIM_REQENACLR1_
/* Interrupt Enable Clear Register 2 */ /* Interrupt Enable Clear Register 2 */
#define VIM_REQENACLR2_ #define VIM_REQENACLR2_
/* Wake-up Enable Set Register 0 */ /* Wake-up Enable Set Register 0 */
#define VIM_WAKEENASET0_ #define VIM_WAKEENASET0_
/* Wake-up Enable Set Register 1 */ /* Wake-up Enable Set Register 1 */
#define VIM_WAKEENASET1_ #define VIM_WAKEENASET1_
/* Wake-up Enable Set Register 2 */ /* Wake-up Enable Set Register 2 */
#define VIM_WAKEENASET2_ #define VIM_WAKEENASET2_
/* Wake-up Enable Clear Register 0 */ /* Wake-up Enable Clear Register 0 */
#define VIM_WAKEENACLR0_ #define VIM_WAKEENACLR0_
/* Wake-up Enable Clear Register 1 */ /* Wake-up Enable Clear Register 1 */
#define VIM_WAKEENACLR1_ #define VIM_WAKEENACLR1_
/* Wake-up Enable Clear Register 2 */ /* Wake-up Enable Clear Register 2 */
#define VIM_WAKEENACLR2_ #define VIM_WAKEENACLR2_
/* IRQ Interrupt Vector Register */ /* IRQ Interrupt Vector Register */
#define VIM_IRQVECREG_ #define VIM_IRQVECREG_
/* FIQ Interrupt Vector Register */ /* FIQ Interrupt Vector Register */
#define VIM_FIQVECREG_ #define VIM_FIQVECREG_
/* Capture Event Register */ /* Capture Event Register */
#define VIM_CAPEVT_ #define VIM_CAPEVT_

12
arch/arm/src/tms570/hardware/tms570ls04x03x_memorymap.h
View File

@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570ls04x03x_memorymap.h * arch/arm/src/tms570/hardware/tms570ls04x03x_memorymap.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,20 +16,20 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
****************************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_MEMORYMAP_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_MEMORYMAP_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_MEMORYMAP_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_MEMORYMAP_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/**************************************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************************************/ ****************************************************************************/
/* Memory Map Overview */ /* Memory Map Overview */

12
arch/arm/src/tms570/hardware/tms570ls04x03x_pinmux.h
View File

@ -1,4 +1,4 @@
/**************************************************************************************************** /****************************************************************************
* arch/arm/src/tms570/hardware/tms570ls04x03x_pinmux.h * arch/arm/src/tms570/hardware/tms570ls04x03x_pinmux.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -17,7 +17,7 @@
* under the License. * under the License.
* *
* *
****************************************************************************************************/ ****************************************************************************/
/* References: /* References:
* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller,
@ -28,16 +28,16 @@
#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_PINMUX_H #ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_PINMUX_H
#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_PINMUX_H #define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_PINMUX_H
/**************************************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "hardware/tms570_memorymap.h" #include "hardware/tms570_memorymap.h"
/**************************************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************************************/ ****************************************************************************/
/* DEFAULT SELECTION ALTERNATE SELECTION ALTERNATE SELECTION BIT /* DEFAULT SELECTION ALTERNATE SELECTION ALTERNATE SELECTION BIT
* FUNCTION BIT FUNCTION 1 BIT FUNCTION 2 BIT * FUNCTION BIT FUNCTION 1 BIT FUNCTION 2 BIT

49
arch/arm/src/tms570/tms570_boot.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/arm/src/tms570/tms570_boot.h * arch/arm/src/tms570/tms570_boot.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_TMS570_TMS570_BOOT_H #ifndef __ARCH_ARM_SRC_TMS570_TMS570_BOOT_H
#define __ARCH_ARM_SRC_TMS570_TMS570_BOOT_H #define __ARCH_ARM_SRC_TMS570_TMS570_BOOT_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <nuttx/compiler.h> #include <nuttx/compiler.h>
@ -46,48 +46,51 @@ extern "C"
#define EXTERN extern #define EXTERN extern
#endif #endif
/************************************************************************************ /****************************************************************************
* Public Function Prototypes * Public Function Prototypes
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Name: tms570_lowsetup * Name: tms570_lowsetup
* *
* Description: * Description:
* Called at the very beginning of _start. Performs low level initialization * Called at the very beginning of _start.
* including setup of the console SCI. This SCI done early so that the serial * Performs low level initialization including setup of the console SCI.
* console is available for debugging very early in the boot sequence. * This SCI done early so that the serial console is available for
* debugging very early in the boot sequence.
* *
************************************************************************************/ ****************************************************************************/
void tms570_lowsetup(void); void tms570_lowsetup(void);
/************************************************************************************ /****************************************************************************
* Name: tms570_boardinitialize * Name: tms570_boardinitialize
* *
* Description: * Description:
* All TMS570 architectures must provide the following entry point. This function * All TMS570 architectures must provide the following entry point. This
* is called near the beginning of _start. This function is called after clocking * function is called near the beginning of _start. This function is
* has been configured but before caches have been enabled and before any devices * called after clocking has been configured but before caches have been
* have been initialized. .data/.bss memory may or may not have been initialized * enabled and before any devices have been initialized.
* .data/.bss memory may or may not have been initialized
* (see the "special precautions" below). * (see the "special precautions" below).
* *
* This function must perform low level initialization including * This function must perform low level initialization including
* *
* - Initialization of board-specific memory resources (e.g., SDRAM) * - Initialization of board-specific memory resources (e.g., SDRAM)
* - Configuration of board specific resources (GIOs, LEDs, etc). * - Configuration of board specific resources (GIOs, LEDs, etc).
* - Setup of the console SCI. This SCI done early so that the serial console * - Setup of the console SCI. This SCI done early so that the serial
* is available for debugging very early in the boot sequence. * console is available for debugging very early in the boot sequence.
* *
* Special precautions must be taken if .data/.bss lie in SRAM. in that case, * Special precautions must be taken if .data/.bss lie in SRAM. in that
* the boot logic cannot initialize .data or .bss. The function must then: * case, the boot logic cannot initialize .data or .bss.
* The function must then:
* *
* - Take precautions to assume that logic does not access any global data that * - Take precautions to assume that logic does not access any global data
* might lie in SDRAM. * that might lie in SDRAM.
* - Call the function arm_data_initialize() as soon as SDRAM has been * - Call the function arm_data_initialize() as soon as SDRAM has been
* properly configured for use. * properly configured for use.
* *
************************************************************************************/ ****************************************************************************/
void tms570_board_initialize(void); void tms570_board_initialize(void);

7
arch/arm/src/tms570/tms570_clockconfig.h
View File

@ -50,9 +50,10 @@ extern "C"
* Name: tms570_clockconfig * Name: tms570_clockconfig
* *
* Description: * Description:
* Called to initialize TMS570 clocking. This does whatever setup is needed to * Called to initialize TMS570 clocking.
* put the SoC in a usable state. This includes, but is not limited to, the * This does whatever setup is needed to put the SoC in a usable state.
* initialization of clocking using the settings in the board.h header file. * This includes, but is not limited to, theinitialization of clocking
* using the settings in the board.h header file.
* *
****************************************************************************/ ****************************************************************************/

21
arch/arm/src/tms570/tms570_gio.c
View File

@ -89,7 +89,9 @@ int tms570_gio_initialize(void)
putreg32(GIO_GCR0_RESET, TMS570_GIO_GCR0); putreg32(GIO_GCR0_RESET, TMS570_GIO_GCR0);
/* Disable all pin interrupts on the pin. Make sure they are all level 0. */ /* Disable all pin interrupts on the pin.
* Make sure they are all level 0.
*/
putreg32(0xffffffff, TMS570_GIO_ENACLR); putreg32(0xffffffff, TMS570_GIO_ENACLR);
putreg32(0xffffffff, TMS570_GIO_LVLCLR); putreg32(0xffffffff, TMS570_GIO_LVLCLR);
@ -129,6 +131,7 @@ int tms570_configgio(gio_pinset_t cfgset)
putreg32(GIO_LVLCLR_PORT_PIN(port, pin), TMS570_GIO_LVLCLR); putreg32(GIO_LVLCLR_PORT_PIN(port, pin), TMS570_GIO_LVLCLR);
/* Setup settings common to both input and output pins */ /* Setup settings common to both input and output pins */
/* Enable/disable the pull-up/down as requested */ /* Enable/disable the pull-up/down as requested */
switch (cfgset & GIO_CFG_MASK) switch (cfgset & GIO_CFG_MASK)
@ -266,13 +269,14 @@ bool tms570_gioread(gio_pinset_t pinset)
return (regval & pinmask) != 0; return (regval & pinmask) != 0;
} }
/************************************************************************************ /****************************************************************************
* Function: tms570_dumpgio * Function: tms570_dumpgio
* *
* Description: * Description:
* Dump all GIO registers associated with the base address of the provided pinset. * Dump all GIO registers associated with the base address of the provided
* pinset.
* *
************************************************************************************/ ****************************************************************************/
#ifdef CONFIG_DEBUG_GPIO_INFO #ifdef CONFIG_DEBUG_GPIO_INFO
int tms570_dumpgio(uint32_t pinset, const char *msg) int tms570_dumpgio(uint32_t pinset, const char *msg)
@ -305,10 +309,13 @@ int tms570_dumpgio(uint32_t pinset, const char *msg)
/* Port specific registers */ /* Port specific registers */
_info(" DIR: %08x DIN: %08x DOUT: %08x PDR: %08x\n", _info(" DIR: %08x DIN: %08x DOUT: %08x PDR: %08x\n",
getreg32(base + TMS570_GIO_DIR_OFFSET), getreg32(base + TMS570_GIO_DIN_OFFSET), getreg32(base + TMS570_GIO_DIR_OFFSET),
getreg32(base + TMS570_GIO_DOUT_OFFSET), getreg32(base + TMS570_GIO_PDR_OFFSET)); getreg32(base + TMS570_GIO_DIN_OFFSET),
getreg32(base + TMS570_GIO_DOUT_OFFSET),
getreg32(base + TMS570_GIO_PDR_OFFSET));
_info(" PULDIS: %08x PSL: %08x\n", _info(" PULDIS: %08x PSL: %08x\n",
getreg32(base + TMS570_GIO_PULDIS_OFFSET), getreg32(base + TMS570_GIO_PSL_OFFSET)); getreg32(base + TMS570_GIO_PULDIS_OFFSET),
getreg32(base + TMS570_GIO_PSL_OFFSET));
leave_critical_section(flags); leave_critical_section(flags);
return OK; return OK;

71
arch/arm/src/tms570/tms570_gio.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/arm/src/tms570/tms570_gio.h * arch/arm/src/tms570/tms570_gio.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_TMS570_TMS570_GIO_H #ifndef __ARCH_ARM_SRC_TMS570_TMS570_GIO_H
#define __ARCH_ARM_SRC_TMS570_TMS570_GIO_H #define __ARCH_ARM_SRC_TMS570_TMS570_GIO_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
@ -33,11 +33,11 @@
#include "hardware/tms570_gio.h" #include "hardware/tms570_gio.h"
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Bit-encoded input to tms570_configgio() ********************************************/ /* Bit-encoded input to tms570_configgio() **********************************/
/* 32-bit Encoding: /* 32-bit Encoding:
* *
@ -85,7 +85,8 @@
#define GIO_OPENDRAIN (1 << 9) /* Bit 9: Open drain mode */ #define GIO_OPENDRAIN (1 << 9) /* Bit 9: Open drain mode */
/* If the pin is an GIO output, then this identifies the initial output value: /* If the pin is an GIO output, then this identifies the initial output
* value:
* *
* .... .... .... .... .... ...V .... .... * .... .... .... .... .... ...V .... ....
*/ */
@ -125,9 +126,9 @@
# define GIO_PIN6 (6 << GIO_PIN_SHIFT) # define GIO_PIN6 (6 << GIO_PIN_SHIFT)
# define GIO_PIN7 (7 << GIO_PIN_SHIFT) # define GIO_PIN7 (7 << GIO_PIN_SHIFT)
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
@ -135,9 +136,9 @@
typedef uint16_t gio_pinset_t; typedef uint16_t gio_pinset_t;
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
#undef EXTERN #undef EXTERN
#if defined(__cplusplus) #if defined(__cplusplus)
@ -148,9 +149,9 @@ extern "C"
#define EXTERN extern #define EXTERN extern
#endif #endif
/************************************************************************************ /****************************************************************************
* Inline Functions * Inline Functions
************************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
* Name: tms570_gio_base * Name: tms570_gio_base
@ -205,9 +206,9 @@ static inline int tms570_gio_pinmask(gio_pinset_t cfgset)
return 1 << ((cfgset & GIO_PIN_MASK) >> GIO_PIN_SHIFT); return 1 << ((cfgset & GIO_PIN_MASK) >> GIO_PIN_SHIFT);
} }
/************************************************************************************ /****************************************************************************
* Public Function Prototypes * Public Function Prototypes
************************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
* Name: tms570_gio_initialize * Name: tms570_gio_initialize
@ -219,13 +220,14 @@ static inline int tms570_gio_pinmask(gio_pinset_t cfgset)
int tms570_gio_initialize(void); int tms570_gio_initialize(void);
/************************************************************************************ /****************************************************************************
* Name: tms570_gioirq_initialize * Name: tms570_gioirq_initialize
* *
* Description: * Description:
* Initialize logic to support a second level of interrupt decoding for GIO pins. * Initialize logic to support a second level of interrupt decoding for GIO
* pins.
* *
************************************************************************************/ ****************************************************************************/
#ifdef CONFIG_TMS570_GIO_IRQ #ifdef CONFIG_TMS570_GIO_IRQ
void tms570_gioirq_initialize(void); void tms570_gioirq_initialize(void);
@ -233,43 +235,43 @@ void tms570_gioirq_initialize(void);
# define tms570_gioirq_initialize() # define tms570_gioirq_initialize()
#endif #endif
/************************************************************************************ /****************************************************************************
* Name: tms570_configgio * Name: tms570_configgio
* *
* Description: * Description:
* Configure a GIO pin based on bit-encoded description of the pin. * Configure a GIO pin based on bit-encoded description of the pin.
* *
************************************************************************************/ ****************************************************************************/
int tms570_configgio(gio_pinset_t cfgset); int tms570_configgio(gio_pinset_t cfgset);
/************************************************************************************ /****************************************************************************
* Name: tms570_giowrite * Name: tms570_giowrite
* *
* Description: * Description:
* Write one or zero to the selected GIO pin * Write one or zero to the selected GIO pin
* *
************************************************************************************/ ****************************************************************************/
void tms570_giowrite(gio_pinset_t pinset, bool value); void tms570_giowrite(gio_pinset_t pinset, bool value);
/************************************************************************************ /****************************************************************************
* Name: tms570_gioread * Name: tms570_gioread
* *
* Description: * Description:
* Read one or zero from the selected GIO pin * Read one or zero from the selected GIO pin
* *
************************************************************************************/ ****************************************************************************/
bool tms570_gioread(gio_pinset_t pinset); bool tms570_gioread(gio_pinset_t pinset);
/************************************************************************************ /****************************************************************************
* Name: tms570_gioirq * Name: tms570_gioirq
* *
* Description: * Description:
* Configure an interrupt for the specified GIO pin. * Configure an interrupt for the specified GIO pin.
* *
************************************************************************************/ ****************************************************************************/
#ifdef CONFIG_TMS570_GIO_IRQ #ifdef CONFIG_TMS570_GIO_IRQ
void tms570_gioirq(gio_pinset_t pinset); void tms570_gioirq(gio_pinset_t pinset);
@ -277,13 +279,13 @@ void tms570_gioirq(gio_pinset_t pinset);
# define tms570_gioirq(pinset) # define tms570_gioirq(pinset)
#endif #endif
/************************************************************************************ /****************************************************************************
* Name: tms570_gioirqenable * Name: tms570_gioirqenable
* *
* Description: * Description:
* Enable the interrupt for specified GIO IRQ * Enable the interrupt for specified GIO IRQ
* *
************************************************************************************/ ****************************************************************************/
#ifdef CONFIG_TMS570_GIO_IRQ #ifdef CONFIG_TMS570_GIO_IRQ
void tms570_gioirqenable(int irq); void tms570_gioirqenable(int irq);
@ -291,13 +293,13 @@ void tms570_gioirqenable(int irq);
# define tms570_gioirqenable(irq) # define tms570_gioirqenable(irq)
#endif #endif
/************************************************************************************ /****************************************************************************
* Name: tms570_gioirqdisable * Name: tms570_gioirqdisable
* *
* Description: * Description:
* Disable the interrupt for specified GIO IRQ * Disable the interrupt for specified GIO IRQ
* *
************************************************************************************/ ****************************************************************************/
#ifdef CONFIG_TMS570_GIO_IRQ #ifdef CONFIG_TMS570_GIO_IRQ
void tms570_gioirqdisable(int irq); void tms570_gioirqdisable(int irq);
@ -305,13 +307,14 @@ void tms570_gioirqdisable(int irq);
# define tms570_gioirqdisable(irq) # define tms570_gioirqdisable(irq)
#endif #endif
/************************************************************************************ /****************************************************************************
* Function: tms570_dumpgio * Function: tms570_dumpgio
* *
* Description: * Description:
* Dump all GIO registers associated with the base address of the provided pinset. * Dump all GIO registers associated with the base address of the provided
* pinset.
* *
************************************************************************************/ ****************************************************************************/
#ifdef CONFIG_DEBUG_GPIO_INFO #ifdef CONFIG_DEBUG_GPIO_INFO
int tms570_dumpgio(uint32_t pinset, const char *msg); int tms570_dumpgio(uint32_t pinset, const char *msg);

24
arch/arm/src/tms570/tms570_gioirq.c
View File

@ -91,7 +91,9 @@ static int tms3570_gio_interrupt(int irq, void *context, FAR void *arg)
void tms570_gioirq_initialize(void) void tms570_gioirq_initialize(void)
{ {
/* Disable all pin interrupts on the pin. Make sure they are all level 0. */ /* Disable all pin interrupts on the pin.
* Make sure they are all level 0.
*/
putreg32(0xffffffff, TMS570_GIO_ENACLR); putreg32(0xffffffff, TMS570_GIO_ENACLR);
putreg32(0xffffffff, TMS570_GIO_LVLCLR); putreg32(0xffffffff, TMS570_GIO_LVLCLR);
@ -102,13 +104,13 @@ void tms570_gioirq_initialize(void)
up_enable_irq(TMS570_REQ_GIO_0); up_enable_irq(TMS570_REQ_GIO_0);
} }
/************************************************************************************ /****************************************************************************
* Name: tms570_gioirq * Name: tms570_gioirq
* *
* Description: * Description:
* Configure an interrupt for the specified GIO pin. * Configure an interrupt for the specified GIO pin.
* *
************************************************************************************/ ****************************************************************************/
void tms570_gioirq(gio_pinset_t pinset) void tms570_gioirq(gio_pinset_t pinset)
{ {
@ -117,13 +119,15 @@ void tms570_gioirq(gio_pinset_t pinset)
irqstate_t flags; irqstate_t flags;
uint32_t regval; uint32_t regval;
/* Start with the pin interrupts disabled. Make sure that level 0 is selected. */ /* Start with the pin interrupts disabled.
* Make sure that level 0 is selected.
*/
putreg32(GIO_ENACLR_PORT_PIN(port, pin), TMS570_GIO_ENACLR); putreg32(GIO_ENACLR_PORT_PIN(port, pin), TMS570_GIO_ENACLR);
putreg32(GIO_LVLCLR_PORT_PIN(port, pin), TMS570_GIO_LVLCLR); putreg32(GIO_LVLCLR_PORT_PIN(port, pin), TMS570_GIO_LVLCLR);
/* Make sure that the pin is configured as an input and that interrupts can e /* Make sure that the pin is configured as an input and that interrupts can
* supported on this port. * e supported on this port.
*/ */
if ((pinset & GIO_MODE_MASK) == GIO_INPUT && port < TMS570_NIRQPORTS) if ((pinset & GIO_MODE_MASK) == GIO_INPUT && port < TMS570_NIRQPORTS)
@ -182,13 +186,13 @@ void tms570_gioirq(gio_pinset_t pinset)
} }
} }
/************************************************************************************ /****************************************************************************
* Name: tms570_gioirqenable * Name: tms570_gioirqenable
* *
* Description: * Description:
* Enable the interrupt for specified GIO IRQ * Enable the interrupt for specified GIO IRQ
* *
************************************************************************************/ ****************************************************************************/
void tms570_gioirqenable(int irq) void tms570_gioirqenable(int irq)
{ {
@ -210,13 +214,13 @@ void tms570_gioirqenable(int irq)
} }
} }
/************************************************************************************ /****************************************************************************
* Name: tms570_gioirqdisable * Name: tms570_gioirqdisable
* *
* Description: * Description:
* Disable the interrupt for specified GIO IRQ * Disable the interrupt for specified GIO IRQ
* *
************************************************************************************/ ****************************************************************************/
void tms570_gioirqdisable(int irq) void tms570_gioirqdisable(int irq)
{ {

46
arch/arm/src/tms570/tms570_lowputc.h
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@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/arm/src/tms570/tms570_lowputc.h * arch/arm/src/tms570/tms570_lowputc.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_TMS570_TMS570_LOWPUTC_H #ifndef __ARCH_ARM_SRC_TMS570_TMS570_LOWPUTC_H
#define __ARCH_ARM_SRC_TMS570_TMS570_LOWPUTC_H #define __ARCH_ARM_SRC_TMS570_TMS570_LOWPUTC_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <nuttx/compiler.h> #include <nuttx/compiler.h>
@ -35,13 +35,13 @@
#include "arm_internal.h" #include "arm_internal.h"
#include "chip.h" #include "chip.h"
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/* This structure describes the configuration of an SCI UART */ /* This structure describes the configuration of an SCI UART */
@ -53,15 +53,15 @@ struct sci_config_s
bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
}; };
/************************************************************************************ /****************************************************************************
* Inline Functions * Inline Functions
************************************************************************************/ ****************************************************************************/
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
#undef EXTERN #undef EXTERN
#if defined(__cplusplus) #if defined(__cplusplus)
@ -72,31 +72,33 @@ extern "C"
#define EXTERN extern #define EXTERN extern
#endif #endif
/************************************************************************************ /****************************************************************************
* Public Function Prototypes * Public Function Prototypes
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Name: tms570_lowsetup * Name: tms570_lowsetup
* *
* Description: * Description:
* Called at the very beginning of _start. Performs low level initialization * Called at the very beginning of _start.
* including setup of the console SCI. This SCI done early so that the serial * Performs low level initialization including setup of the console SCI.
* console is available for debugging very early in the boot sequence. * This SCI done early so that the serial console is available for
* debugging very early in the boot sequence.
* *
************************************************************************************/ ****************************************************************************/
void tms570_lowsetup(void); void tms570_lowsetup(void);
/************************************************************************************ /****************************************************************************
* Name: tms570_sci_configure * Name: tms570_sci_configure
* *
* Description: * Description:
* Configure an SCI for non-interrupt driven operation * Configure an SCI for non-interrupt driven operation
* *
************************************************************************************/ ****************************************************************************/
int tms570_sci_configure(uint32_t base, FAR const struct sci_config_s *config); int tms570_sci_configure(uint32_t base,
FAR const struct sci_config_s *config);
#undef EXTERN #undef EXTERN
#if defined(__cplusplus) #if defined(__cplusplus)

1
arch/arm/src/tms570/tms570_timerisr.c
View File

@ -38,6 +38,7 @@
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
/* The input clock to the RTI is the RTICLK. The RTI source is always VCLK /* The input clock to the RTI is the RTICLK. The RTI source is always VCLK
* which may be divided down by 2. The correct RTICLK frequency must be * which may be divided down by 2. The correct RTICLK frequency must be
* provided by board.h file as BOARD_RTICLK_FREQUENCY. * provided by board.h file as BOARD_RTICLK_FREQUENCY.