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arch/risc-v: Remove dupped irq code from mpfs

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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2022-01-20 23:10:35 +08:00 committed by Xiang Xiao
parent 6dc4dd207f
commit d846bb0235
5 changed files with 26 additions and 20 deletions
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8
arch/risc-v/include/irq.h
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@ -58,9 +58,13 @@
#define RISCV_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */
#define RISCV_IRQ_SAFAULT (7) /* Store/AMO Access Fault */
#define RISCV_IRQ_ECALLU (8) /* Environment Call from U-mode */
/* 9-10: Reserved */
#define RISCV_IRQ_ECALLS (9) /* Environment Call from S-mode */
#define RISCV_IRQ_ECALLH (10) /* Environment Call from H-mode */
#define RISCV_IRQ_ECALLM (11) /* Environment Call from M-mode */
/* 12-15: Reserved */
#define RISCV_IRQ_INSTRUCTIONPF (12) /* Instruction page fault */
#define RISCV_IRQ_LOADPF (13) /* Load page fault */
#define RISCV_IRQ_RESERVED (14) /* Reserved */
#define RISCV_IRQ_SROREPF (15) /* Store/AMO page fault */
/* IRQ 16- : (async event:interrupt=1) */

4
arch/risc-v/include/mpfs/irq.h
View File

@ -33,7 +33,9 @@
/* Map RISC-V exception code to NuttX IRQ */
#define MPFS_IRQ_LOCAL_START (RISCV_IRQ_ASYNC + 16)
#define MPFS_IRQ_ASYNC RISCV_IRQ_ASYNC
#define MPFS_IRQ_LOCAL_START (MPFS_IRQ_ASYNC + 16)
#define MPFS_IRQ_LOCAL_0 (MPFS_IRQ_LOCAL_START + 0) /* Local 0 spare */
#define MPFS_IRQ_LOCAL_1 (MPFS_IRQ_LOCAL_START + 1) /* Local 1 spare */
#define MPFS_IRQ_LOCAL_2 (MPFS_IRQ_LOCAL_START + 2) /* Local 2 spare */

14
arch/risc-v/src/mpfs/mpfs_irq.c
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@ -59,7 +59,7 @@ void up_irqinitialize(void)
/* Disable timer interrupt (in case of hotloading with debugger) */
up_disable_irq(MPFS_IRQ_MTIMER);
up_disable_irq(RISCV_IRQ_MTIMER);
/* enable access from supervisor mode */
@ -141,10 +141,10 @@ void up_irqinitialize(void)
/* Attach the ecall interrupt handler */
irq_attach(MPFS_IRQ_ECALLM, riscv_swint, NULL);
irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
#ifdef CONFIG_BUILD_PROTECTED
irq_attach(MPFS_IRQ_ECALLU, riscv_swint, NULL);
irq_attach(RISCV_IRQ_ECALLU, riscv_swint, NULL);
#endif
#ifndef CONFIG_SUPPRESS_INTERRUPTS
@ -168,13 +168,13 @@ void up_disable_irq(int irq)
int extirq = 0;
uint64_t oldstat = 0;
if (irq == MPFS_IRQ_MSOFT)
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & clear machine software interrupt enable in mie */
asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
}
else if (irq == MPFS_IRQ_MTIMER)
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & clear machine timer interrupt enable in mie */
@ -223,13 +223,13 @@ void up_enable_irq(int irq)
int extirq;
uint64_t oldstat;
if (irq == MPFS_IRQ_MSOFT)
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & set machine software interrupt enable in mie */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
}
else if (irq == MPFS_IRQ_MTIMER)
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & set machine timer interrupt enable in mie */

16
arch/risc-v/src/mpfs/mpfs_irq_dispatch.c
View File

@ -62,11 +62,11 @@ void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs)
/* Check if fault happened */
if (vector < MPFS_IRQ_ECALLU ||
vector == MPFS_IRQ_INSTRUCTIONPF ||
vector == MPFS_IRQ_LOADPF ||
vector == MPFS_IRQ_SROREPF ||
vector == MPFS_IRQ_RESERVED)
if (vector < RISCV_IRQ_ECALLU ||
vector == RISCV_IRQ_INSTRUCTIONPF ||
vector == RISCV_IRQ_LOADPF ||
vector == RISCV_IRQ_SROREPF ||
vector == RISCV_IRQ_RESERVED)
{
up_fault((int)irq, regs);
}
@ -91,7 +91,7 @@ void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs)
((hart_id - 1) * MPFS_PLIC_NEXTHART_OFFSET);
}
if (irq == MPFS_IRQ_MEXT)
if (irq == RISCV_IRQ_MEXT)
{
uint32_t ext = getreg32(claim_address);
@ -102,7 +102,7 @@ void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs)
/* NOTE: In case of ecall, we need to adjust mepc in the context */
if (irq == MPFS_IRQ_ECALLM || irq == MPFS_IRQ_ECALLU)
if (irq == RISCV_IRQ_ECALLM || irq == RISCV_IRQ_ECALLU)
{
*mepc += 4;
}
@ -125,7 +125,7 @@ void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs)
/* MEXT means no interrupt */
if (irq != MPFS_IRQ_MEXT && irq != MPFS_IRQ_INVALID)
if (irq != RISCV_IRQ_MEXT && irq != MPFS_IRQ_INVALID)
{
/* Deliver the IRQ */

4
arch/risc-v/src/mpfs/mpfs_timerisr.c
View File

@ -120,7 +120,7 @@ void up_timer_initialize(void)
/* Attach timer interrupt handler */
irq_attach(MPFS_IRQ_MTIMER, mpfs_timerisr, NULL);
irq_attach(RISCV_IRQ_MTIMER, mpfs_timerisr, NULL);
/* Reload CLINT mtimecmp */
@ -128,5 +128,5 @@ void up_timer_initialize(void)
/* And enable the timer interrupt */
up_enable_irq(MPFS_IRQ_MTIMER);
up_enable_irq(RISCV_IRQ_MTIMER);
}