Fixe LM3S GPIO output settings; fix Eagle-100 LEDs
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1823 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -47,7 +47,7 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
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CHIP_ASRCS =
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CHIP_CSRCS = lm3s_start.c lm3s_syscontrol.c lm3s_irq.c \
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lm3s_gpio.c lm3s_gpioirq.c lm3s_timerisr.c lm3s_lowputc.c \
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lm3s_serial.c lm3s_ssi.c
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lm3s_serial.c lm3s_ssi.c lm3s_dumpgpio.c
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ifdef CONFIG_NET
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CHIP_CSRCS += lm3s_ethernet.c
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154
arch/arm/src/lm3s/lm3s_dumpgpio.c
Normal file
154
arch/arm/src/lm3s/lm3s_dumpgpio.c
Normal file
@ -0,0 +1,154 @@
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/****************************************************************************
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* arch/arm/src/lm3s/lm3s_dumpgpio.c
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include "up_arch.h"
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#include "chip.h"
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#include "lm3s_internal.h"
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* NOTE: this is duplicated in lm3s_gpio.c */
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static const uint32 g_gpiobase[8] =
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{
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LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
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LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE,
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};
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static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lm3s_gpiobaseaddress
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*
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* Description:
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* Given a GPIO enumeration value, return the base address of the
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* associated GPIO registers.
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*
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****************************************************************************/
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static inline uint32 lm3s_gpiobaseaddress(int port)
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{
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return g_gpiobase[port & 7];
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}
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/****************************************************************************
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* Name: lm3s_gpioport
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*
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* Description:
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* Given a GPIO enumeration value, return the base address of the
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* associated GPIO registers.
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*
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****************************************************************************/
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static inline ubyte lm3s_gpioport(int port)
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{
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return g_portchar[port & 7];
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}
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/****************************************************************************
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* Global Functions
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****************************************************************************/
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/****************************************************************************
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* Function: lm3s_dumpgpio
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*
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* Description:
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* Dump all GPIO registers associated with the provided base address
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*
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****************************************************************************/
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int lm3s_dumpgpio(uint32 pinset, const char *msg)
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{
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irqstate_t flags;
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unsigned int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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uint32 base;
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uint32 rcgc2;
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boolean enabled;
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/* Get the base address associated with the GPIO port */
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base = lm3s_gpiobaseaddress(port);
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/* The following requires exclusive access to the GPIO registers */
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flags = irqsave();
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rcgc2 = getreg32(LM3S_SYSCON_RCGC2);
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enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0);
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lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
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lm3s_gpioport(port), pinset, base, msg);
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lldbg(" RCGC2: %08x (%s)\n",
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rcgc2, enabled ? "enabled" : "disabled" );
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/* Don't bother with the rest unless the port is enabled */
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if (enabled)
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{
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lldbg(" AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n",
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getreg32(base + LM3S_GPIO_AFSEL_OFFSET), getreg32(base + LM3S_GPIO_DEN_OFFSET),
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getreg32(base + LM3S_GPIO_DIR_OFFSET), getreg32(base + LM3S_GPIO_DATA_OFFSET + 0x3fc));
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lldbg(" IS: %02x IBE: %02x IEV: %02x IM: %02x RIS: %02x MIS: %02x\n",
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getreg32(base + LM3S_GPIO_IEV_OFFSET), getreg32(base + LM3S_GPIO_IM_OFFSET),
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getreg32(base + LM3S_GPIO_RIS_OFFSET), getreg32(base + LM3S_GPIO_MIS_OFFSET));
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lldbg(" 2MA: %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n",
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getreg32(base + LM3S_GPIO_DR2R_OFFSET), getreg32(base + LM3S_GPIO_DR4R_OFFSET),
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getreg32(base + LM3S_GPIO_DR8R_OFFSET), getreg32(base + LM3S_GPIO_ODR_OFFSET),
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getreg32(base + LM3S_GPIO_PUR_OFFSET), getreg32(base + LM3S_GPIO_PDR_OFFSET),
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getreg32(base + LM3S_GPIO_SLR_OFFSET));
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}
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irqrestore(flags);
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}
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@ -789,7 +789,7 @@ void lm3s_gpiowrite(uint32 pinset, boolean value)
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* "... All bits are cleared by a reset."
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*/
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putreg32((uint32)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (pinno << 2));
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putreg32((uint32)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
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}
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/****************************************************************************
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@ -828,5 +828,5 @@ boolean lm3s_gpioread(uint32 pinset, boolean value)
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* are cleared by a reset."
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*/
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return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (pinno << 2)) != 0);
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return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
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}
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@ -279,6 +279,16 @@ EXTERN void lm3s_gpiowrite(uint32 pinset, boolean value);
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EXTERN boolean lm3s_gpioread(uint32 pinset, boolean value);
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/****************************************************************************
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* Function: lm3s_dumpgpio
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*
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* Description:
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* Dump all GPIO registers associated with the provided base address
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*
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****************************************************************************/
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EXTERN int lm3s_dumpgpio(uint32 pinset, const char *msg);
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/****************************************************************************
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* Name: gpio_irqinitialize
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*
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