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arm_gicv2: accesses the non-secure copy in non-secure state

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Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
This commit is contained in:
zhangyuan21 2023-06-27 08:47:06 +08:00 committed by Xiang Xiao
parent 601202ee4a
commit d8797bde4e
2 changed files with 6 additions and 6 deletions
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6
arch/arm/src/armv7-a/arm_gicv2.c
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@ -189,7 +189,7 @@ void arm_gic_initialize(void)
#elif defined(CONFIG_ARCH_TRUSTZONE_NONSECURE) #elif defined(CONFIG_ARCH_TRUSTZONE_NONSECURE)
/* Clear non-secure state ICCICR bits to be configured below */ /* Clear non-secure state ICCICR bits to be configured below */
iccicr &= ~(GIC_ICCICRS_EOIMODENS | GIC_ICCICRU_ENABLEGRP1 | iccicr &= ~(GIC_ICCICRU_EOIMODENS | GIC_ICCICRU_ENABLEGRP1 |
GIC_ICCICRU_FIQBYPDISGRP1 | GIC_ICCICRU_IRQBYPDISGRP1); GIC_ICCICRU_FIQBYPDISGRP1 | GIC_ICCICRU_IRQBYPDISGRP1);
#endif #endif
@ -260,7 +260,7 @@ void arm_gic_initialize(void)
* NOTE: Only for processors that operate in non-secure state. * NOTE: Only for processors that operate in non-secure state.
*/ */
iccicr |= GIC_ICCICRS_EOIMODENS; iccicr |= GIC_ICCICRU_EOIMODENS;
# elif defined(CONFIG_ARCH_TRUSTZONE_BOTH) # elif defined(CONFIG_ARCH_TRUSTZONE_BOTH)
/* Set EnableNS=1 to enable the CPU to signal non-secure interrupts. /* Set EnableNS=1 to enable the CPU to signal non-secure interrupts.
@ -268,7 +268,7 @@ void arm_gic_initialize(void)
* NOTE: Only for processors that operate in non-secure state. * NOTE: Only for processors that operate in non-secure state.
*/ */
iccicr |= GIC_ICCICRU_EOIMODENS; iccicr |= GIC_ICCICRS_EOIMODENS;
# endif # endif
#endif #endif

6
arch/arm/src/armv7-r/arm_gicv2.c
View File

@ -189,7 +189,7 @@ void arm_gic_initialize(void)
#elif defined(CONFIG_ARCH_TRUSTZONE_NONSECURE) #elif defined(CONFIG_ARCH_TRUSTZONE_NONSECURE)
/* Clear non-secure state ICCICR bits to be configured below */ /* Clear non-secure state ICCICR bits to be configured below */
iccicr &= ~(GIC_ICCICRS_EOIMODENS | iccicr &= ~(GIC_ICCICRU_EOIMODENS |
GIC_ICCICRU_ENABLEGRP1 | GIC_ICCICRU_ENABLEGRP1 |
GIC_ICCICRU_FIQBYPDISGRP1 | GIC_ICCICRU_FIQBYPDISGRP1 |
GIC_ICCICRU_IRQBYPDISGRP1); GIC_ICCICRU_IRQBYPDISGRP1);
@ -244,7 +244,7 @@ void arm_gic_initialize(void)
* NOTE: Only for processors that operate in non-secure state. * NOTE: Only for processors that operate in non-secure state.
*/ */
iccicr |= GIC_ICCICRS_EOIMODENS; iccicr |= GIC_ICCICRU_EOIMODENS;
# elif defined(CONFIG_ARCH_TRUSTZONE_BOTH) # elif defined(CONFIG_ARCH_TRUSTZONE_BOTH)
/* Set EnableNS=1 to enable the CPU to signal non-secure interrupts. /* Set EnableNS=1 to enable the CPU to signal non-secure interrupts.
@ -252,7 +252,7 @@ void arm_gic_initialize(void)
* NOTE: Only for processors that operate in non-secure state. * NOTE: Only for processors that operate in non-secure state.
*/ */
iccicr |= GIC_ICCICRU_EOIMODENS; iccicr |= GIC_ICCICRS_EOIMODENS;
# endif # endif
#endif #endif