Update a README.

arch/arm/src/samd5e5/chip/sam_gclk.h

@@ -147,7 +147,7 @@
 #define GCLK_CHAN_SDHCn_SLOW         3         /* SDHC0-1 Slow */
 #define GCLK_CHAN_SDHC0_SLOW         3         /* SDHC0 Slow */
 #define GCLK_CHAN_SDHC1_SLOW         3         /* SDHC1 Slow */
-#define GCLK_CHAN_SERCOMn_SLOW       3         /* SERCOM0=7 Slow */
+#define GCLK_CHAN_SERCOMn_SLOW       3         /* SERCOM Slow (common) */
 #define GCLK_CHAN_SERCOM0_SLOW       3         /* SERCOM0 Slow */
 #define GCLK_CHAN_SERCOM1_SLOW       3         /* SERCOM1 Slow */
 #define GCLK_CHAN_SERCOM2_SLOW       3         /* SERCOM2 Slow */

arch/arm/src/samd5e5/sam_lowputc.c

@@ -286,16 +286,16 @@ int sam_usart_internal(const struct sam_usart_config_s * const config)
 {
   int ret;
 
-  /* Enable clocking to the SERCOM module */
-
-  sercom_enable(config->sercom);
-
   /* Configure the GCLKs for the SERCOM module */
 
   sercom_coreclk_configure(config->sercom, config->coregen,
                            (bool)config->corelock);
   sercom_slowclk_configure(config->sercom, config->slowgen);
 
+  /* Enable clocking to the SERCOM module */
+
+  sercom_enable(config->sercom);
+
   /* Set USART configuration according to the board configuration */
 
   ret = sam_usart_configure(config);

configs/metro-m4/README.txt

@@ -80,7 +80,28 @@ STATUS
     debugging from SRAM (with FLASH unlocked and erased).  Several
     errors in clock configuration logic have been corrected and it now
     gets through clock configuration okay.  It now hangs in the low-level
-    USART initialzation.
+    USART initialization.
+
+    It hangs trying to enabled the SERCOM slow clock channel.  The clock
+    sequence is:
+
+      1. 32.678KHz crystal -> XOSC32K
+         This is configured and says that XOSC32K is ready.
+      2. XOSCK32 -> GCLK3.
+         This is configured and it says that is is ready (GENEN=1).
+      3. GCLK3 ->SERCOM slow clock channel.
+         This hangs when I try to enable the peripheral clock.
+
+  2018-08-31:  I found a workaround by substituting OSCULP32K for XOSC32
+    as the source to GCLK3 (workaround *NOT* committed):
+
+    -#define BOARD_GCLK3_SOURCE  5  /* Select XOSC32K as GCLK3 source */
+    +#define BOARD_GCLK3_SOURCE  4  /* Select OSCULP32K as GCLK3 source */
+
+    This gets past all clock and USART configuration, but then there is a
+    hang in sam_lowputc().  All of the USART3 registers are zero so the wait
+    for data register empty (DRE) causes the hang.  It appears that the
+    SERCOM3 module is not properly enabled or not receiving clocking.
 
 Unlocking FLASH
 ===============