arch/arm/src/lpc54xx: Add reset logic. Some changes while debugging LDC. Does not yet work (hangs).
This commit is contained in:
Gregory Nutt
parent
f215660296
commit
d93a2d4f39
@ -81,7 +81,7 @@ endif
|
|||||||
|
|
||||||
CHIP_ASRCS =
|
CHIP_ASRCS =
|
||||||
CHIP_CSRCS = lpc54_start.c lpc54_clockconfig.c lpc54_irq.c lpc54_clrpend.c
|
CHIP_CSRCS = lpc54_start.c lpc54_clockconfig.c lpc54_irq.c lpc54_clrpend.c
|
||||||
CHIP_CSRCS += lpc54_allocateheap.c lpc54_lowputc.c lpc54_gpio.c
|
CHIP_CSRCS += lpc54_allocateheap.c lpc54_lowputc.c lpc54_gpio.c lpc54_reset.c
|
||||||
|
|
||||||
ifneq ($(CONFIG_SCHED_TICKLESS),y)
|
ifneq ($(CONFIG_SCHED_TICKLESS),y)
|
||||||
CHIP_CSRCS += lpc54_timerisr.c
|
CHIP_CSRCS += lpc54_timerisr.c
|
||||||
|
|||||||
@ -191,141 +191,141 @@
|
|||||||
|
|
||||||
/* Main system configuration */
|
/* Main system configuration */
|
||||||
|
|
||||||
#define LPC54_SYSCON_AHBMATPRIO (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBMATPRIO_OFFSET)
|
#define LPC54_SYSCON_AHBMATPRIO (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBMATPRIO_OFFSET)
|
||||||
#define LPC54_SYSCON_SYSTCKCAL (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSTCKCAL_OFFSET)
|
#define LPC54_SYSCON_SYSTCKCAL (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSTCKCAL_OFFSET)
|
||||||
#define LPC54_SYSCON_NMISRC (LPC54_SYSCON_BASE+LPC54_SYSCON_NMISRC_OFFSET)
|
#define LPC54_SYSCON_NMISRC (LPC54_SYSCON_BASE + LPC54_SYSCON_NMISRC_OFFSET)
|
||||||
#define LPC54_SYSCON_ASYNCAPBCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_ASYNCAPBCTRL_OFFSET)
|
#define LPC54_SYSCON_ASYNCAPBCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_ASYNCAPBCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_PIOPORCAP0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PIOPORCAP0_OFFSET)
|
#define LPC54_SYSCON_PIOPORCAP0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PIOPORCAP0_OFFSET)
|
||||||
#define LPC54_SYSCON_PIOPORCAP1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PIOPORCAP1_OFFSET)
|
#define LPC54_SYSCON_PIOPORCAP1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PIOPORCAP1_OFFSET)
|
||||||
#define LPC54_SYSCON_PIORESCAP0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PIORESCAP0_OFFSET)
|
#define LPC54_SYSCON_PIORESCAP0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PIORESCAP0_OFFSET)
|
||||||
#define LPC54_SYSCON_PIORESCAP1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PIORESCAP1_OFFSET)
|
#define LPC54_SYSCON_PIORESCAP1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PIORESCAP1_OFFSET)
|
||||||
#define LPC54_SYSCON_PRESETCTRL0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRL0_OFFSET)
|
#define LPC54_SYSCON_PRESETCTRL0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRL0_OFFSET)
|
||||||
#define LPC54_SYSCON_PRESETCTRL1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRL1_OFFSET)
|
#define LPC54_SYSCON_PRESETCTRL1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRL1_OFFSET)
|
||||||
#define LPC54_SYSCON_PRESETCTRL2 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRL2_OFFSET)
|
#define LPC54_SYSCON_PRESETCTRL2 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRL2_OFFSET)
|
||||||
#define LPC54_SYSCON_PRESETCTRLSET0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLSET0_OFFSET)
|
#define LPC54_SYSCON_PRESETCTRLSET0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRLSET0_OFFSET)
|
||||||
#define LPC54_SYSCON_PRESETCTRLSET1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLSET1_OFFSET)
|
#define LPC54_SYSCON_PRESETCTRLSET1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRLSET1_OFFSET)
|
||||||
#define LPC54_SYSCON_PRESETCTRLSET2 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLSET2_OFFSET)
|
#define LPC54_SYSCON_PRESETCTRLSET2 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRLSET2_OFFSET)
|
||||||
#define LPC54_SYSCON_PRESETCTRLCLR0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLCLR0_OFFSET)
|
#define LPC54_SYSCON_PRESETCTRLCLR0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRLCLR0_OFFSET)
|
||||||
#define LPC54_SYSCON_PRESETCTRLCLR1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLCLR1_OFFSET)
|
#define LPC54_SYSCON_PRESETCTRLCLR1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRLCLR1_OFFSET)
|
||||||
#define LPC54_SYSCON_PRESETCTRLCLR2 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLCLR2_OFFSET)
|
#define LPC54_SYSCON_PRESETCTRLCLR2 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRLCLR2_OFFSET)
|
||||||
#define LPC54_SYSCON_SYSRSTSTAT (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSRSTSTAT_OFFSET)
|
#define LPC54_SYSCON_SYSRSTSTAT (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSRSTSTAT_OFFSET)
|
||||||
#define LPC54_SYSCON_AHBCLKCTRL0 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRL0_OFFSET)
|
#define LPC54_SYSCON_AHBCLKCTRL0 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRL0_OFFSET)
|
||||||
#define LPC54_SYSCON_AHBCLKCTRL1 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRL1_OFFSET)
|
#define LPC54_SYSCON_AHBCLKCTRL1 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRL1_OFFSET)
|
||||||
#define LPC54_SYSCON_AHBCLKCTRL2 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRL2_OFFSET)
|
#define LPC54_SYSCON_AHBCLKCTRL2 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRL2_OFFSET)
|
||||||
#define LPC54_SYSCON_AHBCLKCTRLSET0 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLSET0_OFFSET)
|
#define LPC54_SYSCON_AHBCLKCTRLSET0 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRLSET0_OFFSET)
|
||||||
#define LPC54_SYSCON_AHBCLKCTRLSET1 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLSET1_OFFSET)
|
#define LPC54_SYSCON_AHBCLKCTRLSET1 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRLSET1_OFFSET)
|
||||||
#define LPC54_SYSCON_AHBCLKCTRLSET2 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLSET2_OFFSET)
|
#define LPC54_SYSCON_AHBCLKCTRLSET2 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRLSET2_OFFSET)
|
||||||
#define LPC54_SYSCON_AHBCLKCTRLCLR0 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLCLR0_OFFSET)
|
#define LPC54_SYSCON_AHBCLKCTRLCLR0 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRLCLR0_OFFSET)
|
||||||
#define LPC54_SYSCON_AHBCLKCTRLCLR1 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLCLR1_OFFSET)
|
#define LPC54_SYSCON_AHBCLKCTRLCLR1 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRLCLR1_OFFSET)
|
||||||
#define LPC54_SYSCON_AHBCLKCTRLCLR2 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLCLR2_OFFSET)
|
#define LPC54_SYSCON_AHBCLKCTRLCLR2 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRLCLR2_OFFSET)
|
||||||
#define LPC54_SYSCON_MAINCLKSELA (LPC54_SYSCON_BASE+LPC54_SYSCON_MAINCLKSELA_OFFSET)
|
#define LPC54_SYSCON_MAINCLKSELA (LPC54_SYSCON_BASE + LPC54_SYSCON_MAINCLKSELA_OFFSET)
|
||||||
#define LPC54_SYSCON_MAINCLKSELB (LPC54_SYSCON_BASE+LPC54_SYSCON_MAINCLKSELB_OFFSET)
|
#define LPC54_SYSCON_MAINCLKSELB (LPC54_SYSCON_BASE + LPC54_SYSCON_MAINCLKSELB_OFFSET)
|
||||||
#define LPC54_SYSCON_CLKOUTSELA (LPC54_SYSCON_BASE+LPC54_SYSCON_CLKOUTSELA_OFFSET)
|
#define LPC54_SYSCON_CLKOUTSELA (LPC54_SYSCON_BASE + LPC54_SYSCON_CLKOUTSELA_OFFSET)
|
||||||
#define LPC54_SYSCON_SYSPLLCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSPLLCLKSEL_OFFSET)
|
#define LPC54_SYSCON_SYSPLLCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSPLLCLKSEL_OFFSET)
|
||||||
#define LPC54_SYSCON_AUDPLLCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_AUDPLLCLKSEL_OFFSET)
|
#define LPC54_SYSCON_AUDPLLCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_AUDPLLCLKSEL_OFFSET)
|
||||||
#define LPC54_SYSCON_SPIFICLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_SPIFICLKSEL_OFFSET)
|
#define LPC54_SYSCON_SPIFICLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_SPIFICLKSEL_OFFSET)
|
||||||
#define LPC54_SYSCON_ADCCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_ADCCLKSEL_OFFSET)
|
#define LPC54_SYSCON_ADCCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_ADCCLKSEL_OFFSET)
|
||||||
#define LPC54_SYSCON_USB0CLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_USB0CLKSEL_OFFSET)
|
#define LPC54_SYSCON_USB0CLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_USB0CLKSEL_OFFSET)
|
||||||
#define LPC54_SYSCON_USB1CLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_USB1CLKSEL_OFFSET)
|
#define LPC54_SYSCON_USB1CLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_USB1CLKSEL_OFFSET)
|
||||||
#define LPC54_SYSCON_FCLKSEL0 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL0_OFFSET)
|
#define LPC54_SYSCON_FCLKSEL0 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL0_OFFSET)
|
||||||
#define LPC54_SYSCON_FCLKSEL1 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL1_OFFSET)
|
#define LPC54_SYSCON_FCLKSEL1 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL1_OFFSET)
|
||||||
#define LPC54_SYSCON_FCLKSEL2 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL2_OFFSET)
|
#define LPC54_SYSCON_FCLKSEL2 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL2_OFFSET)
|
||||||
#define LPC54_SYSCON_FCLKSEL3 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL3_OFFSET)
|
#define LPC54_SYSCON_FCLKSEL3 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL3_OFFSET)
|
||||||
#define LPC54_SYSCON_FCLKSEL4 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL4_OFFSET)
|
#define LPC54_SYSCON_FCLKSEL4 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL4_OFFSET)
|
||||||
#define LPC54_SYSCON_FCLKSEL5 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL5_OFFSET)
|
#define LPC54_SYSCON_FCLKSEL5 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL5_OFFSET)
|
||||||
#define LPC54_SYSCON_FCLKSEL6 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL6_OFFSET)
|
#define LPC54_SYSCON_FCLKSEL6 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL6_OFFSET)
|
||||||
#define LPC54_SYSCON_FCLKSEL7 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL7_OFFSET)
|
#define LPC54_SYSCON_FCLKSEL7 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL7_OFFSET)
|
||||||
#define LPC54_SYSCON_FCLKSEL8 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL8_OFFSET)
|
#define LPC54_SYSCON_FCLKSEL8 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL8_OFFSET)
|
||||||
#define LPC54_SYSCON_FCLKSEL9 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL9_OFFSET)
|
#define LPC54_SYSCON_FCLKSEL9 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL9_OFFSET)
|
||||||
#define LPC54_SYSCON_MCLKCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_MCLKCLKSEL_OFFSET)
|
#define LPC54_SYSCON_MCLKCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_MCLKCLKSEL_OFFSET)
|
||||||
#define LPC54_SYSCON_FRGCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_FRGCLKSEL_OFFSET)
|
#define LPC54_SYSCON_FRGCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_FRGCLKSEL_OFFSET)
|
||||||
#define LPC54_SYSCON_DMICCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_DMICCLKSEL_OFFSET)
|
#define LPC54_SYSCON_DMICCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_DMICCLKSEL_OFFSET)
|
||||||
#define LPC54_SYSCON_SCTCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_SCTCLKSEL_OFFSET)
|
#define LPC54_SYSCON_SCTCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_SCTCLKSEL_OFFSET)
|
||||||
#define LPC54_SYSCON_LCDCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_LCDCLKSEL_OFFSET)
|
#define LPC54_SYSCON_LCDCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_LCDCLKSEL_OFFSET)
|
||||||
#define LPC54_SYSCON_SDIOCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_SDIOCLKSEL_OFFSET)
|
#define LPC54_SYSCON_SDIOCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_SDIOCLKSEL_OFFSET)
|
||||||
#define LPC54_SYSCON_SYSTICKCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSTICKCLKDIV_OFFSET)
|
#define LPC54_SYSCON_SYSTICKCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSTICKCLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_ARMTRCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_ARMTRCLKDIV_OFFSET)
|
#define LPC54_SYSCON_ARMTRCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_ARMTRCLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_CAN0CLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_CAN0CLKDIV_OFFSET)
|
#define LPC54_SYSCON_CAN0CLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_CAN0CLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_CAN1CLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_CAN1CLKDIV_OFFSET)
|
#define LPC54_SYSCON_CAN1CLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_CAN1CLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_SC0CLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_SC0CLKDIV_OFFSET)
|
#define LPC54_SYSCON_SC0CLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_SC0CLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_SC1CLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_SC1CLKDIV_OFFSET)
|
#define LPC54_SYSCON_SC1CLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_SC1CLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_AHBCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKDIV_OFFSET)
|
#define LPC54_SYSCON_AHBCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_CLKOUTDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_CLKOUTDIV_OFFSET)
|
#define LPC54_SYSCON_CLKOUTDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_CLKOUTDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_FROHFDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_FROHFDIV_OFFSET)
|
#define LPC54_SYSCON_FROHFDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_FROHFDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_SPIFICLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_SPIFICLKDIV_OFFSET)
|
#define LPC54_SYSCON_SPIFICLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_SPIFICLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_ADCCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_ADCCLKDIV_OFFSET)
|
#define LPC54_SYSCON_ADCCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_ADCCLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_USB0CLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_USB0CLKDIV_OFFSET)
|
#define LPC54_SYSCON_USB0CLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_USB0CLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_USB1CLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_USB1CLKDIV_OFFSET)
|
#define LPC54_SYSCON_USB1CLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_USB1CLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_FRGCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_FRGCTRL_OFFSET)
|
#define LPC54_SYSCON_FRGCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_FRGCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_DMICCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_DMICCLKDIV_OFFSET)
|
#define LPC54_SYSCON_DMICCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_DMICCLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_MCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_MCLKDIV_OFFSET)
|
#define LPC54_SYSCON_MCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_MCLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_LCDCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_LCDCLKDIV_OFFSET)
|
#define LPC54_SYSCON_LCDCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_LCDCLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_SCTCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_SCTCLKDIV_OFFSET)
|
#define LPC54_SYSCON_SCTCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_SCTCLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_EMCCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_EMCCLKDIV_OFFSET)
|
#define LPC54_SYSCON_EMCCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_EMCCLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_SDIOCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_SDIOCLKDIV_OFFSET)
|
#define LPC54_SYSCON_SDIOCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_SDIOCLKDIV_OFFSET)
|
||||||
#define LPC54_SYSCON_FLASHCFG (LPC54_SYSCON_BASE+LPC54_SYSCON_FLASHCFG_OFFSET)
|
#define LPC54_SYSCON_FLASHCFG (LPC54_SYSCON_BASE + LPC54_SYSCON_FLASHCFG_OFFSET)
|
||||||
#define LPC54_SYSCON_USB0CLKCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_USB0CLKCTRL_OFFSET)
|
#define LPC54_SYSCON_USB0CLKCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_USB0CLKCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_USB0CLKSTAT (LPC54_SYSCON_BASE+LPC54_SYSCON_USB0CLKSTAT_OFFSET)
|
#define LPC54_SYSCON_USB0CLKSTAT (LPC54_SYSCON_BASE + LPC54_SYSCON_USB0CLKSTAT_OFFSET)
|
||||||
#define LPC54_SYSCON_FREQMECTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_FREQMECTRL_OFFSET)
|
#define LPC54_SYSCON_FREQMECTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_FREQMECTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_MCLKIO (LPC54_SYSCON_BASE+LPC54_SYSCON_MCLKIO_OFFSET)
|
#define LPC54_SYSCON_MCLKIO (LPC54_SYSCON_BASE + LPC54_SYSCON_MCLKIO_OFFSET)
|
||||||
#define LPC54_SYSCON_USB1CLKCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_USB1CLKCTRL_OFFSET)
|
#define LPC54_SYSCON_USB1CLKCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_USB1CLKCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_USB1CLKSTAT (LPC54_SYSCON_BASE+LPC54_SYSCON_USB1CLKSTAT_OFFSET)
|
#define LPC54_SYSCON_USB1CLKSTAT (LPC54_SYSCON_BASE + LPC54_SYSCON_USB1CLKSTAT_OFFSET)
|
||||||
#define LPC54_SYSCON_EMCSYSCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_EMCSYSCTRL_OFFSET)
|
#define LPC54_SYSCON_EMCSYSCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_EMCSYSCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_EMCDLYCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_EMCDLYCTRL_OFFSET)
|
#define LPC54_SYSCON_EMCDLYCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_EMCDLYCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_EMCDLYCAL (LPC54_SYSCON_BASE+LPC54_SYSCON_EMCDLYCAL_OFFSET)
|
#define LPC54_SYSCON_EMCDLYCAL (LPC54_SYSCON_BASE + LPC54_SYSCON_EMCDLYCAL_OFFSET)
|
||||||
#define LPC54_SYSCON_ETHPHYSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_ETHPHYSEL_OFFSET)
|
#define LPC54_SYSCON_ETHPHYSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_ETHPHYSEL_OFFSET)
|
||||||
#define LPC54_SYSCON_ETHSBDCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_ETHSBDCTRL_OFFSET)
|
#define LPC54_SYSCON_ETHSBDCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_ETHSBDCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_SDIOCLKCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_SDIOCLKCTRL_OFFSET)
|
#define LPC54_SYSCON_SDIOCLKCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_SDIOCLKCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_FROCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_FROCTRL_OFFSET)
|
#define LPC54_SYSCON_FROCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_FROCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_SYSOSCCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSOSCCTRL_OFFSET)
|
#define LPC54_SYSCON_SYSOSCCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSOSCCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_WDTOSCCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_WDTOSCCTRL_OFFSET)
|
#define LPC54_SYSCON_WDTOSCCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_WDTOSCCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_RTCOSCCTRL_ (LPC54_SYSCON_BASE+LPC54_SYSCON_RTCOSCCTRL_OFFSET)
|
#define LPC54_SYSCON_RTCOSCCTRL_ (LPC54_SYSCON_BASE + LPC54_SYSCON_RTCOSCCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_USBPLLCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_USBPLLCTRL_OFFSET)
|
#define LPC54_SYSCON_USBPLLCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_USBPLLCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_USBPLLSTAT (LPC54_SYSCON_BASE+LPC54_SYSCON_USBPLLSTAT_OFFSET)
|
#define LPC54_SYSCON_USBPLLSTAT (LPC54_SYSCON_BASE + LPC54_SYSCON_USBPLLSTAT_OFFSET)
|
||||||
#define LPC54_SYSCON_SYSPLLCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSPLLCTRL_OFFSET)
|
#define LPC54_SYSCON_SYSPLLCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSPLLCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_SYSPLLSTAT (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSPLLSTAT_OFFSET)
|
#define LPC54_SYSCON_SYSPLLSTAT (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSPLLSTAT_OFFSET)
|
||||||
#define LPC54_SYSCON_SYSPLLNDEC (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSPLLNDEC_OFFSET)
|
#define LPC54_SYSCON_SYSPLLNDEC (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSPLLNDEC_OFFSET)
|
||||||
#define LPC54_SYSCON_SYSPLLPDEC (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSPLLPDEC_OFFSET)
|
#define LPC54_SYSCON_SYSPLLPDEC (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSPLLPDEC_OFFSET)
|
||||||
#define LPC54_SYSCON_SYSPLLMDEC (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSPLLMDEC_OFFSET)
|
#define LPC54_SYSCON_SYSPLLMDEC (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSPLLMDEC_OFFSET)
|
||||||
#define LPC54_SYSCON_AUDPLLCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_AUDPLLCTRL_OFFSET)
|
#define LPC54_SYSCON_AUDPLLCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_AUDPLLCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_AUDPLLSTAT (LPC54_SYSCON_BASE+LPC54_SYSCON_AUDPLLSTAT_OFFSET)
|
#define LPC54_SYSCON_AUDPLLSTAT (LPC54_SYSCON_BASE + LPC54_SYSCON_AUDPLLSTAT_OFFSET)
|
||||||
#define LPC54_SYSCON_AUDPLLNDEC (LPC54_SYSCON_BASE+LPC54_SYSCON_AUDPLLNDEC_OFFSET)
|
#define LPC54_SYSCON_AUDPLLNDEC (LPC54_SYSCON_BASE + LPC54_SYSCON_AUDPLLNDEC_OFFSET)
|
||||||
#define LPC54_SYSCON_AUDPLLPDEC (LPC54_SYSCON_BASE+LPC54_SYSCON_AUDPLLPDEC_OFFSET)
|
#define LPC54_SYSCON_AUDPLLPDEC (LPC54_SYSCON_BASE + LPC54_SYSCON_AUDPLLPDEC_OFFSET)
|
||||||
#define LPC54_SYSCON_AUDPLLMDEC (LPC54_SYSCON_BASE+LPC54_SYSCON_AUDPLLMDEC_OFFSET)
|
#define LPC54_SYSCON_AUDPLLMDEC (LPC54_SYSCON_BASE + LPC54_SYSCON_AUDPLLMDEC_OFFSET)
|
||||||
#define LPC54_SYSCON_AUDPLLFRAC (LPC54_SYSCON_BASE+LPC54_SYSCON_AUDPLLFRAC_OFFSET)
|
#define LPC54_SYSCON_AUDPLLFRAC (LPC54_SYSCON_BASE + LPC54_SYSCON_AUDPLLFRAC_OFFSET)
|
||||||
#define LPC54_SYSCON_PDSLEEPCFG0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDSLEEPCFG0_OFFSET)
|
#define LPC54_SYSCON_PDSLEEPCFG0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDSLEEPCFG0_OFFSET)
|
||||||
#define LPC54_SYSCON_PDSLEEPCFG1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDSLEEPCFG1_OFFSET)
|
#define LPC54_SYSCON_PDSLEEPCFG1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDSLEEPCFG1_OFFSET)
|
||||||
#define LPC54_SYSCON_PDRUNCFG0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFG0_OFFSET)
|
#define LPC54_SYSCON_PDRUNCFG0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDRUNCFG0_OFFSET)
|
||||||
#define LPC54_SYSCON_PDRUNCFG1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFG1_OFFSET)
|
#define LPC54_SYSCON_PDRUNCFG1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDRUNCFG1_OFFSET)
|
||||||
#define LPC54_SYSCON_PDRUNCFGSET0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFGSET0_OFFSET)
|
#define LPC54_SYSCON_PDRUNCFGSET0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDRUNCFGSET0_OFFSET)
|
||||||
#define LPC54_SYSCON_PDRUNCFGSET1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFGSET1_OFFSET)
|
#define LPC54_SYSCON_PDRUNCFGSET1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDRUNCFGSET1_OFFSET)
|
||||||
#define LPC54_SYSCON_PDRUNCFGCLR0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFGCLR0_OFFSET)
|
#define LPC54_SYSCON_PDRUNCFGCLR0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDRUNCFGCLR0_OFFSET)
|
||||||
#define LPC54_SYSCON_PDRUNCFGCLR1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFGCLR1_OFFSET)
|
#define LPC54_SYSCON_PDRUNCFGCLR1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDRUNCFGCLR1_OFFSET)
|
||||||
#define LPC54_SYSCON_STARTER0 (LPC54_SYSCON_BASE+LPC54_SYSCON_STARTER0_OFFSET)
|
#define LPC54_SYSCON_STARTER0 (LPC54_SYSCON_BASE + LPC54_SYSCON_STARTER0_OFFSET)
|
||||||
#define LPC54_SYSCON_STARTER1 (LPC54_SYSCON_BASE+LPC54_SYSCON_STARTER1_OFFSET)
|
#define LPC54_SYSCON_STARTER1 (LPC54_SYSCON_BASE + LPC54_SYSCON_STARTER1_OFFSET)
|
||||||
#define LPC54_SYSCON_STARTERSET0 (LPC54_SYSCON_BASE+LPC54_SYSCON_STARTERSET0_OFFSET)
|
#define LPC54_SYSCON_STARTERSET0 (LPC54_SYSCON_BASE + LPC54_SYSCON_STARTERSET0_OFFSET)
|
||||||
#define LPC54_SYSCON_STARTERSET1 (LPC54_SYSCON_BASE+LPC54_SYSCON_STARTERSET1_OFFSET)
|
#define LPC54_SYSCON_STARTERSET1 (LPC54_SYSCON_BASE + LPC54_SYSCON_STARTERSET1_OFFSET)
|
||||||
#define LPC54_SYSCON_STARTERCLR0 (LPC54_SYSCON_BASE+LPC54_SYSCON_STARTERCLR0_OFFSET)
|
#define LPC54_SYSCON_STARTERCLR0 (LPC54_SYSCON_BASE + LPC54_SYSCON_STARTERCLR0_OFFSET)
|
||||||
#define LPC54_SYSCON_STARTERCLR1 (LPC54_SYSCON_BASE+LPC54_SYSCON_STARTERCLR1_OFFSET)
|
#define LPC54_SYSCON_STARTERCLR1 (LPC54_SYSCON_BASE + LPC54_SYSCON_STARTERCLR1_OFFSET)
|
||||||
#define LPC54_SYSCON_HWWAKE (LPC54_SYSCON_BASE+LPC54_SYSCON_HWWAKE_OFFSET)
|
#define LPC54_SYSCON_HWWAKE (LPC54_SYSCON_BASE + LPC54_SYSCON_HWWAKE_OFFSET)
|
||||||
#define LPC54_SYSCON_AUTOCGOR (LPC54_SYSCON_BASE+LPC54_SYSCON_AUTOCGOR_OFFSET)
|
#define LPC54_SYSCON_AUTOCGOR (LPC54_SYSCON_BASE + LPC54_SYSCON_AUTOCGOR_OFFSET)
|
||||||
#define LPC54_SYSCON_JTAGIDCODE (LPC54_SYSCON_BASE+LPC54_SYSCON_JTAGIDCODE_OFFSET)
|
#define LPC54_SYSCON_JTAGIDCODE (LPC54_SYSCON_BASE + LPC54_SYSCON_JTAGIDCODE_OFFSET)
|
||||||
#define LPC54_SYSCON_DEVICE_ID0 (LPC54_SYSCON_BASE+LPC54_SYSCON_DEVICE_ID0_OFFSET)
|
#define LPC54_SYSCON_DEVICE_ID0 (LPC54_SYSCON_BASE + LPC54_SYSCON_DEVICE_ID0_OFFSET)
|
||||||
#define LPC54_SYSCON_DEVICE_ID1 (LPC54_SYSCON_BASE+LPC54_SYSCON_DEVICE_ID1_OFFSET)
|
#define LPC54_SYSCON_DEVICE_ID1 (LPC54_SYSCON_BASE + LPC54_SYSCON_DEVICE_ID1_OFFSET)
|
||||||
|
|
||||||
/* Asynchronous system configuration */
|
/* Asynchronous system configuration */
|
||||||
|
|
||||||
#define LPC54_SYSCON_ASYNCPRESETCTRL (LPC54_ASYSCON_BASE+LPC54_SYSCON_ASYNCPRESETCTRL_OFFSET)
|
#define LPC54_SYSCON_ASYNCPRESETCTRL (LPC54_ASYSCON_BASE + LPC54_SYSCON_ASYNCPRESETCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_ASYNCPRESETCTRLSET (LPC54_ASYSCON_BASE+LPC54_SYSCON_ASYNCPRESETCTRLSET_OFFSET)
|
#define LPC54_SYSCON_ASYNCPRESETCTRLSET (LPC54_ASYSCON_BASE + LPC54_SYSCON_ASYNCPRESETCTRLSET_OFFSET)
|
||||||
#define LPC54_SYSCON_ASYNCPRESETCTRLCLR (LPC54_ASYSCON_BASE+LPC54_SYSCON_ASYNCPRESETCTRLCLR_OFFSET)
|
#define LPC54_SYSCON_ASYNCPRESETCTRLCLR (LPC54_ASYSCON_BASE + LPC54_SYSCON_ASYNCPRESETCTRLCLR_OFFSET)
|
||||||
#define LPC54_SYSCON_ASYNCAPBCLKCTRL (LPC54_ASYSCON_BASE+LPC54_SYSCON_ASYNCAPBCLKCTRL_OFFSET)
|
#define LPC54_SYSCON_ASYNCAPBCLKCTRL (LPC54_ASYSCON_BASE + LPC54_SYSCON_ASYNCAPBCLKCTRL_OFFSET)
|
||||||
#define LPC54_SYSCON_ASYNCAPBCLKCTRLSET (LPC54_ASYSCON_BASE+LPC54_SYSCON_ASYNCAPBCLKCTRLSET_OFFSET)
|
#define LPC54_SYSCON_ASYNCAPBCLKCTRLSET (LPC54_ASYSCON_BASE + LPC54_SYSCON_ASYNCAPBCLKCTRLSET_OFFSET)
|
||||||
#define LPC54_SYSCON_ASYNCAPBCLKCTRLCLR (LPC54_ASYSCON_BASE+LPC54_SYSCON_ASYNCAPBCLKCTRLCLR_OFFSET)
|
#define LPC54_SYSCON_ASYNCAPBCLKCTRLCLR (LPC54_ASYSCON_BASE + LPC54_SYSCON_ASYNCAPBCLKCTRLCLR_OFFSET)
|
||||||
#define LPC54_SYSCON_ASYNCAPBCLKSELA (LPC54_ASYSCON_BASE+LPC54_SYSCON_ASYNCAPBCLKSELA_OFFSET)
|
#define LPC54_SYSCON_ASYNCAPBCLKSELA (LPC54_ASYSCON_BASE + LPC54_SYSCON_ASYNCAPBCLKSELA_OFFSET)
|
||||||
|
|
||||||
/* Other system configuration */
|
/* Other system configuration */
|
||||||
|
|
||||||
#define LPC54_SYSCON_BODCTRL (LPC54_OSYSCON_BASE+LPC54_SYSCON_BODCTRL_OFFSET)
|
#define LPC54_SYSCON_BODCTRL (LPC54_OSYSCON_BASE + LPC54_SYSCON_BODCTRL_OFFSET)
|
||||||
|
|
||||||
/* Register bit definitions *****************************************************************/
|
/* Register bit definitions *****************************************************************/
|
||||||
|
|
||||||
@ -819,12 +819,11 @@
|
|||||||
|
|
||||||
/* Asynchronous system configuration */
|
/* Asynchronous system configuration */
|
||||||
|
|
||||||
/* Async peripheral reset control */
|
/* Async peripheral reset control, set, and clear registers */
|
||||||
#define SYSCON_ASYNCPRESETCTRL_
|
|
||||||
/* Set bits in ASYNCPRESETCTRL */
|
#define SYSCON_ASYNCPRESET_CTIMER3 (1 << 13) /* Bit 13: CTIMER3 reset control */
|
||||||
#define SYSCON_ASYNCPRESETCTRLSET_
|
#define SYSCON_ASYNCPRESET_CTIMER4 (1 << 14) /* Bit 14: CTIMER4 reset control */
|
||||||
/* Clear bits in ASYNCPRESETCTRL */
|
|
||||||
#define SYSCON_ASYNCPRESETCTRLCLR_
|
|
||||||
/* Async peripheral clock control */
|
/* Async peripheral clock control */
|
||||||
#define SYSCON_ASYNCAPBCLKCTRL_
|
#define SYSCON_ASYNCAPBCLKCTRL_
|
||||||
/* Set bits in ASYNCAPBCLKCTRL */
|
/* Set bits in ASYNCAPBCLKCTRL */
|
||||||
|
|||||||
@ -54,6 +54,7 @@
|
|||||||
|
|
||||||
#include "chip/lpc54_syscon.h"
|
#include "chip/lpc54_syscon.h"
|
||||||
#include "chip/lpc54_emc.h"
|
#include "chip/lpc54_emc.h"
|
||||||
|
#include "lpc54_reset.h"
|
||||||
#include "lpc54_emc.h"
|
#include "lpc54_emc.h"
|
||||||
|
|
||||||
#ifdef CONFIG_LPC54_EMC
|
#ifdef CONFIG_LPC54_EMC
|
||||||
@ -240,8 +241,7 @@ void lpc54_emc_initialize(FAR const struct emc_config_s *config)
|
|||||||
|
|
||||||
/* Reset the EMC */
|
/* Reset the EMC */
|
||||||
|
|
||||||
putreg32(SYSCON_PRESETCTRL2_EMC, LPC54_SYSCON_PRESETCTRLSET2);
|
lpc54_reset_emc();
|
||||||
putreg32(SYSCON_PRESETCTRL2_EMC, LPC54_SYSCON_PRESETCTRLCLR2);
|
|
||||||
|
|
||||||
/* Set the EMC sytem configure */
|
/* Set the EMC sytem configure */
|
||||||
|
|
||||||
|
|||||||
@ -53,6 +53,7 @@
|
|||||||
#include "chip/lpc54_syscon.h"
|
#include "chip/lpc54_syscon.h"
|
||||||
#include "chip/lpc54_pinmux.h"
|
#include "chip/lpc54_pinmux.h"
|
||||||
#include "lpc54_gpio.h"
|
#include "lpc54_gpio.h"
|
||||||
|
#include "lpc54_reset.h"
|
||||||
#include "lpc54_lcd.h"
|
#include "lpc54_lcd.h"
|
||||||
|
|
||||||
#include <arch/board/board.h>
|
#include <arch/board/board.h>
|
||||||
@ -192,10 +193,6 @@ struct fb_vtable_s g_fbobject =
|
|||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Public Data
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Functions
|
* Private Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@ -534,6 +531,12 @@ int up_fbinitialize(int display)
|
|||||||
lpc54_gpio_config(GPIO_LCD_CLKIN); /* Optional clock input */
|
lpc54_gpio_config(GPIO_LCD_CLKIN); /* Optional clock input */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
lcdinfo("Enable clocking to the LCD controller\n");
|
||||||
|
|
||||||
|
/* Enable clocking to the LCD peripheral */
|
||||||
|
|
||||||
|
putreg32(SYSCON_AHBCLKCTRL2_LCD, LPC54_SYSCON_AHBCLKCTRLSET2);
|
||||||
|
|
||||||
/* Route Main clock (or LCK CLKIN) to the LCD. */
|
/* Route Main clock (or LCK CLKIN) to the LCD. */
|
||||||
|
|
||||||
#ifdef CONFIG_LPC54_LCD_USE_CLKIN
|
#ifdef CONFIG_LPC54_LCD_USE_CLKIN
|
||||||
@ -542,6 +545,10 @@ int up_fbinitialize(int display)
|
|||||||
putreg32(SYSCON_LCDCLKSEL_MAINCLK, LPC54_SYSCON_LCDCLKSEL);
|
putreg32(SYSCON_LCDCLKSEL_MAINCLK, LPC54_SYSCON_LCDCLKSEL);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/* Reset the LCD */
|
||||||
|
|
||||||
|
lpc54_reset_lcd();
|
||||||
|
|
||||||
lcdinfo("Configuring the LCD controller\n");
|
lcdinfo("Configuring the LCD controller\n");
|
||||||
|
|
||||||
/* Disable the cursor */
|
/* Disable the cursor */
|
||||||
@ -558,7 +565,7 @@ int up_fbinitialize(int display)
|
|||||||
|
|
||||||
putreg32(0, LPC54_LCD_CTRL);
|
putreg32(0, LPC54_LCD_CTRL);
|
||||||
|
|
||||||
/* Initialize pixel clock */
|
/* Initialize pixel clock. Set the LCD clock divier. */
|
||||||
|
|
||||||
#ifdef CONFIG_LPC54_LCD_USE_CLKIN
|
#ifdef CONFIG_LPC54_LCD_USE_CLKIN
|
||||||
lcddiv = ((uint32_t)CONFIG_LPC54_LCD_CLKIN_FREQUENCY /
|
lcddiv = ((uint32_t)CONFIG_LPC54_LCD_CLKIN_FREQUENCY /
|
||||||
@ -707,7 +714,9 @@ int up_fbinitialize(int display)
|
|||||||
putreg32(0, LPC54_LCD_INTMSK);
|
putreg32(0, LPC54_LCD_INTMSK);
|
||||||
lcdinfo("Enabling the display\n");
|
lcdinfo("Enabling the display\n");
|
||||||
|
|
||||||
for (i = LPC54_LCD_PWREN_DELAY; i; i--);
|
for (i = LPC54_LCD_PWREN_DELAY; i; i--)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
/* Enable LCD */
|
/* Enable LCD */
|
||||||
|
|
||||||
@ -717,7 +726,9 @@ int up_fbinitialize(int display)
|
|||||||
|
|
||||||
/* Enable LCD power */
|
/* Enable LCD power */
|
||||||
|
|
||||||
for (i = LPC54_LCD_PWREN_DELAY; i; i--);
|
for (i = LPC54_LCD_PWREN_DELAY; i; i--)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
regval = getreg32(LPC54_LCD_CTRL);
|
regval = getreg32(LPC54_LCD_CTRL);
|
||||||
regval |= LCD_CTRL_LCDPWR;
|
regval |= LCD_CTRL_LCDPWR;
|
||||||
@ -793,7 +804,9 @@ void up_fbuninitialize(int display)
|
|||||||
regval &= ~LCD_CTRL_LCDPWR;
|
regval &= ~LCD_CTRL_LCDPWR;
|
||||||
putreg32(regval, LPC54_LCD_CTRL);
|
putreg32(regval, LPC54_LCD_CTRL);
|
||||||
|
|
||||||
for (i = LPC54_LCD_PWRDIS_DELAY; i; i--);
|
for (i = LPC54_LCD_PWRDIS_DELAY; i; i--)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
regval &= ~LCD_CTRL_LCDEN;
|
regval &= ~LCD_CTRL_LCDEN;
|
||||||
putreg32(regval, LPC54_LCD_CTRL);
|
putreg32(regval, LPC54_LCD_CTRL);
|
||||||
@ -801,6 +814,10 @@ void up_fbuninitialize(int display)
|
|||||||
/* Turn off clocking to the LCD. modifyreg32() can do this atomically. */
|
/* Turn off clocking to the LCD. modifyreg32() can do this atomically. */
|
||||||
|
|
||||||
putreg32(SYSCON_LCDCLKSEL_NONE, LPC54_SYSCON_LCDCLKSEL);
|
putreg32(SYSCON_LCDCLKSEL_NONE, LPC54_SYSCON_LCDCLKSEL);
|
||||||
|
|
||||||
|
/* Disable clocking to the LCD peripheral */
|
||||||
|
|
||||||
|
putreg32(SYSCON_AHBCLKCTRL2_LCD, LPC54_SYSCON_AHBCLKCTRLCLR2);
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
|
|||||||
79
arch/arm/src/lpc54xx/lpc54_reset.c
Normal file
79
arch/arm/src/lpc54xx/lpc54_reset.c
Normal file
@ -0,0 +1,79 @@
|
|||||||
|
/****************************************************************************
|
||||||
|
* arch/arm/src/lpc54/lpc54_reset.c
|
||||||
|
*
|
||||||
|
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||||
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Included Files
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
|
||||||
|
#include "up_arch.h"
|
||||||
|
#include "lpc54_reset.h"
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Public Functions
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Name: lpc54_reset
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Reset the selected peripheral
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
void lpc54_reset(uintptr_t setreg, uintptr_t clrreg,
|
||||||
|
uintptr_t statreg, uint32_t mask)
|
||||||
|
{
|
||||||
|
/* Set the bit to put the peripheral in reset */
|
||||||
|
|
||||||
|
putreg32(mask, setreg);
|
||||||
|
|
||||||
|
/* Wait until the peripheral is in reset */
|
||||||
|
|
||||||
|
while ((getreg32(statreg) & mask) == 0)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear the bit to take the peripheral out of reset */
|
||||||
|
|
||||||
|
putreg32(mask, clrreg);
|
||||||
|
|
||||||
|
/* Wait until the peripheral is out of reset */
|
||||||
|
|
||||||
|
while ((getreg32(statreg) & mask) != 0)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
}
|
||||||
139
arch/arm/src/lpc54xx/lpc54_reset.h
Normal file
139
arch/arm/src/lpc54xx/lpc54_reset.h
Normal file
@ -0,0 +1,139 @@
|
|||||||
|
/****************************************************************************
|
||||||
|
* arch/arm/src/lpc54xx/lpc54_reset.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||||
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_RESET_H
|
||||||
|
#define __ARCH_ARM_SRC_LPC54XX_LPC54_RESET_H
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Included Files
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Pre-processor Definitions
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#define lpc54_reset_peripheral0(m) \
|
||||||
|
lpc54_reset(LPC54_SYSCON_PRESETCTRLSET0, LPC54_SYSCON_PRESETCTRLCLR0, \
|
||||||
|
LPC54_SYSCON_PRESETCTRL0, (m))
|
||||||
|
|
||||||
|
#define lpc54_reset_peripheral1(m) \
|
||||||
|
lpc54_reset(LPC54_SYSCON_PRESETCTRLSET1, LPC54_SYSCON_PRESETCTRLCLR1, \
|
||||||
|
LPC54_SYSCON_PRESETCTRL1, (m))
|
||||||
|
|
||||||
|
#define lpc54_reset_peripheral2(m) \
|
||||||
|
lpc54_reset(LPC54_SYSCON_PRESETCTRLSET2, LPC54_SYSCON_PRESETCTRLCLR2, \
|
||||||
|
LPC54_SYSCON_PRESETCTRL2, (m))
|
||||||
|
|
||||||
|
#define lpc54_reset_async_peripheral(m) \
|
||||||
|
lpc54_reset(LPC54_SYSCON_ASYNCPRESETCTRLSET, LPC54_SYSCON_ASYNCPRESETCTRLCLR, \
|
||||||
|
LPC54_SYSCON_ASYNCPRESETCTRL, (m))
|
||||||
|
|
||||||
|
#define lpc54_reset_flash() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_FLASH)
|
||||||
|
#define lpc54_reset_fmc() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_FMC)
|
||||||
|
#define lpc54_reset_eeprom() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_EEPROM)
|
||||||
|
#define lpc54_reset_spifi() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_SPIFI)
|
||||||
|
#define lpc54_reset_inputmux() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_INPUTMUX)
|
||||||
|
#define lpc54_reset_iocon() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_IOCON)
|
||||||
|
#define lpc54_reset_gpio0() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO0)
|
||||||
|
#define lpc54_reset_gpio1() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO1)
|
||||||
|
#define lpc54_reset_gpio2() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO2)
|
||||||
|
#define lpc54_reset_gpio3() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO3)
|
||||||
|
#define lpc54_reset_pint() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_PINT)
|
||||||
|
#define lpc54_reset_gint() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GINT)
|
||||||
|
#define lpc54_reset_dma() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_DMA)
|
||||||
|
#define lpc54_reset_crc() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_CRC)
|
||||||
|
#define lpc54_reset_wwdt() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_WWDT)
|
||||||
|
#define lpc54_reset_rtc() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_RTC)
|
||||||
|
#define lpc54_reset_adc0() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_ADC0)
|
||||||
|
|
||||||
|
#define lpc54_reset_mrt() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_MRT)
|
||||||
|
#define lpc54_reset_sct0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_SCT0)
|
||||||
|
#define lpc54_reset_mcan0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_MCAN0)
|
||||||
|
#define lpc54_reset_mcan1() lpc54_reset_peripheral1SYSCON_PRESETCTRL1_MCAN1)
|
||||||
|
#define lpc54_reset_utick() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_UTICK)
|
||||||
|
#define lpc54_reset_flexcomm0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM0)
|
||||||
|
#define lpc54_reset_flexcomm1() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM1)
|
||||||
|
#define lpc54_reset_flexcomm2() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM2)
|
||||||
|
#define lpc54_reset_flexcomm3() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM3)
|
||||||
|
#define lpc54_reset_flexcomm4() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM4)
|
||||||
|
#define lpc54_reset_flexcomm5() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM5)
|
||||||
|
#define lpc54_reset_flexcomm6() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM6)
|
||||||
|
#define lpc54_reset_flexcomm7() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM7)
|
||||||
|
#define lpc54_reset_dmic() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_DMIC)
|
||||||
|
#define lpc54_reset_ctimer2() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_CTIMER2)
|
||||||
|
#define lpc54_reset_usb0d() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_USB0D)
|
||||||
|
#define lpc54_reset_ctimer0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_CTIMER0)
|
||||||
|
#define lpc54_reset_ctimer1() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_CTIMER1)
|
||||||
|
|
||||||
|
#define lpc54_reset_lcd() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_LCD)
|
||||||
|
#define lpc54_reset_sdio() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SDIO)
|
||||||
|
#define lpc54_reset_usb1h() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB1H)
|
||||||
|
#define lpc54_reset_usb1d() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB1D)
|
||||||
|
#define lpc54_reset_usb1ram() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB1RAM)
|
||||||
|
#define lpc54_reset_emc() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_EMC)
|
||||||
|
#define lpc54_reset_eth() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_ETH)
|
||||||
|
#define lpc54_reset_gpio4() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_GPIO4)
|
||||||
|
#define lpc54_reset_gpio5() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_GPIO5)
|
||||||
|
#define lpc54_reset_otp() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_OTP)
|
||||||
|
#define lpc54_reset_rng() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_RNG)
|
||||||
|
#define lpc54_reset_flexcomm8() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_FLEXCOMM8)
|
||||||
|
#define lpc54_reset_flexcomm9() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_FLEXCOMM9)
|
||||||
|
#define lpc54_reset_usb0hmr() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB0HMR)
|
||||||
|
#define lpc54_reset_usb0hsl() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB0HSL)
|
||||||
|
#define lpc54_reset_sha() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SHA)
|
||||||
|
#define lpc54_reset_sc0() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SC0)
|
||||||
|
#define lpc54_reset_sc1() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SC1)
|
||||||
|
|
||||||
|
#define lpc54_reset_ctimer3() lpc54_reset_async_peripheral(SYSCON_ASYNCPRESET_CTIMER3)
|
||||||
|
#define lpc54_reset_ctimer4() lpc54_reset_async_peripheral(SYSCON_ASYNCPRESET_CTIMER4)
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Public Functions
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Name: lpc54_reset
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Reset the selected peripheral
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
void lpc54_reset(uintptr_t setreg, uintptr_t clrreg,
|
||||||
|
uintptr_t statreg, uint32_t mask);
|
||||||
|
|
||||||
|
#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_RESET_H */
|
||||||
@ -40,9 +40,8 @@ STATUS
|
|||||||
minor clock source setting). That port required modifications only
|
minor clock source setting). That port required modifications only
|
||||||
for differences in some SYSCON and pin-related settings.
|
for differences in some SYSCON and pin-related settings.
|
||||||
2017-12-13: Created the fb configuration for testing the LCD. Only
|
2017-12-13: Created the fb configuration for testing the LCD. Only
|
||||||
minimal testing has been performed. As of this writing, there is
|
minimal testing has been performed. As of this writing, the system
|
||||||
no video output from the apps/examples/fb test: The backlight is on
|
hangs while initializing the LCD.
|
||||||
but the display is blank/white.
|
|
||||||
|
|
||||||
Configurations
|
Configurations
|
||||||
==============
|
==============
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user