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Cosmetic changes from review of last PR

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This commit is contained in:
Gregory Nutt 2017-06-14 15:32:54 -06:00
parent 2a723bdeb7
commit d958cec7a4
6 changed files with 35 additions and 25 deletions
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3
arch/arm/src/stm32/stm32_irq.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_irq.c
*
* Copyright (C) 2009-2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -389,6 +389,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_RTC
/* RTC was initialized earlier but IRQs weren't ready at that time */
stm32_rtc_irqinitialize();
#endif

27
arch/arm/src/stm32/stm32_rtc.h
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@ -2,7 +2,7 @@
* arch/arm/src/stm32/stm32_rtc.h
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Copyright (C) 2011-2013, 2015-2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2011-2013, 2015-2017 Gregory Nutt. All rights reserved.
* Author: Uros Platise <uros.platise@isotel.eu> (Original for the F1)
* Gregory Nutt <gnutt@nuttx.org> (On-going support and development)
*
@ -76,37 +76,40 @@
* Pre-processor Definitions
****************************************************************************/
#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */
#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */
#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a
* second base */
#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */
#if defined(CONFIG_STM32_STM32F10XX)
/* RTC is only a counter, store RTC data in backup domain register DR1 (if CONFIG_RTC_HIRES) and DR2 (state) */
/* RTC is only a counter, store RTC data in backup domain register DR1 (if
* CONFIG_RTC_HIRES) and DR2 (state).
*/
#if !defined(CONFIG_RTC_MAGIC)
# define CONFIG_RTC_MAGIC (0xface) /* only 16 bit */
# define CONFIG_RTC_MAGIC (0xface) /* only 16 bit */
#endif
#define RTC_MAGIC_REG STM32_BKP_DR2
#define RTC_MAGIC_REG STM32_BKP_DR2
#else /* !CONFIG_STM32_STM32F10XX */
#if !defined(CONFIG_RTC_MAGIC)
# define CONFIG_RTC_MAGIC (0xfacefeee)
# define CONFIG_RTC_MAGIC (0xfacefeee)
#endif
#if !defined(CONFIG_RTC_MAGIC_REG)
# define CONFIG_RTC_MAGIC_REG (0)
# define CONFIG_RTC_MAGIC_REG (0)
#endif
#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_RTC_MAGIC_REG)
#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_RTC_MAGIC_REG)
#endif /* CONFIG_STM32_STM32F10XX */
#define RTC_MAGIC CONFIG_RTC_MAGIC
#define RTC_MAGIC_TIME_SET CONFIG_RTC_MAGIC_TIME_SET
#define RTC_MAGIC CONFIG_RTC_MAGIC
#define RTC_MAGIC_TIME_SET CONFIG_RTC_MAGIC_TIME_SET
#if !defined(CONFIG_RTC_MAGIC_TIME_SET)
# define CONFIG_RTC_MAGIC_TIME_SET (CONFIG_RTC_MAGIC + 1)
# define CONFIG_RTC_MAGIC_TIME_SET (CONFIG_RTC_MAGIC + 1)
#endif
/****************************************************************************

4
arch/arm/src/stm32/stm32_rtcc.c
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@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_rtcc.c
*
* Copyright (C) 2012-2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2012-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -788,7 +788,7 @@ int stm32_rtc_irqinitialize(void)
#ifdef CONFIG_RTC_ALARM
# warning "Missing EXTI setup logic"
/* then attach the ALARM interrupt handler */
/* Attach the ALARM interrupt handler */
irq_attach(STM32_IRQ_RTC_WKUP, rtc_interrupt, NULL);
up_enable_irq(STM32_IRQ_RTC_WKUP);

18
arch/arm/src/stm32/stm32_rtcounter.c
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@ -6,7 +6,7 @@
*
* With extensions, modifications by:
*
* Copyright (C) 2011-2013, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2011-2013, 2015, 2017 Gregory Nutt. All rights reserved.
* Author: Gregroy Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -384,21 +384,22 @@ int up_rtc_initialize(void)
stm32_pwr_enablebkp(true);
regval = getreg32(RTC_MAGIC_REG);
if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET)
{
/* reset backup domain if bad magic */
/* Reset backup domain if bad magic */
modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST);
modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0);
putreg16(RTC_MAGIC, RTC_MAGIC_REG);
}
/* Select the lower power external 32,768Hz (Low-Speed External, LSE) oscillator
* as RTC Clock Source and enable the Clock */
* as RTC Clock Source and enable the Clock.
*/
modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
/* enable RTC and wait for RSF */
/* Enable RTC and wait for RSF */
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
@ -416,7 +417,10 @@ int up_rtc_initialize(void)
stm32_rtc_wait4rsf();
#ifdef CONFIG_RTC_HIRES
/* enable overflow interrupt - alarm interrupt is enabled in stm32_rtc_setalarm */
/* Enable overflow interrupt - alarm interrupt is enabled in
* stm32_rtc_setalarm.
*/
modifyreg16(STM32_RTC_CRH, 0, RTC_CRH_OWIE);
#endif
@ -457,9 +461,9 @@ int up_rtc_initialize(void)
int stm32_rtc_irqinitialize(void)
{
#if defined(CONFIG_RTC_HIRES) || defined(CONFIG_RTC_ALARM)
/* Configure RTC interrupt to catch overflow and alarm interrupts. */
#if defined(CONFIG_RTC_HIRES) || defined(CONFIG_RTC_ALARM)
irq_attach(STM32_IRQ_RTC, stm32_rtc_interrupt, NULL);
up_enable_irq(STM32_IRQ_RTC);
#endif

3
arch/arm/src/stm32/stm32f40xxx_rtcc.c
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@ -1075,7 +1075,8 @@ int up_rtc_initialize(void)
int stm32_rtc_irqinitialize(void)
{
/* nothing to do */
/* Nothing to do */
return OK;
}

5
arch/arm/src/stm32l4/stm32l4_rtcc.c
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@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32l4/stm32l4_rtcc.c
*
* Copyright (C) 2012-2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2012-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* dev@ziggurat29.com (adaptations to stm32l4)
*
@ -1020,7 +1020,8 @@ int up_rtc_initialize(void)
int stm32_rtc_irqinitialize(void)
{
/* nothing to do */
/* Nothing to do */
return OK;
}